(36) (2013) (farhadi) (ieee trans power electron)

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 2, FEBRUARY 2013 625

A Generalized Cascaded Multilevel Inverter UsingSeries Connection of Submultilevel Inverters

Mohammad Farhadi Kangarlu, Student Member, IEEE, and Ebrahim Babaei, Member, IEEE

Abstract—Application of multilevel inverters for higher powerpurposes in industries has become more popular. This is partlybecause of high-quality output waveform of multilevel inverters incomparison with two-level inverters. In this paper, initially a newtopology for submultilevel inverter is proposed and then series con-nection of the submultilevel inverters is proposed as a generalizedmultilevel inverter. The proposed multilevel inverter uses reducednumber of switching devices. Special attention has been paid to ob-tain optimal structures regarding different criteria such as numberof switches, standing voltage on the switches, number of dc voltagesources, etc. The proposed multilevel inverter has been analyzedin both symmetric and asymmetric conditions. The validity of theproposed multilevel inverter is verified with both computer simu-lations using PSCAD/EMTDC software and laboratory prototypeimplementation.

Index Terms—Generalized topology, multilevel inverter, optimalstructure, submultilevel inverter.

I. INTRODUCTION

MULTILEVEL inverters include an array of power semi-conductors and dc voltage sources, the output of which

generate voltages with stepped waveforms [1]. In comparisonwith a two-level voltage-source inverter (VSI), the multilevelVSI enables to synthesize output voltages with reduced har-monic distortion and lower electromagnetic interference [2].By increasing the number of levels in the multilevel inverters,the output voltages have more steps in generating a staircasewaveform, which has a reduced harmonic distortion. However,a larger number of levels increase the number of devices thatmust be controlled and the control complexity [3].

There are three well-known types of multilevel inverters [4],[5]: the neutral point clamped (NPC) multilevel inverter, theflying capacitor (FC) multilevel inverter, and the cascadedH-bridge (CHB) multilevel inverter. The NPC multilevel in-verter, also called diode-clamped, can be considered the firstgeneration of multilevel inverter introduced by Nabae et al. [6]which was a three-level inverter. The three-level case of the NPCmultilevel inverters has been widely applied in different indus-tries. Unlike the NPC type, the FC multilevel inverter offers

Manuscript received July 30, 2011; revised November 16, 2011 and February4, 2012; accepted May 24, 2012. Date of current version September 27, 2012.Recommended for publication by Associate Editor J. R. Rodriguez.

The authors are with the Faculty of Electrical and Computer Engineer-ing, University of Tabriz, 51664 Tabriz, Iran (e-mail: [email protected];[email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2012.2203339

some redundant switching states that can be used to regulatethe capacitors voltage. However, the control scheme becomescomplicated. Moreover, the number of capacitors increases byincreasing the number of voltage levels.

The CHB multilevel inverters use series-connected H-bridgecells with an isolated dc voltage sources connected to eachcell. The CHB multilevel inverters can be divided into twogroups from the viewpoint of values of the dc voltage sources:the symmetric and the asymmetric topology. In the symmetrictopology, the values of all of the dc voltage sources are equal.This characteristic gives the topology good modularity. How-ever, the number of the switching devices rapidly increases byincreasing the number of output voltage level. In order to in-crease the number of output voltage level, the values of the dcvoltage sources are selected to be different, these topologiesare called asymmetric [7], [8]. The CHB multilevel invertershave been industrially employed in several applications fieldssuch as pump, fans, compressors, etc. In addition, they haverecently been proposed for other applications like photovoltaicpower-conversion system and wind power conversion [9]. Thetopologies discussed previously are the conventional topologies.Many other multilevel inverter topologies have been introducedin recent years. One of the topologies is the modular multi-level inverter [10]. This topology is simpler than the cascadedfour-switch H-bridge-based inverter and has several advantages,such as modular extension to any number of levels and redun-dancy [11]. However, the topology does not consider reductionin the number of components used. Other multilevel invertertopologies have been introduced in [12]–[15]. The multilevelinverter presented in [15] is based on symmetric topology anduses series/parallel connection of the dc voltage sources. Thistopology uses lower number of switches in comparison with thesymmetric CHB multilevel inverter. The topologies presentedin [12] and [13] consider reduction in the components. Thesetopologies are basically based on asymmetric topologies; hence,the used dc voltage sources have different values. However, thenumber of switching devices still remains high in these topolo-gies. A nine-level active NPC inverter has been presented in [16]which is the modification of the standard active NPC converter.Nami et al. [17] present a hybrid multilevel inverter using theCHB and the diode-clamped topology.

This paper proposes a new multilevel inverter topology usingseries-connected submultilevel inverters. The proposed multi-level inverter uses reduced number of switches. Initially, theproposed submultilevel inverter is described and then the seriesconnection of them to form a multilevel inverter is discussed.The optimal structures of the proposed multilevel inverter re-garding several factors (e.g., number of switches, number of dc

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626 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 28, NO. 2, FEBRUARY 2013

Fig. 1. Proposed generalized submultilevel inverter.

voltage sources, standing voltage on the switches, etc.) are alsoobtained. The power loss of the proposed topology is calcu-lated. Afterward, the proposed multilevel inverter is comparedwith other multilevel inverter topologies considering the num-ber of switches. A design example is then given which is usedfor simulation and experimental studies.

II. PROPOSED GENERALIZED MULTILEVEL INVERTER

A. Proposed Submultilevel Inverter

Fig. 1 shows the proposed submultilevel inverter. As depictedin Fig. 1, the topology consists of n dc voltage sources. In gen-eral, the dc voltage sources can have different values. However,in order to have equal voltage steps, they are considered to bethe same and equal to Vdc . Each submultilevel inverter consistsof n + 2 switches. Some of the switches are unidirectional andthe others are bidirectional. The unidirectional switches consistof an insulated gate bipolar transistor (IGBT) with an antipar-allel diode. The switches S1 , S ′

1 , S(n+2)/2 , and S ′(n+2)/2 are

unidirectional and the other switches are bidirectional; hence,they have to withstand both positive and negative voltages. Forinstance, when S(n+2)/2 is turned ON, the voltage Vdc is on theswitch Sn/2 , and if the switch S(n−2)/2 is turned ON, the volt-age equal to −Vdc is on the switch Sn/2 . The same conditionsare valid for the other switches. Therefore, the switches have towithstand both positive and negative voltages. In addition, theswitches have to conduct backward current that is as a result ofinductive characteristic of the load. It can be concluded that theswitches must be bidirectional. There are several circuit config-urations for bidirectional switches. In this study, the commonemitter topology is used as it needs one gate driver for a switch.Considering the types of the switches, 2n IGBTs are required inthe proposed submultilevel inverter. It is worth mentioning thatthe number of the antiparallel diodes is equal to the number ofIGBTs.

The proposed submultilevel inverter can only generate zeroand positive voltage levels. The zero output voltage is obtainedwhen the switches S1 and S ′

1 are turned ON simultaneously.The other voltage levels are generated by proper switching be-tween the switches. Table I shows the states of the switches foreach output voltage value. In this table, 1 means that the cor-responding switch is turned ON and 0 indicates the OFF state.

TABLE IOUTPUT VOLTAGES FOR STATES OF SWITCHES

Considering Fig. 1, for each value of the output voltage of sub-multilevel inverter, two switches must be turned ON, one fromthe upper switches and the other from the lower switches. Forexample, to get output voltage of Vdc , the switches S ′

1 and S2 areturned ON. In order to obtain the output voltage of (n − 1)Vdc ,the switches Sn/2 and S ′

(n+2)/2 should be turned ON.Considering Fig. 1, the following equations can be written:

Nswitch,sub ={

2, for n = 1

(n + 2), for n ≥ 2(1)

Ndriver,sub = Nswitch,sub (2)

NIGBT ,sub = 2n (3)

Nsource,sub = n (4)

where, Nswitch,sub , Ndriver,sub , NIGBT ,sub , and Nsource,sub arethe number of switches, number of switches drivers in one sub-multilevel inverter, number of IGBTs in one submultilevel in-verter, and number of dc sources in one submultilevel inverter,respectively.

For the proposed typical submultilevel inverter (see Fig. 1),the standing voltage on the switches is calculated. A switch ex-periences different off-state voltages in different switching com-binations. Among these off-state voltages, the highest voltage isconsidered to be the standing voltage of the switch. This can be acriterion for voltage rating of the switch. For example, in Fig. 1,the switch S1 experiences the maximum off-state voltage whenthe switch S(n+2)/2 is turned ON that is equal to (n/2)Vdc . Forthe switch S2 , the standing voltage is (n/2 − 1)Vdc . For theswitches S ′

1 and S ′2 , the standing voltage is equal to (n/2)Vdc

and (n/2 − 1)Vdc , respectively. This calculation can be donefor any switch in the submultilevel inverter. The standing volt-age for the submultilevel inverter is sum of all standing voltageon the switches in their off state [12]. For a submultilevel in-verter including n dc voltage sources, the standing voltage onthe switches depends on n and whether it is odd or even. Fordifferent n, the standing voltage on the switches of ith submul-tilevel inverter (Vstand,i) can be obtained by (5), shown at thebottom of the next page.

B. Proposed Generalized Multilevel Inverter

The proposed submultilevel inverters can be connected inseries to achieve the desired voltage and number of voltage

KANGARLU AND BABAEI: GENERALIZED CASCADED MULTILEVEL INVERTER 627

Fig. 2. Proposed general multilevel inverter using series connection of mproposed submultilevel inverters, each one has n dc voltage sources.

levels. Fig. 2 shows m submultilevel inverters in series. Eachsubmultilevel inverter has n dc voltage source. The dc voltagesources in each submultilevel inverter are equal.

The output voltage of the submultilevel inverters (and seriesconnection of them) is always positive or zero. To operate as aninverter, it is necessary to change the voltage polarity in everyhalf cycle. For this purpose, an H-bridge inverter is added to theoutput of the series connected submultilevel inverters.

It is important to note that the switches of the H-bridge mustwithstand higher voltage. This should be considered in the de-sign of the inverter. However, these switches are turned ON andOFF once during a fundamental cycle. So, these switches wouldbe high-voltage low-frequency switches.

Considering that the multilevel inverter shown in Fig. 2 in-cludes m submultilevel inverter (using (1)–(4) and consideringthe H-bridge part), the following equations can be written:

Nswitch ={

2m + 4, for n = 1

m · (n + 2) + 4, for n ≥ 2(6)

Ndriver = Nswitch (7)

NIGBT = 2mn + 4 (8)

Nsource = mn (9)

where Nswitch , Ndriver , NIGBT , and Nsource are the number ofswitches, number of switches drivers (which is equal to numberof switches), number of IGBTs, and total number of dc sources,respectively.

Considering (6) and (8), in general, the number of IGBTs isnot equal to the number of switches in the proposed multilevelinverter; hence, some of the switches are bidirectional (whichis considered as one switch) and consist of two IGBTs. Theproposed topology can be extended to three-phase systems usingthree single-phase units. Like the other multilevel converters, theswitches cannot be shared between the phases, and therefore,three single-phase structures should be used. In the extensionof the proposed topology to the three-phase systems withoutusing transformer, attention should be paid that the dc voltagesources in the different phases must be independent (isolated)so that the load can be star/delta connected. It is very importantto note that also in the well-known CHB topology (extended tothree-phase), independent dc voltage sources are required fordifferent phases [18]. Therefore, from this point of view, theproposed topology acts as like as the CHB topology.

Two conditions can be considered regarding the value of thedc voltage sources used in the proposed multilevel inverter; allof them can be equal leading to a symmetric topology or theirvalues can be different leading to asymmetric topology. Thesetwo conditions are discussed as follows.

1) Proposed Symmetric Multilevel Inverter: For the sym-metric multilevel inverter, all of the dc voltage sources are con-sidered to be equal. Therefore, the following equations can bewritten for the symmetric topology:

Vdc,1 = Vdc,2 = · · · = Vdc,m (10)

Nlevel = 2mn + 1 (11)

where Nlevel is the number of output voltage levels.Since in the case of the symmetric topology the cascaded

submultilevel inverters have the same condition, the following

Vstand,i =

⎧⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎨⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎪⎩

2

((n −1 )

4 −1)

∑k=0

(n − 1

2− k

)Vdc,i + 2

( n + 12 −1)/2∑k=0

(n + 1

2− k

)Vdc,i +

n − 14

Vdc,i =(

3n2

8+ n +

58

)Vdc,i

if n is odd andn − 1

2is even

2( n −1

2 −1)/2∑k=0

(n − 1

2− k

)Vdc,i + 2

( n + 14 −1)∑k=0

(n + 1

2− k

)Vdc,i +

n + 14

Vdc,i =(

3n2

8+ n +

58

)Vdc,i

if n is odd andn − 1

2is odd

4( n

2 −1)/2∑k=0

(n

2− k

)Vdc,i =

(3n2

8+ n +

12

)Vdc,i , if n is even and

n

2is odd

4( n

4 −1)∑k=0

(n

2− k

)Vdc,i +

n

2Vdc,i =

(3n2

8+ n

)Vdc,i if n is even and

n

2is even

(5)


relations can be expressed regarding the standing voltage on theswitches:

Vstand,1 = Vstand,2 = · · · = Vstand,m (12)

Vstand,total = m · Vstand,1 + 4mnVdc,1 (13)

where Vstand,total is the total standing voltage on the switchesof the multilevel inverter.

Using (11), m is obtained as follows:

m =(

Nlevel − 12n

)(14)

From (13) and (14), the following equation is obtained:

Vstand,total =(

Nlevel − 12

)·(

Vstand,1

n+ 4Vdc,1

). (15)

2) Proposed Asymmetric Multilevel Inverter: For the asym-metric topology, the value of the dc voltage sources is differentfrom a submultilevel inverter to another. In other words, if the dcsources of the first submultilevel inverter is Vdc,1 , the dc sourcesof the second submultilevel inverter is Vdc,2 . To get maximumnumber of level for the output voltage, there must be no redun-dancy. This is achieved when the value of the dc voltage sourcesin submultilevel inverters have the following relation:

Vdc,2 = (n + 1) · Vdc,1

Vdc,3 = (n+1)Vdc,1 +nVdc,2 = (n+1)Vdc,1 + n(n + 1)Vdc,1

= (n + 1)(n + 1)Vdc,1 = (n + 1)2Vdc,1 . (16)

Therefore, in general, the following relation should be validfor the dc sources of the submultilevel inverters:

Vdc,i = (n + 1)i−1 · Vdc,1 , i = 1, 2, 3, . . . , m (17)

where Vdc,i is the value of the dc sources in the ith submultilevelinverter.

The maximum value of the output voltage (sum of all dcvoltage sources) for the proposed asymmetric topology can beobtained as follows:

Vo,max = n

m∑i=1

Vdc,i . (18)

Using (17) and (18), the maximum value of the output voltagecan be written as

Vo,max = [(n + 1)m − 1]Vdc,1 . (19)

With the aforementioned arrangement of the dc voltagesources, the number of voltage levels will be equal to

Nlevel = 2(n + 1)m − 1. (20)

For the asymmetric topology, the total standing voltage ofthe switches (Vstand,total) is sum of standing voltages on theswitches of the submultilevel inverters (

∑mi=1 Vstand,i) and

also the standing voltage on the switches of the H-bridge part(4Vo,max ). Therefore, it can be written as follows:

Vstand,total =m∑

i=1

Vstand,i + 4Vo,max . (21)

Using (5), (17), (19), and (21), the total standing voltage ofthe switches can be written as follows:

Vstand,total =[(n + 1)m − 1

n

]

· Vstand,1 + 4[(n + 1)m − 1] · Vdc,1 . (22)

Using (20) and (22), the total standing voltage in terms ofnumber of output voltage level and n can be expressed asfollows:

Vstand,total =(

Nlevel − 12

)·(

Vstand,1

n+ 4Vdc,1

). (23)

C. Optimal Structures

In this section, the aim is to determine the optimal structuresconsidering different aspects. For the proposed multilevel in-verter, there are two design parameters. The first parameter isthe number of dc sources in each submultilevel inverter n andthe other is the number of series connected submultilevel in-verters, m. Both m and n affect maximum value of the outputvoltage. However, one of them can be used as a parameter fortopology optimization and the other should be left to meet thedesired maximum value of the output voltage (output voltagerating of the multilevel inverter). Here, m is used to meet therequired nominal voltage. Therefore, n is used as a variableto determine the optimal structures. In the following, the op-timal structures are discussed for the proposed symmetric andasymmetric multilevel inverters.

1) Optimal Structures of the Symmetric Topology: The aimis to determine the parameter n in order to use minimum numberof IGBTs for a specific number of levels. Using (8) and (11),NIGBT can be written as follows:

NIGBT = Nlevel + 3. (24)

The aforementioned equation shows that for a specific valueof the number of levels, the number of IGBTs is independent ofn and it is constant. Therefore, variation of the parameter n doesnot affect the number of IGBTs. The same result is obtained forthe case in which the aim is to have maximum number of voltagelevels for a given number of IGBTs.

Another aspect for optimization of the topology can be usingthe minimum number of gate driver circuits for a constant num-ber of voltage levels. Using (6), (7), and (11), the number of thegate drivers (and its normalization) can be written as follows:

Ndriver =

⎧⎨⎩

(Nlevel − 1) + 4, for n = 1

n + 22n

(Nlevel − 1) + 4, for n ≥ 2

Normalized Ndriver =Ndriver − 4Nlevel − 1

=

⎧⎨⎩

1, for n = 1

n + 22n

, for n ≥ 2.

(25)

Fig. 3 shows variation of the normalized value of the numberof drivers versus n for a given number of voltage levels. Thefigure indicates that as n increases, the number of required


Fig. 3. Normalized Ndriver and normalized total standing voltage on theswitches versus n for the symmetric topology.

gate driver circuits decreases. Therefore, higher n gives bettertopology from the viewpoint of number of gate drivers.

Standing voltage on the switches is the other factor whichis considered for optimization of the topology. The aim is todetermine n in a way that the total standing voltage is minimizedfor a given number of voltage levels. Using (15), the followingequation is obtained:

Normalized Vstand,total =Vstand,total

(Nlevel − 1) · Vdc,1− 2 =

Vstand,1

2nVdc,1.

(26)Fig. 3 also shows the variation of the normalized total standing

voltage on the switches versus n. It is clear from the figure thatthe standing voltage on the switches is minimum for both n = 1and n = 2. The higher values of n lead to a topology with higherstanding voltage. In other words, the topology with n = 1 andn = 2 give the best topology from the viewpoint of standingvoltage.

From the previous discussion, it can be concluded that thevalue of n does not affect the number of IGBTs. However, asn goes up (higher than 2), the number of gate drivers decreasesand, on the contrary, the standing voltage increases. This impliesthat a tradeoff may be considered between the number of gatedrivers and standing voltage. For instance, n = 3 can be acandidate for the better topology in the symmetric condition.

2) Optimal Structures of the Asymmetric Topology: The firstoptimal structure is to determine n to obtain the maximum volt-age level for a constant number of switches (or driver circuits).

Using (6) and (20), the number of voltage levels in terms ofnumber of switches is as follows:

Nlevel =

⎧⎨⎩

2(2)N sw i t ch −4

2 − 1, for n = 1

2(n + 1)N sw i t ch −4

(n + 2 ) − 1, for n ≥ 2

=

⎧⎨⎩

2(212 )N sw i t ch −4 − 1, for n = 1

2[(n + 1)

1(n + 2 )

](N sw i t ch −4) − 1, for n ≥ 2.

(27)

In (27), the number of switches is considered as a constant.Therefore, the number of voltage levels is maximized for suchan n that maximizes the following term:

D =

{2

12 , for n = 1

(n + 1)1

(n + 2 ) , for n ≥ 2.(28)

Fig. 4 shows the variation of D versus n. As the figure indi-cates, n = 1 gives the optimal structure from the viewpoint ofnumber of switches.

Fig. 4. Variation of D, (29), 2(n + 1)1/2n , and n/ ln(n + 1) versus n.

Similarly, another optimal structure can be obtained for mini-mizing the number of switches for a constant number of voltagelevels. In this case, using (27), the following equation can bewritten:

Nswitch − 4ln

(N l e v e l−4

2

) =

⎧⎪⎪⎨⎪⎪⎩

2ln 2

, for n = 1

(n + 2)ln(n + 1)

, for n ≥ 2.

(29)

The variation of (29) versus n is also depicted in Fig. 4. It isclear that n = 1 gives again the optimal structure.

Considering (7), the number of gate drivers is equal to thenumber of switches. Therefore, n = 1 also gives the optimalstructure from the viewpoint of minimum gate drivers.

In the previous analysis, the number of switches was consid-ered as a criterion for determining the optimal structures. Asmentioned before, the number of switches is not equal to thenumber of IGBTs. If the number of IGBTs is used as a criterion,the results will be the same.

Considering (8) and (20), the number of voltage levels as afunction of n for a constant number of IGBTs is as follows:

Nlevel = 2(n + 1)N IG B T −4

2 n − 1

= 2[(n + 1)

12 n

](N IG B T −4) − 1. (30)

Taking into account that the number of IGBTs has been con-sidered to be constant, in (30), the number of voltage levels willbe maximum if the term 2(n + 1)1/2n is maximum.

Fig. 4 also shows the variation of 2(n + 1)1/2n versus n. Asthis figure shows, the number of levels decreases as n increases.Therefore, the maximum number of voltage level for a constantnumber of IGBTs is obtained when n is equal to 1. The sameresult can be obtained for the minimum number of IGBTs for aconstant number of voltage levels.

The number of the dc voltage sources Nsource is the othervariable which is used to obtain optimal topology. The aim isto minimize the number of required dc voltage sources for aspecific number of voltage levels. Using (9) and (20), Nsourcecan be written as follows in terms of the number of outputvoltage levels and the number of dc voltage sources in eachsubmultilevel inverter:

Nsource =n

ln(n + 1)· ln

(Nlevel + 1

2

). (31)


The aforementioned equation gets its minimum value whenthe term n/ ln(n + 1) is minimum. Variation of this term versusn is also shown in Fig. 4. It is clear that the minimum value isachieved when n = 1.

To obtain the optimal structure from viewpoint of standingvoltage on the switches, using (23), the normalized total standingvoltage is obtained as follows:

Normalized Vstand,total =Vstand,total

(Nlevel − 1) · Vdc,1− 2 =

Vstand,1

2nVdc,1.

(32)This equation is same as (26). Therefore, for the asymmetric

topology (like the symmetric topology), the optimal structureconsidering the total standing voltage on the switches is achievedfor n = 1 and n = 2. It is important to note that the standingvoltage on the switches is the same for these two values of n.This is clear from Fig. 1 for n = 1 and n = 2.

It can be concluded from the previous analysis that the optimalstructure (for the asymmetric topology) from the viewpoint ofthe number of used switches, IGBTs, dc voltage sources, andthe value of the standing voltage on the switches is obtainedwhen n is 1.

III. CALCULATION OF LOSSES

Typically, two kinds of losses are associated with power elec-tronic converters. The conduction losses are caused by equiv-alent resistance and the on-state voltage drop of the semicon-ductor devices. The switching losses are caused by nonidealoperation of switches. Calculation of the losses of the proposedmultilevel inverter is discussed as follows.

A. Conduction Losses

In order to calculate the conduction losses, first conductionlosses of a typical power transistor and diode are calculated; thenthey are developed to the multilevel inverter. The instantaneousconduction losses of a transistor (pc,T (t)) and diode (pc,D (t))can be written as follows:

pc,T (t) = [VT + RT iβ (t)] i(t) (33)

pc,D (t) = [VD + RD i(t)] i(t) (34)

where VT and VD are the on-state voltage of the transistor anddiode, respectively. RT and RD are the equivalent resistance ofthe transistor and diode, respectively, and β is a constant relatedto the specification of the transistor.

In the proposed submultilevel inverter, consider that there arex(t) transistors and y(t) diodes in the current path in any instantof time. The value of x(t) and y(t) depends on the output voltagelevel and operating conditions (mainly direction of the current).Considering Fig. 1, depending on the voltage level and currentdirection, in the proposed submultilevel inverter there might betwo diodes, two transistors, one transistor and one diode, twodiodes and one transistor, two transistors and one diode, andtwo transistors and two diodes in the current path. Therefore,using (33) and (34), the average conduction power loss of the

proposed submultilevel inverter can be calculated as follows:

Pc,sub,j =1π

∫ π

0

[(x(t)VT ,j + y(t)VD,j

+x(t)RT ,j iβ (t) + y(t)RD,j i(t)

)i(t)

]

× d(ωt). (35)

The specifications of the switches used in different submul-tilevel inverters may be different. Therefore, the index j in theaforementioned equation is used in order to refer to the jth sub-multilevel inverter. As the losses are calculated for the typicaljth submultilevel inverter, it can be extended to other cascadedsubmultilevel inverters.

As the conduction power loss of the cascaded submultilevelinverters are calculated one by one, they are added together toobtain the total conduction power loss Pc, sub of the cascadedsubmultilevel inverters:

Pc,sub =m∑

j=1

Pc,sub,j . (36)

In the power loss calculated previously, the H-bridge part ofthe proposed multilevel inverter has not been considered. If thepower factor angle is ϕ, then in every half cycle, the diodes andtransistors of the H-bridge part conduct for time interval corre-sponding to ϕ and π−ϕ, respectively. If the output current isconsidered to be sinusoidal as i(t) = Im sin(ωt), the conductionpower loss of the H-bridge can be obtained as follows:

Pc,H =1π

[∫ φ

02pc,D (t)d(ωt) +

∫ π

φ

2pc,T (t)d(ωt)]

=2π

[VD,H Im (1 − cos φ) +

RD,H I2m

4(2φ − sin(2φ))

+ VT ,H Im (1 + cos φ)

+ RT ,H Iβ+1m

∫ π

φ

sinβ+1(ωt)d(ωt)]. (37)

In the aforementioned equation, the index H indicates theparameters related to the H-bridge.

The total conduction loss of the proposed multilevel inverteris obtained as follows:

Pc = Pc,sub + Pc,H . (38)

B. Switching Losses

The switching losses are calculated for a typical switch, andthen, the results are extended for the proposed multilevel in-verter. For this calculation, the linear approximation of the volt-age and current during switching period is used. Using this ap-proximation, energy loss during the turn-off period of a switchcan be obtained as follows:

Eoff ,k

=∫ to f f

0v(t)i(t)dt =

∫ to f f

0

[(Vsw,k

tofft

) (− I

toff(t − toff )

)]dt

=16Vsw,k I toff (39)


Fig. 5. (a) Number of IGBTs and (b) number of driver circuits versus numberof levels for the symmetric topologies.

where Eoff ,k is the turn-off loss of the switch k, toff is the turn-off time of the switch, I is the current through the switch beforeturning OFF, and Vsw,k is the off-state voltage on the switch.

The turn-on loss of the switch can be calculated as follows:

Eon,k =∫ to n

0v(t)i(t)dt

=∫ to n

0

[(Vsw,k

tont

)(− I ′

ton(t − ton)

)]dt

=16Vsw,k I ′ ton (40)

where Eon,k is the turn-on loss of the switch k, ton is the turn-ontime of the switch, and I ′ is the current through the switch afterturning ON.

The switching losses depend on the number of switchingtransitions. Therefore, it depends on the modulation method.Generally, the average switching power loss can be written asfollows:

Psw = 2f

⎡⎣N sw i t ch∑

k=1

⎛⎝No n , k∑

i=1

Eon,k i +No f f , k∑i=1

Eoff ,k i

⎞⎠

⎤⎦ (41)

where f is the fundamental frequency, Non,k and Noff ,k arethe number of turning ON and OFF the switch k during a halffundamental cycle. Also, Eon,k i is the energy loss of the switchk during the ith turning ON and Eoff ,k i is the energy loss of theswitch k during the ith turning OFF.

Using (38) and (41), the total losses of the multilevel inverterwill be

PLoss = Pc + Psw . (42)

IV. COMPARISON OF THE PROPOSED TOPOLOGY

WITH THE OTHER TOPOLOGIES

A. Symmetric Topology

Fig. 5(a) shows the number of IGBTs versus the numberof voltage levels in different topologies. As the figure shows,for any specific value of Nlevel , the proposed topology useslower number of IGBTs in comparison with [15] and CHB. Therequired number of gate driver circuits in the aforementionedtopologies versus Nlevel is shown in Fig. 5(b). The figure clearlyshows that the proposed topology uses the least Ndriver . Stand-ing voltage on the switches of the topologies is presented inFig. 6. The figure shows that the CHB has the best characteristicfrom the viewpoint of standing voltage on the switches and the

Fig. 6. Standing voltage on the switches versus number of levels for thesymmetric topologies.

Fig. 7. (a) Per-unit conduction power loss and (b) per-unit switching powerloss versus number of levels for the symmetric topologies (RT = 0.15 Ω, VT =2.5 V, RD = 0.1 Ω, VD = 1.5 V, n = 3, ton = toff = 2 μs).

proposed topology is better than [15] in terms of standing voltageon the switches. Fig. 7(a) and (b) shows the calculated per-unitconduction and switching power loss of the topologies, respec-tively. To draw the figures, n is considered to be 3 (n = 3) andm varies as the number of levels varies. Also, for all of the tran-sistors, the on-state resistance and voltage drop are consideredto be 0.15 Ω (RT = 0.15 Ω) and 2.5 V (VT = 2.5 V), respec-tively. The on-state resistance and voltage drop of the diodesare assumed to be 0.1 Ω (RD = 0.1 Ω) and 1.5 (VD = 1.5 V),respectively. The on-time ton and off-time toff of the switchesis assumed 2 μs. Each dc voltage source has the value of 100 V.The resistance of the load is 45 Ω and its inductance is 55 mH sothat ϕ = 21◦. It is important to note that the base value for theper-unit losses is the converter rated output power. As Fig. 7(a)shows, the proposed topology and that of [15] have lower con-duction loss than the CHB. Also, the conduction power loss ofthe proposed topology is lower than that of [15]. This result waspredictable since the number of semiconductor devices in thecurrent path in any instant of time for the proposed topologyis lower than that of the other two topologies. However, thisnumber is close for the proposed topology and [15]. Accordingto Fig. 7(b), switching power loss of the proposed topology islower than that of [15]. However, the switching power loss ofthe proposed topology is higher than that of CHB. It is worthmentioning that the conduction losses are the major part of thelosses.

Despite the number of IGBTs, in the proposed symmetrictopology, variety of the switches in terms of the voltage rat-ings is higher than the symmetric CHB topology. This can beconsidered a disadvantage for the proposed symmetric topol-ogy when comparing with the symmetric CHB topology. In theproposed symmetric topology with n = 3, three different kindsof switches in terms of voltage ratings are required. However,the proposed topology considerable reduces the total number ofswitches.


Fig. 8. Number of IGBTs versus the number of output voltage level in thesubmultilevel inverters.

Fig. 9. Standing voltage on the switches versus the number of output voltagelevel in the submultilevel inverters.

Fig. 10. Number of IGBTs versus the number of output voltage levels.

B. Asymmetric Topology

The proposed topology in this paper is compared with thetopologies presented in [12] and [13] and the asymmetric CHBtopology. Initially, the proposed submultilevel inverter (seeFig. 1) is compared with the submultilevel inverters proposedin [12] and [13]. It is noticeable that the submultilevel inverteris called as basic unit in [12] and [13]. The number of IGBTsversus the number of voltage levels is shown in Fig. 8 for theproposed submultilevel inverter and the basic units presentedin [12] and [13]. As shown in Fig. 8, the proposed submulti-level inverter uses lower number of IGBTs in comparison withthe others. Fig. 9 shows the sum of the standing voltage on theswitches for the submultilevel inverters. As shown in the figure,the proposed submultilevel inverter has a better condition fromthe viewpoint of standing voltage on the switches.

In the previous comparison, the submultilevel inverters havebeen compared together. Here, the aim is to compare the multi-level inverters resulted from series connection of the submulti-level inverters. For the comparison purpose, the required numberof IGBTs for each number of output voltage levels is depictedin Fig. 10. It can be seen from this figure that the proposedtopology uses a considerable lower number of IGBTs for anyspecific number of output voltage level in comparison with thetopologies presented in [12] and [13] and the asymmetric CHBtopology. For the topology presented in [13], the optimal topol-ogy derived in [19] is used for comparison.

Fig. 11. Sum of the standing voltage on the switches for different topologies.

Fig. 12. (a) Per-unit conduction losses and (b) per-unit switching losses forthe proposed asymmetric topology and the asymmetric CHB topology (RT =0.15 Ω, VT = 2.5 V, RD = 0.1 Ω, VD = 1.5 V, n = 1, ton = toff = 2 μs).

The other aspect of comparison is the standing voltage onthe switches. Fig. 11 shows the sum of standing voltage on theswitches for different topologies. The standing voltage is statedin per unit where the base value is the value of the dc voltagesource in the first submultilevel inverter (i.e., Vdc,1 = 1 p.u.). Asshown in the figure, the standing voltage on the switches of theproposed topology is lower than the topology presented in [12]and [13]. However, the standing voltage of the CHB topologyis lower than all of the topologies.

Fig. 12(a) and (b), respectively, shows the per-unit conductionand switching losses of the proposed topology and that of theasymmetric CHB topology. The characteristic of the switchesand the load data is the same as the symmetric one given inthe previous section. The base value for per unit is the ratedconverter output power. In this case, the value of n is consid-ered to be 1. Fig. 12(a) shows that the proposed topology haslower conduction losses due to lower number of semiconductordevices that are in the current path in any instant of time. Also,according to Fig. 12(b), the switching power loss of the proposedtopology is slightly lower than that of the asymmetric CHB. Thetopologies in [12] and [13] are not considered in this comparisonsince they need snubber circuits for their bidirectional switches,which makes the calculation of their losses different. Also, thesnubber circuit will increase the losses of [12] and [13].

The variety of the switches in the proposed asymmetric topol-ogy (with n = 1) and the asymmetric CHB topology is shownin Fig. 13. The variety of the switches indicates requirementfor switches with different voltage ratings. As shown in thefigure, both of the topologies need switches with different volt-age ratings. However, for any number of levels, the proposedasymmetric topology needs one more different switch than theasymmetric topology. Therefore, the requirement for differentswitches is almost equal for both of the topologies.


Fig. 13. Variety of the switches versus the number of output voltage levels.

V. MEDIUM-VOLTAGE APPLICATION CONSIDERATIONS

Theoretically, the proposed topologies can be designed forany voltage level. However, practically there are limitationswhen applying the topologies in medium- and high-voltage ap-plications. Considering the switches used in the H-bridge partof the proposed topologies (T1 − T4), these switches must beable to tolerate a voltage equal to the rated output voltage ofthe multilevel inverter. These switches turn ON and OFF onceduring a fundamental cycle. Also, they are switched in zero volt-age condition; hence, the switches of the submultilevel invertersprovide zero voltage level when the switches operate. Besidesthese facts, the four mentioned switches restrict the applicationof the proposed topologies for high voltage. It is very importantto note that this problem is not just for the proposed topology.The topologies in which a high-voltage H-bridge is used (e.g.,the topologies presented in [12], [15], and [20]) have the sameproblem. In these topologies, the switches of the high-voltageH-bridge have to tolerate a voltage equal to sum of all dc voltagesources. In other words, in the proposed topology and that of,e.g., [12], [15], and [20], there are four switches that must beable to operate in the rated voltage of the inverter. As a result, it isnecessary to determine the voltage level in which the applicationof the proposed topology is advantageous. One main criterion isto avoid series connection of the switches to form a high-voltageswitch, otherwise the proposed topology will not show its ad-vantages. Assume that the highest voltage common commercialIGBT has a voltage rating equal to VIGBT ,max . Then, the max-imum operating voltage (three-phase line–line rms voltage) ofthe proposed topology can be written as follows:

Vrated =

√32· VIGBT ,max

α(43)

where Vrated is the rated three-phase line–line rms voltage ofthe proposed multilevel inverter and α (safety factor) is a factorto ensure the safe operation of the IGBT in practice. It may beconsidered about α = 1.7.

If (43) is satisfied, then the series connection of the switcheswill not be required. In other words, (43) can be used to de-termine the voltage rating of the proposed topology based onthe availability of the IGBT or it can be used to determine thevoltage rating of the highest voltage IGBT required for a spe-cific rated voltage of the multilevel inverter. Two examples ofmedium-voltage design are given as follows.

For the first example, suppose that the highest volt-age commercially available IGBT voltage rating is 3300 V(VIGBT ,max = 3300 V). Using (43), the rated three-phase line–line voltage will be equal to about 2.3 kV. If the proposed

TABLE IITYPICAL IGBTS IN DIFFERENT VOLTAGE RATINGS

31-level asymmetric topology (with n = 1 as shown in Fig. 16)is considered, to produce such a voltage, the values of the dcsources will be 125.2, 250.4, 500.8, and 1001.6 V. Table IIshows an example of commercially common IGBT voltage rat-ings. Considering the commercial IGBTs and taking into ac-count Fig. 16, two 250-V IGBTs for switches S1 and S ′

1 , two600-V IGBTs for switches S2 and S ′

2 , two 1200-V IGBTs forswitches S3 and S ′

3 , two 1700-V IGBTs for switches S4 andS ′

4 , and four 3300-V IGBTs for switches T1 − T4 are requiredin the proposed topology. It is very important to note that al-though these switches are high-voltage switches, they operatein fundamental frequency and zero voltage condition. On theother hand, if the asymmetric CHB topology is considered, four250-V, four 600-V, four 1200-V, and four 1700-V IGBTs willbe required.

As another example of high-voltage, another design is con-sidered for three-phase 6-kV rms line–line voltage. So, the peakvoltage will be about 4.9 kV. Considering the 31-level inverter(see Fig. 16), the value of the dc voltage sources will be about327, 654, 1307, and 2612 V. Therefore, considering the voltagerating of the commercial IGBTs, the IGBTs with the voltage rat-ings of 600 V (for S1 and S ′

1), 1200 V (for S2 and S ′2), 2500 V

(for S3 and S ′3), and 4500 V (for S4 and S ′

4) can be used whichare available. For high-voltage operation, the switches may beconnected in series [21], [22], and for high-current applicationthey may be connected in parallel [21], [23]. However, specialattention should be paid to distribute the voltage on them equallyand synchronous operation of them. In order to equally distributevoltage on the switches, balancing resistors should be used [21],[24]. For the mentioned example, the switches T1 − T4 of theproposed topology will need series-connected IGBTs (each ofthe switches may require two 3300-V or two 4500-V IGBTs).Therefore, application of the proposed multilevel inverter in thisvoltage level is challenging (although it is possible). As a re-sult, it is recommended that (43) to be satisfied when using theproposed topology in medium-voltage applications.

Form the two examples discussed previously, it can be con-cluded that with today’s semiconductor technology, the pro-posed topology and the topologies presented in [12], [15],and [20] are not well suited for higher voltages since they usean H-bridge, the switches of which have to withstand a voltageequal to rated voltage of the multilevel inverter. Therefore, withthe existing IGBTs, they are recommended for low-voltage ap-plications. However, the semiconductor technology is progress-ing with a considerable rate. Some years back, IGBTs even withvoltage ratings presented in Table II (e.g., 3300 V, 4500 V) didnot exist. Considering the progressing trend of the semiconduc-tor technology, in future higher voltage IGBTs will be produced


Fig. 14. Thirteen-level inverter based on the proposed symmetric topologywith n = 3 and m = 2.

Fig. 15. Simulation results for the 13-level symmetric topology.

commercially. This will make the mentioned topologies suitablefor medium-voltage applications.

VI. SIMULATION AND EXPERIMENTAL RESULTS

This section deals with the simulation and experimental vali-dation of the proposed multilevel inverter topology. For the pro-posed symmetric multilevel inverter, only the simulation resultsare presented, but, for the asymmetric topology both simulationand experimental results are given.

For all of the studies, the load is an RL load with the valueof 45 Ω and 55 mH. The output voltage frequency is assumed50 Hz.

There are many control methods for multilevel inverter. It isnoticeable that the staircase control method is used in this pa-per [1]. The term staircase control method is used to state that inthis method, transition from one level of voltage to the next levelhappens once as shown in Fig. 15 (for example). This controlmethod tends to generate a staircase voltage which minimizesthe error with respect to the reference voltage. It is worth notingthat the calculation of optimal switching angles for differentgoals, such as elimination of the selected harmonics and mini-mizing total harmonic distortion (THD), is not the objective ofthis paper.

A. Symmetric Topology

Fig. 14 shows the 13-level inverter based on the proposedsymmetric multilevel inverter with n = 3. Six dc voltage sourceseach of them 100 V have been used so that the maximum outputvoltage will be 600 V. The number of IGBTs for a 13-levelinverter in the proposed topology is 16. For the same numberof voltage levels, the topology of [15] and CHB use 19 and 24IGBTs, respectively, which are higher than that of the proposedtopology.

Fig. 15 shows the load voltage and scaled load current ofthe 13-level inverter. As the figure shows, all of the expectedvoltage levels are generated at the output voltage. The loadvoltage is sine-waved current as a result of the RL load which

Fig. 16. Thirty-one-level inverter based on the proposed optimal structurewith n = 1 and m = 4 (used for simulations and experimentation).

operates as a low-pass filter for the current. The load current hasalso phase difference with the load voltage because of inductivecharacteristic of the load.

B. Asymmetric Topology

For the asymmetric topology, first a design example of theproposed multilevel inverter is given and then it is used forsimulation and experimental studies.

1) Design Example: The aim is to design a peak 150-V mul-tilevel inverter with minimum 30 levels of output voltage. Asdiscussed before, the proposed multilevel inverter is optimal forn = 1 from different points of view. In order the number ofoutput voltage level to be higher than its minimum (i.e., 30), thenumber of cascaded submultilevel inverters should be 4 (m =4). Therefore, a 31-level 150-V inverter based on the proposedgeneralized multilevel inverter regarding the optimal structureswill be as shown in Fig. 16 in which the values of the dc voltagesources are shown in the figure. The proposed 31-level inverterin Fig. 16 uses 12 IGBTs. The number of the dc sources is 4 withbinary increment. On the other hand, a 21-level inverter basedon the topology presented in [13] uses 20 IGBTs which is muchmore than the number of IGBTs in the proposed topology, and atthe same time, the number of output voltage level is lower thanthat of the proposed topology. A 17-level inverter based on [12]uses 16 IGBTs and 4 dc voltage sources. In comparison withthe proposed topology, shown in Fig. 16, the topology presentedin [12] uses more IGBTs, and at the same time, the number ofoutput voltage levels is considerably lower.

2) Simulation and Experimental Results: The validity of theproposed multilevel inverter is demonstrated with both simu-lation and experimental results. For the simulation and experi-mentation, the 31-level inverter shown in Fig. 16 is used. TheBUP306D-type IGBTs are used. Also the AT89C52 microcon-troller is used to prepare gate signals for the switches. TektronixTDS 2024B four-channel digital storage oscilloscope is used formeasurements in laboratory. Each switch has a driver circuit.The driver circuit used in this paper consists of an optoisolator,a Schmit trigger, and a buffer. For a switch in the inverter, anisolated driver circuit is required. The isolation is achieved us-ing optoisolators. The states of the switches in different voltagelevels have been stored in the microcontroller as a lookup ta-ble. The microcontroller provides the switching signals for thedriver circuits and the driver circuits drive the switches. In the


Fig. 17. Output voltage of each submultilevel inverter: from top to bottomtraces are first, second, third, and fourth submultilevel inverter output voltage,respectively.

Fig. 18. (Upper trace) Output voltage of cascaded submultilevel inverters.(Lower trace) Load voltage and scaled load current.

experimental prototype, the constant dc supplies existing in thelaboratory have been used as the dc voltage sources.

In order to generate the triggering signals for the switchesused in the inverter, the reference output voltage is comparedwith the available voltage levels. These levels are determinedby the available dc voltage sources and operation modes of theinverter. Then, the switches that generate the nearest voltagelevel to the reference output voltage are turned on. As an ex-ample, when the voltage level of 30 V (in Fig. 16) is nearest tothe reference output voltage, the switches S ′

1 , S′2 , S3 , and S4 are

turned ON and the other switches are turned OFF.Fig. 17 shows the output voltage of each submultilevel in-

verter shown in Fig. 16. Clearly, the output voltage of eachsubmultilevel inverter corresponds to its dc voltage sources.Considering the figure, the first submultilevel inverter operateswith the lowest voltage, but in return its operating frequencyis highest among the submultilevel inverters. Inversely, the lastsubmultilevel inverter operates with highest voltage and lowestfrequency. The switching frequency of the switches S1–S4 is1500, 720, 300, and 100 Hz, respectively.

Fig. 18 shows the output voltage of the cascaded submultilevelinverters, load voltage, and scaled load current. As shown in the

Fig. 19. Experimental results. From top to bottom, the traces are output voltageof cascaded submultilevel inverters, load voltage, and load current.

figure, the output voltage of the cascaded submultilevel invertersis always nonnegative. The polarity of the voltage is changedusing the H-bridge connected to the output of the submultilevelinverters. The load current is scaled to become visible in thesame frame with the load voltage.

In the test condition (R = 45 Ω, L = 55 mH, Vo,max =150 V), the power loss of the proposed multilevel inverter,shown in Fig. 16, is about 12 W. However, the power loss of theasymmetric CHB topology with the same conditions (with thesame value of voltage and load) is about 15.5 W. This can be asa result of the fact that in the proposed topology, less semicon-ductor devices are in the current path in any instant of time incomparison with the asymmetric CHB topology. In this condi-tion, output active power of the inverter is about 217 W. Also,the specification of the switches (their resistance and on-statevoltage) is as given in Section IV.

Fig. 19 shows the experimental results. The upper trace of thefigure shows the total output voltage of the cascaded submul-tilevel inverters. The middle trace shows the load voltage andthe lower trace shows the load current. The load voltage andcurrent THD is %1.44 and %0.2, respectively. The figures showa good correspondence with the simulation results. In practice,the switches are not ideal and they have voltage drop in theiron-state due to resistance and reverse on-state voltage of them.Therefore, the peak of the output voltage may not reach 150 Vbecause of some voltage drop on the switches.

VII. CONCLUSION

In this paper, initially, a submultilevel inverter has been pro-posed and then the cascaded submultilevel inverters have beenconsidered as a generalized multilevel inverter in both symmet-ric and asymmetric conditions. The number of the dc voltagesources in each submultilevel inverter is equal, but their val-ues are different from one submultilevel inverter to another.Therefore, the proposed multilevel inverter can be categorizedin asymmetric group. The optimal structures for the proposedmultilevel inverter were obtained considering several factorssuch as the number of switching devices, number of dc voltagesources, number of output voltage levels, standing voltage onthe switches etc. For the asymmetric topology, almost all of the


factors dictate that the number of dc voltage sources per sub-multilevel inverter should be 1. The comparison between theproposed topology and the topologies presented in [12], [13],and [15] and the CHB topologies has been presented consideringseveral factors. The simulation results of a 13-level symmetrictopology based on the proposed multilevel inverter have beenpresented. In the case of asymmetric topology, the simulationand experimental results have been presented for a 31-level in-verter based on the proposed optimal structure to validate theability of the proposed topology in generating of desired outputvoltage.

REFERENCES

[1] J. Rodriguez, J. S. Lai, and F. Z. Peng, “Multilevel inverters: A surveyof topologies, controls, and applications,” IEEE Trans. Ind. Electron.,vol. 49, no. 4, pp. 724–738, Aug. 2002.

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[4] A. A. Boora, A. Nami, F. Zare, A. Ghosh, and F. Blaabjerg, “Voltage-sharing converter to supply single-phase asymmetrical four-level diodeclamped inverter with high power factor loads,” IEEE Trans. PowerElectron., vol. 25, no. 10, pp. 2507–2520, Oct. 2010.

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Mohammad Farhadi Kangarlu (S’09) was born inKangarlu, East Azerbaijan, Iran, in 1987. He receivedthe B.S. and M.S. degrees (first class Hons.) both inelectrical power engineering from the University ofTabriz, Tabriz, Iran, in 2008 and 2010, respectively,where he is currently working toward the Ph.D. de-gree in electrical power engineering (power electron-ics and systems).

He is the author or coauthor of more than 25 jour-nal and conference papers and one book. He alsoholds seven patents in the area of power electronics.

His research interests include power electronic converters analysis and design,power quality, and custom power devices.

Dr. Farhadi Kangarlu received the Best Researcher Award of the East Azer-baijan Province in 2011. He also received the Distinguished Student Award ofthe University of Tabriz in 2007 and 2011.

Ebrahim Babaei (M’10) was born in Ahar, Iran,in 1970. He received the B.S. and M.S. degrees(first class Hons.) in electrical engineering from theDepartment of Engineering, University of Tabriz,Tabriz, Iran, in 1992 and 2001, respectively, where healso received the Ph.D. degree in electrical engineer-ing from the Department of Electrical and ComputerEngineering, in 2007.

In 2004, he joined the Faculty of Electrical andComputer Engineering, University of Tabriz. He wasan Assistant Professor from 2007 to 2011 and has

been an Associate Professor since 2011. He is the author of more than 140journal and conference papers. His current research interests include the anal-ysis and control of power electronic converters, matrix converters, multilevelconverters, flexible ac transmission systems devices, power system transients,and power system dynamics.

(36) (2013) (farhadi) (ieee trans power electron)

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