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A rch i t ec t u reThese devices use NAND Flash electrical and command interfaces. Data, commands,and addresses are multiplexed onto the same pins and received by I/O control circuits.The commands received at the I/O control circuits are latched by a command registerand are transferred to control logic circuits for generating internal signals to control de-vice operations. The addresses are latched by an address register and sent to a row de-coder to select a row address, or to a column decoder to select a column address.
Data is transferred to or from the NAND Flash memory array, byte by byte, through adata register and a cache register.
The NAND Flash memory array is programmed and read using page-based operationsand is erased using block-based operations. During normal page operations, the dataand cache registers act as a single register. During cache operations, the data and cacheregisters operate independently to increase data throughput.
The status register reports the status of die (LUN) operations.
F i g u re 14: N A N D F l ash D i e (LU N) F u nc t i o n a l B l ock D i a g r a m
Sta tus regist er
Command regist er
Vccq Vssq
CE#
CLE
N/A
ALE
RE# WP#
D Q[7:0]
Async
WE#
R/B#
CE#
CLE
D QS
ALE
W /R#WP#
D Q[7:0]
Sync
CLK
R/B#
Vcc Vss
Controllogic
Data Regist er
Cache Regist er
Ro
w D
ecod
e
Column Decode
N A ND FlashArray
Data regist er
Cache regist er
Ro
w D
ecod
e
Column decode
N A ND Flash array (2 planes)
A ddress regist erI/Ocontrol
Notes: 1. N/A: This signal is tri-st a ted w hen the asynchronous in terface is act ive .2. Some devices do no t include the synchronous in terface .
Micron Confiden tial and Proprie tary
32 G b , 64 G b , 128 G b , 256 G b A sy nch ro n o us/Sy nch ro n o us N A N DA rch i t ec t u re
PDF: 09005ae f83e0bed4M73A_32Gb_64Gb_128Gb_256Gb_AsyncSync_N A ND .pdf Rev. F 5/12 EN 23 Micron Technology, Inc. reserves the righ t to change products or speci f ica tions w ithout no tice .
© 2010 Micron Technology, Inc. A ll righ ts reserved .
Banks vs. Planes
PDF: 09005aef8331b189 / Source: 09005aef8331b1c4 Micron Technology, Inc., reserves the right to change products or speci f ications without notice .32gb_nand_mlc_l63a__2.fm - Rev. A 12/08 EN 15 ©2008 Micron Technology, Inc. A ll rights reserved .
32Gb, 64Gb, 128Gb: NAND FlashArray Organization
Micron Confidential and Proprietary Advance
Array Organization
Figure 8: Array Organization: 32Gb and 64Gb Devices
Note: For 64Gb devices, the 32Gb array organization shown here applies to each chip enable (CE# and CE2#).
Notes: 1. Block address concatenated with page address = actual page address. CAx = column address; PAx = page address; BAx = block address.
2. Column address 4313 (10D9h) is the maximum valid column address.3. Plane select bit:
0 = plane of even-numbered blocks1 = plane of odd-numbered blocks
Table 3: Array Addressing: 32Gb and 64Gb
Cycle I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 I/O0
First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA0Second LO W LO W LO W CA12 CA11 CA10 CA9 CA8Third BA73 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA8Fif th LO W LO W LO W LO W BA19 BA18 BA17 BA16
Cache register
Data register
4096 blocksper plane
8192 blocksper die
1 block 1 block
I/O0
I/O7
1 page = (4K + 218 bytes)
1 block = (4K + 218) bytes x 128 pages = (512K + 27K) bytes
1 plane = (512K + 27K) bytes x 4096 blocks = 17,256Mb
1 die = 17,256Mb x 2 planes = 34,512Mb
Plane of even-numbered blocks
(0, 2, 4, 6, ..., 8188, 8190)
Plane of odd-numbered blocks
(1, 3, 5, 7, ..., 4095, 8191)
2184096 218
4314 bytes4314 bytes
2182184096
4096
4096
Banks vs. Planes
DISK & FLASH
Disk
Chapter 17 THE PHYSICAL LAYER 621
RAMAC to the washing machine-size disk drives of the 1970s and 1980s and, fi nally, to the palm-size disk drives of the 1990s and today. Today’s disk drives all have their working components sealed inside an alu-minum case, with an electronics card attached to one side. The components must be sealed because, with the very low fl ying height of the head over the disk surface, just a tiny amount of contaminant can spell disaster for the drive.
This section very briefl y describes the various mechanical and magnetic components of a hard disk drive [Sierra 1990, Wang & Taratorin 1999, Ashar 1997, Mee & Daniel 1996, Mamun et al. 2006, Schwaderer & Wilson 1996]. The desirable characteristics of each of these components are discussed. The major physi-cal components are illustrated in Figure 17.8, which shows an exposed view of a disk drive with the cover removed. The principles of operation for most com-ponents can be fully explained within this chapter. For the servo system, additional information will be required, and it will be described in Chapter 18.
17.2.1 DisksThe recording medium for hard disk drives is
basically a very thin layer of magnetically hard mate-rial on a rigid circular substrate [Mee & Daniel 1996]. A fl exible substrate is used for a fl exible, or fl oppy, disk. Some of the desirable characteristics of record-ing media are the following:
Thin substrate so that it takes up less spaceLight substrate so that it requires less power to spinHigh rigidity for low mechanical resonance and distortion under high rotational speed; needed for servo to accurately follow very narrow tracksFlat and smooth surface to allow the head to fl y very low without ever making contact with the disk surfaceHigh coercivity (Hc) so that the magnetic recording is stable, even as areal density is increased
••
•
•
•
Actuator
Flex cable
Load/UnloadRamp
Disk
Spindle & Motor
Head Disk Assembly
Magnet structureof Voice
Coil Motor
Case
FIGURE 17.8: Major components of today’s typical disk drive. The cover of a Hitachi Global Storage Technologies UltraStarTM 15K147 is removed to show the inside of a head-disk assembly. The actuator is parked in the load/unload ramp.
ch17_P379751.indd 621ch17_P379751.indd 621 8/8/07 3:55:16 PM8/8/07 3:55:16 PM
Flash SSD
Rotating Disks vs. SSDsMain take-aways
Forget everything you knew about rotating disks. SSDs are different
SSDs are complex software systems
One size doesn’t fit all
Rotating Disks vs. SSDsMain take-aways
Forget everything you knew about rotating disks. SSDs are different
SSDs are complex software systems
One size doesn’t fit all
Magnet structure of
voice coil motor
Spindle & Motor
Disk
Actuator
Flash
Memory Arrays
Load / Unload
Mechanism
(a) HDD (b) SSD
Flash memory arrays
Circuit board
ATA Interface
Disk Issues
• Keeping ahead of Flash in price-per-GB is difficult (and expensive)
• Dealing with timing in a polar-coordinate system is non-trivial
• OS schedules disk requests to optimize both linear & rotational latencies; ideally, OS should not have to become involved at that level
• Tolerating long-latency operations creates fun problems
• E.g., block-fill not atomic; must reserve buffer for duration; Belady’s MIN designed for disks & thus does not consider incoming block in analysis
• Internal cache & prefetch mechanisms are slightly behind the times
Flash SSD Issues
• Flash does not allow in-place update of data (must block-erase first); implication is significant amount of garbage collection & storage management
• Asymmetric read [1x] & program times [10x] (plus erase time [100x])
• Proprietary firmware (heavily IP-oriented, not public, little published)
• Lack of models: timing/performance & power, notablyFlash Translation Layer is a black box (both good & bad)Ditto with garbage collection heuristics, wear leveling, ECC, etc.
• Result: poorly researched (potentially?)E.g., heuristics? how to best organize concurrency? etc.
SanDisk SSD Ultra ATA 2.5” Block Diagram
Flash SSD Organization & Operation
Ctrl
IDE
ATA
SCSI
Host
x16
SR
AM
MPU
ECCD
ata
Bu
ffer
x32
Flash Translation
Layer
Data
&
Ctrl
x32
Fla
sh C
on
tro
ller
x16
x8
x8
x16
x8
x8
Flash
Array
Flash
Array
Flash
ArrayFlash
Array
Host I/F
LayerNAND I/F
Layer
• Numerous Flash arrays
• Arrays controlled externally (controller rel. simple, but can stripe or interleave requests)
• Ganging is device-specific
• FTL manages mapping (VM), ECC, scheduling, wear leveling, data movement
• Host interface emulates HDD
Flash SSD Organization & Operation
Ctrl
IDE
ATA
SCSI
Host
x16
SR
AM
MPU
ECCD
ata
Bu
ffer
x32
Flash Translation
Layer
Data
&
Ctrl
x32
Fla
sh C
on
tro
ller
x16
x8
x8
x16
x8
x8
Flash
Array
Flash
Array
Flash
ArrayFlash
Array
Host I/F
LayerNAND I/F
Layer
I/O
Contr
ol
I/O
Column
Row
Data Reg
Cache Reg
Control
Logic
Cmd Reg
Status Reg
Addr Reg
CE#W#
R#
Flash Memory Bank
Data Reg
Cache Reg
2K bytes
1 Block
1 Page = 2 K bytes
1 Blk = 64 Pages
1024 Blocks per Device (1 Gb)
Flash
Array
• 2 KB Page
• 128 KB Block
• 2 μs page read
• 200 μs page program
• 3 ms block erase
• 32 GB total storage
Flash SSD Timing
Cmd Addr
5 cycles0.2 us
25 us 3 us
2048 cycles81.92 us
I/O [7:0]
R/W
Read page from memory array into data register
Xfer from data to cache register
Subsequent page is accessed while data is read out from cache register
Cmd
5 cycles0.2 us
3 us
2048 cycles81.92 us
I/O [7:0]
R/W
Xfer from cache to data register
Page is programmed while data for subsequent page is written into cache register200 us
Read 8 KB(4 Pages)
Write 8 KB(4 Pages)
Rd0 Rd1 Rd2 Rd3
DO0 DO1 DO2 DO3
Addr DI0 DI1 DI2 DI3
Pr0 Pr1 Pr2 Pr3
disk-interface speeds are scaling up with serial interface and fiber channel, SSD’s performance is
expected to be limited by the media transfer rate. We have measured the effect of media transfer rate on
the performance of NAND Flash SSD by scaling I/O bus bandwidth from 25 MB/s (8-bit wide bus at 25
MHz) up to 400 MB/s (32-bit wide bus at 100 MHz). As shown in Figure 7, performance does not
improve significantly beyond 100 MB/s.
However, note that, even when performance saturates at high bandwidths, it is still possible to
achieve significant performance gains by increasing the level of concurrency by either banking or
implementing superblocks. Performance saturates at 100MB/s because the real limitation to NAND Flash
memory performance is the device’s core interface—the requirement to read and write the flash storage
array through what is effectively a single port (the read/cache registers)—and this is a limitation that
concurrency overcomes.
5.4. Increasing the Degree of Concurrency
As shown previously, flash memory performance can be improved significantly if request latency is
reduced by dividing the flash array into independent banks and utilizing concurrency. The flash controller
can support these concurrent requests through multiple flash memory banks via the same channel or
through multiple independent channels to different banks, or through a combination of two. To get a
better idea of the shape of the design space, we have focused on changing the degree of concurrency one
I/O bandwidth at a time. Figure 8 shows example configurations modeled in our simulations with
bandwidths ranging from 25 MB/s to 400 MB/s. This is equivalent to saying, “I have 4 50 MHz 8-bit I/O
channels... what should I do? Gang them together, use them as independent channels, or a combination of
the two?”
The performance results are shown in Figure 9. Though increasing the number of available
concurrency in the storage sub-system (number of banks x number of channels) typically increases
16
pro
Fit T
RIA
L v
ers
ion
Host
Host
I/F
Fla
sh
Contr
oll
er
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
k
Ban
kHost
Host
I/F
Fla
sh
Contr
oll
er
Host
Host
I/F
Fla
sh
Contr
oll
er
(a) Single channel (b) Dedicated channel for each bank (c) Multiple shared channels
Figure 8: Flash SSD Organizations. (a) Single I/O bus is shared - 1, 2, or 4 banks; (b) dedicated I/O bus: 1, 2, or 4
buses and single bank per bus; (c) multiple shared I/O channels - 2 or 4 channels with 2 or 4 banks per channel.
Some Performance Studies
0
1
2
3
4
1 x
8 x
25
1 x
8 x
50
2 x
8 x
25
1 x
16 x
50
1 x
8 x
100
2 x
8 x
50
1 x
16 x
50
4 x
8 x
25
2 x
16 x
25
1 x
32 x
25
2 x
8 x
100
1 x
16 x
100
4 x
8 x
50
2 x
16 x
50
1 x
32 x
50
4 x
16 x
25
2 x
32 x
25
4 x
8 x
100
2 x
16 x
100
1 x
32 x
100
4 x
16 x
50
2 x
32 x
50
4 x
32 x
25
4 x
16 x
100
2 x
32 x
100
4 x
32 x
50
4 x
32 x
100
Read Response Time vs. Organization
Resp
on
se T
ime
(m
se
c)
Configuration
I/O Access Optimization
• Access time increasing with level of banking on single channel
• Increase cache register size
• Reduce # of I/O access requests
Fla
sh C
ontr
oll
er
Data Reg
Cache Reg
Data Reg
Cache Reg
Data RegCache Reg
Data RegCache Reg
Independent
Banks
Flash
Array
Flash
Array
Flash
Array
Cmd
5 cycles0.2 us
3 us
2048 cycles81.92 us
I/O [7:0]
R/W
Xfer from cache to data register
Page is programmed while data for subsequent page is transferred200 us
Write 8 KB(4 Pages)
Addr DI0 DI1 DI2 DI3
Pr0 Pr1 Pr2 Pr3
Cache Reg
Data Reg
1 Block
1 Page
64 Pages
Flash
Array
2 K bytes
1 PageCache Reg
Data Reg
1 Block
1 Page
64 Pages
2 K bytes
4 Pages
Cmd
5 cycles0.2 us
3 us
8192 cycles327.68 us
I/O [7:0]
R/W
Xfer from cache to data register Page is programmed200 us
Write 8 KB(4 Pages)
Addr DI0 DI1 DI2 DI3
Pr0 Pr1 Pr2 Pr3 (d) Write
using 8 KB
cache register
(a) 2 KB Cache Register (b) 8 KB Cache Register
(c) Write
using 2 KB
cache register
Fla
sh C
on
tro
ller
Data Reg
Cache Reg
Data Reg
Cache Reg
Data RegCache Reg
Data RegCache Reg
Independent
Banks
Flash
Array
Flash
Array
Flash
Array
Cmd
5 cycles0.2 us
3 us
2048 cycles81.92 us
I/O [7:0]
R/W
Xfer from cache to data register
Page is programmed while data for subsequent page is transferred200 us
Write 8 KB(4 Pages)
Addr DI0 DI1 DI2 DI3
Pr0 Pr1 Pr2 Pr3
Cache Reg
Data Reg
1 Block
1 Page
64 Pages
Flash
Array
2 K bytes
1 PageCache Reg
Data Reg
1 Block
1 Page
64 Pages
2 K bytes
4 Pages
Cmd
5 cycles0.2 us
3 us
8192 cycles327.68 us
I/O [7:0]
R/W
Xfer from cache to data register Page is programmed200 us
Write 8 KB(4 Pages)
Addr DI0 DI1 DI2 DI3
Pr0 Pr1 Pr2 Pr3 (d) Write
using 8 KB
cache register
(a) 2 KB Cache Register (b) 8 KB Cache Register
(c) Write
using 2 KB
cache register
8 KB Write, 2 KB reg. - 4 I/O accesses
8 KB reg. - Single I/O access
I/O Access Optimization
• Implement different bus-access policies for reads and writes
Cmd Addr
5 cycles0.2 us
25 us 3 us
2048 cycles81.92 us
I/O [7:0]
R/W
Read page from memory array
Xfer from data to cache register
Subsequent page is accessed while data is read out
Read 8 KB(4 Pages)
Rd0 Rd1 Rd2 Rd3
DO0 DO1 DO2 DO3
Cmd
5 cycles0.2 us
3 us
2048 cycles81.92 us
I/O [7:0]
R/W
Xfer from cache to data register
Page is programmed while data for subsequent page is read200 us
Write 8 KB(4 Pages)
Addr DI0 DI1 DI2 DI3
Pr0 Pr1 Pr2 Pr3
Access to I/O bus is not needed for 3 us and bus can be released if another memory bank asks for it. However, at the end of 3 us, it has to be acquired again.
Writes do not need I/O access as frequently as reads. I/O bus access is required between programming pages - 200us
(a) Release bus when it is not needed
Cmd Addr
5 cycles0.2 us
25 us 3 us
2048 cycles81.92 us
I/O [7:0]
R/W
Read page from memory array
Xfer from data to cache register
Subsequent page is accessed while data is read out
Read 8 KB(4 Pages)
Rd0 Rd1 Rd2 Rd3
DO0 DO1 DO2 DO3
Hold I/O bus between data burst even if it is not needed
(b) Reads hold bus during entire data transfer
Writes do not need I/O access as frequently as reads
Cmd Addr
5 cycles0.2 us
25 us 3 us
2048 cycles81.92 us
I/O [7:0]
R/W
Read page from memory array
Xfer from data to cache register
Subsequent page is accessed while data is read out
Read 8 KB(4 Pages)
Rd0 Rd1 Rd2 Rd3
DO0 DO1 DO2 DO3
Cmd
5 cycles0.2 us
3 us
2048 cycles81.92 us
I/O [7:0]
R/W
Xfer from cache to data register
Page is programmed while data for subsequent page is read200 us
Write 8 KB(4 Pages)
Addr DI0 DI1 DI2 DI3
Pr0 Pr1 Pr2 Pr3
Access to I/O bus is not needed for 3 us and bus can be released if another memory bank asks for it. However, at the end of 3 us, it has to be acquired again.
Writes do not need I/O access as frequently as reads. I/O bus access is required between programming pages - 200us
(a) Release bus when it is not needed
Cmd Addr
5 cycles0.2 us
25 us 3 us
2048 cycles81.92 us
I/O [7:0]
R/W
Read page from memory array
Xfer from data to cache register
Subsequent page is accessed while data is read out
Read 8 KB(4 Pages)
Rd0 Rd1 Rd2 Rd3
DO0 DO1 DO2 DO3
Hold I/O bus between data burst even if it is not needed
(b) Reads hold bus during entire data transfer
Reads: Hold I/O bus between data bursts
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