32-bit microcontroller mb91101/mb91101a hardware manual · i-bus 16-bit bus for internal...

FUJITSU SEMICONDUCTORCONTROLLER MANUAL

FR3032-Bit Microcontroller

MB91101/MB91101AHardware Manual

CM71-10102-2E

FUJITSU LIMITED

FR3032-Bit Microcontroller

MB91101/MB91101AHardware Manual

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PREFACE

Purposes and Intended Readers of This Manual

Thank you very much for purchasing Fujitsu semiconductor products.

MB91101/MB91101A has been developed as one of the products of the "32-bit single-chipmicro controller FR30 series" featuring a CPU with a new core RISC architecture. It has optimalspecifications for embedded use that requires high-performance CPU processing power.

This manual describes the functions and operations of MB91101/MB91101A for engineers whodevelop products using MB91101/MB91101A. Read through this manual.

For details on various instructions, see "Instruction Manual".

Trademarks

FR is an abbreviation of FUJITSU RISC controller and a product of Fujitsu Limited.

F2MC is an abbreviation of FUJITSU Flexible Microcontroller and a registered trademark ofFujitsu Limited.

Other system names and product names in this manual are trademarks of respectivecompanies or organizations.

The TM and ® marks are not necessarily spelled out in the text.

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Overall Organization of This Manual

This manual has 15 chapters and an appendix as shown below.

Chapter 1 Overview of MB91101/MB91101A

This chapter explains the basics required to know overall concepts such as the features ofMB91101/MB91101A, block diagrams, and function outlines.

Chapter 2 Precautions for Handling the Devices

This chapter describes precautions for handling MB91101/MB91101A devices.

Chapter 3 CPU and Controller

This chapter describes basics such as the architecture, specifications, and instructions of theCPU core of the FR Series. Also, this chapter describes the generation and control of theclock that controls MB91101/MB91101A in detail.

Chapter 4 External Bus Interface

This chapter describes basics information about the external bus interface, registerconfigurations and functions, and bus operation. Examples of programming bus timing andbus operation are also in this chapter.

Chapter 5 I/O Ports

This chapter explains the outline of I/O ports, register configurations, and conditions for usingexternal pins as I/O.

Chapter 6 External Interrupt/NMI Control

This chapter explains the outline of the external interrupt and NMI controller, configurationsand functions of registers, and operation of the external interrupt and NMI controller.

Chapter 7 Delayed Interrupt Module

This chapter explains the outline of the delayed interrupt module, configurations andfunctions of registers, and operation of the delayed interrupt module.

Chapter 8 Interrupt Controller

This chapter explains the outline of the interrupt controller, configurations and functions ofregisters, and operation of the interrupt controller. Examples of the hold request cancelrequest function are also in this chapter.

Chapter 9 U-TIMER

This chapter explains the outline of U-TIMER, configurations and functions of registers, andoperation of U-TIMER.

Chapter 10 UART

This chapter explains the outline of UART, configurations and functions of registers, andoperation of UART.

Chapter 11 A/D Converter (Successive approximation type)

This chapter explains the outline of the A/D converter, configurations and functions ofregisters, and operation of the A/D converter.

Chapter 12 16-bit Reload Timer

This chapter explains the outline of the 16-bit reload timer, configuration and functions ofregisters, and operation of the 16-bit reload timer.

Chapter 13 Bit Search Module

This chapter describes the outline of the bit search module, configurations and functions ofregisters, operation of the bit search module, and save and restore processing.

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Chapter 14 PWM Timer

This chapter explains the outline of the PWM timer, configurations and functions of registers,and operation of the PWM timer.

Chapter 15 DMAC

This chapter explains the outline of DMAC, configurations and functions of registers, andoperation of the DMAC.

Appendix

The appendices provide more details and programming references concerning the I/O maps,interrupt vectors, pin statuses in CPU states, precautions on using the little endian area, anda list of instructions.

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©2000 FUJITSU LIMITED Printed in Japan

1. The contents of this document are subject to change without notice. Customers are advised to consultwith FUJITSU sales representatives before ordering.

2. The information and circuit diagrams in this document are presented as examples of semiconductordevice applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU isunable to assume responsibility for infringement of any patent rights or other rights of third partiesarising from the use of this information or circuit diagrams.

3. The contents of this document may not be reproduced or copied without the permission of FUJITSULIMITED.

4. FUJITSU semiconductor devices are intended for use in standard applications (computers, officeautomation and other office equipments, industrial, communications, and measurement equipments,personal or household devices, etc.).CAUTION:Customers considering the use of our products in special applications where failure or abnormaloperation may directly affect human lives or cause physical injury or property damage, or whereextremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls,sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested toconsult with FUJITSU sales representatives before such use. The company will not be responsible fordamages arising from such use without prior approval.

5. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury,damage or loss from such failures by incorporating safety design measures into your facility andequipment such as redundancy, fire protection, and prevention of over-current levels and otherabnormal operating conditions.

6. If any products described in this document represent goods or technologies subject to certainrestrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the priorauthorization by Japanese government should be required for export of those products from Japan.

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READING THIS MANUAL

Page Layout

In this manual, an entire section is presented on a single page or spread whenever possible.The reader can thus view a section without having to flip pages.

The content of each section is summarized immediately below the title. You can obtain a roughoverview of this product by reading through these summaries.

Also, higher level section headings are given in lower sections so that you can know to whichsection the text you are currently reading belongs without referring to the table of contents or thecover of each chapter.

Notation in the Manual

The following table provides explanations of the main terms used in this manual.

Term Meaning

I-BUS 16-bit bus for internal instructions. Since the FR series adopts the internal Harvard architecture, independent buses are used for instructions and data. Bus converters are connected to I-BUS.

D-BUS Data bus with internal 32-bit width. Internal resources are connected to D-BUS.

C-BUS Internal multiplex bus connected to I-BUS and D-BUS through switches. External interface modules are connected to C-BUS. Data and instructions are multiplexed in the external data bus.

R-BUS Data bus with internal 16-bit width. R-BUS is connected to D-BUS through an adapter. Various I/O, the clock generator, and interrupt controller are connected to R-BUS.Since R-BUS has the 16-bit width, and addresses and data are multiplexed in it, multiple cycles of time are required for CPU to access these resources.

E-unit Operation executing unit

φ System clock. This clock is output to each built-in resource connected to R-BUS from the clock generator. Though this clock operates with the same cycles as the source clock frequency at its fast speed, it is divided by PCK1 and 0 at the clock generator GCR register into 1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16) of the source clock frequency.

θ System clock. This is an operating clock for resources connected to any bus other than R-BUS and CPU. Though this clock operates with the same cycles as the source clock frequency at its fast speed, it is divided by CCK1 and 0 at the clock generator GCR register into 1, 1/2, 1/4, and 1/8 (or 1/2, 1/4, 1/8, and 1/16) of the source clock frequency.

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CONTENTS

CHAPTER 1 OVERVIEW ................................................................................................... 11.1 Features ................................................................................................................................................ 21.2 Terminology ........................................................................................................................................... 61.3 Component Configuration ...................................................................................................................... 71.4 Block Diagram ..................................................................................................................................... 101.5 Pin Array Diagram ............................................................................................................................... 111.6 Diagram of External Dimensions ......................................................................................................... 131.7 List of Pin Descriptions ........................................................................................................................ 151.8 Input/Output Circuit Types ................................................................................................................... 23

CHAPTER 2 Precautions for Handling the Devices ..................................................... 272.1 Precautions for Handling the Pins and Circuits ................................................................................... 282.2 Precautions when Using Each Device ................................................................................................. 302.3 Precautions for Power-on .................................................................................................................... 32

CHAPTER 3 CPU AND CONTROLLERS ........................................................................ 333.1 Memory Space ..................................................................................................................................... 343.2 CPU ..................................................................................................................................................... 363.3 Outline of Instructions .......................................................................................................................... 393.4 Instruction Cache ................................................................................................................................. 41

3.4.1 Control Register Configuration ....................................................................................................... 443.4.2 Cache States in Each Operation Mode .......................................................................................... 463.4.3 Cacheable Area of the Instruction Cache ....................................................................................... 483.4.4 How to Set I-Cache for Use ............................................................................................................ 49

3.5 Programming Models and Registers ................................................................................................... 523.5.1 General-purpose Register .............................................................................................................. 543.5.2 PS (Program Status) ...................................................................................................................... 553.5.3 PC (Program Counter) .................................................................................................................... 583.5.4 TBR (Table Base Register) ............................................................................................................ 593.5.5 RP (Return Pointer) ........................................................................................................................ 603.5.6 SSP (System Stack Pointer) ........................................................................................................... 613.5.7 USP (User Stack Pointer) ............................................................................................................... 623.5.8 Multiply & Divide Register ............................................................................................................... 63

3.6 Data Structure ...................................................................................................................................... 643.6.1 Word Alignment .............................................................................................................................. 653.6.2 Memory Map ................................................................................................................................... 66

3.7 Branch Instruction ................................................................................................................................ 683.8 EIT (Exception/Interrupt/Trap) ............................................................................................................. 72

3.8.1 ICR (Interrupt Control Register) ...................................................................................................... 753.8.2 SSP (System Stack Pointer) ........................................................................................................... 763.8.3 TBR (Table Base Register) ............................................................................................................ 773.8.4 Multi-EIT Processing ...................................................................................................................... 793.8.5 Operation of EIT ............................................................................................................................. 81

3.9 Reset Sequence .................................................................................................................................. 85

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3.10 Operation Mode .................................................................................................................................. 863.11 Clock Generator .................................................................................................................................. 89

3.11.1 RSRR, WTCR ................................................................................................................................ 913.11.2 STCR (Standby Control Register) .................................................................................................. 933.11.3 CTBR (Time Base Timer Clear Register) ...................................................................................... 953.11.4 GCR (Gear Control Register) ......................................................................................................... 963.11.5 WPR (Watchdog Reset Postponement Register) .......................................................................... 993.11.6 PDRR (DMA Request Disable Register) ...................................................................................... 1003.11.7 PCTR (PLL Control Register) ...................................................................................................... 1013.11.8 List of the Standby Operations .................................................................................................... 1023.11.9 Stop State .................................................................................................................................... 1033.11.10 Sleep State .................................................................................................................................. 1073.11.11 Watchdog Function ...................................................................................................................... 1103.11.12 Gear Function .............................................................................................................................. 1123.11.13 Rest Cause Holding ..................................................................................................................... 1143.11.14 DMA Disabled .............................................................................................................................. 1163.11.15 Clock Doubler Function ............................................................................................................... 1183.11.16 State Transition Diagram ............................................................................................................. 1213.11.17 Example of PLL Clock Settings ................................................................................................... 1223.11.18 List of Blocks Using the Peripheral System Clock ....................................................................... 126

CHAPTER 4 EXTERNAL BUS INTERFACE ................................................................. 1274.1 Overview of the External Bus Interface ............................................................................................. 1284.2 Block Diagram ................................................................................................................................... 1294.3 Bus Interface Areas .......................................................................................................................... 1304.4 Bus Interface ..................................................................................................................................... 1314.5 List of Registers of the External Bus Interface .................................................................................. 132

4.5.1 Area Select Register (ASR) and Area Mask Register (AMR) ...................................................... 1334.5.2 Area Mode Register 0 (AMD 0) .................................................................................................... 1364.5.3 Area Mode Register 1 (AMD 1) .................................................................................................... 1384.5.4 Area Mode Register 32 (AMD 32) ................................................................................................ 1394.5.5 Area Mode Register 4 (AMD 4) .................................................................................................... 1404.5.6 Area Mode Register 5 (AMD 5) .................................................................................................... 1414.5.7 DRAM Control Registers 4 and 5 (DMCRs 4 and 5) .................................................................... 1424.5.8 Refresh Control Register (RFCR) ................................................................................................ 1454.5.9 External Pin Control Register 0 (EPCR 0) ................................................................................... 1474.5.10 External Pin Control Register 1 (EPCR 1) ................................................................................... 1504.5.11 DRAM Signal Control Register (DSCR) ....................................................................................... 1514.5.12 Little Endian Register (LER) ........................................................................................................ 1534.5.13 Mode Register (MODR) ............................................................................................................... 154

4.6 Relationship between Data Bus Widths and Control Signals ........................................................... 1564.6.1 Big Endian Bus Access ................................................................................................................ 1584.6.2 Little Endian Bus Access ............................................................................................................. 1644.6.3 External Access ........................................................................................................................... 1684.6.4 DRAM .......................................................................................................................................... 173

4.7 Bus Timing ........................................................................................................................................ 1774.7.1 Basic Read Cycle ........................................................................................................................ 1804.7.2 Basic Write Cycle ......................................................................................................................... 1824.7.3 Read Cycle in Each Mode ........................................................................................................... 184

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4.7.4 Write Cycle in Each Mode ............................................................................................................ 1864.7.5 Read/Write Mixed Cycle ............................................................................................................... 1884.7.6 Automatic Wait Cycle ................................................................................................................... 1894.7.7 External Wait Cycle ...................................................................................................................... 1904.7.8 Normal DRAM Interface: Read .................................................................................................... 1914.7.9 Normal DRAM Interface: Write .................................................................................................... 1934.7.10 Normal DRAM Read Cycle ........................................................................................................... 1954.7.11 Normal DRAM Write Cycle ........................................................................................................... 1974.7.12 Automatic Wait Cycle for the Normal DRAM Interface ................................................................. 1994.7.13 DRAM Interface in the Fast Page Mode ....................................................................................... 2004.7.14 Single DRAM Interface: Read ..................................................................................................... 2034.7.15 Single DRAM Interface: Write ...................................................................................................... 2044.7.16 Single DRAM Interface ................................................................................................................. 2054.7.17 Hyper DRAM Interface: Read ...................................................................................................... 2064.7.18 Hyper DRAM Interface: Write ...................................................................................................... 2074.7.19 Hyper DRAM Interface ................................................................................................................. 2084.7.20 DRAM Refresh ............................................................................................................................. 2094.7.21 External Bus Request ................................................................................................................... 2114.7.22 Internal Clock Multiplication Operation (Clock Doubler) ............................................................... 2124.7.23 External Bus Operation Program Examples ................................................................................. 213

CHAPTER 5 I/O PORTS ................................................................................................. 2175.1 Outline of the I/O Ports ...................................................................................................................... 2185.2 Port Data Registers (PDRs) ............................................................................................................... 2195.3 Data Direction Registers (DDRs) ....................................................................................................... 2205.4 Relation Between External Pins and Switching Registers ................................................................. 221

CHAPTER 6 U-TIMER .................................................................................................... 2296.1 Outline of the U-TIMER ..................................................................................................................... 2306.2 Registers of the U-TIMER .................................................................................................................. 2316.3 Operation of the U-TIMER ................................................................................................................ 233

CHAPTER 7 16-BIT RELOAD TIMER ........................................................................... 2357.1 Outline of the 16-bit Reload Timer ..................................................................................................... 2367.2 Control Status Register (TMCSR) ..................................................................................................... 2387.3 16-Bit Timer Register (TMR)/16-Bit Reload Register (TMRLR) ......................................................... 2407.4 Operation of 16-Bit Reload Timer ..................................................................................................... 2417.5 Operating State of the Counter .......................................................................................................... 243

CHAPTER 8 PWM TIMER .............................................................................................. 2458.1 Outline of the PWM Timer ................................................................................................................ 2468.2 Block Diagram of the PWM Timer ..................................................................................................... 2488.3 Control Status Registers (PCNH, PCNL) ........................................................................................... 2508.4 PWM Cycle Setting Register (PCSR) ................................................................................................ 2548.5 PWM Duty Setting Register (PDUT) .................................................................................................. 2558.6 PWM Timer Register (PTMR) ............................................................................................................ 2568.7 General Control Register 1 (GCN1) ................................................................................................... 2578.8 General Control Register 2 (GCN2) ................................................................................................... 260

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8.9 PWM Operation ................................................................................................................................ 2618.10 One-Shot Operation .......................................................................................................................... 2638.11 Interrupt ............................................................................................................................................ 2658.12 PWM Output All "L" and All "H" ......................................................................................................... 2668.13 Activating Two or More Channels of the PWM Timer ....................................................................... 267

CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL .............................................. 2699.1 Overview of the External Interrupts/NMI Controller .......................................................................... 2709.2 Enable Interrupt Request Register (ENIR) ........................................................................................ 2719.3 External Interrupt Request Register (EIRR) ...................................................................................... 2729.4 External Level Register (ELVR) ........................................................................................................ 2739.5 External Interrupt Operation .............................................................................................................. 2749.6 External Interrupt Level ..................................................................................................................... 2759.7 NMI (Non Maskable Interrupt) Operations ........................................................................................ 276

CHAPTER 10 DELAYED INTERRUPT MODULE ........................................................... 27710.1 Overview of the Delayed Interrupt Module ........................................................................................ 27810.2 Delayed Interrupt Control Register (DICR) ....................................................................................... 27910.3 Operations of the Delayed Interrupt Module ..................................................................................... 280

CHAPTER 11 INTERRUPT CONTROLLER .................................................................... 28111.1 Overview of the Interrupt Controller ................................................................................................. 28211.2 Block Diagram of the Interrupt Controller .......................................................................................... 28511.3 Interrupt Control Register (ICR) ........................................................................................................ 28611.4 Hold Request Cancel Request/Level Setting Register (HRCL) ........................................................ 28811.5 Priority Determination ....................................................................................................................... 28911.6 Returning from the Standby Mode (Stop/Sleep) ............................................................................... 29311.7 Hold Request Cancel Request .......................................................................................................... 29411.8 Examples of the Hold Request Cancel Request Function (HRCR) .................................................. 295

CHAPTER 12 A/D CONVERTER (Successive approximation type) ............................ 29912.1 Overview of the A/D Converter (Successive Approximation Type) ................................................... 30012.2 Control Status Register (ADCS) ....................................................................................................... 30312.3 Data Register (ADCR) ...................................................................................................................... 30812.4 Operations of the A/D Converter ....................................................................................................... 30912.5 Conversion Data Protection Function ............................................................................................... 31112.6 Precautions when Using the A/D Converter ..................................................................................... 313

CHAPTER 13 UART ........................................................................................................ 31513.1 Overview of UART ............................................................................................................................ 31613.2 Serial Mode Register (SMR) ............................................................................................................. 31813.3 Serial Control Register (SSR) ........................................................................................................... 32013.4 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) .......................................... 32213.5 Serial Status Register (SSR) ............................................................................................................ 32313.6 Operations of UART .......................................................................................................................... 32513.7 Asynchronous (Start-stop transmission) Mode ................................................................................. 32713.8 CLK Synchronous Mode ................................................................................................................... 32813.9 Interrupt Occurrence of UART and Flag Set Timing ......................................................................... 330

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13.10 Precautions for Using UART and an Application Example ................................................................ 33313.11 Example of Settings of the Baud Rate and U-TIMER Reload Value ................................................. 335

CHAPTER 14 DMAC ........................................................................................................ 33714.1 Overview of the DMAC ...................................................................................................................... 33814.2 DMAC Parameter Descriptor Pointer (DPDP) ................................................................................... 34114.3 DMAC Control Status Register (DACSR) .......................................................................................... 34214.4 DMAC Pin Control Register (DATCR) ............................................................................................... 34414.5 Registers in Descriptors on the RAM ................................................................................................. 34714.6 Transfer Modes of the DMAC ............................................................................................................ 350

14.6.1 Step Transfer (Single/Block Transfer) .......................................................................................... 35414.6.2 Continuous Transfer ..................................................................................................................... 35514.6.3 Burst Transfer ............................................................................................................................... 35614.6.4 Differences Depending on the DREQ Sense Modes (Precaution on the Edge Mode) ................. 35714.6.5 Differences Depending on the DREQ Sense Modes (Precaution on the Level Mode) ................ 358

14.7 Transfer Acceptance Signal Output and Transfer Completion Signal Output ................................... 35914.8 Precautions on the DMAC ................................................................................................................. 36014.9 DMAC Timing Charts ......................................................................................................................... 364

14.9.1 Timing Chart of the Descriptor Access Section ............................................................................ 36514.9.2 Timing Chart of the Data Transfer Section ................................................................................... 36714.9.3 Transfer Stop Timing Chart in the Continuous Transfer Mode ..................................................... 36914.9.4 Transfer Completion Operation Timing Chart ............................................................................... 371

CHAPTER 15 BIT SEARCH MODULE ............................................................................ 37315.1 Overview of the Bit Search Module ................................................................................................... 37415.2 Registers of the Bit Search Module ................................................................................................... 37515.3 Operations of the Bit Search Module and Save and Restore Processing ......................................... 377

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FIGURES

Figure 1.4-1 Overall block diagram ............................................................................................................... 10

Figure 1.5-1 Pin Array Diagram (QFP-100) .................................................................................................. 11

Figure 1.5-2 Pin Array Diagram (SQFP-100) ................................................................................................ 12

Figure 1.6-1 Diagram of External Dimensions (FPT-100P-M06) .................................................................. 13

Figure 1.6-2 Diagram of External Dimensions (FPT-100P-M05) .................................................................. 14

Figure 2.2-1 Example of Using an External Clock (Normal Case) ................................................................ 30

Figure 2.2-2 Example of Using an External Clock (Possible Only If Vcc=5V, and 12.5 MHz or Below) ....... 30

Figure 2.2-3 Example of Power Supply Connection (When Operating with 5V Power Supply) .................... 31

Figure 2.2-4 Example of Power Supply Connection (when Operating with 3V Power Supply) ..................... 31

Figure 2.2-5 Example of a 5V Power Supply when STOP Mode .................................................................. 31

Figure 3.1-1 Memory Map ............................................................................................................................. 35

Figure 3.2-1 Internal Architecture .................................................................................................................. 37

Figure 3.2-2 Instruction Pipeline ................................................................................................................... 38

Figure 3.4-1 I-CACHE-1 Instruction Cache Configuration ............................................................................ 41

Figure 3.4-2 I-CACHE-2 Instruction Cache Tag ............................................................................................ 42

Figure 3.4-3 I-CACHE-3 Instruction Cache Control Register (ICHCR) ......................................................... 44

Figure 3.5-1 Basic Programming Model (General-purpose Register) ........................................................... 52

Figure 3.5-2 Basic Programming Model (Special Register) .......................................................................... 53

Figure 3.5-3 General-purpose Register ........................................................................................................ 54

Figure 3.6-1 Memory Map ............................................................................................................................. 66

Figure 3.6-2 Series Common Memory Map .................................................................................................. 67

Figure 3.8-1 Interrupt Stack .......................................................................................................................... 76

Figure 3.8-2 Multi-EIT Processing ................................................................................................................. 80

Figure 3.11-1 Block Diagram of the Clock Generator ..................................................................................... 90

Figure 3.11-2 Block Diagram of the Stop Controller ..................................................................................... 103

Figure 3.11-3 Block Diagram of the Sleep Controller .................................................................................... 107

Figure 3.11-4 Block Diagram of the Watchdog Controller ............................................................................. 110

Figure 3.11-5 Operation of the Watchdog Timer ........................................................................................... 111

Figure 3.11-6 Block Diagram of the Gear Controller ..................................................................................... 112

Figure 3.11-7 Block Diagram of the Reset Cause Circuit ............................................................................. 114

Figure 3.11-8 Block Diagram of the DMA Disable Circuit ............................................................................. 116

Figure 3.11-9 State Transition Diagram ........................................................................................................ 121

Figure 3.11-10 Example of PLL Clock Settings .............................................................................................. 122

Figure 3.11-11 Clock System Reference Diagram .......................................................................................... 123

Figure 4.2-1 Block Diagram of the External Gus Interface .......................................................................... 129

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Figure 4.3-1 Chip Select Area Setting Example .......................................................................................... 130

Figure 4.5-1 Examples of Maps for Which Chip Select Areas Have Been Set ............................................ 135

Figure 4.6-1 Data Bus Widths and Control Signals in the Normal Bus Interface ......................................... 156

Figure 4.6-2 Data Bus Widths and Control Signals in the DRAM Interface ................................................. 156

Figure 4.6-3 Relationship between an Internal Register and an External Data Bus in the Word Access .... 158

Figure 4.6-4 Relationship between an Internal Register and an External Data Bus in the Half Word Access .................................................................................................................................................... 158

Figure 4.6-5 Relationship between an Internal Register and an External Data bus in the Byte Access ...... 159

Figure 4.6-6 Relationship between an Internal Register and an External Data Bus for the 16-bit Bus Width .... ..................................................................................................................................................159

Figure 4.6-7 Relationship between an Internal Register and an External Data Bus for the 8-bit Bus Width 160

Figure 4.6-8 External Bus Access for the 16-bit Bus Width ......................................................................... 161

Figure 4.6-9 External Bus Access for the 8-bit Bus Width ........................................................................... 162

Figure 4.6-10 Example of the MB91101 being Connected to an External Device ......................................... 163

Figure 4.6-11 Relationship between an Internal Register and an External Data Bus in the Word Access .... 165

Figure 4.6-12 Relationship between an Internal Register and an External Data Bus in the Half Word Access ... ..................................................................................................................................................165

Figure 4.6-13 Relationship between an Internal Register and an External Data Bus in the Byte Access ..... 165

Figure 4.6-14 Relationship between an Internal Register and an External Data Bus for the 16-bit Bus Width .... ..................................................................................................................................................166

Figure 4.6-15 Relationship between an Internal Register and an External Data Bus for the 8-bit Bus Width 166

Figure 4.6-16 Example of the MB91101 being Connected to an External Device (for the 16-bit Bus Width) 167

Figure 4.6-17 Example of the MB91101 being Connected to an External Device (for the 8-bit Bus Width) .. 167

Figure 4.6-18 Example of Connecting the MB91101 and One DRAM Device with 8-Bit Output (8-Bit Data Bus) ..................................................................................................................................................174

Figure 4.6-19 Example of Connecting the MB91101 and Two DRAM Devices with 8-Bit Output (16-Bit Data Bus) ..................................................................................................................................................175

Figure 4.6-20 Example of Connecting the MB91101 and Two DRAM Devices with 16-Bit Output (16-Bit Data Bus) ..................................................................................................................................................176

Figure 4.7-1 Basic Read Cycle Timing Example ......................................................................................... 180

Figure 4.7-2 Basic Write Cycle Timing Example .......................................................................................... 182

Figure 4.7-3 Read Cycle Timing Example 1 ................................................................................................ 184





Figure 4.7-8 Write Cycle Timing Example 1 ................................................................................................ 186




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Figure 4.7-13 Read/Write Mixed Cycle Timing Example .............................................................................. 188

Figure 4.7-14 Automatic Wait Cycle Timing Example ................................................................................... 189

Figure 4.7-15 External Wait Cycle Timing Example ...................................................................................... 190

Figure 4.7-16 Normal DRAM Interface Read Timing Example ..................................................................... 191

Figure 4.7-17 Normal DRAM Interface Write Timing Example ..................................................................... 193

Figure 4.7-18 Normal DRAM Read Cycle Timing Example 1 ....................................................................... 195



Figure 4.7-21 Normal DRAM Write Cycle Timing Example 1 ....................................................................... 197



Figure 4.7-24 Normal DRAM Interface Automatic Wait Cycle Timing Example ............................................ 199

Figure 4.7-25 Fast Page Mode DRAM Interface Timing Example 1 ............................................................. 200




Figure 4.7-29 Single DRAM Interface Read Timing Example ....................................................................... 203

Figure 4.7-30 Single DRAM Interface Write Timing Example ....................................................................... 204

Figure 4.7-31 Single DRAM Interface Timing Example ................................................................................ 205

Figure 4.7-32 Hyper DRAM Interface Read Timing Example ....................................................................... 206

Figure 4.7-33 Hyper DRAM Interface Write Timing Example ....................................................................... 207

Figure 4.7-34 Hyper DRAM Interface Timing Example ................................................................................. 208

Figure 4.7-35 CAS Before RAS (CBR) Refresh Timing Example ................................................................. 209

Figure 4.7-36 CBR Refresh Automatic Wait Cycle Timing Example ............................................................. 210

Figure 4.7-37 Self Refresh Timing Exampl ................................................................................................... 210

Figure 4.7-38 Bus Right Releasing Timing Example .................................................................................... 211

Figure 4.7-39 Bus Right Obtaining Timing Example ..................................................................................... 211

Figure 4.7-40 x2 Clock Timing Example (BW-16bit, Access-Word Read) .................................................... 212

Figure 4.7-41 x1 Clock Timing Example (BW-16bit, Access-Word Read) .................................................... 212

Figure 5.1-1 Basic Configurataion of the I/O Ports ..................................................................................... 218

Figure 6.1-1 List of the Registers in the U-TIMER ...................................................................................... 230

Figure 6.1-2 B lock Diagram of the U-TIMER ............................................................................................. 230

Figure 7.1-1 List of Registers in 16-bit Reload Timer .................................................................................. 236

Figure 7.1-2 Block Diagram of 16-bit Reload Timer .................................................................................... 237

Figure 7.4-1 Timing of Counter Activation and Operation ........................................................................... 241

Figure 7.4-2 Timing of the Underflow Operation. ........................................................................................ 242

Figure 7.5-1 State Transition of the Counter ............................................................................................... 243

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Figure 8.1-1 List of the Registers of the PWM Timer. .................................................................................. 247

Figure 8.2-1 General Block Diagram of the PWM Timer ............................................................................. 248

Figure 8.2-2 Block Diagram of One Channel of the PWM Timer ................................................................. 249

Figure 8.9-1 PWM Operation Timing Chart (Trigger Re-activation Prohibited) ........................................... 262

Figure 8.9-2 PWM Operation Timing Chart (Trigger Re-activation Allowed) ............................................... 262

Figure 8.10-1 One-shot Operation Timing Chart (Trigger Re-activation Prohibited) ..................................... 263

Figure 8.10-2 One-shot Operation Timing Chart (Trigger Re-activation Allowed) ......................................... 264

Figure 8.11-1 Timing Chart of the Interrupt Source (PWM Output: Normal Polarity) ..................................... 265

Figure 8.12-1 Example of Setting all PWM Output to Level "L" ..................................................................... 266

Figure 8.12-2 Example of Setting all PWM Output to Level "H" .................................................................... 266

Figure 9.1-1 Register List of the External Interrupt/NMI Controller .............................................................. 270

Figure 9.1-2 Block Diagram of the External Interrupt/NMI Controller ......................................................... 270

Figure 9.5-1 External Interrupt Operation .................................................................................................... 274

Figure 9.6-1 Clear Operation of the Request Source Holding Circuit During Level Setting ......................... 275

Figure 9.6-2 Clear Operation of the Request Source Holding Circuit During Level Setting ......................... 275

Figure 9.7-1 Request Detection Section of NMI .......................................................................................... 276

Figure 10.1-1 Register List of the Delayed Interrupt Module ......................................................................... 278

Figure 10.1-2 Block Diagram of the Delayed Interrupt Module ...................................................................... 278

Figure 11.1-1 Register List of the Interrupt Controller (1/2) ........................................................................... 283

Figure 11.1-2 Register List of the Interrupt Controller (2/2) ........................................................................... 284

Figure 11.2-1 Block Diagram of the Interrupt Controller ................................................................................ 285

Figure 11.8-1 Hardware Configuration to Use the Hold Request Cancel Request Function ......................... 296

Figure 11.8-2 Timing Example of a Hold Request Cancel Request Sequence (Interrupt Level: HRCL > a) . 296

Figure 11.8-3 Timing Example of a Hold Request Cancel Request Sequence (Interrupt Level: HRCL > a > b) .. ..................................................................................................................................................297

Figure 12.1-1 Register List of the A/D Converter ........................................................................................... 301

Figure 12.1-2 Block Diagram of the A/D Converter. ...................................................................................... 302

Figure 12.5-1 Flow of the Data Protection Function When the DMA Transfer is Used .................................. 312

Figure 13.1-1 Register List of UART .............................................................................................................. 316

Figure 13.1-2 Block Diagram of UART .......................................................................................................... 317

Figure 13.7-1 Transfer Data Format in Asynchronous (Start-Stop Transmission) Mode (Mode 0 and Mode 1) .. ..................................................................................................................................................327

Figure 13.8-1 Transfer Data Format in CLK Synchronous Mode (Mode 2) ................................................... 328

Figure 13.9-1 Set Timing of ORE, FRE, and RDRF (Mode 0) ....................................................................... 330

Figure 13.9-2 Set Timing of ORE, FRE, and RDRF (Mode 1) ....................................................................... 331

Figure 13.9-3 Set Timing of ORE and RDRF (Mode 2) ................................................................................. 331

Figure 13.9-4 Setting Timing of TDRE (Mode 0 and Mode 1) ....................................................................... 332

Figure 13.9-5 Setting Timing of TDRE (Mode 2) ........................................................................................... 332

Figure 13.10-1 Example of System Construction Using Mode 1 ..................................................................... 333

xvi

Figure 13.10-2 Communication Flow Chart in Mode 1 .................................................................................... 334

Figure 14.1-1 List of DMAC Registers .......................................................................................................... 339

Figure 14.1-2 Block Diagram of the DMA ..................................................................................................... 340

Figure 14.6-1 Combinations of Request Senses and Transfer Modes ......................................................... 353

Figure 14.6-2 Step Transfer [CLK Doubler Used, Internal Descriptor, Block Size = 1] ................................. 354

Figure 14.6-3 Continuous Transfer [CLK Doubler Used, Internal Descriptor] ............................................... 355

Figure 14.6-4 Burst Transfer [CLK Doubler Used, Internal Descriptor] ......................................................... 356

Figure 14.6-5 Precaution on Timing in the Edge Mode ................................................................................. 357

Figure 14.6-6 Precaution on Timing in the Level Mode ................................................................................ 358

Figure 14.8-1 Restriction of DMAC ............................................................................................................... 362

Figure 15.1-1 List of Bit Search Module Registers ........................................................................................ 374

Figure 15.1-2 Block Diagram of the Bit Search Module ................................................................................ 374

xvii

TABLES

Table 1.3-1 Product Type Configuration ........................................................................................................ 7

Table 1.3-2 Packages and Product Type Support ......................................................................................... 8

Table 1.3-3 Combination of the Clock Gears .................................................................................................. 9

Table 1.7-1 Pin Description .......................................................................................................................... 15

Table 1.7-2 DRAM control pins ..................................................................................................................... 22

Table 1.8-1 Input/Output Circuit Forms ....................................................................................................... 23

Table 3.4-1 Cache States in Each Operation Mode .................................................................................... 46

Table 3.4-2 Update of Cache Entries .......................................................................................................... 47

Table 3.8-1 Interrupt Level .......................................................................................................................... 73

Table 3.8-2 Interrupt Causes and Interrupt Control Registers/Interrupt Vectors ......................................... 75

Table 3.8-3 Vector Table ............................................................................................................................. 77

Table 3.8-4 The priority of EIT cause acceptance ........................................................................................ 79

Table 3.8-5 Order of Execution of Each EIT Handler .................................................................................. 80

Table 3.10-1 Mode Pins and Setting Modes .................................................................................................. 86

Table 3.10-2 Bus Mode Setting Bit and the function ..................................................................................... 87

Table 3.11-1 List of the Standby Operations ............................................................................................... 102

Table 4.4-1 BUS-1 ..................................................................................................................................... 131

Table 4.5-1 Page Size of DRAM to be Connected .................................................................................... 142

Table 4.5-2 Combinations of Bus Widths that can be Used in Areas 4 and 5 ........................................... 144

Table 4.5-3 Mode Setting Using the Combination of Bits (LE2, LE1, and LE0) ........................................ 153

Table 4.5-4 Bus Mode Setting Bit and the function .................................................................................... 154

Table 4.6-1 Relationship between Data Bus Widths and Control Signals ................................................. 157

Table 4.6-2 DRAM Control Pins and Bus Widths ...................................................................................... 173

Table 4.6-3 Page Size Selection Bit .......................................................................................................... 174

Table 5.4-1 List of Function Choices of External Pins ................................................................................ 221




Table 7.2-1 CSL Bit Setting Clock Source .................................................................................................. 238

Table 8.3-1 Selection of the Count Clock ................................................................................................... 251

Table 8.3-2 PWM Output When "1" is Written to PGMS ............................................................................ 251

Table 8.3-3 Selection of the Trigger Input Edge ......................................................................................... 251

Table 8.3-4 Selection of the Interrupt Source ............................................................................................. 252

Table 8.3-5 Specification of the Polarity of the PWM Output and the Edge ............................................... 253

Table 8.7-1 Selection of Ch3 Trigger Input ................................................................................................. 258

xviii

Table 8.7-2 Selection of Ch2 Trigger Input ................................................................................................ 258



Table 9.4-1 Allocation of the External Interrupt Request Levels ................................................................ 273

Table 11.3-1 Correspondence Between the Interrupt Level Bits and the Interrupt Level ............................ 287

Table 11.5-1 Relations of the Interrupt Sources, Interrupt No. and Interrupt Levels ................................... 290

Table 11.5-2 Relations of the Interrupt Sources, Interrupt No. and Interrupt Levels ................................... 291

Table 11.7-1 Settings of the Interrupt Levels that Generate a Hold Request Cancel Request .................... 294

Table 12.2-1 Selection of the A/D Activation Source ................................................................................... 304

Table 12.2-2 Selection of the A/D Converter Operating Mode .................................................................... 305

Table 12.2-3 Settings of the A/D Conversion Start Channels ...................................................................... 306

Table 12.2-4 Settings of the A/D Cconversion End Channels ..................................................................... 306

Table 13.2-1 Selection of the Operating Mode of UART ............................................................................. 318

Table 13.6-1 Operating Modes of UART ..................................................................................................... 325

Table 13.11-1 Baud Rate and U-TIMER Reload Value in Asynchronous (Start-Stop Transmission) Mode .. 335

Table 13.11-2 Baud Rate and U-TIMER Reload Value in CLK Synchronous Mode ..................................... 335

Table 14.2-1 Descriptor Address of Each Channel ...................................................................................... 341

Table 14.4-1 Selecting a Transfer Request Input Detect Level ................................................................... 345

Table 14.4-2 Specifying the Transfer Request Acceptance Output ............................................................. 345

Table 14.4-3 Specifying the Transfer Completion Output ............................................................................ 346

Table 14.5-1 Transfer Source and Destination Address Update Mode Specification .................................. 348

Table 14.5-2 Address Increment/Decrement Unit ........................................................................................ 348

Table 14.5-3 Transfer Data Size Specification ............................................................................................ 348

Table 14.5-4 Transfer Mode Specification ................................................................................................... 349

Table 14.8-1 Combinations of Clock Gears ................................................................................................. 362

Table 14.8-2 DMA Transfer Request Causes .............................................................................................. 363

Table 14.9-1 Description of Symbols Used in the Timing Charts ................................................................ 364

Table 15.3-1 Bit Positions and Returned Values (Decimal) ......................................................................... 378

Table A-1 I/O MAP .................................................................................................................................. 383

Table B-1 Interrupt vector table (1/2) ...................................................................................................... 393

Table B-2 Interrupt vector table (2/2) ...................................................................................................... 394

Table C-1 Terminology used in the lists of pin statuses .......................................................................... 396

Table C-2 Pin statuses in the external 16-bit bus and 2CAS1WR mode (1/2) ........................................ 397




Table C-6 External 8-bit bus mode (1/2) ................................................................................................. 403

Table C-7 External 8-bit bus mode (2/2) ................................................................................................. 405

xix

Table E-1 Add/subtract Operation Instructions (10 Instructions) ............................................................. 419

Table E-2 Compare Operation Instructions (3 Instructions) .................................................................... 419

Table E-3 Logical Operation Instructions (12 Instructions) ...................................................................... 419

Table E-4 Bit Manipulation Arithmetic Instructions (8 Instructions) .......................................................... 420

Table E-5 Add/subtract Operation Instructions (10 instructions) ............................................................. 421

Table E-6 Shift Arithmetic Instructions (9 Instructions) ............................................................................ 421

Table E-7 Immediate Value Data Transfer Instruction (Immediate Value Set /16-bit/32-bit Immediate Value Transfer Instructions) (3 Instructions) 422

Table E-8 Memory Load Instructions (13 Instructions) ............................................................................ 422

Table E-9 Memory Store Instructions (13 Instructions) ............................................................................ 423

Table E-10 Transfer Instructions Between Registers/Special-purpose Registers Transfer Instructions (5 Instructions) 423

Table E-11 Non-delay Normal Branch Instruction (23 Instructions) .......................................................... 424

Table E-12 Branch Instructions with Delays (20 Instructions) .................................................................. 425

Table E-13 Direct Addressing Instructions ................................................................................................ 426

Table E-14 Resource Instructions (2 Instructions) .................................................................................... 426

Table E-15 Co-processor Instructions (4 Instructions) ............................................................................. 426

1

CHAPTER 1 OVERVIEW

This chapter explains the general outlines of features and block diagrams of MB91101 and MB91101A. If not specifically mentioned, explanations in this manual apply to both MB91101 and MB91101A.

1.1 Features

1.2 Terminology

1.3 Component Configuration

1.4 Block Diagram

1.5 Pin Array Diagram

1.6 Diagram of External Dimensions

1.7 List of Pin Functions

1.8 Input/Output Circuit Forms

2

CHAPTER 1 OVERVIEW

1.1 Features

This device is a standard single-chip micro controller with 32-bit RISC CPU (FR series) as its core, containing various I/O resources and the bus control feature for embedded control that requires high-performance/high-speed CPU processing. Though external bus access is basically used to support a wide address space accessed by the 32-bit CPU, 1 KB instruction cache memory and 2 KB RAM are contained to speed up execution of instructions by CPU.This device has optimal specifications for embedded use that requires high-performance CPU processing power such as the navigation system, high-performance FAX, and printer control.If not specifically mentioned, descriptions in this manual are common to MB91101 and MB91101A.

Features

FR-CPU

The following lists the features of FR-CPU.

• 32-bit RISC, load/store architecture, 5-stage pipeline

• Operating frequency 50 MHz internally [25 MHz externally] (when PLL is used and thesource clock frequency is 12.5 MHz)

• General-purpose register 32 bits × 16

• 16-bit fixed length instruction (basic instruction), 1 instruction/1 cycle

• Memory: instructions for memory-to-memory transfer, bit processing, and barrel shift---Instructions appropriate to embedded use

• Function entry/exit instruction, multi-load/-store instruction---high-level language compliantinstruction

• Register interlock function---simplification of assembler description

• Branch instruction with a delayed slot---reduction of overheads for branch processing

• Flexible support of built-in multiplier

• Signed 32-bit multiplication---5 cycles

• Signed 16-bit multiplication---3 cycles

• Interrupt (PC and PS save)---6 cycles, 16 priority levels

Bus interface

The following lists the features of the bus interface.

• Clock doubler used 50 MHz internally, external bus operating at 25 MHz

• 25-bit address bus (32 MB space)

• 16/8-bit data bus

3

1.1 Features

• Basic external bus cycle---2 clock cycles

• Chip select output that can be set in minimum 64 Kbytes---6

• Support of interfaces for various types of memory

• DRAM interface (areas 4 and 5)

• Automatic wait cycle---Any cycle between 0 to 7 cycles can be set for each area.

• Unused data/address pins can also be used as input/output ports.

• Little endian mode support (one area selected from areas 1 to 5)

DRAM interface

The following lists the features of the DRAM interface.

• Independent control of 2 banks (areas 4 and 5)

• Double CAS DRAM (normal DRAM I/F)/Single CAS DRAM/Hyper DRAM

• Basic bus cycle---normally 5 cycle, 2-cycle access is possible in high-speed page mode

• Programmable waveforms---1-cycle automatic wait can be inserted into RAS and CAS

• DRAM refresh

• CBR refresh (The interval can be set arbitrarily by the 6-bit timer)

• Self refresh mode

• 8/9/10/12-column address support

• 2CAS/1WE and 2WE/1CAS can be selected

Cache memory

The following lists the features of cache memory.

• 1 KB instruction cache

• 2-way set associative

• 32 blocks/way, 4 entries (4 words)/block

• Lock function---specific program code residing in cache

DMAC (DMA Controller)

The following lists the features of DMAC (DMA Controller).

• 8 channels

• Transfer request sources interrupt requests of external pins/built-in resources

• Transfer sequence step transfer/block transfer

• Burst transfer/continuous transfer

• Transfer data length selectable from 8 bits/16 bits/32 bits

• Can be stopped by NMI/interrupt requests.

UART

The following lists the features of UART.

• Independent 3 channels

• Full duplex double buffer

• Data length---7 to 9 bits (without parity), 6 to 8 bits (with parity)

4

CHAPTER 1 OVERVIEW

• Asynchronous (start-stop synchronization), CLK synchronous communication selectable

• Multi-processor mode

• 16-bit timer (U-Timer) is contained as the baud rate generator---Can generate any baud rate

• External clocks can be used as a transfer clock.

• Error detection---parity, frame, overrun

A/D converter (Successive approximation type)

The following lists the features of the A/D converter (Successive approximation type).

• 10-bit resolution, 4 channels

• Sequential compare conversion---5.6 µs at 25 MHz

• Sample & hold circuit contained

• Conversion mode---selectable from the singe conversion/scan conversion/repeat conversion

• Start---selectable from the software/external trigger/built-in timer

Reload timer

• 16-bit timer---3 channels

• Internal clock---2-clock cycle resolution, selectable from 2/8/32 dividing

Other interval timers

• 16-bit timer---3 channels (U-TIMER)

• PWM timer---4 channels

• Watchdog timer---1 channel

Bit search module

Searches the position of the first "1"/"0" change bit from MSB in one word.

Interrupt controller

• External interrupt input---unmaskable interrupt (NMIX), normal interrupt X 4 (INT0 to INT3)

• Internal interrupt sources---UART, DMAC, A/D, UTIMER, delayed interrupt

• Excluding unmaskable interrupt, the priority level can be set to programmable (16 levels).

Reset causes

Power-on reset/hardware standby/watchdog timer/software reset/external reset

Power saving mode

Sleep/stop mode

Clock control

Gear function---Operating frequencies can be independently for CPU and peripherals.

The gear clock can be selected from 1/1, 1/2, 1/4, 1/8 (or 1/2, 1/4, 1/8, 1/16)

However, the operating frequency for peripherals is limited to 25 MHz.

Package QFP-100, SQFP-100

5

1.1 Features

CMOS technology (0.35 µµµµm)

Power

• When 5V power supply is used

• CPU power supply 5.0 V plus or minus 10% (The built-in regulator is used)

• A/D power supply 2.7 V to 3.6 V

• When 3V power supply is used

• CPU power supply 2.7 V to 3.6 V (The built-in regulator is not used)

• A/D power supply 2.7 V to 3.6 V

6

CHAPTER 1 OVERVIEW

1.2 Terminology

This section explains main terms used in this manual.

Terms

I-BUS

16-bit bus for internal instructions. Since the FR series adopts the internal Harvard architecture,independent buses are used for instructions and data. Bus converters are connected to I-BUS.

D-BUS

Data bus with internal 32-bit width. Internal resources are connected to D-BUS.

C-BUS

Internal multiplex bus connected to I-BUS and D-BUS through switches. External interfacemodules are connected to C-BUS. Data and instructions are multiplexed in the external databus.

R-BUS

Data bus with internal 16-bit width. R-BUS is connected to D-BUS through an adapter. VariousI/O, the clock generator, and interrupt controller are connected to R-BUS.

Since R-BUS has the 16-bit width, and addresses and data are multiplexed in it, multiple cyclesof time are required for CPU to access these resources.

E-unit

Operation executing unit

φφφφ

System clock that is output to each built-in resource connected to R-BUS from the clockgenerator. Though this clock operates with the same cycles as the source clock frequency at itsfast speed, it is divided by PCK 1 and 0 at the clock generator GCR register into 1, 1/2, 1/4, and1/8 (or 1/2, 1/4, 1/8, and 1/16) of the source clock frequency.

θθθθ

System clock as an operating clock for resources connected to any bus other than R-BUS andCPU. Though this clock operates with the same cycles as the source clock frequency at its fastspeed, it is divided by CCK1 and 0 at the clock generator GCR register into 1, 1/2, 1/4, and 1/8(or 1/2, 1/4, 1/8, and 1/16) of the source clock frequency.

7



Table 1.3-1 lists the configuration of product types. The table also shows the differences between MB91101 and MB91101A.

Product Type Configuration

Table 1.3-1 Product Type Configuration

Product name MB91V101 MB91101(MB91101R)

MB91V101A MB91101A

Item

Classification Product for evaluation/development

Regular production product

Product for evaluation/development

Regular production product

CPU function 32-bit RISC, load/store architecture, 5-stage pipelineGeneral-purpose register: 16Instruction: 16-bit fixed length, 1 instruction/1 cycleInterrupt: 6 cycles, 16 priority levelsOperating frequency: 50 MHz internally, (PLL used, 12.5 MHz X 4)

Bus interface Address: 25 bits (32 MB space)Data: 8/16 bitsCS output: 6 (in minimum 64 KB)Others: automatic wait cycle, Little-Endian mode, Clock doubler used (50 MHz internally, 25 MHz in external buses)

DRAM interface Independent control of 2 banksNormal DRAM, Single-CAS DRAM, Hyper DRAM

Instruction cache 1 KB, 2 way set associativeLock function

DMAC Simplified type, 8 channelsStep transfer, block transfer, burst transfer, continuous transferTransfer request source: external 3, built-in resources 5

Built-in data RAM 512 X 32 bits (2 K)

UART Independent 3 channels7 to 9 (without parity), 6 to 8 (with parity)Asynchronous (start-stop synchronization)/CLK synchronous modeBaud rate generator (U-TIMER) contained

Timer 16-bit reload timer---3 channelsPWM timer---4 channelsWatchdog timer---1 channelU-TIMER (16 bits)---3 channels

8

CHAPTER 1 OVERVIEW

Packages and Product Type Support

Differences between MB91101 and MB91101A.

The following four items restrict the use of MB91101, but these restrictions do not apply toMB91101A.

• If DREQ is dropped under the following condition when DMAC is used, one (one transfersize for the single transfer and one block for the block transfer) extra transfer occurs.

Condition for the occurrence

DMAC transfer destination: if external memory, and the level mode, and the handshakeDREQ-DACK synchronizes with DACK generated during transfer destination access tonegate the DREQ request.

• DMA transfer occurs twice with one transfer request under the following condition duringDMAC transfer in the transmission operation of built-in UART.

A/D converter 10-bit resolution, 4 channels

Bit search module Searches in one cycle the position of the "1"/"0" change bit within one word.

External interrupt Normal interrupt---4 channelsUnmaskable interrupt---1 channel

Process CMOS (0.35 µm)

Operating voltage 5.0 V plus or minus 10%/3.3 V plus or minus 0.3 V (up to 50 MHZ)/3.0 V plus or minus 0.3 V (up to 40MHz) 2.7 V to 3.6 V (A/D converter)

Table 1.3-1 Product Type Configuration (Continued)


MB91V101A MB91101A

Item

Table 1.3-2 Packages and Product Type Support


MB91V101A MB91101A

Package

PGA-135C-A02 O ES - O ES -

FPT-100P-M06 - O - O

FPT-100P-M05 - O - O

BGA-112P-M01 - (*) - (*)

O: Yes

-: No

(*): Prior consultation with both the Packaging Engineering Dept. and Planning Dept. is required.

9


Condition for the occurrence

DMAC transfer source: if external memory, and DMA transfer destination: UART sendregister, and the operating frequency of CPU is faster than that of peripheral resources.

Y1: Normal operation

Y2: Problem found

N: Problem found

• In synchronous transfer mode of the built-in UART, write operation to SODR is not allowedsimultaneously with the end of transmission (the RDRF bit is set to "1").

• Do not mix CAS output and any output port from the CAS0L, CAS0H, CAS1L, and CAS1Hpins of the CAS output pin on the DRAM interface. If CAS output and any input port orDMAC pin mix, set the PDR bit of the corresponding input port or DMAC pin to "1".

The specifications of MB91101A are improved for the following item.

• No clock is supplied internally during power-on for about 42 ms (@ source clock frequency12.5 MHz) to wait for the built-in regulator to stabilize. During this period of time, the state ofport pins is undefined and not initialized. Thus, ports may be in an output state andmeasures must be taken if output signals collide externally.

• In MB91101A, only the pin state is initialized to the state before time wait of about 42 msby setting the RSTX pin to the "L" level state after the internal power is started.

Table 1.3-3 Combination of the Clock Gears

Peripherals

1/1 1/2 1/4 1/8

CPUs 1/1 Y1 Y2 N N

1/2 Y1 Y1 Y2 N

1/4 Y1 Y1 Y1 Y2

1/8 Y1 Y1 Y1 Y1

10

CHAPTER 1 OVERVIEW

1.4 Block Diagram

Figure 1.4-1 shows an overall block diagram.

Block Diagram

Figure 1.4-1 Overall block diagram

• Pins are depicted based on their functionality (Pins are partly multiplexed).

• To use REALOS, use the external interrupts or built-in timer for time management.

FR CPU

RAM2KB Instruct ion CacheI-bus

1KB

Bit Search Module(16bi t ) Harvard

PrincetonD31 D16

D-bus (32bi t ) Bus Converter A24 A00DMAC(8ch) RDX

WR0X 1XRDY

Bus Control ler CLKDREQ0 DREQ1DREQ2 C-bus CS0X 5XDACK0 DACK1 DACK2 BRQBGRNTXEOP0 EOP1 EOP2 32bit 16bi t

Bus Converter DRAMControl ler RAS0RAS1CS0L CS1LCS0HCS1HDW0XDW1X

X0 X1 Clock Control Uni tRSTX (Watch Dog Timer)

INT0 INT3 Interrupt Control Port 0 - BNMIX Unit (32bi t )

AN0 AN3 10bit A/D UART(3ch) SI0 SI1 SI2AVCC AVRH Converter (4ch) R-bus (16bi t ) wi th SO0 SO1 SO2AVSS AVRL Baud Rate Timer SC0 SC1 SC2

Reload Timer (3ch) PWMTimer (4ch) OCPA0 OCPA3TRG0 3

Port

HSTX

11



The following figure shows a pin array diagram.

Pin Array Diagram

Figure 1.5-1 Pin Array Diagram (QFP-100)

80

7879

777675

7374

727170

6869

676665

6364

626160

5859

575655

5354

5251

9697989910

0 9192939495 8687888990 8182838485

2627282930

12345678910111213141516171819202122232425

46 47 48 49 5031 32 33 34 35 36 37 38 39 40 41 42 43 44 45

CS

0L/P

B1

SC

0/P

F2/

OC

PA

3S

I1/P

F3/

TR

G2

SO

1/P

F4/

TR

G3

SI2

/PF

5/O

CP

A1

SO

2/P

F6/

OC

PA

2P

F7/

OC

PA

0/A

TG

XD

AC

K1/

PE

7D

AC

K0/

PE

6D

RE

Q1/

PE

5D

RE

Q0/

PE

4IN

T3/

PE

3/S

C2

INT

2/P

E2/

SC

1V

SS

X1

X0

VC

C5

INT

1/P

E1

INT

0/P

E0

RA

S0/

PB

0

A08

A06A07

A05

A09A10A11A12A13A14A15A16/P60A17/P61A18/P62A19/P63A20/P64A21/P65VSSA22/P66A23/P67A24/EOP0AVCCAVRHAVSS/AVRLAN0AN1AN2

SO0/PF1/TRG1SI0/PF0/TRG0AN3

P20/D16P21/D17

P22/D18

P85/WR1XWR0X

RDXP82/BRQ

P81/BGRNTXP80/RDY

MD2MD1MD0VSS

RSTXHSTXNMIX

CS0X

PA1/CS1XPA2/CS2X

EOP1/PA3/CS3XPA4/CS4XPA5/CS5X

PA6/CLK

PB7/DW1X

DACK2/PB6/CS1H

PB2/CS0HPB3/DW0X

EOP2/PB4/RAS1DREQ2/PB5/CS1L

A04

A03

A02

A01

VC

C5

A00

D31

VS

SD

30D

29D

28D

27D

26D

25D

24P

27/D

23

P26

/D22

P25

/D21

P24

/D20

P23

/D19

(TOP VIEW)

FPT-100P-M06

VCC3

12

CHAPTER 1 OVERVIEW

Figure 1.5-2 Pin Array Diagram (SQFP-100)

P20/D16P85/WR1X

WR0XRDX

P82/BRQP81/BGRNTX

P80/RDYMD2MD1MD0VSS

RSTXHSTXNMIXCS0X

PA1/CS1XPA2/CS2X

EOP1/PA3/CS3XPA4/CS4XPA5/CS5X

PA6/CLKVCC3

PB7/DW1XDACK2/PB6/CS1HDREQ2/PB5/CS1L

A08A09A10A11A12A13A14A15A16/P60A17/P61A18/P62A19/P63A20/P64A21/P65VSSA22/P66A23/P67A24/EOP0AVCCAVRHAVSS/AVRLAN0AN1AN2AN3

SO

0/P

F1/

TR

G1

SC

0/P

F2/

OC

PA

3S

I1/P

F3/

TR

G2

SO

1/P

F4/

TR

G3

SI2

/PF

5/O

CP

A1

SO

2/P

F6/

OC

PA

2P

F7/

OC

PA

0/A

TG

XD

AC

K1/

PE

7D

AC

K0/

PE

6D

RE

Q1/

PE

5D

RE

Q0/

PE

4IN

T3/

PE

3/S

C2

INT

2/P

E2/

SC

1V

SS

5X

1X

0V

CC

INT

1/P

E1

INT

0/P

E0

RA

S0/

PB

0C

S0L

/PB

1C

S0H

/PB

2D

W0X

/PB

3R

AS

1/P

B4/

EO

P2

SI0

/PF

0/T

RG

0A

07A

06A

05A

04A

03A

02A

01V

CC

5A

00D

31V

SS

D30

D29

D28

D27

D26

D25

D24

P27

/D23

P26

/D22

P25

/D21

P24

/D20

P23

/D19

P22

/D18

P21

/D17

7778798081828384858687888990919293949596979899100 76

494847464544434241403938373635343332313029282726 50

25242322212019181716151413121110987654321

51525354555657585960616263646566676869707172737475

( T O P V I E W )

F P T - 1 0 0 P - M 0 5

13



The following figure shows a diagram of package external dimensions (reference diagram).

Diagram of External Dimensions (Reference Diagram)

Figure 1.6-1 Diagram of External Dimensions (FPT-100P-M06)

0. 65mm

14 20mm

0. 80mm

(FPT-1 00P-M06 )

Plastic/QFP, 100 pins Lead pitch

Package width X

Lead form Gull-wing

Packaging Plastic molding

Pin flat

package length

section length

Plastic/QFP, 100 pins

Unit: mm (inches)

EIAJ code: *QFP100-P-1420-4

0.18(.007)MAX

14

CHAPTER 1 OVERVIEW

Figure 1.6-2 Diagram of External Dimensions (FPT-100P-M05)

0. 50mm

14 14mm

(FPT-1 00P-M05)

Plastic/LQFP, 100 pins Lead pitch

Package width X

Lead form Gull-wing

Packaging Plastic molding

package length

Plastic/LQFP, 100 pins

Unit: mm (inches)

EIAJ code: *QFP100-P-1414-1

15

1.7 List of Pin Descriptions


The following table shows a list of pin descriptions.

List of Pin Descriptions

Table 1.7-1 shows a list of pin functions. For a diagram of pin arrays, see Figures 1.5-1 and1.5-2 (Note that the pin numbers are different in QFP and SQFP).

Note that NO. in the table is not the pin number of PKG.

Table 1.7-1 Pin Description

Pin no. Pin name Circuit type

Function

LQFP*1 QFP*2

25 to 32 28 to 35 D16 to D23 C Bit 16 to bit 23 of external data bus

P20 to P27 Can be configured as I/O ports when external data bus width is set to 8-bit.

33 to 39, 41

36 to 42, 44

D24 to D30, D31

C Bit 24 to bit 31 of external data bus

42,44 to 58

45, 47 to 61

A00, A01 to A15

F Bit 00 to bit 15 of external address bus

59 to 64, 66, 67

62 to 67, 69, 70

A16 to A21, A22, A23

F Bit 16 to bit 23 of external address bus

P60 to P65, P66, P67

Can be configured as I/O ports when not used address bus.

68 71 A24 L Bit 24 of external address bus

EOP0 Can be configured as DMAC EOP output (ch.0) when DMAC EOP output is enabled.

19 22 RDY L External ready inputInputs "0" when bus cycle is being executed and not completed.

P80 Can be configured as a port when RDY is not used.

20 23 BGRNT F External bus release acknowledge outputOutput "L" level when external bus is released.

P81 Can be configured as a port when BGRNT is not used.

21 24 BRQ C External bus release request inputInputs "1" when release of external bus is required.

P82 Can be configured as a port when BRQ is not used.

16

CHAPTER 1 OVERVIEW

22 25 RD L Read strobe output pin for external bus

23 26 WR0 L Write strobe output pin for external busRelation between control signals and effective byte locations is as follows:

24 27 WR1 F Note: WR1 is Hi-Z during resetting. Attach an external pull-up resister when using at 16-bit bus width.

P85 Can be configured as a port when WR1 is not used.

11 14 CS0 L Chip select 0 output ("L" active)

10 13 CS1 F Chip select 1 output ("L" active)

PA1 Can be configured as a port when CS1 is not used.




PA3 Can be configured as a port when CS3 and EOP1 are not used.

EOP1EOP output pin for DMAC (ch.1) This function is available when EOP output for DMAC is enabled.





5 8 CLK F System clock output Output clock signal of external bus operating frequency.

PA6 Can be configured as a port when CLK is not used.

96 99 RAS0 F RAS output for DRAM bank 0Refer to the DRAM interface for details.

PB0 Can be configured as a port when RAS0 is not used.



Function

LQFP*1 QFP*2

16-bit bus width 8-bit bus width

D15 to D08

D15 to D00

WR0

WR1

WR0

(I/O port enabled)

17


97 100 CS0L F CASL output for DRAM bank 0Refer to the DRAM interface for details.

PB1 Can be configured as a port when CS0L is not used.

98 1 CS0H F CASL output for DRAM bank 0Refer to the DRAM interface for details.

PB2 Can be configured as a port when CS0H is not used.

99 2 DW0 F WE output for DRAM bank 0 ("L" active)Refer to the DRAM interface for details.

PB3 Can be configured as a port when DW0 is not used.

100 3 RAS1 F RAS output for DRAM bank 1Refer to the DRAM interface for details.

PB4 Can be configured as a port when RAS1 and EOP2 are not used.

EOP2 DMAC EOP output (ch.2)This function is available when DMAC EOP output is enabled.

1 4 CS1L F CASL output for DRAM bank 1Refer to the DRAM interface for details.

PB5 Can be configured as a port when CS1L and DREQ2 are not used.

DREQ2 External transfer input pin for DMAThis pin is used for input when external trigger is selected to cause DMAC operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.

2 5 CS1H F CASH output for DRAM bank 1Refer to the DRAM interface for details.

PB6 Can be configured as a port when CS1H and DACK2 are not used.

DACK2 External transfer input pin for DMAC (ch.2)This function is available when tranfer request output for DMAC is enabled.

3 6 DW1 F WE output for DRAM bank 1 ("L" active)Refer to the DRAM interface for details.

PB7 Can be configured as a port when DW1 is not used.

16 to 18 19 to 21 MD0 to MD2

G Mode pins 0 to 2MCU basic operation mode is set by these pins.Directly connect these pins with Vcc or Vss for use.

92 95 X0 A Clock (oscillator) input



Function

LQFP*1 QFP*2

18

CHAPTER 1 OVERVIEW

91 94 X1 A Clock (oscillator) input

14 17 RST B External reset input

13 16 HST H Hardware standby input ("L" active)

12 15 NMI H NMI (non-maskable interrupt pin) input ("L" active)

95, 94 98, 97 INT0, INT1 F External interrupt request input pinsThese pins are used for input during corresponing interrupt is enabled, and it is necessary to disable output for other functions from these pins unless such output is made intentionally.

PE0, PE1 Can be configured as a I/O port when INT0, INT1 are not used.

89 92 INT2 F External interrupt request input pinThis pin is used for input during corresponing interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.

SC1 Clock I/O pin for UART1Clock output is available when clock output of UART1 is enabled.

PE2 Can be configured as a I/O port when INT2 and SC1 are not used.This function is available when UART1 clock output is disabled.

88 91 INT3 F External interrupt request input pinThis pin is used for input during corresponing interrupt is enabled, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.

SC2 Clock I/O pin for UART2Clock output is available when clock output of UART2 is enabled.

PE3 Can be configured as a I/O port when INT3 and SC2 are not used.This function is available when UART2 clock output is disabled.

87, 86 90, 89 DREQ0, DREQ1

F External transfer request input pins for DMAThese pins are used for input when external trigger is selected to cause DMA operation, and it is necessary to disable output for other functions from these pins unless such output is made intentionally.

PE4, PE5 Can be configured as a I/O port when DREQ0, DREQ1 are not used.



Function

LQFP*1 QFP*2

19


85 88 DACK0 F External transfer request acknowledge output pin for DMAC (ch.0)This function is available when transfer request output for DMAC is enabled.

PE6 Can be configured as a I/O port when DACK0 is not used.This function is available when transfer request acknowledge output for DMAC or DACK0 output is disabled.

84 87 DACK1 F External transfer request acknowledge output pin for DMAC (ch.1)This function is available when transfer request output for DMAC is enabled.

PE7 Can be configured as a I/O port when DACK1 is not used.This function is available when transfer request acknowledge output for DMAC or DACK1 output is disabled.

76 79 SI0 F UART0 data input pin.This pin is used for input during UART0 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.

TRG0 PWM timer external trigger input pinThis pin is used for input during PWM timer external trigger is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.

PF0 Can be configured as a I/O port when SI0 and TRG0 are not used.

77 80 SO0 F UART0 data input pin.This function is available when UART0 data output is enabled.

TRG1 PWM timer external trigger input pinThis function is available when serial data output of PF1, UART0 are disabled.

PF1 Can be configured as a I/O port when SO0 and TRG1 are not used.This function is available when serial data output of UART0 is disabled.



Function

LQFP*1 QFP*2

20

CHAPTER 1 OVERVIEW

78 81 SC0 F UART0 clock I/O pin.Clock output is available when UART0 clock output is enabled.

OCPA3 PWM timer output pinThis function is available when PWM timer output is enabled.

PF2 Can be configured as a I/O port when SC0 and OCPA3 are not used.This function is available when UART0 clock output is disabled.

79 82 SI1 F UART1 data input pin.This function is available when UART0 data output is enabled.

TRG2 PWM timer external trigger input pinThis pin is used for input during UART1 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.

PF3 Can be configured as a I/O port when SI1 and TRG2 are not used.

80 83 SO1 F UART1 data output pin.This function is available when UART1 data output is enabled.

TRG3 PWM timer external trigger input pinThis function is available when PF4, UART1 data outputs are disabled.

PF4 Can be configured as a I/O port when SO1 and TRG3 are not used.This function is available when UART1 data output is disabled.

81 84 SI2 F UART2 data input pin.This pin is used for input during UART2 is in input operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.


PF5 Can be configured as a I/O port when SI2 and OCPA1 are not used.



Function

LQFP*1 QFP*2

21


82 85 SO2 F UART2 data output pin.This function is available when UART2 data output is enabled.


PF6 Can be configured as a I/O port when SO2 and OCPA2 are not used.This function is available when UART2 data output is disabled.

83 86 OCPA0 F PWM timer output pinThis function is available when PWM timer output is enabled.

PF7 Can be configured as a I/O port when OCPA0 and ATG are not used.This function is available when PWM timer output is disabled.

ATG External trigger input pin for A/D converterThis pin is used for input when external trigger is selected to cause A/D converter operation, and it is necessary to disable output for other functions from this pin unless such output is made intentionally.

72 to 75 75 to 78 AN0 to AN3

D Analog input pins of A/D converterThis function is available when AIC register is set to specify analog input mode.

69 72 AVcc - Power supply pin (Vcc) for A/D converter

70 73 AVRH - Reference voltage input (high) for A/D converterMake sure to turn on and off this pin with potential of AVRH or more applied to Vcc.

71 74 AVss/AVRL

- Power supply pin (Vss) for A/D converter and reference voltage input pin (low)

43, 93 46, 96 Vcc5 - 5 V power supply pin (Vcc) for digital circuitAlways two pins must be connected to the power supply (connect to 3 V power supply when operating at 3 V).

4 7 Vcc3 - Bypass capacitor pin for internal capacitor.Also connect this pin to 3 V power supply when operating at 3 V.

15, 40, 65, 90

18, 43, 68, 93

Vss - Earth level (Vss) for digital circuit



Function

LQFP*1 QFP*2

22

CHAPTER 1 OVERVIEW

DRAM Control Pins

*1: FPT-100P-M05

*2: FPT-100P-M06

Note: In most of the above pins, I/O port and resource I/O are multiplexed e.g. P82 and BRQ. Incase of conflict between output of I/O port and resource I/O, priority is always given to the output of resource I/O.

Table 1.7-2 DRAM control pins

Pin Data bus in 16-bit mode Data bus in 8-bit mode

Remarks

2CAS/1WR mode

1CAS/2WR mode

-

RAS0 Area 4 RAS Area 4 RAS Area 4 RAS Relationship between L and H and the lower one bit (A0) of the address when the data bus is in 16-bit mode:"L" : "0""H" : "1"CASL: CAS corresponding to an area where A0 is "0"CASH: CAS corresponding to an area where A0 is "1"WELX: WEX corresponding to an area where A0 is "0"WEHX: WEX corresponding to an area where A0 is "1"

RAS1 Area 5 RAS Area 5 RAS Area 5 RAS

CS0L Area 4 CASL Area 4 CAS Area 4 CAS

CS0H Area 4 CASH Area 4 WELX Area 4 CAS


CS1H Area 5 CASH Area WELX Area 5 CAS

DW0X Area 4 WEX Area 4 WEHX Area 4 WEX

DW1X Area 5 WEX Area 5 WEHX Area 5 WEX

23

1.8 Input/Output Circuit Types


Table 1.8-3 lists the input/output circuit types.

Input/Output Circuit Types

Table 1.8-1 Input/Output Circuit Forms

Classification Circuit form Remarks

A • Oscillation feedback resistance 1 MΩ approx.With standby control

B • CMOS levelHysteresis inputWithout standby controlWith pull-up resistor

X1

X0

Standby control signal

Clock input

Vcc

VSS

N-ch

Digital input

R

P-ch P-ch

24

CHAPTER 1 OVERVIEW

C • CMOS level I/OWith standby control

D Analog input

E • N-channel open-drain output• CMOS level input

With standby control

Table 1.8-1 Input/Output Circuit Forms (Continued)



Digital output

Digital output

Digital input

P-ch

N-chR

Digital output

Digital output

Analog input

R

P-ch

N-ch


Digital input

Digital output

P-ch

N-chR

25


F • CMOS level output• CMOS level

Hysteresis inputWith standby control

G • CMOS level inputWith standby control

H • CMOS levelHysteresis inputWith standby control

I • CMOS level out• CMOS level

Hysteresis inputWithout standby control




Digital output

Digital output

Digital input

P-ch

N-chR

Digital input

P-ch

N-chR

Digital input

R

P-ch

N-ch

Digital input

Digital output

Digital outputR

P-ch

N-ch

26

CHAPTER 1 OVERVIEW

J • CMOS level output• TIL level input

With standby control

K • CMOS level input/outputWith standby control

• Large current drive

L • CMOS level output



Standby control signalTTL

Digital output

Digital output

Digital input

R

P-ch

N-ch

Digital output

Digital output

Digital input


R

P-ch

N-ch

Digital output

Digital output

P-ch

N-ch

27

CHAPTER 2 Precautions for Handling the Devices

This chapter explains precautions when particular devices required for both MB91101 and MB91101A are handled and used.

2.1 Precautions for Handling the Pins and Circuits

2.2 Precautions when Using Each Device

2.3 Precautions for Power-on

28



This section explains about latch-up prevention, handling of pin processing, and circuit handling.

Latch-up Prevention

The latch-up phenomenon may occur in CMOS IC if a voltage higher than Vcc or lower than Vssis applied to the input pin or output pin, or if a voltage exceeding the rated voltage is appliedbetween Vcc and Vss. If the latch-up phenomenon occurs, the supply current increases rapidly,leading to thermal damage of elements. Thus, sufficient care must be taken to ensure that themaximum voltage rating is not exceeded when using the device.

Handling of Pin Processing

Processing of an unused input pin

If an unused input pin is left open, a malfunction may occur. Thus, perform pull-up or pull-downprocessing.

Processing of an NC pin

Be sure to use the NC pin in an open state.

Processing of an output pin

A large current may flow if the output pin is short-circuited to the power supply or another outputpin, or a large-capacity load is connected. Since the device deteriorates if such as state lastsfor a long time, sufficient care must be taken to ensure that the maximum voltage rating is notexceeded when using the device.

Processing of a power pin

If there are multiple Vcc and Vss, voltages to be the same are connected inside a device toprevent malfunctioning such as latch-up when designing the device. Be sure to connect allvoltages to the power supply and ground externally for reducing unnecessary radiation,preventing malfunctioning of the strobe signal due to the rising ground level, and obeying thetotal output current standard.

Also, consideration should be given to connecting Vcc/Vss of this device with as low animpedance as possible from the current source.

We recommend connecting a ceramic capacitor of about 0.1 (F between Vcc and Vss near thisdevice as a bypass capacitor.

Processing of a mode pin (MD0 to MD2)

Use these pins by connecting them directly to Vcc or Vss. To prevent the device from enteringthe test mode accidentally due to noise, make the pattern length between each mode pin andVcc/Vss on the printed circuit boards as short as possible so that the pins can be connected at alow impedance.

29


Circuit Handling

Handling of a crystal oscillator circuit

Noise in the vicinity of the X0 and X1 pins may cause a malfunction in the device. Design theprinted circuit board so that X0, X1, the crystal oscillator (or ceramic oscillator), and the bypasscapacitor are as close to the ground as possible.

Printed circuit board setting

Since stable operation can be expected from an art work of printed circuit boards surroundingthe X0 and X1 pins with the ground, it is strongly recommended.

30



This section explains precautions when using the external reset input, external clock, and built-in DC-DC regulator.

Precautions when Using External Reset Input

To make the internal state a reset state by entering the "L" level to the RSTX pin, at least fivemachine cycles of the "L" level input to the RSTX pin are required.

Precautions when Using an External Clock

To use an external clock, supply in principle a clock of the phase opposite X0 to the X0 pin orX1 pin. However, if the STOP mode (oscillation stop mode) is used, add a resistor of about 1KΩ externally to avoid output collision because the X1 pin stops with the "H" output in STOPmode.

An external clock limited to 12.5 MHz or below can be used in a circuit connection in which thesupply clock is connected to X0 pin alone when 5V supply voltage is used.

The following figures are two examples of how to use the external clock.

Figure 2.2-1 Example of Using an External Clock (Normal Case)

Figure 2.2-2 Example of Using an External Clock (Possible Only If Vcc=5V, and 12.5 MHz or Below)

Precautions when Using the Built-in DC-DC Regulator

Since MB91101/MB91101A contains a regulator, be sure to supply 5V to the Vcc5 pin andattach a bypass capacitor of about 0.1 µF to the Vcc3 pin for the regulator when the 5V powersupply is used.

A separate 3V power supply is needed for the A/D converter.

When the device is operated by the 3V power supply, connect both the Vcc5 and Vcc3 pins tothe 3V power supply.

The following figure shows two examples of power supply connection.

X0

X1MB91101/MB91101A

X0

OPEN X1MB91101/MB91101A

31


Figure 2.2-3 Example of Power Supply Connection (When Operating with 5V Power Supply)

Figure 2.2-4 Example of Power Supply Connection (when Operating with 3V Power Supply)

Precautions Using the STOP Mode

The regulator contained in MB91101/MB91101A stops in STOP mode. The internal 3V powersupply may drop below the operation guarantee voltage because the leak current (ICCH)increases in STOP mode or because the regulator stops in normal operation due tomalfunctioning resulting from noise or power failures. Thus, if the built-in regulator is used andthe STOP mode is used with the 5V power, be sure to supply power from outside so that the 3Vpower supply does not drop. If the 3V power supply drops, the built-in regulator can berestarted by the reset input (In this case, set the reset to the L level during oscillationstabilization wait time tosc).

The following figure is an example of using STOP mode with a 5V power supply.

Figure 2.2-5 Example of a 5V Power Supply when STOP Mode

5V

3V

Vcc5 Vcc3

AVcc

AVRH

AVss

Vss

GND

3V

Vcc5 Vcc3

AVcc

AVRH

AVss

VssGND

VCC5

VCC3

VSS

5V

32


2.3 Precautions for Power-on

This section explains precautions for the pins and input during power-on.

Processing of the RSTX Pin

Be sure to start the RSTX pin from the "L" level for power-on, and then set the pin to the "H"level only after the power supply reaches the Vcc level by securing at least five cycles of theinternal operating clock.

Pin State

The state of pins during power-on is unstable. The circuits are initialized after the oscillation isstarted by power-on and the operation of the built-in regulator becomes stable. Thus, about 42ms are required from the start of oscillation to circuit initialization for the source clock frequency12.5 MHz (For MB91101A, only the pin state is initialized to that before the wait time of about 42ms by setting the RSTX pin to the "L" level after the internal power is started up).

Precautions during Input of Source Clock Frequency

During power-on, be sure to supply the clock until the oscillation wait state is released.

Hardware Standby

If the device is turned on with the HSTX pin set to the "L" level, the standby mode is notentered. Though the HSTX pin is enabled after the reset is released, it is necessary to set thepin to the "H" level.

Power-on Reset

Be sure to enable the power-on reset when the device is turned on again after the supplyvoltage drops below the operation guarantee voltage during power-on.

Turn on the power in the following order:

When 5V is used: Vcc5 --> AVCC -->AVRH

When 3V is used: Vcc5 + Vcc3 --> AVCC -->AVRH

33

CHAPTER 3 CPU AND CONTROLLERS

This chapter explains the memory space of MB91101/MB91101A, CPU, and each controller.

3.1 Memory Space

3.2 CPU

3.3 Outline of Instructions

3.4 Instruction Cache

3.5 Programming Models and Registers

3.6 Data Structure

3.7 Branch Instruction

3.8 EIT (Exception/Interrupt/Trap)

3.9 Reset Sequence

3.10 Operation Mode

3.11 Clock Generator

34


3.1 Memory Space

4 GB (232 addresses) of logical address space is available for the FR series, and CPU accesses the space linearly.

Memory Space

Direct addressing area

The following area of the address space is used for I/O. This area is called the directaddressing area and its addresses can be specified directly for operands in instructions. Thedirect addressing area differs depending on the size of data to be accessed as shown below.

• byte data access---0-0FFH

• half word data access---0-1FFH

• word data access---0-3FFH

Memory map

The following figure shows the memory space of this product type.

35

3.1 Memory Space

Figure 3.1-1 Memory Map

I/O map

See the Appendix.

0000 0000H

I/O

0000 0400H

I/O

0000 0800H

0000 1000H

0000 1800H

0001 0000H

FFFF FFFFH

External ROM/external bus mode


See I/O Map (Appendix A)

Access prohibited

Built-in RAM

External area

Access prohibited

- This product type has the above mode only.

36


3.2 CPU

FR CPU is a high-performance core that adopts then RISC architecture and at the same introduces advanced instructions for embedded use.

CPU

• Adoption of the RISC architecture

• Basic instruction 1 instruction/1 cycle

• 32-bit architecture

• General-purpose register 32-bit X 16

• Linear memory space of 4 GB

• On-board multiplier

• 32-bit X 32-bit multiplication 5 cycles

• 16-bit X 16-bit multiplication 3 cycles

• Enhancement of the interrupt processing function

• High response speed (6 cycles)

• Multi-interrupt support

• Level mask function (16 levels)

• Enhancement of the I/O operation instructions

• Memory-memory transfer instruction

• Bit processing instruction

• High code efficiency

• Basic instruction word length 16-bit

• Power saving

• Sleep mode/stop mode

Internal Architecture

CPU of FR adopts the Harvard architecture in which the instruction bus and data bus areindependent. The on-chip instruction cache is connected to the instruction bus (I-BUS).

The bus converter for 32-bit <--> 16-bit conversion is connected to the data bus (D-BUS) toimplement the interface between CPU and peripheral resources. The bus converter for Harvard<--> Princeton conversion is connected to both I-BUS and D-BUS to implement the interfacebetween CPU and the bus controller. Figure 3.2-1 shows the internal architecture.

37

3.2 CPU

Figure 3.2-1 Internal Architecture

Pipeline System of CPU

CPU implements FR architecture of 32-bit RISC in a compact fabrication. To execute oneinstruction per cycle, the 5-stage instruction pipeline system is adopted. The pipeline consistsof the following stages.

• Instruction fetch (IF)---Outputs an instruction address to fetch an instruction.

• Instruction decode (ID)---Decodes a fetched instruction. The registers are also read.

• Execution (EX)---Executes an operation.

• Memory access (MA)---Accesses memory for a load operation or store operation.

• Write back (WB)---Writes an operation result (or loaded memory data) into a register.

32

I-ADDR

16

I-DATA

3232bit

D-ADDR

16bit 32

D-DATA

16 32

Instruction cache

bus converter

Resources

Harvard

Princeton

bus converter

Bus controller

38


Figure 3.2-2 Instruction Pipeline

Instructions are not executed in random order. That is, if instruction A enters the pipeline priorto instruction B, instruction A always reaches the write back stage before instruction B.

Instructions are executed in principle on one instruction per cycle basis.

However, multiple cycles are required for the load/store instructions with memory wait, branchinstructions without delay slots, and multi-cycle instructions. Also, the execution speed ofinstructions slows down if the supply of instructions is delayed.

Instruction Cache

Thanks to the on-chip instruction cache, a high-performance system can be built withoutgenerating costs involved in external high-speed memory and control logic related to memory.Also, if the external bus speed is slow, the speed of instructions supplied to CPU can beincreased.

Details on the instruction cache will be provided later.

32-bit<---->16-bit bus converter

D-BUS accessed at high speed with a 32-bit width and R-BUS accessed with a 16-bit width areinterfaced by this converter to implement data access from CPU to the built-in peripheralcircuits.

If a peripheral circuit is accessed by CPU with a 32-bit width, this converter converts the accessinto two 16-bit access operations to access R-BUS. Some built-in peripheral circuits arerestricted in terms of access width.

Harvard <----> Princeton bus converter

This converter implements a smooth interface with external buses by matching the instructionaccess and data access of CPU.

CPU has the Harvard architecture in which the instruction bus and data bus are independent.The bus controller that controls external buses, on the other hand, has the Princetonarchitecture of the single bus. This bus converter prioritizes instruction access and data accessof CPU to control access to the bus controller. In this way, the access order to external buses isalways optimized.

Also, this bus converter has a 2-word write buffer to eliminate the bus wait time of CPU and a 1-word pre-fetch buffer for instruction fetch.

Instruction 1

Instruction 2

Instruction 3

Instruction 4

Instruction 5

Instruction 6

39



FR supports, in addition to a general RISC instruction system, the logical operations and bit manipulations optimized for embedded use and direct addressing instructions.

Outline of Instructions

A set of instructions can be found in the Appendix. Each instruction has a 16-bit length (Someinstructions have 32- or 48-bit length) and so higher memory utilization ratio can be achieved.

• Arithmetic operation

• Load and store

• Branch

• Logical operation bit manipulation

• Direct addressing

• Others

Arithmetic operation

Standard arithmetic operation instructions (addition, subtraction, and comparison) and shiftinstructions (logical shift and arithmetic operation shift) are provided. Arithmetic operations ofaddition and subtraction can include operations with carry used in multi-word length operationsand operations suitable for address calculation in which flag values are not changed.

Also, 32-bit X 32-bit and 16-bit X 16-bit multiplication instructions and 32-bit/32-bit step divisioninstructions are provided.

Furthermore, the immediate transfer instruction that sets immediate data to the registers and theregister-to-register transfer instruction are provided.

All arithmetic operation instructions use the general-purpose registers and multiply & divideregister for operations.

Load and store

Load and store are instructions for performing read and write operations for external memory.These instructions can also be used for read and write operations of peripheral circuits (I/O) inthe chip.

Load and store have the access lengths of the byte, half-word and word. In addition to generalregister indirect memory addressing, some instructions can perform displacement registerindirect memory addressing and register increment/decrement register indirect memoryaddressing.

Branch

Instructions for branch, call, interrupt, and return operations. Because some branch instructionshave delay slots and others do not, application optimization is possible.

Details on the branch instructions are provided in APPENDIX.

Logical operation and bit manipulation

Logical operation instructions can perform logical operations between general-purpose registersor between a general-purpose register and memory (and I/O). Bit manipulation instructions can

40


manipulate memory (and I/O) contents directly. Memory addressing is general register indirect.

Direct addressing

Direct addressing instructions are used for access between I/O and general-purpose registersor between I/O and memory. By addressing directly for I/O instead of indirectly throughregisters in instructions, high-speed high-efficiency access is possible.

Some instructions can perform register increment/decrement register indirect memoryaddressing.

Others

Instructions to perform flag settings in the PS register, stack manipulation, and code/zeroextension. The function entry/exit and register multi-load/-store instructions compliant with high-level languages are also provided.

41



The instruction cache is temporary memory. When accessing instruction code from external low-speed memory, the instruction cache is used to speed up the access speed of the accessed instruction code by holding it internally.

Instruction Cache

The instruction cache and instruction cache tag cannot be accessed directly for read/writeoperations by software.

To turn off the instruction cache after turning it on, be sure to use the subroutine described in"Precautions" of "3.4.4 How to set I-Cache for use".

Structure of the instruction cache

• Basic instruction length of FR: 2 bytes

• Block: Two way sets associative

• Block: One way consists of 32 blocks. One block consists of 16 bytes, that corresponds to 4sub-blocks; one sub-block consists of 4 bytes, that corresponds to data length per busaccess.

Figure 3.4-1 I-CACHE-1 Instruction Cache Configuration

4 bytes4 bytes

13

4 bytes

12

4 bytes

11

4 bytes

10

32 blocks

32 blocks

Way 2

Block 0

Block 31

Block 0

Block 31

Way 1

Cache tag

Cache tag

Cache tag

Cache tag

Sub-clock 3

Sub-clock 3

Sub-clock 3

Sub-clock 3

Sub-clock 2

Sub-clock 2

Sub-clock 2

Sub-clock 2

Sub-clock 1

Sub-clock 1

Sub-clock 1

Sub-clock 1 Sub-clock 0

Sub-clock 0

Sub-clock 0

Sub-clock 0

42


Figure 3.4-2 I-CACHE-2 Instruction Cache Tag

• Bit 31 to 9 Address tag

• Bit 7 to 4 Sub-block valid

• Bit 3 TAG valid bit

• Bit 1 LRU (Way 1 only)

Way 1

SBV3

31

Address tag Free

09 08

SBV2 SBV1 SBV0 TAGV LRU ETLK

07 06 05 04 03 02 01 00

TAG validSub-block valid

LRUEntry clock

Way 2

SBV3

31

Address tag Free

09 08

SBV2 SBV1 SBV0 TAGV ETLK

07 06 05 04 03 02 01 00

TAG validSub-block valid

Entry clock

Free

Free

High-order 23 bits of the memory address of an instruction cached in the relevant block are stored.The memory address IA of the instruction data stored in the sub-block k of the block i can be calculated in the following way; IA = address tag x 211 + i x 24 + k x 22.This tag is used to check matching of the instruction address requested by CPU for access. The following is the response in accordance with the result of the tag checking.1. If the requested instruction data exists in the cache (hit), the data is transferred from

the cache to CPU in the same cycle.2. If the requested instruction data does not exist in the cache (miss), the data acquired

from external access is acquired by CPU and cache simultaneously.

If SBV* = 1, the current instruction data of the address indicated by the tag has been entered in the corresponding sub-block.Normally, two instructions are stored in one sub-block (excluding immediate transfer instructions).

This bit indicates whether the address tag value is valid. If this bit is 0, this block becomes invalid regardless of the sub-block valid bits (for flush).

This bit exists only in the instruction cache tag of the way 1.This bit indicates to which way (way 1 or way 2) the entry accessed last belongs for the selected set. If LRU=1, an entry in way 1 was accessed last. If LRU=0, an entry in way 2 was accessed last.

43


• Bit 0 Entry lock

This bit locks all entries inside the block corresponding to the tag to the cache.When ETLK = 1, the cache is locked and entries are not updated if a cache miss occurs. However, invalid sub-blocks are updated.If a cache miss occurs when both way 1 and way 2 are entry-blocked, external memory is accessed after one cycle used for cache miss determination.

44


3.4.1 Control Register Configuration

ICHCR (I-CacHe Control Register) controls operation of the instruction cache.The write operation to ICHCR does not affect cache operations of instructions fetched within three cycles after the write operation.

Control Register Configuration

Figure 3.4-3 I-CACHE-3 Instruction Cache Control Register (ICHCR)

• Bit 5 Global lock

• Bit 4 Auto lock fail

• Bit 3 Entry auto lock

06 05 04 03

- GBLK - ALFL EOLK ENABELKR ELSH

07 04 05 06 Initial value Access

--000000 R/W

Global lock

Auto lock fail

Entry auto lock

Entry unlock

Flush

Enable

Address

This bit locks all current entries.When GBLK = 1, valid entries in the cache are not updated if a cache miss occurs.However, invalid sub-blocks are updated. Instruction data fetch operations are the same as those when the cache is not locked.Also when the global lock is valid, the penalty of one cycle is inflicted.

ALFL = 1 is set if there is an attempt to lock a locked entry.If an update of an entry-auto-locked entry is attempted for a locked entry, the new entry is not locked in the cache. This bit is referenced for debugging such programs and can be cleared by inputting "0".

This bit switches enable/disable of auto locking for each entry in the instruction cache. An entry accessed (only if missed) when EOLK = 1 is locked by setting the entry lock bit in the cache tag to 1 through hardware. Locked entries are then not updated if a cache miss occurs. However, invalid sub-blocks are updated. To lock entries reliably, set this bit after flushing it.

45


• Bit 2 Entry unlock

<Precautions>

Do not entry-unlock (ELKR=1) when the instruction cache enable (ENAB=1) is set.

• Bit 1 Flush

This bit instructs the instruction cache to be flushed.

If FLSH = 1, the cache contents are flushed. Note that the content of this bit is held in one clockcycle and is cleared to 0 in the 2nd and following clock cycles.

<Precautions>

Do not flush (FLSH=1) when the instruction cache enable (ENAB=1) is set.

• Bit 0 Enable

This bit switches enable/disable of the instruction cache. When ENAB = 0, the cache isdisabled and instruction access from CPU is performed directly from external memory,bypassing the cache. In the disabled state, cache contents are preserved.

This bit instructs all entry block bits in the cache tag to be cleared.In the next cycle after setting ELKR = 1, all entry block bits in the cache tag are cleared to 0. Note that the content of this bit is held in one clock cycle and is cleared to 0 in the 2nd and following clock cycles.

46


3.4.2 Cache States in Each Operation Mode

The disable/flush indicate the states after bits only are changed by bit manipulation instructions.

Cache States in Each Operation Mode

Table 3.4-1 Cache States in Each Operation Mode

After reset Disable Flush

Cache memory Contents are undefined

State just before being held. Rewrite while disabled is not possible.

State just before being held.

Tag Address tag

Contents are undefined



Sub-block valid bit




LRU Contents are undefined



Entry lock bit



State just before being held (entry unlock required).

Tag valid bit


State just before being held. Flush while disabled is possible.

All entries are invalid.

47


Update of Cache Entries

Entries in the cache are updated in the following way.

Control register

Global lock Unlock State just before being held. Rewrite while disabled is possible.


Auto lock fail

No fail State just before being held. Rewrite while disabled is possible.


Entry auto lock

Unlock State just before being held. Rewrite while disabled is possible.


Entry unlock

No unlock State just before being held. Rewrite while disabled is possible.


Enable Disable Disable State just before being held.

Flush No flush State just before being held. Rewrite while disabled is possible.

Flush in the cycle just after memory access, then return to 0.

Table 3.4-1 Cache States in Each Operation Mode (Continued)

After reset Disable Flush

Table 3.4-2 Update of Cache Entries

Unlock Lock

Hit Do not update Do not update

Miss Memory is loaded to update cache entries.

No update for tag misses. Update if the sub-block is invalid.

48


3.4.3 Cacheable Area of the Instruction Cache

The instruction cache makes all space cacheable areas.

Cacheable Area

• In products with a built-in ROM, the built-in ROM can be made the target for caching.

• It is assumed that no instruction access is made to any space other than that of externalareas and the built-in ROM. Thus, if instruction access is made to the control register in theI/O area, it is not the target for caching.

• If the contents of external memory are updated by DMA transfer, coherency with the cache isnot maintained. In such a case, it is necessary to maintain coherency by flushing the cache.

49


3.4.4 How to Set I-Cache for Use

The following shows how to set I-Cache for use.

How to Set I-Cache for Use

(1) Initialization

Before using I-Cache, cache contents must be cleared.

Clear past data by setting the Flash bit and ELKR bit of the register to "1".

This initializes the cache.

To clear the cache after starting, be sure to clear while it is cache-disabled.

(2) Enabling the cache (ON)

Set the ENAB bit to "1" to enable I-Cache.

Instruction access hereafter will be acquired by the cache.

The cache can be enabled simultaneously with the cache initialization.

ldi #0x000003e7, r0 // address of the I-Cache control register

ldi #0B00000110, r1 // FLSH bit (1st bit)

// ELKR bit (2nd bit)

stb r1, @r0 // write to the register


ldi #0B00000000, r1 // cache disable


ldi #0B00000010, r1 // FLSH bit (1st bit)



ldi #0B00000001, r1 // ENAB bit (0th bit)




// FLSH bit (1st bit)

// ELKR bit (2nd bit)


50


(3) Disabling the cache (OFF)

Set the ENAB bit to "0" to disable I-Cache.

This state is the same as that without cache and is ineffectual.

It may be better to disable the cache if the overhead of cache affects processing.

<Precautions>

Use the following subroutine to disable the cache.

• When used in a function call

• When the cache is disabled in a program

(4) Locking all contents in the cache

The cache can be locked so that the instructions currently in I-Cache should not be driven out.

Set the GBLK bit of the register to "1". If the ENAB bit is not set to "1", the cache is not enabledand so locked instructions in the cache cannot be used.




LDI #0x3e7,R0LDI #0,R1stb r1, @r0 ;cache offNOP ;Instruction additionNOP ;NOP ;RET ; RET ;RET ;

LDI #CACHE_OFF_EXIT,R2LDI #0x3e7,R0LDI #0,R1stb r1, @r0 ;cache offNOP ;Instruction additionNOP ;NOP ;JMP @R2 ; JMP @R2 ;JMP @R2 ;CACHE_OFF_EXIT:

ldi #0x000003e7, r0 //address of the I-Cache control register

ldi #0B001000001, r1 //ENAB bit (0th bit)

//GBLK bit (5th bit)

51


(5) Locking specific instructions to the cache

To lock a specific group of instructions (such as subroutines) to the cache, set the EOLK bit to"1" before executing these instructions.

Locked instructions are accessed like a high-speed internal ROM.

(6) Unlocking the cache

Lock information of instruction locked in (5) is released.

Since only lock information is released, locked instructions are replaced by new instructionsindividually according to the state of the LRU bit.

stb r1, @r0 //write to the register



// EOLK bit (3rd bit)



ldi #0B00000000, r1 // cache disable


ldi #0B00000100, r1 // ELKR bit (2nd bit)


52



This section explains the registers of CPU that are basic to programming. CPU registers can be divided into the following two groups.

Basic Programming Group

General-purpose register

The user can specify the purpose of use for each general-purpose register.

Figure 3.5-1 Basic Programming Model (General-purpose Register)

Special register

Special registers are used for specific purposes.

3 2 b i t s

[ I n i t i a l v a l u e ]

XXXX XXXXH

XXXX XXXXH

0000 0000H

53


Figure 3.5-2 Basic Programming Model (Special Register)

Detailed explanations of the register can be found in "3.5.1" to "3.5.8".

3 2 b i t s

P r o g r a m c o u n t e r

P r o g r a m s t a t u s SCR

T a b l e b a s e r e g i s t e r

R e t u r n p o i n t e r

S y s t e m s t a c k p o i n t e r

U s e r s t a c k p o i n t e r

M u l t i p l y & d i v i d e r e s u l t r e g i s t e r

54


3.5.1 General-purpose Register

The registers R0 to R15 are general-purpose registers and are used as accumulators and memory access pointers (fields that point to addresses) in a variety of operations. The user can specify the purpose of using each register.

General-purpose Register

Figure 3.5-3 General-purpose Register

Of the 16 registers, special uses are assumed for the following registers and so have specificinstructions.

• R13: virtual accumulator

• R14: frame pointer

• R15: stack point

The initial value after reset is not defined for R0 to R14. The initial value after reset for R15 is00000000H (SSP value).

3 2 b i t s

[ I n i t i a l v a l u e ]

XXXX XXXXH

XXXX XXXXH

0000 0000H

55


3.5.2 PS (Program Status)

PS is a register for holding the program status. This register is divided into ILM, SCR, and CCR (three parts).

PS (Program Status)

Undefined bits in the figure are all reserved bits. When the register is read, "0" is always readfrom these undefined bits.

CCR (Condition Code Register)

[bit 5] Stack flag

This flag specifies the stack pointer to be used as R15.

This flag is cleared to "0" by reset.

Set "0" to this flag before executing the RETI instruction.

[bit 4] Interrupt permission flag

This flag controls permission/prohibition of user interrupt requests.

31 20 16 10 8 7 0

[Initial value]

--00XXXXB

Value Description

0 SSP is used as R15. This flag is automatically set to "0" when EIT occurs (However, the value saved to the stack is that prior to being cleared).

1 USP is used as R15.

Value Description

0 User interrupt prohibited. This flag is cleared to "0" when the INT instruction is executed (However, the value saved to the stack is that prior to being cleared).

1 User interrupt permitted. User interrupt request mask processing is controlled by the value held by ILM.

56


This flag is cleared to "0" by reset.

[bit 3] Negative flag

This flag indicates the sign when the operation result is interpreted as an integer represented as2’s complement.

The initial state by the reset operation is not defined.

[bit 2] Zero flag

This flag indicates whether the operation result is 0 or not.


[bit 1] Overflow flag

This flag indicates whether overflow occurred as a result of operations by interpreting operandsused in the operations as integers represented by 2’s complements.


[bit 0] Carrier flag

This flag indicates whether carry or borrow from the highest-order bit occurred in the operations.


Value Description

0 Indicates that the operation result is a positive integer.

1 Indicates that the operation result is a negative integer.

Value Description

0 Indicates that the operation result is any value other than 0.

1 Indicates that the operation result is 0.

Value Description

0 Indicates that overflow did not occur as a result of operations.

1 Indicates overflow occurred as a result of operations.

Value Description

0 Indicates that neither carry nor borrow occurred.

1 Indicates that either carry or borrow occurred.

57


SCR (System Condition code Register)

[bit 10, 9] Step division flag

These flags hold intermediate data when step division is executed.

These flags must not be changed while division operations are being executed.

To perform other processing while step division operations are being executed, the value of thePS register is saved and then returned so that the step division restart can be guaranteed.


These flags are set by referencing the dividend and divisor after the DIVOS instruction isexecuted. These flags are forced to be cleared by execution of the DIVOU instruction.

[bit 8] Step trace trap flag

This flag is used to specify whether to enable the step trace trap.

This flag is initialized to "0" by the reset operation.

The step trace trap function is used by the emulator. These flags cannot be used in userprograms when an emulator is used.

ILM

This register holds the interrupt level mask value. The held by ILM is used for the level mask.

Interrupt requests are accepted only if the interrupt level of interrupt requests entering CPU isstronger than the level indicated by this ILM.

The level values range from 0 (00000B) (strongest) to 31 (11111B) (weakest).

The values that can be set from programs are restricted.

If the original value is 16 to 31, values that can be set as a new value is 16 to 31. If aninstruction in which 0 to 15 is set is executed, a value (specified value + 16) is transferred.

If the original value is 0 to 15, any value in the range of 0 to 31 can be set.

This flag is initialized to 15 (01111B) by the reset operation.

10

D1 D0 XX0B

[Ini t ia l value]

Value Description

0 Step trace trap is disabled

1 Step trace trap is enabled. At this point, user NMI and user interrupts are all prohibited.

58


3.5.3 PC (Program Counter)

PC is a program counter and indicates the address of the instruction being executed.

PC (Program Counter)

[bit 31-0]

The address of the instruction being executed is indicated by the program counter.

When PC is updated with execution of an instruction, the bit 0 is set to "0". Bit 0 can only bechanged to "1" by specifying an odd address as a branch destination address. However, bit 0 isinvalid even in this case and it is necessary to place instructions at any address having multiplesof 2.

The initial value by the reset operation is not defined.

P C

3 1 0

X X X X X X X X H

Ini t ia l value

59


3.5.4 TBR (Table Base Register)

TBR is a table base register and holds the first address of the vector table used for EIT processing.

TBR (Table Base Register)

The initial value by the reset operation is 000FFC00H.

T B R

3 1 0

0 0 0 F F C 0 0 H

Ini t ia l value

60


3.5.5 RP (Return Pointer)

RP is a return pointer and holds the address to which the subroutine returns.

RP (Return Pointer)

When executing the CALL instruction, the value of PC is transferred to this RP.

When executing the RET instruction, the value of RP is transferred to PC.


R P

3 1 0

X X X X X X X X H

Ini t ia l value

61


3.5.6 SSP (System Stack Pointer)

SSP is a system stack pointer.

SSP (System Stack Pointer)

If the S flag is "0", this register works as R15.

SSP can be specified.

This register can also be used as a stack pointer to specify the stack to save PS and PC whenEIT occurs.This register can also be used as a stack pointer to specify the stack to save PS andPC when EIT occurs.

The initial value by the reset operation is 00000000H.

S S P

3 1 0

0 0 0 0 0 0 0 0 H

Ini t ia l value

62


3.5.7 USP (User Stack Pointer)

USP is a user stack pointer.If the S flag is "1", this register works as R15.USP can be specified.

USP (User Stack Pointer)


This register cannot be used in the RETI instruction.

U S P

3 1 0

X X X X X X X X H

Ini t ia l value

63


3.5.8 Multiply & Divide Register

The multiply & divide registers are registers for multiplication/division and each has a 32-bit length.

Multiply & Divide Register


For multiplication

If a 32-bit X 32-bit multiplication operation is executed, the operation result of the 64-bit length isstored in the multiply & divide result store register in the following arrangement.

• MDH---high-order 32 bits

• MDL---low-order 32 bits

If a 16-bit X 16-bit multiplication operation is executed, the result is stored in the following way.

• MDH---undefined

• MDL---32-bit result

For division

When the calculation starts, the dividend is stored in MDL.

If a division operation is executed by the DIVOS/DIVOU, DIV1, DIV2, DIV3, and DIV4instructions, the result is stored in MDL and MDH.

• MDH---residue

• MDL---quotient

M D H

3 1 0

M D L

64


3.6 Data Structure

The data structure (layout) of FR is as follows:- Bit ordering: l ittle endian- Byte ordering: big endian

Data Structure

Bit ordering

FR adopts the little endian as bit ordering.

Byte ordering

FR adopts the big endian as byte ordering.

bit 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 130 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0

MSB LSB

M e m o r y bi t31 23 15 7 0

10101010 11001100 11111111 00010001bit7 0

n a d d r e s s 10101010

(n+1) a d d r e s s 11001100

(n+2) a d d r e s s 11111111

(n+3) a d d r e s s 00010001

65

3.6 Data Structure

3.6.1 Word Alignment

This section explains address assignment for program access and data access.

Program Access

Programs of FR must be placed at any address having multiples of 2.

The bit 0 of PC is set to "0" when PC is updated with the execution of an instruction.

Bit 0 can only be changed to "1" by specifying an odd address as a branch destination address.

However, the bit 0 is invalid even in this case and it is necessary to place instructions at anyaddress having multiples of 2.

There is no odd address exception.

Data Access

In the FR series, the forced alignment is performed to the addresses when data is accesseddepending on width as shown below.

Word access: The address is a multiple of 4 (The lowest 2 bits are forced to 00)

Half word access: The address is a multiple of 2 (The lowest bit is forced to 0)

Byte access: -

Addresses, some bits of which are forced to 0 during word and half word access, are the resultsof calculation of effective addresses. For example, in addressing mode of @(R13, Ri), registersbefore the addition (even if the lowest bit is 1) are used as is and the lowest bit as the result ofcalculation is masked. Registers before the calculation are not masked.

[Example]

LD@(R13,R2),R0

A d d i t i o n r e s u l t

F o r c e d m a s k i n g o f 2 l o w e s t b i t s

A d d r e s s p i n

66


3.6.2 Memory Map

The address space is linear with 32-bit addresses.

Memory Map

Figure 3.6-1 Memory Map

Direct Addressing Area

The following area in the address space is used for I/O. This area can be specified directly asan operand address in an instruction by using direct addressing.

The size of the address area that can be addressed by direct addressing depends on datalength.

• Byte data (8 bits)---0 to 0FFH

• Half word data (16 bits)---0 to 1FFH

• Word data (32 bits)---0 to 3FFH

Vector Table Initial Area

The area of 000FFC00H to 000FFFFFH is the EIT vector table initial area.

The vector table to be used for EIT processing can be placed at any address by rewriting TBR.This table is placed at this address by initializing the reset operation.

Series Common Memory Map

The FR series defines the memory map as shown in the following figure.

This memory map is common to all product types.

0000 0000H

0000 0100H

0000 0200H

0000 0400H

000F FC00H

000F FFFFH

FFFF FFFFH

Byte data

Half word data

Word data


Vector table initial area

67

3.6 Data Structure

Figure 3.6-2 Series Common Memory Map

<Precautions>

In single chip mode, the external area cannot be accessed.

(PDR)

Byte I /O

HalfWord I/O

Word I/O

1KB


Other I /O

Access prohibi ted

Bui l t - in RAM or

access prohibi ted

External area (*1)

Bui l t - in ROM or

external area (*1)Ini t ia l vector area

External area (*1)

*1: In s ingle chip mode, the external area cannot be accessed.

68



In the FR series, it is possible to specify either operation with a delayed slot or without a delayed slot for the branch instructions.

Operation with a Delayed Slot

Instruction

The following instructions perform a branch operation with a delayed slot.

Explanation of the Operation

In an operation with a delayed slot, before executing instructions at the branch destination, aninstruction just after the branch instruction (called the "delayed slot") is executed beforebranching.

Because an instruction in the delayed slot is executed before branching, the apparent executionspeed is 1 cycle. If no effective instruction can be inserted into the delayed slot, the NOPinstruction must be placed.

[Example]

For a conditional branch instruction, the instruction in the delayed slot is executed regardless ofwhether or not the branch condition is satisfied.

Though it seems that the order of execution of some instructions is reversed for delayed branchinstructions, this applies only to the update operation of PC; other operations (such as registerupdating and referencing) are executed in the described order.

JMP:D @Ri CALL:D label12 CALL:D @Ri RET:D

BRA:D label9 BNO:D label9 BEQ:D label9 BNE:D label9

BC:D label9 BNC:D label9 BN:D label9 BP:D label9

BV:D label9 BNV:D label9 BLT:D label9 BGE:D label9

BLE:D label9 BGT:D label9 BLS:D label9 BHI:D label9

; List of instructions

ADD R1, R2 ;

BRA:D LABEL ; Branch instruction

MOV R2, R3 ; Delayed slot---Executed before branching

:

LABEL : ST R3, @R4 ; Branch destination

69


The following are examples.

[Example]

[Example]

[Example]

[Example]

(1) Ri referenced by the JMP:D @Ri/CALL:D @Ri instructions is not affected even if the instruction in the delayed slot updates Ri.

LDI:32 #Label, R0

JMP:D @R0 ; Branch to Label

LDI:8 #0, R0 ; Branch destination address is not affected

:

(2) RP referenced by the RET:D instruction is not affected even if the instruction in the delayed slot updates RP.

RET:D ; Branch to the address indicated by RP set before here

MOV R8, RP ; Return operation is not affected

:

(3) Also the flag referenced by the Bcc:D rel instruction is not affected by the instruction in the delayed slot.

ADD #1, R0 ; Flag change

BC:D Overflow ; Branch depending on execution results of the above instruction

ANDCCR #0 ; This flag update is not referenced by the above branch instruction.

:

(4) If RP is referenced by the instruction in the delayed slot of the CALL:D instruction, the content updated by the CALL:D instruction is read.

CALL:D Label ; Branch after updating RP

MOV RP, R0 ; Transfer of RP in execution results of the above CALL:D

:

70


Restrictions

(1) Instructions that can be placed in the delayed slot

Only instructions that satisfy the following conditions can be placed in the delayed slot.

• 1-cycle instruction

• No branch instruction

• Instructions that do not affect operations even if the order of execution changes.

"1-cycle instructions" are those instructions whose field of the number of cycles in the list ofinstructions is "1", "a", "b", "c", or "d".

(2) Step trace trap

No step trace trap occurs between the execution of a branch instruction with a delay slot andthe delayed slot.

(3) Interrupt/NMI

No interrupt/NMI is accepted between the execution of a branch instruction with a delay slot andthe delayed slot.

(4) Undefined instruction exception

If the delayed slot contains an undefined instruction, no undefined instruction exception occurs.At this time, the undefined instruction operates as an NOP instruction.

Operation without Delayed Slot

Instruction

The following instructions perform a branch operation without delayed slot.

Explanation of the Operation

In the operation without delayed slot, instructions are executed in the order of listed instructions.There is no chance of an instruction just after the branch instruction executed before branching.

JMP @Ri CALL label12 CALL @Ri RET

BRA label9 BNO label9 BEQ label9 BNE label9

BC label9 BNC label9 BN label9 BP label9

BV label9 BNV label9 BLT label9 BGE label9

BLE label9 BGT label9 BLS label9 BHI label9

71


[Example]

The number of execution cycles for a branch instruction without delayed slot is 2 cycles ifbranched and 1 cycle if not branched.

The instruction code efficiency can be increased compared with branch instructions with adelayed slot in which NOP is clearly written down because a dummy instruction to be insertedinto the delayed slot no longer be required.

Execution speed and code efficiency can be achieved at the same time by selecting theoperation with a delayed slot when effective instructions are to be placed in or the operationwithout delayed slot when no instructions are to be placed in.

; List of instructions

ADD R1, R2 ;

BRA LABEL ; Branch instruction (without delayed slot)

MOV R2, R3 ; Not executed

:

LABEL : ST R3, @R4 ; Branch destination

72



EIT signifies executing other programs because the program currently being executed is interrupted due to an event.EIT is the generic name for the exception (Exception), interrupt (Interrupt), and Trap (Trap).

EIT (Exception/Interrupt/Trap)

An exception is an event that occurs in connection with the context being executed. Executionis restarted from the instruction causing the exception.

An interrupt is an event that occurs independent of the context being executed. Event causesare hardware.

A trap is an event that occurs in connection with the context being executed. Some traps arespecified in programs such as a system call. Execution is restarted from the next instruction ofthe instruction causing the exception.

Features

• Multi-interrupt support for interrupts

• Level mask function for interrupts (15 levels can be used by the user)

• Trap instruction (INT)

• EIT for starting the emulation (hardware/software)

EIT Causes

The following lists some of the EIT causes.

• Reset

• User interrupt (internal resources, external interrupt)

• NMI

• Delayed interrupt

• Undefined instruction exception

• Trap instruction (INT)

• Trap instruction (INTE)

• Step trace trap

• Coprocessor absence trap

• Coprocessor error trap

Return from EIT

• RETI instruction

Interrupt Level

The interrupt levels are 0 to 31 and managed by 5 bits.

73


Table 3.8-1 lists the allocation of each level.

- Operations are enabled at levels of 16 to 31.

The undefined instruction exception, coprocessor absence trap, coprocessor error trap, and INTinstruction are not affected by the interrupt level. ILM is also not changed.

I Flag

This flag specifies permission/prohibition of interrupts and is set up as four bits of CCR on thePS register.

Table 3.8-1 Interrupt Level

Level Cause Remarks

Binary Decimal

00000 0 (System reserved)

: : :

: : :


00100 4 INTE instructionStep trace trap

If the original value of ILM is 16 to 31, a value in this range cannot be set to ILM by a program.


: : :

: : :


01111 15 NMI (for users)

10000 16 Interrupt User interrupt prohibited when ILM is set

10001 17 Interrupt

: : :

: : :

11110 30 Interrupt

11111 31 - Interrupt prohibited when ICR is set

Value Description

0 Interrupt prohibited. When the INT instruction is executed, this value is cleared to 0 (However, the value saved to the stack is that prior to being cleared).

1 Interrupt permitted. Interrupt request mask processing is controlled by the value held by ILM.

74


ILM

ILM is a PS register (20 to 16) that holds the level mask value. Interrupt requests are acceptedonly if the interrupt level of interrupt requests entering CPU is stronger than the level indicatedby this ILM.

The level values range from 0 (00000B) (strongest) to 31 (11111B) (weakest).

The values that can be set from programs are restricted. If the original value is 16 to 31, valuesthat can be set as a new value are 16 to 31. If an instruction in which 0 to 15 is set is executed,a value (specified value + 16) is transferred. If the original value is 0 to 15, any value in therange of 0 to 31 can be set.

<Precautions>

Use the SETILM instruction to set any value.

Level Mask for the Interrupts/NMI

When NMI and an interrupt request occur, the interrupt level (Table 3.8-1) of the interrupt causeis compared with the level mask value held by ILM. If the following condition is satisfied, therequest is masked and is not accepted.

• Interrupt level of the cause larger than or euqal to level mask value

Delayed Slot

Regarding the delayed slot of branch instructions, restrictions exist for EIT.

See "3.7 Branch Instruction".

75


3.8.1 ICR (Interrupt Control Register)

ICR is a register set up in the interrupt controller and sets the level for each interrupt request.

ICR (Interrupt Control Register)

ICR is provided for each interrupt request entry. ICR is mapped into the I/O space and isaccessed through a bus from CPU.

ICR bit configuration

[bit 4] ICR4

Always "1".

[bit 3 to 0] ICR3 to 0

Four low-order bits of the interrupt of the corresponding interrupt cause. Both read and writeoperations are possible.

Along with the bit 4, any value in the range of 16 to 31 can be set to ICR.

ICR mapping

*1) See the chapter of "Interrupt Controller".

Table 3.8-2 Interrupt Causes and Interrupt Control Registers/Interrupt Vectors

Interrupt cause

Interrupt control register Corresponding interrupt vector

Number Address Number Address

Hexadecimal Decimal

IRQ00 ICR00 00000400H 10H 16 TBR+3BCH

IRQ01 ICR01 00000401H 11H 17 TBR+3B8H

IRQ02 ICR02 00000402H 12H 18 TBR+3B4H

::

::

::

::

::

::

IRQ45 ICR45 0000042DH 3DH 61 TBR+308H

IRQ46 ICR46 0000042EH 3EH 62 TBR+304H

IRQ47 ICR47 0000042FH 3FH 63 TBR+300H

76


3.8.2 SSP (System Stack Pointer)

SSP is used as a pointer to point to the data save/return stack for EIT acceptance and return operations.

SSP (System Stack Pointer)

8 is subtracted from the content when processing EIT and 8 is added when returning from EITthrough execution of the RETI instruction.

The initial value by the reset operation is 00000000H.

Interrupt Stack

Values of PC and PS are saved to the area indicated by SSP and then returned. After aninterrupt, PC is stored at the address indicated by SSP and PS is stored at the addressindicated by (SSP+4).

Figure 3.8-1 Interrupt Stack

bit31 0

00000000H

[Initial value]

[ A f t e r i n t e r r u p t ]

80000000H 7FFFFFF8H

M e m o r y

80000000H 80000000H

7FFFFFFCH 7FFFFFFCH

7FFFFFF8H 7FFFFFF8H

[ B e f o r e i n t e r r u p t ]

M e m o r y

77


3.8.3 TBR (Table Base Register)

TBR is a register to indicate the first address of the vector table for EIT.

TBR (Table Base Register)

The address obtained by adding an offset value defined for each cause of TBR and EITbecomes the vector address.

The initial value by the reset operation is 000FFC00H.

EIT Vector Table

The 1 KB area from the address indicated by TBR is the vector area for EIT.

The size of one vector is 4 bytes, and the relation between the vector number and vectoraddress can be expressed as follows:

The lower two bits of operation values resulted from the addition are handled as "00".

The area of 000FFC00H to 000FFFFFH is the initial area of the vector table by the resetoperation.

Specific functions are allocated to part of the vectors. Table 3.8-3 lists the architectural vectortable.

bit31 0

000FFC00H

[Ini t ia l value]

vctadr = TBR + vctofs

= TBR + (3FCH - 4 x vct)

vctadr: vector address

vctofs: vector offset

vct: vector number

Table 3.8-3 Vector Table

Vector offset (hexadecimal)

Vector number Explanation

Hexadecimal Decimal

3FC 00 0 Reset (*1)

3F8 01 1 System reserved



78


::

::

::

::

3E0 07 7 System reserved

3DC 08 8 System reserved

3D8 09 9 INTE instruction

3D4 0A 10 System reserved

3D0 0B 11 System reserved

3CC 0C 12 Step trace trap

3C8 0D 13 System reserved

3C4 0E 14 Undefined instruction exception

3C0 0F 15 NMI (for users)

3BC 10 16 Maskable interrupt cause #0

3B8 11 17 Maskable interrupt cause #1 (*2)

::

::

::

::

300 3F 63 Maskable interrupt cause/INT instruction

2FC 40 64 System reserved (used by REALOS)

2F8 41 65 System reserved (used by REALOS)

2F4 42 66 Maskable interrupt cause/INT instruction

::

::

::

::

000 FF 255

*1: Even if the value of TBR changes, the reset vector always uses the fixed address 000FFFFCH.

*2: For the vector table of this product type, see APPENDIX.

Table 3.8-3 Vector Table (Continued)

Vector offset (hexadecimal)

Vector number Explanation

Hexadecimal Decimal

79


3.8.4 Multi-EIT Processing

If multiple EIT causes occur simultaneously, CPU repeats the operation of selecting and accepting one EIT cause and executing an EIT sequence and then detecting another EIT cause.

Multi-EIT Processing

If there is no EIT cause that can be accepted when EIT causes are detected, the instruction ofthe handler of the EIT cause accepted last is executed.

Thus, the order of handler execution of each cause when multiple EIT causes occursimultaneously is determined by the following:

• Priority of EIT cause acceptance

• Priority of EIT cause acceptance

The priority of EIT cause acceptance is the order of EIT sequence execution in which PC isupdated after saving PS and PC and (if necessary) other causes are masked. The handler of acause accepted first is not necessarily executed first.

Table 3.8-4 lists the priorities of EIT cause acceptance.

Table 3.8-5 lists the order of execution of each handler of the EIT causes occurring

Table 3.8-4 The priority of EIT cause acceptance

Acceptance priority

Cause Masking of other causes

1 Reset Other causes are discarded

2 Undefined instruction exception Cancel

3 INT instruction I flag=0

4 User interrupt ILM = Accepted cause level

5 NMI (for users) ILM=15

6 (INTE instruction) ILM=4 (*1)

7 NMI (for emulators) ILM=4

8 Step trace trap ILM=4

9 INTE instruction ILM=4

*1: The priority when the INTE instruction and NMI (for emulators) occur simultaneously becomes 6 (In MB91V101, NMI (for emulators) is used for break by data access).

80


simultaneously by adding mask processing for other causes after accepting an EIT cause.

Figure 3.8-2 Multi-EIT Processing

Table 3.8-5 Order of Execution of Each EIT Handler

Order of handler execution

Cause

1 Reset (*1)

2 Undefined instruction exception

3 Step trace trap (*2)

4 INTE instruction (*2)

5 NMI (for users)

6 INT instruction

7 User interrupt

*1: Other causes are discarded.

*2: When the INTE instruction is step-executed, only EIT of the step trace trap occurs. Causes due to INTE are ignored.

INT instruct ion

NMI handler

Executed f i rst

Executed next

(high) NMI occurred

( low) INT instruct ion

Prior i ty

Main rout ine

execut ion

handler

81


3.8.5 Operation of EIT

This section explains each operation of EIT (exception, interrupt, trap).

Operation of EIT

In the following explanation, "PC" of the transfer destination means the address of an instructionthat detected each EIT cause. "Address of the next instruction" means the following if theinstruction that detected EIT is:

• LDI:32 --- PC+6

• LDI:20, COPOP, COPLD, COPST, COPSV --- PC+4

• Others --- PC+2

Operation of the User Interrupt/NMI

When a user interrupt or NMI (for users) occurs, whether the request is to be accepted isdetermined in the following order.

Determination whether to accept an interrupt request

1. The interrupt levels of requests that occurred simultaneously are compared and the requestwith the highest level (the smallest value) is selected. The value held by the correspondingICR is used as the level for the maskable interrupt and a predefined value for NMI.

2. If multiple interrupt requests with the same level occur, the interrupt request with the smallestinterrupt number is selected.

3. If the formula of interrupt level larger than or equal to level mask value is true, the interruptrequest is masked and thus not accepted.

• If the formula of interrupt level < level mask value is true, go to 4.

4. If the selected interrupt request is a maskable interrupt and the I flag is 0, the interruptrequest is masked and thus not accepted. If the I flag is 1, go to 5.

• If the selected interrupt request is NMI, go to 5 regardless of the value of the I flag.

5. If the above conditions are satisfied, interrupt requests are accepted between instructionprocessing.

If a user interrupt/NMI request is accepted when an EIT request is detected, CPU operates inthe following manner using the interrupt number corresponding to the accepted interruptrequest.

[Operation]

( ) represents the address pointed by each register.

1. SSP-4 --> SSP

2. PS --> (SSP)

3. SSP-4 --> SSP

4. Address of the next instruction --> (SSP)

5. Interrupt level of the accepted request --> ILM

6. "0" --> S flag

82


7. (TBR + vector offset of the accepted interrupt request) --> PC

New EIT is checked for before executing the first instruction of the handler after the interruptsequence is completed. If, at this point, any EIT that can be accepted has occurred, CPUmakes a transition to the EIT processing sequence.

Operation of the INT Instruction

INT #u8

Branches to the interrupt handler of the vector indicated by u8.

[Operation]

1. SSP-4 --> SSP

2. PS --> (SSP)

3. SSP-4 --> SSP

4. PC+2 --> (SSP)

5. "00100" --> ILM

6. "0" --> S flag

7. (TBR+3FCH-4Xu8) --> PC

83


Operation of the INTE Instruction

INTE

Branches to the interrupt handler of the vector of the vector number #9.

[Operation]

1. SSP-4 --> SSP

2. PS --> (SSP)

3. SSP-4 --> SSP

4. PC+2 --> (SSP)

5. "00100" --> ILM

6. "0" --> S flag

7. (TBR+3D8H)--> PC

Do not use the INTE instruction in a processing routine of the INTE instruction and step tracetrap.

EIT is not caused by INTE during step execution.

Operation of the Step Trace Trap

If the step trace function is enabled by setting the T flag of SCR in PS, every time an instructionis executed, a trap occurs and processing is broken.

[Conditions for step trace trap detection]

1. T flag = 1

2. No delayed branch instruction

3. Any processing routine other than that of the INTE instruction or step trace trap is notexecuted

4. If the above conditions are satisfied, a break occurs between instruction processing.

[Operation]

1. SSP-4 --> SSP

2. PS --> (SSP)

3. SSP-4 --> SSP

4. Address of the next instruction --> (SSP)

5. "00100" --> ILM

6. "0" --> S flag

7. (TBR+3CCH)--> PC

If the step trace trap is enabled by setting the T flag, NMI (for users) and the user interrupt areprohibited.

EIT will not be caused by the INTE instruction.

Operation of the Undefined Instruction Exception

If an instruction is found to be undefined while decoding, an undefined instruction exceptionoccurs.

84


[Conditions for the undefined instruction exception]

1. An instruction is found to be undefined when decoding.

2. The instruction is placed outside the delayed slot (not just after a delayed branch exception).

3. If the above conditions are satisfied, an undefined instruction exception occurs andprocessing is broken.

[Operation]

1. SSP-4 --> SSP

2. PS --> (SSP)

3. SSP-4 --> SSP

4. PC --> (SSP)

5. "0" --> S flag

6. (TBR+3C4H)--> PC

The address of the instruction that detected the undefined instruction exception is saved as PC.

Operation of the RETI Instruction

RETI instruction is the instruction that returns from the EIT process routine.

[Operation]

1. (R15) --> PC

2. R15+4 --> R15

3. (R15) --> PS

4. R15+4 --> R15

Note that the stack pointer referenced to return PS and PC is selected according to the contentof the S flag. When executing an instruction that operates R15 (stack pointer) in an interrupthandler, we recommend using USP as R15 by setting the S flag to "1" and returning the S flagto "0" before the RETI instruction.

85

3.9 Reset Sequence

3.9 Reset Sequence

When a reset cause is removed, CPU executes the reset sequence as shown below.

Reset Sequence

Reset causes are as follows.

• Input from an external reset pin

• Software reset by the SRST bit manipulation on the standby control register STCR

• Count-out of the watchdog timer

• Release of the hardware standby

• Power-on reset

Power-on reset

When a reset cause occurs, CPU is initialized.

External reset pin/software reset/release from the hardware standby

• The pin is set to the predefined state.

• Each resource inside the device is reset. The control register is initialized to the predefinedvalue.

• The slowest gear is selected as the clock.

Reset Sequence

When a reset cause is removed, CPU executes the following reset sequence

(000FFFFCH) --> PC

<Precautions>

After the reset, set the operation mode more minutely using the mode register settings (See thesection of the mode register).

86


3.10 Operation Mode

The operation mode is controlled by the mode pins (MD2, 1, 0) and mode register (MODR).

Operation Mode

The operation can be divided into the bus mode and the access mode.

Bus Mode

The bus mode is a mode to control the operations of internal ROM and the external accessfunction, and can be specified by the mode setting pins (MD2, 1, 0) and the M1 and M0 bits inthe mode register (MODR).

Access Mode

The access mode is a mode to control the external data bus width and can be specified by themode setting pins (MD2, 1, 0) and the BW1 and BW0 bits in AMD0/AMD1/AMD3/AMD4/AMD5(Area MoDe Register).

Mode Pin

Operations can be specified as listed in the following table by using the MD2, 1, and 0 pins.

*1: This LSI device does not support the single chip mode.

Bus mode Access mode

Single chip

Internal-ROM-external bus

External-ROM-external bus

16-bit bus width

8-bit bus width

Table 3.10-1 Mode Pins and Setting Modes

Mode pin Mode name Reset vector

access area

External data bus width

Remarks

MD2 MD1 MD0

0 0 0 External vector mode 0

External 8 bit External-ROM-external bus mode

0 0 1 External vector mode 1

External 16 bit External-ROM-external bus mode

0 1 0 - - - Setting prohibited

0 1 1 Internal vector mode

Internal (Mode register) Single chip mode (*1)

1 - - - - - Use prohibited

87

3.10 Operation Mode

Mode Data

Data that is written into "0000 07FFH" by CPU after the reset is called mode data.

What exists at "0000 07FFH" is a mode register (MODR). After this register is set, operationproceeds in a mode that is set in this register.

The mode register can be set only once by being written in following the reset.

The setting by this register is enabled immediately after the write operation into this register.

Bus Mode Setting Bit (M1, M0)

This bit specifies the bus mode after the write operation into the mode register.

The following table lists the relations between the bits and the functions.

Note: For product types without internal ROM, set only "10" in the above table. Thus, only "10"can be set for this product type.

Other Bits (*)

Set always "0" to these bits.

<Precautions>

Be sure to set AMD0 to AMD5 to determine the bus width of each CS (ChipSelect) area beforewriting into MODR. MODR has no bit to set its bus width.

The values of the mode pins MD2 to 0 determine the bus width before writing into MODR, andthe values set in BW1 and 0 of AMD0 to 5 determine the bus width after writing into MODR. Forexample, the external reset vector is normally done in the area 0 (area in which CS0X is active)and the bus width at this time is determined by the MD2 to 0 pins. If the bus width is set to the16 bits this time using MD2 to 0 and a write operation is performed to MODR without settinganything to AMD0, a malfunction will occur because the initial value of the bus width of AMD0 isset to 8 bits and the area 0 makes a transition to the 8-bit bus mode for bus operation after thewrite operation to MODR. To avoid such problems, it is necessary to set AMD0 to 5 beforewriting into MODR.

Initial value

MODR address:000007FFH M1 M0 * * * * * * XXXXXXXX W

Bus mode setting bit

Access

Table 3.10-2 Bus Mode Setting Bit and the function

M1 M0 Function Remarks

0011

0101

Single chip modeInternal-ROM-external bus modeExternal-ROM-external bus mode- Setting prohibited

88


MODR write

RSTX (reset)

Bus width setting MD2,1,0 BW1, 0 of AMD0-5

89



The clock generator functions to generate the CPU clock and peripheral clocks (including the gear function).

Features of the Clock Generator (Power-saving Mechanism)

The clock generator is a module with the following functions.

• CPU clock generation (including the gear function)

• Peripheral clock generation (including the gear function)

• Reset occurrence and causes are held

• Standby function (including the hardware standby)

• DMA request disabled

• PLL (multiplier) is contained

List of Registers

15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00

RSRR/WTCR STCR

PDRR CTBR

GCR WPR

PCTR

90


Block Diagram

Figure 3.11-1 Block Diagram of the Clock Generator

X0 PLLX1

1/2

R

|

B

U

S

[Gear controller]

Oscillator

GCR register

CPU gear

Peripheral

PCTR register

Selection

Internal

CPU clock

Internal bus clock

External bus clock

Peripheral DMA clockInternal peripheral

STOP state

SLEEP state

CPU hold request

[Stop/sleep controller]Internal interrupt

Internal reset

CPU hold

DMA request

Power-on cell

RSTX pin

STCR register

State

Reset

DMA disable circuit

PDRR register

[Reset cause circuit]

RSRR register

[Watchdog controller]

WPR register

CTBR register

Watchdog F/F

Time base timerCount clock

HSTX pin

Internal reset

clock

transition control circuit

gearclock generation

circuit

circuitcircuit

generation

F/F

permission

91


3.11.1 RSRR, WTCR

RSRR (reset cause register) is a register to hold the type of reset that occurred. WTCR (watchdog control register) is a register to specify the cycle of the watchdog timer.

RSRR (Reset Cause Register) and WTCR (Watchdog Control Register)

Register configuration

Bit contents

[bit 15] PONR

If this bit is "1", the reset that occurred last was a power-on reset. If this bit is "1", bits otherthan this bit of this register are invalid.

[bit 14] HSTB

If this bit is "1", the reset that occurred last was a reset resulting from the hardware standby.

[bit 13] WDOG

If this bit is "1", the reset that occurred last was a watchdog reset.

[bit 12] ERST

If this bit is "1", the reset that occurred last was a reset resulting from an external reset pin.

[bit 11] SRST

If this bit is "1", the reset that occurred last was a reset resulting from a software reset cause.

[bit 10] (Reserved)

This bit is a reserved bit. Its read value is not defined.

15 14 13 12 11 10 09 08Access

00000480H PONR WDOG ERST SRST WT1 WT0 1XXXX-00 R/W

RSRR(R) WTCR(W)

HSTB

Initial value after power-on

92


[bit 09, 08] WT1, 0

These bits specify the cycle of the watchdog timer. The following table lists the relationsbetween these bits and the cycles to be selected. These bits are initialized by all resets.

If CHC of GCR is 1, φ is twice X0. If CHC of GCR is 0, φ is the cycle of the oscillation frequencyof PLL.

WT1 WT0 Minimum write interval to WPR required to disable the

watchdog reset

Time between last 5AH write to WPR and watchdog reset

occurrence

0 0 φ × 215 [Initial value] φ × 215 to φ × 216

0 1 φ × 217 φ × 217 to φ × 218

1 0 φ × 219 φ × 219 to φ × 220

1 1 φ × 221 φ × 221 to φ × 222

93


3.11.2 STCR (Standby Control Register)

STCR (standby control register) is a register to control the standby operation and to specify the oscillation stabilization wait time.

STCR (Standby Control Register)


Bit contents

[bit 07] STOP

Writing "1" into this bit leads to a stop state in which the clock in the internal peripheral isstopped, the clock of the internal CPU is stopped, and the oscillation is stopped.

[bit 06] SLEP

Writing "1" into this bit leads to a sleep state in which the clock of the internal CPU isstopped.

If 1 is written into both the bit 07 and this bit, the bit 07 takes precedence, leading to a stopstate.

[bit 05] HIZX

If a stop state is entered with this bit set to "1", a device pin will have a high impedance.

[bit 04] SRST

Writing "0" into this bit leads to a software reset request.

[bit 03, 02] OSC1, 0

These bits specify the oscillation stabilization wait time. The following table lists the relationsbetween these bits and the wait time to be selected. These bits are initialized by the power-on reset and hardware standby reset and are not affected by other resets.

φ is twice the frequency of X0

07 06 05 04 03 02 01 00 Initial value Access

00000481H STOP SLEP HIZX SRST OSC1 OSC0 000111-- R/W

OSC1 OSC0 Oscillation stabilization wait time

0 0 φ × 215

0 1 φ × 217

1 0 φ × 219

1 1 φ × 221 [Initial value]

94


[bit 01, 00] (Reserved)

These bits are reserved bits. Their read value is not defined.

95


3.11.3 CTBR (Time Base Timer Clear Register)

CTBR (time base timer clear register) is a register to initialize the time base timer to 0.

CTBR (time base timer clear register)


Bit contents

[bit 07-00]

If A5H and 5AH are written successively into this register, the time base timer is cleared to 0just after 5AH. The read value from this register is not defined. There is no limit to the timeinterval between A5H write and 5AH write.

<Precautions>

If the time base timer is cleared using this register, the oscillation stabilization wait interval,watchdog cycle, and cycles of peripherals using the time base vary temporarily.


00000483H D7 D6 XXXXXXXX WD0D1D2D3D4D5

96


3.11.4 GCR (Gear Control Register)

GCR (gear control register) is a register to control the gear function of the peripheral system clock.

GCR (Gear Control Register)


Bit contents

[bit 15,14] CCK1, 0

These bits specify the gear cycle of the CPU system. The following table lists the relationsbetween these bits and the cycles to be selected. These bits are initialized by the resetoperation.

PLL: Oscillation frequency of PLL

Source clock frequency: Input frequency from X0

[bit 13] DBLAK

This bit indicates the operation state of the clock doubler. This bit is read-only and writeoperations to this bit are ignored. This bit is initialized by the reset operation.

There is a time lag in switching the bus frequency and whether the operation has actually


00000484H CCK1 CCK0 DBLAK DBLON PCK1 PCK0 CHC 110011-1 R/W

CCK1 CCK0 CHC CPU system machine clock

0 0 0 PLL × 1

0 1 0 PLL × 1/2

1 0 0 PLL × 1/4

1 1 0 PLL × 1/8

0 0 1 Source clock frequency× 1/2

0 1 1 Source clock frequency× 1/2× 1/2

1 0 1 Source clock frequency× 1/2× 1/4

1 1 1 Source clock frequency× 1/2× 1/8 [Initial value]

97


been switched can be checked using this bit.

[bit 12] DBLON

This bit specifies the operation state of the clock doubler. This bit is initialized by the resetoperation.

[bit 11, 10] PCK1, 0

These bits specify the gear cycle of the peripheral system. The following table lists therelations between these bits and the cycles to be selected. These bits are initialized by thereset operation.

<Precautions>

When the CPU system clock operates at frequencies higher than 25 MHz, set the peripheralsystem clock to half the CPU system clock frequency or lower.

The maximum frequency of the peripheral system clock is 25 MHz.

To change the CPU system gear and peripheral system gear at the same time, first set both tothe same gear and then set each to the desired gear. If both the CPU system gear andperipheral system gear have the same setting before changing the gear, or if only one gear ischanged, or both gears are set to the same setting, the gear can be set directly to the desiredvalue.

If the clock doubler is ON, the CPU system gear is fixed regardless of the value of GCR, and sothe gear can be set to the desired value directly.

DBLAK Internal: external operating frequencies

0 Operating at 1:1 [Initial value]

1 Operating at 2:1

DBLON Internal: external operating frequencies

0 Operating at 1:1 [Initial value]

1 Operating at 2:1

PCK1 PCK0 CHC Peripheral system machine clock (source clock frequency: input frequency from X0)

0 0 0 PLL × 1

0 1 0 PLL × 1/2

1 0 0 PLL × 1/4

1 1 0 PLL × 1/8

0 0 1 Source clock frequency × 1/2

0 1 1 Source clock frequency × 1/2 × 1/2

1 0 1 Source clock frequency × 1/2 × 1/4

1 1 1 Source clock frequency × 1/2 × 1/8 [Initial value]

PLL: Oscillation frequency of PLLSource clock frequency: Input frequency from X0

98


[Program example]

[bit 09] Reserved bit

Write 1 into this bit.

[bit 08] CHC

This bit sets the selection of the standard clock. This bit is initialized by the reset operation.If the VSTP bit of the PCTR register is 1, 0 written into this bit is ignored.

<Precautions>

If a transition to the stop mode occurs when VSTP of PCTR is 0, the value of VSTP remains 0though PLL stops oscillation. When the stop mode is exited, for example, by an externalinterrupt, about 100 µs is needed in addition to the oscillation stabilization wait time set byOSC1, 0 of STCR before the oscillation of PLL is stabilized. Thus, do not set this bit to 0 beforethis time.

ldi #0x484, r1

ldi #0x0d, r0

stb r0,@r1 ; CPU:1/1,peripheral:1/8

:

:

ldi #0x484, r1

ldi #0xcd, r0

stb r0,@r1 ; CPU:1/8,peripheral:1/8 First set to the same ratio

ldi #0xc5, r0

stb r0,@r1 ; CPU:1/8,peripheral:1/2 Then set to the desired value

CHC Clock selection

1 Use 2 dividing of the oscillator circuit as the standard clock. [Initial value]

0 Use the oscillation output from PLL as the standard clock.

99


3.11.5 WPR (Watchdog Reset Postponement Register)

WPR is a register to clear the flip flop for the watchdog. Using this register, watchdog reset can be postponed.

WPR (Watchdog Reset Postponement Register)


Bit contents

[bit 07-00]

If A5H and 5AH are written successively into this register, the flip flop for the watchdog timeris cleared to 0 just after 5AH to postpone the watchdog reset.

The read value from this register is not defined. Though there is no limit to the time intervalbetween A5H write and 5AH write, the watchdog reset occurs if both pieces of data are notwritten within the period as listed in the following table. However, since the flip flop iscleared automatically in a stop, sleep, or hold state, the watchdog reset is automaticallypostponed if any of these conditions arise.

If CHC of GCR is 1, φ is twice X0. If CHC of GCR is 0, φ is the cycle of the oscillation frequencyof PLL.

07 06 05 04 03 02 01 00

00000485H D7 D6 D5 D4 D3 D2 D1 D0 XXXXXXXX W

Initial value Access

WT1 WT0 Minimum write interval to WPR required to disable

the watchdog reset

Time between last 5AH write to WPR and watchdog reset

occurrence

0 0 φ × 2 15 φ × 2 15 to φ × 2 16

0 1 φ × 2 17 φ × 2 17 to φ × 2 18

1 0 φ × 2 19 φ × 2 19 to φ × 2 20

1 1 φ × 2 21 φ × 2 21 to φ × 2 22

100


3.11.6 PDRR (DMA Request Disable Register)

PDRR is a register to operate CPU by disabling DMA requests temporarily.

PDRR (DMA Request Disable Register)


Bit contents

[bit 11-08] D3-0

If any value other than 0 is written into this register, subsequent DMA transfer requests toCPU from DMA are disabled, and the DMA transfer cannot be performed if 0 is not writteninto this register.

<Precautions>

The PDRR register must be used together with HRCL.

15 14 13 12 11 10 09 08

00000482H - - - - D3 D2 D1 D0 ----0000 R/W

Access Initial value

101


3.11.7 PCTR (PLL Control Register)

PCTR is a register to control the oscillation of PLL. The setting of this register can be changed only if CHC of GCR is 1.

PCTR (PLL Control Register)


Bit contents

[bit 15-14] SLCT1, 0

These bits control the multiplication ratio of PLL and are initialized only during power-on.

The internal operating frequency when CHC of GCR is set to 0 is set to these bits.

[bit 13-12] Reserved bits

Write 0 to these bits.

[bit 13-12] VSTP

These bits control the oscillation of PLL and are initialized during power-on and by externalresets. If PLL is stopped while the device is used, it is necessary to always stop the deviceafter the reset release.

<Precautions>

If a transition to the stop mode or hardware standby mode occurs, the oscillation of PLL stopsregardless of the setting of these bits.


00000488H SLCT1 SLCT0 VSTP 00--0--- R/W

SLCT1 SLCT0 Internal operating frequency (if the source clock frequency is 12.5 MHz)

0 0 12.5 MHz operation [Initial value]

0 1 25.0 MHz operation

1 X 50.0 MHz operation

VSTP PLL operation

0 Oscillation [Initial value]

1 Oscillation stop

102


3.11.8 List of the Standby Operations

Table 3.11-1 list the operations of the standby mode.

List of Operations

Table 3.11-1 List of the Standby Operations

Transition condition

Oscillator Internal clock Peripheral Pin How to release

CPU/internal

bus

DMA/peripheral

Run Y Y Y Y Operating

Sleep SLEP of STCR is "1"

Y N Y Y Operating

Stop STOP of STCR is "1"

N N N N (*1)

Hardware standby

HSTX="0" N N N N Hi-Z HSTX="1"

Y: Operating

N: Stopped

Reset: RSTX="0"STOP of STCR is "0"Watchdog resetPower-on reset

(*1) If HIZX of STCR is "0", the previous state is heldIf HIZX is "1", Hi-Z

103


3.11.9 Stop State

The stop state is one of the following states and can reduce power consumption to a minimum.• All internal clocks are stopped• The oscillator circuit operation is stopped.

Stop State

The transition to the stop state can be made using one of the following methods.

• Write to the standby control register (STCR) by an instruction

• Application of the L level to the HSTX pin

The stop state can be exited by one the following methods.

• Interrupt request (However, limited to the peripherals where interrupt requests can occureven in a stop state)

• Application of the L level to the RSTX pin

• Application of the L level --> H level to the HSTX pin

Since all internal clocks are stopped in a stop state, all internal peripherals are stopped exceptthose that can cause an interrupt to return.

Figure 3.11-2 Block Diagram of the Stop Controller

Transition to the Stop State

Transition to the stop state by an instruction

To enter the stop state, write "1" into the bit 7 of STCR.

When CPU does not use the internal bus, clocks are stopped in the following order; CPU clock,internal bus clock, internal DMA clock, and internal peripheral clock. The oscillator circuit is

STOP state transition request signal

STCRSTOP CPU clock

clear

Internal

Stop signal

.or.

Sta

te tr

ansi

tion

cont

rol c

ircui

t

Sta

te d

ecod

er

Inte

rnal

clo

ck g

ener

atio

n ci

rcui

tgeneration

Internal bus clock

DMA clock

Internal

clock

Clock stop request signal

Clock release request signal

CPU clock

Internal bus clock

Internal DMA clock, external bus clock

Internal peripheral clock

Internal bus

Internal interruptInternal reset

CPU hold permission

CPU hold request

STOP state display signal

HSTX pin F/F

generation

generation

peripheral

generation

104


stopped simultaneously with the internal peripheral clock.

<Precautions>

• To make a transition to the stop state using the instruction, proceed as follows.

• Before writing to STCR, set an identical value to the pair of CCK1-0 and PCK1-0 of GCR tomake the gear ratio of the CPU system clock and peripheral system clock the same.

• Do not make a transition to the stop state when the CHC bit of GCR is "0" (PLL operating).To make a transition to the stop state, set the CHC bit of GCR to "1" (selection of the 2dividing system) to switch the clock before entering the stop state.

• Turn off the clock doubler before entering the stop state.

• At least six successive NOP instructions are needed just after writing to STCR.

[Setting: Example of the highest gear speed]

Making a transition to the stop state using the HSTX pin

To enter the stop state, apply the L level to the HSTX pin.

After applying the L level to the HSTX pin, clocks are stopped in the following order: CPU clock -->, internal bus clock -->, internal DMA clock -->, and internal peripheral clock when CPU doesnot use the internal bus. The oscillator circuit is stopped simultaneously with the internalperipheral clock.

<Precautions>

It is not possible to make a transition to the stop state even if the L level is applied during a resetoperation (RSTX=L). Also, the stop state cannot be entered if the reset operation is releasedwhile the HSTX pin is at the L level. In this case, it is possible to enter the stop state raising theHSTX pin to the H level and again lowering it to the L level.

LDI:20 #GCR,R0

LDI:8 #00000011b,R1 ; CHC=1,CPU=peripheral gear ratio

STB R1,@R0 ; DBLON=0

loop

BTSTH #0010b,@r0 ;

BNE loop ; Wait until DBLAK=0

LDI:20 #STCR,R0

LDI:8 #10010000b,r1 ; STOP=1

STB R1@R0

NOP ;

NOP ;

NOP ;

NOP ;

NOP ;

NOP ;

105


Likewise, the stop state cannot be entered after releasing the power-on reset if turned on withthe HSTX pin at the L level.

Return from the Stop State

The return from the stop state can be triggered by reset operations including the interrupts andhardware standby.

Return by an interrupt

If the interrupt permission bit attached to the peripheral function is enabled, the stop state isexited when an interrupt occurs in the peripherals.

The following shows the transition from the stop state to the normal operating state.

• Interrupt occurred --> oscillator circuit operation restart --> oscillation stabilization wait -->internal peripheral clock supply restart after stabilization --> internal DMA clock supply restart--> internal bus clock supply restart --> internal CPU clock supply restart

Program execution after the oscillation stabilization wait time is as follows:

• If the level of the interrupt that occurred is permitted by the I flag of ILM of CPU, the registeris saved and then the interrupt processing routine is executed by fetching the interruptvector.

• If the level of the interrupt that occurred is prohibited by the I flag of ILM of CPU, instructionsafter the instruction that instructed CPU to enter the stop state are executed.

Return by the RSTX pin


• Application of the L level to the RSTX pin --> internal reset occurred --> oscillator circuitoperation restart --> oscillation stabilization wait --> internal peripheral clock supply restartafter stabilization --> internal DMA clock supply restart --> internal bus clock supply restart --> internal CPU clock supply restart --> reset vector fetch --> execution restart of instructionsfrom the reset entry address

<Precautions>

If the HSTX pin is at the L level and the device in the stop state, no reset operation is performeduntil the HSTX pin is raised to the H level.

Return by the HSTX pin


• Application of the H level to the HSTX pin --> internal reset occurred --> oscillator circuitoperation restart --> oscillation stabilization wait --> internal peripheral clock supply restartafter stabilization --> internal DMA clock supply restart --> internal bus clock supply restart --> internal CPU clock supply restart --> reset vector fetch --> execution restart of instructionsfrom the reset entry address

<Precautions>

• If an interrupt request has already occurred from the peripherals, the stop state is notentered and a write operation is ignored.

• The internal clock is not supplied at all during oscillation stabilization wait for reset operationsother than the power-on reset. All internal clocks are supplied for the power-on resetbecause the internal state must be initialized.

• If the HSTX pin is lowered to the L level in the stop state, the stop state is immediatelyreleased and the specified oscillation stabilization wait time is counted. If the HSTX pin is atthe L level after the oscillation stabilization wait time, a transition to the stop state by the

106


HSTX pin takes place.

107


3.11.10 Sleep State

The sleep state stops the CPU clock and internal bus clock, and can contribute to the reduction of power consumption when CPU operation is not needed.

Sleep State

The transition to the sleep state is triggered by writing an instruction into the standby controlregister (STCR). The sleep state is exited when interrupt requests and reset causes occur.

Since the internal DMA clock and peripheral clock operate in the sleep state, interrupts of allinternal peripherals using these two clock can release the sleep state.

Block Diagram

Figure 3.11-3 Block Diagram of the Sleep Controller

Transition to the Sleep State

To enter the sleep state, write 0 to the bit 7 of STCR and 1 to the bit 6.

After the sleep request is issued, clocks are stopped in the order of the CPU clock -> internalbus clock when CPU does not use the internal bus.

<Precautions>

• To make a transition to the sleep state using the instruction, use the routine described below.

• Before writing to STCR, set an identical value to the pair of CCK1-0 and PCK1-0 of GCR tomake the gear ratio of the CPU system clock and peripheral system clock the same.

• The CHC bit of GCR is optional.

• Before entering the sleep mode, disable DMA.

• Turn off the clock doubler before making a transition to the sleep mode.

STCRSTOP

clear

.or.

F/F

STOP state transition request signalStop signal

STOP state display signal

Internal bus

Internal interruptInternal reset

CPU hold permission

CPU hold request

HSTX pin

CPU clock

Internal bus clock

Internal DMA clock, external bus clock


Sta

te t

rans

ition

con

trol

cir

cuit

Sta

te d

ecod

er CPU clock generation

Internal bus clock generation

Clock stop request signal

Clock release request signal

Internal

clock peripheral

generation

Internal DMA clock generation, external bus clock generation

Inte

rnal

clo

ck g

ener

atio

n ci

rcui

t

108


• At least six successive NOP instructions are needed just after writing to STCR.

[Setting: Example of the highest gear speed]

Return from the Sleep State

The return from the sleep state can be triggered by reset operations including the interrupts andhardware standby.

Return by an interrupt

If the interrupt permission bit attached to the peripheral function is enabled, the sleep state isexited when an interrupt occurs in the peripherals.

The following shows the transition from the sleep state to the normal operating state.

• interrupt occurred --> internal bus clock supply restart --> internal CPU clock supply restart

Program execution after the clock supply is as follows:

• If the level of the interrupt that occurred is permitted by the I flag of ILM of CPU, the registeris saved and then the interrupt processing routine is executed by fetching the interruptvector.

• If the level of interrupt that occurred is prohibited by the I flag of ILM of CPU, instructionsafter the instruction that instructed CPU to enter the sleep state are executed.

Return by any reset request other than that resulting from the hardware standby


• Internal reset occurred --> internal bus clock supply restart --> internal CPU clock supplyrestart --> reset vector fetch --> execution restart of instructions from the reset entry address

Return by the HSTX pin


• Application of the L level to the HSTX pin --> transition to the hardware standby state -->application of the H level to the HSTX pin --> internal reset occurred --> oscillator circuitoperation restart --> oscillation stabilization wait --> internal peripheral clock supply restart

LDI:20 #GCR,R0

LDI:8 #00000011b,R1 ; CHC=1,CPU=peripheral gear ratio

STB R1,@R0 ; If DBLON=0

LDI:20 #STCR,R0

LDI:8 #01010000b,R1 ; SLEP=1

STB R1,@R0

NOP ;

NOP ;

NOP ;

NOP ;

NOP ;

NOP ;

109


after stabilization --> internal DMA clock supply restart --> internal bus clock supply restart--> internal CPU clock supply restart --> reset vector fetch --> execution restart ofinstructions from the reset entry address

110


3.11.11 Watchdog Function

The watchdog function can detect any runaway state of programs.

Watchdog Function

If A5H and 5AH were not written into the watchdog reset postponement register within thespecified period of time due to runaway of programs, the watchdog timer generates a watchdogreset request.

Block diagram

Figure 3.11-4 Block Diagram of the Watchdog Controller

How to start the watchdog timer

The watchdog timer can be started by writing to the watchdog control register (WTCR). At thistime, the interval time of the watchdog timer is set to the WT1 and 0 bits. The interval time thatis set in the first write is enabled and all other settings written thereafter are ignored.

[Example]

How to postpone the reset

Once the watchdog timer is started, it is necessary to write A5H and 5AH into the watchdogreset postponement register (WPR) periodically by programs. The flip fop for watchdog resetremembers the fall of the tap selected by the time base timer, and a reset is generated if this flipflop is not cleared when the 2nd fall is detected.

The following figure shows the operation of the watchdog timer.

WPR RSRRA5&5A WDOG

clrCTBR

WTx

and F/F

F/F

Latch

Watchdog

Select

Edge sense circuit

Sta

te t

rans

ition

con

trol

cir

cuit

Sta

te d

ecod

er Reset generation

Time base timer

Reset state transition request signal

Reset state

Internal reset

Internal bus

Time base timer dividing output

Time base timer dividing output

LDI:8 #00000010b,R1 ; WT1,0=10

LDI:20 #WTCR,R2

STB R1,@R2 ; Watchdog timer start

111


Figure 3.11-5 Operation of the Watchdog Timer

<Precautions>

• There is no specified interval between the first A5H write and the next 5AH write. Thewatchdog reset can be postponed only if the interval between two A5H write operations iswithin the time interval specified by the WT bit and there is one 5AH write operation inbetween.

• If anything other than 5AH is written after the first A5H write operation, the first A5H operationis ignored. Thus, in this case, A5H must be written again.

Time Base Timer

The time base timer is used as a timer to supply the clock to the watchdog timer and also as atimer for oscillation stabilization wait. The operating clock φ is twice X0 if CHC of GCR is 1, andis the same cycles as the oscillation frequency of PLL if CHC of GCR is 0.

As the count when DRAM is refreshed, the value of 1/25 this time base timer is used as thecount clock in RFCR.

Watchdog start Watchdog clear

Watchdog reset

Time base timer overflow

Watchdog flip flop

WTE write

1/21 1/22 1/23 1/218 1/219 1/220 1/221

112


3.11.12 Gear Function

The gear function is a function to supply the clock after thinning it out.

Gear Function

There are two independent circuits for CPU and peripherals, and data can be sent and receivedbetween CPU and peripherals even with different gear ratios. In addition, either a clock with thesame cycle as the clock from PLL or a clock through 2 frequency-dividing circuit can bespecified as the source clock.

Block diagram

Figure 3.11-6 Block Diagram of the Gear Controller

Settings

The desired gear ratio can be set by setting desired values to the CCK1 and 0 bits of the gearcontrol register (GCR) for the CPU clock control and PCK1 and 0 bits of the same register forthe peripheral clock control.

CPU system gear interval GCR

CCK CPU clock system CPU clock

PCK

DBLON

CHC

X0X1 1/2

PLL

Internal bus

Oscillator circuit

generation circuit

instruction signal

Sel

ectin

g

Source clock

Peripheral system gear interval instruction signal

Peripheral clock

circuit

Inte

rnal

clo

ck g

ener

atio

n ci

rcui

t

Internal bus clock

Internal DMA clock

External bus clock


gear interval

system gear interval generation

circ

uit

113


[Example]

If the CHC bit of the gear control register is set to "1", the 2 dividing circuit output is selected asthe source clock. If it is set to "0", a clock with the same cycle as that from the oscillator circuitis used. Since the source clock is switched, both the CPU system and the peripheral systemchange simultaneously.

[Example]

The following figure shows the timing of clocks.

LDI:20 #GCR,R2

LDI:8 #11111110b,R1 ; CCK=11,PCK=11,CHC=0

STB R1.@R2 ; CPU clock=1/8f, Peripheral clock=1/8f, f=direct

LDI:8 #01111010b,R1 ; CCK=01,PCK=10,CHC=0

STB R1,@R2 ; CPU clock=1/2f, Peripheral clock=1/4f, f=direct

LDI:8 #00111010b,R1 ; CCK=00,PCK=10,CHC=0

STB R1,@R2 ; CPU clock=f, Peripheral clock=1/4f, f=direct

LDI:8 #00110010b,R1 ; CCK=00,PCK=00,CHC=0

STB R1,@R2 ; CPU clock=f, Peripheral clock=f, f=direct

LDI:8 #10110010b,R1 ; CCK=10,PCK=00,CHC=0

STB R1,@R2 ; CPU clock=1/4f, Peripheral clock=f, f=direct

LDI:8 #01110001b,R1 ; CCK=01,PCK=00,CHC=1

LDI:20 #GCR,R2

STB R1,@R2 ; CPU clock=1/2f, Peripheral clock=f, f=1/2xtal

LDI:8 #00110011b,R1 ; CCK=00,PCK=00,CHC=1

STB R1,@R2 ; CPU clock=f, Peripheral clock=f, f=1/2xtal

LDI:8 #00110010b,R1 ; CCK=00,PCK=00,CHC=0

STB R1,@R2 ; CPU clock=f, Peripheral clock=f, f=direct

CPU clock(a)

CPU clock(b)

CHC

CCK value 01 00

PCK value 00

Peripheral clock(a)

Peripheral clock(b)

Source clock

114


3.11.13 Rest Cause Holding

The cause for the reset occurring just before is held.

Reset Cause Holding

All flags are set to "0" by reading. If the flags are not read, cause flags set once will notdisappear.

Block diagram

Figure 3.11-7 Block Diagram of the Reset Cause Circuit

Settings

No special setting is required to use this function. At the start section of the program to beplaced at the reset entry address, place instructions to read the reset cause register and branchto an appropriate program.

PONR PONR

WDOG WDOG

RSTX ERST ERSTinput circuit

SRST SRST

clr

SRSTState=RST State

STCR.or.

HSTBinput circuit

HSTB HSTB

Internal bus

From power-on cell

HSTX pin

RSTX pin

WatchdogInitialization

Decoder

by reading

transition circuit

reset detection circuit

115


[Example]

<Precautions>

• If the PONR bit is 1, handle the contents of other bits as undefined. Therefore, place aninstruction to check the power-on reset at the start if it is necessary to check the reset cause.

• Reset cause checks other than the power-on reset check can be placed at any location.Priorities are determined by order of placement.

RESET-ENTRY

LDI:20 #RSRR,R10

LDI:8 #10000000B,R2

LDUB @R10,R1 ; GET RSRR VALUE INTO R1

MOV R1,R10 ; R10 USED AS A TEMPORARY REGISTER

AND R2,R10 ; WAS PONR RESET?

BNE PONR-RESET

LSR #1,R2 ; POINT NEXT BIT


AND R2,R10 ; WAS HARDWARE STANDBY RESET?

BNE HSTBRESET

LSR #1,R2 ; POINT NEXT BIT


AND R2,R10 ; WAS WATCH DOG RESET?

BNE WDOG-RESET

:

116


3.11.14 DMA Disabled

In FR series, DMA transfer is interrupted to branch to the relevant interrupt routine if an interrupt cause with high priority occurs during DMA transfer.

DMA Disabled

This feature is enabled as long as there is an interrupt request. However, once the interruptcause is cleared, the disable function does not work and the DMA transfer restarts in theinterrupt processing routine. Thus, to disable the DMA transfer restart in the processing routineof the interrupt cause of the level to interrupt DMA transfer after the interrupt cause is cleared,use the disable function. The DMA disable function is started by setting a value other than 0 tothe DMA disable register and stopped by setting 0 to the register.

Block diagram

Figure 3.11-8 Block Diagram of the DMA Disable Circuit

Settings

This function is mainly used in interrupt processing routines. Before an interrupt cause iscleared by an interrupt processing routine, the DMA disable register is incremented by 1, thenDMA transfer will not be performed. After completing interrupt processing, the DMA disableregister is decremented by 1 before returning. For a multi-interrupt, the DMA transfer will still bedisabled because the DMA disable register is not yet 0. If the interrupt is not a multi-interrupt,the DMA transfer is immediately enabled because the DMA disable register is 0.

PDRR

D3

D2

D1

D0 .nor..and.

State transition control circuit

Internal bus

DMA request

117


[Example]

<Precautions>

• Since the number of bits of the register is four, this function cannot be used for multi-interrupts exceeding the 15 levels. Be sure to place the priority of a DMA task at least 15levels higher than other interrupt levels.

• Since causes are automatically cleared when an NMI interrupt is accepted for, DMA transferrestarts after accepting the interrupt.

INTENTRY

LDI:20 #PDRR,R10

LD @R10,R1 ; GET PDRR VALUE INTO R1

ADD #1,R1

ST R1,@R10 ; PDRR:=PDRR+1, DMA disabled

LDI:20 #int-REG,R10 ; int occurred with int-REG

LDI:8 #10H,R1 ; example, int-flaG=#10h

ST R1,@R10 ; CLEAR int-REQ, (but still DMA disabled)

:

; INTErrupt execute routine

:

LDI:20 #PDRR,R10

LD @R10,R1 ; GET PDRR VALUE INTO R1

ADD2 #-1,R1

ST R1,@R10 ; PDRR:=PDRR-1, DMA may be enabled

RETI

118


3.11.15 Clock Doubler Function

To avoid more demanding external bus timing with an increase of the internal operating frequencies, the ratio between the external bus frequency and internal operating frequency can be taken to be 1:2.

Starting the Clock Doubler Function

The clock doubler function is enabled by setting DBLON of GCR to 1. If DBLON is set to 1, theexternal bus clock is switched when all access of C-BUS is completed. Thus, there is sometime lag, and the timing of switching can be known through the value of DBLAK of GCR.

If the clock doubler function is started, the gear for the CPU system will be 1/1 regardless of thesetting of GCR.

<Precautions>

In this device, up to 25 MHz can be set as the operating frequency of the external bus. Thus, toturn on the clock doubler function, proceed as shown below:

[Example]

Stopping the Clock Doubler Function

The clock doubler function is disabled by setting DBLON of GCR to 0. At the same time, thegear of the CPU system returns from 1/1 to the setting of the CCK bit.

[Example]

To use the clock of PLL after turning off the clock doubler function, proceed as shown below:

DOUBLER-ON

LDI:20 #GCR,R0

BORL #0001B,@R0 ; Switching to 2 dividing system (CHC=1)

BORH #0001B,@R0 ; Clock doubler ON (DBLON=1)

LOOP

BTSTH #0010B,@R0 ; DBLAK check

BEQ LOOP ; Loop until DBLAK becomes 1

BANDL #1110B,@R0 ; Switching to PLL system (CHC=0)

DOUBLER-OFF

LDI:20 #GCR,R0


BANDH #1110B,@R0 ; Clock doubler OFF (DBLON=0)

119


[Example]

Precautions for ON-OFF of the Clock Doubler Function

If the clock doubler is turned on and turned off, dead cycles may occur in the internal clock.Dead cycles appear as errors in time measurement by the timer or in UART transfer.

Combination of the Operating Frequencies by ON/OFF of the Clock Doubler Function

The operating frequencies of this device are determined by a combination of the SLCT1-0 bitsof the PCTR register and settings of the GCR register as shown in the following table (Examplein which 12.5 MHz is used as the source frequency):

DOUBLER-OFF

LDI:20 #GCR,R0


BANDH #1110B,@R0 ; Clock doubler OFF (DBLON=0)

LDI:20 #PCTR,R1

LDI:8 #01000000B,R2

STB R2,@R1 ; PLL=25 MHz

BANDL #1110,@R0 ; Switching to PLL (CHC=0)

GCR Oscillation frequency

of PLL (MHz)

Clock doubler

Internal operating frequency

(MHz)

External bus

frequency (MHz)

Remarks

CHC Gear

2 dividing

1/1 - OFF 6.25 6.25

1/2 - OFF 3.12 3.12

1/4 - OFF 1.56 1.56

1/8 - OFF 0.78 0.78 Initial value

(*1) - ON 6.25 3.12

PLL (*3) - 50.0 OFF 50.0 50.0 Setting prohibited

1/1 25.0 OFF 25.0 25.0

1/2 25.0 OFF 12.5 12.5

1/4 25.0 OFF 6.25 6.25

1/8 25.0 OFF 3.12 3.12

1/1 12.5 OFF 12.5 12.5

120


*1: Fixed to 1/1 regardless of settings

*2: Switch to the 2 dividing system before turning off the clock doubler.

*3: It is necessary to switch to the 2 dividing system to change the oscillation frequency of PLL.

PLL (*3) 1/2 12.5 OFF 6.25 6.25

1/4 12.5 OFF 3.12 3.12

1/8 12.5 OFF 1.56 1.56

(*1) 50.0 ON 50.0 25.0 (*2)

(*1) 25.0 ON 25.0 12.5

(*1) 12.5 ON 12.5 6.25

GCR Oscillation frequency

of PLL (MHz)

Clock doubler

Internal operating frequency

(MHz)

External bus

frequency (MHz)

Remarks

CHC Gear

121


3.11.16 State Transition Diagram

Figure 3.11-9 shows a state transition diagram.

State Transition Diagram

Figure 3.11-9 State Transition Diagram

Power-on

Oscillation

Reset state

Running state

Sleep state

Stop state

Oscillation

(3)(1)

(1)

(5)

(2)

(3)

(6)

(3)

(4) (5)

(3)

(1) Oscillation stabilization wait time end(2) Reset release(3) Reset input(4) STCR register SLEP=1(5) Interrupt input or NMI input(6) STCR register STOP=1

Hardware standby state

(7)

(7)

(8)

(7)

(7)

(7)

(7) Hardware standby input(8) Hardware standby release

stabilization wait reset state

stabilization wait state

122


3.11.17 Example of PLL Clock Settings

The following figure shows an example of procedures for switching to the 50 MHz operation using PLL.

Example of PLL Clock Settings

Figure 3.11-10 Example of PLL Clock Settings

Notes

1. Bits DBLON, VSTP, and SLCT1, indicated above, can be set in any order.

2. The operating frequency of the peripheral must not exceed more than 25 MHz.

NoCHC = 1

CHC -1Yes

NoDBLON = 1

DBLON -1Yes

DBLACK= 1No

Yes

NoVSTP = 0

VSTP -0Yes

WAIT 100

SLCT1 -1

CHC -0

Before making any settings related to PLL,

By turning on the doubler, the gear is fixed to CPU=1/1.

PLL is restarted if it is stopped. When PLL is restarted,

Switch the output tap from PLL to 50 MHz

Switch the clock from the 2 dividing system to PLL

switch to the 2 dividing clock.

Any setting is allowed for peripherals.

at least 100 µs of wait time must be taken by software

for stabilization.

123


3. When VCO of PLL is restarted, 100 µs or more of wait time must be taken by software forstabilization. Also note that setting the cache memory or other operations on or off must notresult in insufficient wait time.

Clock System Reference Diagram

Figure 3.11-11 Clock System Reference Diagram

Example of an Assembler Source

2 dividing CHC DBLON CPU

12.5MHz 1/2 1 DBLACKPLL input 0 Peripherals

Source frequency input

1/250MHz SLCT1,0 GCR register

1 X0 1

VSTP 1/2 0 0STAND-BY 25MHz

PCTR register

1/212.5MHz

system input

; ************************************************************

; PLL Sample Program

; ************************************************************

; Load Setting Data

ldi:20 #GCR, R0

ldi:20 #PCTR,R1

ldi:8 #GCR_MASK,R2 ; GCR_MASK = 0000 0001 b

ldi:8 #PCTR_MASK,R3 ; PCTR_MASK = 0000 1000 b

ldub @R0,R4 ; read GCR register

ldub @R1,R5 ; read PCTR register

st PS,@-R15 ; push processor status

stilm #0x0 ; disable interrupt

;

and R4,R2

beq CHC_0

bra CHC_1

124


CHC_0:

borl #0001B,@r0 ; to 1/2 clock @r0=GCR register

CHC_1:

call VCO_RUN

call DOUBLER_ON

PLL_SET_END:

ld @R15+, PS ; pop processor status

; ************************************************************

; VCO Setting

; ************************************************************

VCO_RUN:

st R3,@-R15 ; push R3

ldi:8 #PCTR _MASK,R3 ; PCTR_MASK =0000 1000 b

and R5, R3 ; PTCR->VSTP=1 ?

beq LOOP_100US_END ; if VSTP = 0 return

st R2, @-R15 ; push R2 for LooPCounter

bandl #0111B,@r1 ; set VSTP = 0

ldi:20 #0x15E,R2 ; wait 100 µS

WAIT_100US: ; 100us = 160ns(6.25MHz) * 7 * 100 (2BC)cycle

add2 #(-1), R2 ; 2BCh/2 = 15Eh (if cache on)

bne WAIT_100US ;

LOOP_100US_END:

ld @R15+, R2 ; Pop R2

ld @R15+, R3 ; Pop R3

ret

; ************************************************************

; doubler ON

; ************************************************************

DOUBLER_ON:

borh #0001B,@r0 ; doubler ON

LOOP_DBLON1:

btsth #0010B,@r0 ; check DBLACK

125


beq LOOP_DBLON1 ; loop while DBLACK = 0

bandl #1110B,@r0 ; to 1/1(PLL) clock

nop

nop

nop

nop

nop

nop

ret

126


3.11.18 List of Blocks Using the Peripheral System Clock

This section shows the blocks using the peripheral system clock that can be set by the gear function. See the clock generator (operation) in 3.11.12 Gear Function.

List of Blocks Using the Peripheral System Clock

In the following blocks, the peripheral clock is used as the operating clock.

Calculate the operating time based on the divider ratio specified with the PCK0 and 1 bits of theGCR register in the clock generator.

• Clock generator

• Interrupt controller

• Port D to port F

• U-TIMER (channel 0, 1, 2)

• UART (channel 0, 1, 2)

• A/D converter

• 16-bit reload timer (channel 0, 1, 2)

• External interrupt

• NMI controller

• Delayed interrupt module

127

CHAPTER 4 EXTERNAL BUS INTERFACE

This chapter describes the external bus interface.

4.1 Overview of the External Bus Interface

4.2 Block Diagram

4.3 Bus Interface Areas

4.4 Bus Interface

4.5 List of Registers of the External Bus Interface

4.6 Relationship between Data Bus Widths and Control Signals

4.7 Bus Timing

128


4.1 Overview of the External Bus Interface

The external bus interface controls the interface with the external memory and the external I/O.

Features of the External Bus Interface

The following lists the features of the external bus interface.

• Outputs a 25-bit (32-megabyte) address.

• Consists of six independent banks due to the chip select function.

• Allows the user to set an area at any location in the logical address space in steps of 64kilobytes at the minimum.

• Allows the user to set the total of six 32-megabyte areas due to the address pin and thechip select pin.

• Allows the user to set a 16-bit or 8-bit bus width for each chip select area.

• Inserts programmable, automatic memory wait (seven cycles at the maximum).

• Supports the DRAM interface.

• Three types of DRAM interfaces <Double CAS DRAM (normal DRAM interface), singleCAS DRAM, hyper DRAM)

• Two banks independently controlled (control signals such as RAS and CAS)

• Allows the user to select either 2CAS/1WE or 1CAS/2WE DRAM.

• Supports the fast page mode.

• Supports the CBR/self refresh mode.

• Programmable waveform

• Can use unused addresses or data pins as I/O ports.

• Supports the little endian mode.

• Uses a clock doubler. Internal 50 MHz and external bus 25 MHz operation.

129

4.2 Block Diagram

4.2 Block Diagram

Figure 4.2-1 shows a block diagram of the external bus interface.

Block Diagram of the External Bus Interface

Figure 4.2-1 Block Diagram of the External Gus Interface

32 32 A-OUT

EXTERNALDATA BUS

MUX

write buffer switch

read buffer switch

DATA BLOCK

ADDRESS BLOCK

+1or+2

EXTERNALADDRESS BUS

inpage

address buffer shifter

ASR CS0X-CS5X

AMR

comparator

DRAM control RAS0,RAS1CS0L,CS1LCS0H,CS1H

underflow DW0X,DW1XDMCR

refresh counter

from TBT

External bus controller RDXWR0X,WR1X

All blocks controlBRQ

registers BGRNTX& CLK

control RDY

ADDRESS BUS DATA BUS

130


4.3 Bus Interface Areas

The bus interface provides the total of six types of chip select areas.

Bus Interface Areas

Area Select Registers (ASRs) 1 to 5 and Area Mask Registers (AMRs) 1 to 5 can be used toplace an area at any location in a four-gigabyte space in steps of 64 kilobytes at the minimum(*1).

If an area specified in these registers is accessed via the external bus, a corresponding chipselect signal from CS0X to CS5X becomes active "L". Upon reset, these pins, excepting CS0X,become inactive "H".

*1 Area 0 is allocated to a space other than the areas specified in ASRs 1 to 5. Upon reset, anexternal area other than 00010 0000H to 0005 FFFFH is Area 0.

Figure 4.3-1 (a) shows an example of placing Areas 1 to 5 in 00100000H to 0014FFFFH in stepsof 64 kilobytes. Figure 4.3-1 (b) shows an example of placing Area 1 in 00000000H to0007FFFFH in steps of 512 kilobytes and Areas 2 to 5 in 00100000H to 004FFFFFH in steps ofone megabyte.

Figure 4.3-1 Chip Select Area Setting Example

00000000H 00000000H CS1X(512K)

00080000H CS0X(512K)

00080000H CS0X(1M byte) 000FFFFFH

CS2X(1M byte)

000FFFFFH 001FFFFFH

0010FFFFH CS1X(64k byte) CS3X(1M byte)

0011FFFFH CS2X(64k byte) 002FFFFFH


0013FFFFH CS4X(64k byte) 003FFFFFH


004FFFFFH

CS0X CS0X

(a) (b)

131

4.4 Bus Interface

4.4 Bus Interface

Two types of bus interface are provided: a normal bus interface and a DRAM interface. These interfaces can be used only in a predefined area.

Bus Interface

Table 4.4-1 shows the correspondence between chip select areas and available interfacefunctions. An Area Mode Register (AMD) is used to select the interface that should be used.

If no interface is selected, a normal bus interface is used.

DRAM Interface

A DRAM interface provides two channels and uses Areas 4 and 5.

• Three types of DRAM interfaces <Double CAS DRAM (normal DRAM interface), single CASDRAM, and hyper DRAM>

• Fast page mode

• Selection of 2CAS/1WE or 1CAS/2WE

• CBR refresh method

• Self refresh mode

• Programmable waveform output for RAS and CAS

Specifying the Bus Size

Each area may have any bus width specified in the setting in a register.

When the register is reset, area 0 has a bus width specified in pins MD 2, 1, and 0. After themode register (MODR) is written, area 0 has a bus size specified in the AMD 0 register.

Table 4.4-1 BUS-1

Area Available bus interface Remarks

Normal bus Time sharing

DRAM

0 O - - Upon reset

1 O - -

2 O - -

3 O - -

4 O - O

5 O - O

132



This section shows the list of registers of the external bus interface.

List of Registers of the External Bus Interface

AMD (Area MoDe register)

DSCR (DRAM Signal Control Register)

LER (Little Endian Register)

MODR (MODe Register)

For information on registers ASR through LER, see Sections 4.5.1, "Area Select Register (ASR)and Area Mask Register (AMR)" through 4.5.12, "Little Endian Register (LER)". For informationon the MODR, see Section 3.10, "Operation Mode".

31 -------- 24 23 -------- 16 15 -------- 8 7 -------- 0

(Area Select Reg. 1) (Area Mode Reg. 1)





(ReFresh Control Register)

(External Pin Control 0) (External Pin Control 1)

(DRAM Control Reg. 4) (DRAM Control Reg. 5)

133


4.5.1 Area Select Register (ASR) and Area Mask Register (AMR)

Area Select Registers (ASRs 1 to 5) and Area Mask Registers (AMRs 1 to 5) specify the range of address space corresponding to Chip Select Areas 1 to 5.

Configurations of Area Select Registers (ASRs) and Area Mask Registers (AMRs)

The following shows the configuration of Area Select Registers (ASRs) and Area MaskRegisters (AMRs).

Area Select Registers (ASRs 1 to 5)

Area Mask Registers (AMRs 1 to 5)

15 14 13 12 2 1 0ASR1 Initial value Access

0000 060CH A31 A30 A29 A18 A17 A16 0001H W

15 14 13 12 2 1 0ASR2

0000 0610H A31 A30 A29 A18 A17 A16 0002H W

15 14 13 12 2 1 0ASR3

0000 0614H A31 A30 A29 A18 A17 A16 0003H W

15 14 13 12 2 1 0ASR4

0000 0618H A31 A30 A29 A18 A17 A16 0004H W

15 14 13 12 2 1 0ASR5

0000 061CH A31 A30 A29 A18 A17 A16 0005H W

Address:

Initial value AccessAddress:




134


Area Select Registers (ASRs 1 to 5) and Area Mask Registers (AMRs 1 to 5) specify the rangeof address space corresponding to Chip Select Areas 1 to 5.

ASRs 1 to 5 specify the upper 16 bits of an address (A31 to A16) and mask address bits towhich AMRs 1 to 5 correspond. Each bit in AMRs 1 to 5 indicate "care" when set to "0" and"don’t care" when set to "1".

"Care" means "0" or "1" if the ASR is set to "0" or "1," respectively, to indicate an addressspace.

"Don’t care" means both "0" and "1" regardless of the setting in the ASR to indicate an addressspace.

The following shows an example of a chip select area being specified using an ASR and anAMR combination.

(Example 1)

If we set:

a bit set to "1" in ASR 1 corresponds to a bit set to "0" in AMR 1. Thus, Area 1 has the following64-kilobyte address space:

(Example 2)

If we set:

15 14 13 12 2 1 0AMR1

0000 060EH A31 A30 A29 A18 A17 A16 0000H W

15 14 13 12 2 1 0AMR2

0000 0612H A31 A30 A29 A18 A17 A16 0000H W

15 14 13 12 2 1 0AMR3

0000 0616H A31 A30 A29 A18 A17 A16 0000H W

15 14 13 12 2 1 0AMR4

0000 061AH A31 A30 A29 A18 A17 A16 0000H W

15 14 13 12 2 1 0AMR5

0000 061EH A31 A30 A29 A18 A17 A16 0000H W






ASR1 = 00000000 00000011B

AMR1 = 00000000 00000000B

00000000 00000011 00000000 00000000B (00030000H)

to

00000000 00000011 11111111 11111111B (0003FFFFH)

ASR2 = 00001111 11111111B

135


a bit set to "0" in AMR 2 corresponds to the "care" setting i.e., "1 or 0" in ASR 2, and a bit set to"1" in AMR 2 corresponds to the "don’t care" setting regardless of "1" or "0" in ASR 2. Thus,Area 2 has the following 256-kilobyte address space:

The address space in each of Areas 1 to 5 can be allocated using ASRs 1 to 5 and AMRs 1 to 5in a four-gigabyte space in a minimum of 64 kilobyte steps. The bus access to an areaspecified in one of these registers results in the corresponding chip select pin (CS0X to CS5X)having an "L" output.

Area 0 is allocated to a space other than the areas specified in ASRs 1 to 5 and AMRs 1 to 5.Upon reset, an area other than 0001 000H to 0005 FFFFH is allocated to Area 0 depending onthe initial values in ASRs 1 to 5 and AMRs 1 to 5.

<Precaution>

Set up chip select areas such that overlap does not occur.

Figure 4.5-1 shows a map based on the initial value of 64 kilobytes upon reset and a map basedon the areas set in Examples 1 and 2.

Figure 4.5-1 Examples of Maps for Which Chip Select Areas Have Been Set

AMR2 = 00000000 00000011B

00001111 11111100 00000000 00000000B (0FFC0000H)

to

00001111 11111111 11111111 11111111B (0FFFFFFFH)

Initial value Setting values in Examples 1 and 2

00000000H 00000000H

Area 0

00010000H Area 0

Area 1 64KB

00020000H 00030000H

Area 2 64KB Area 1 64KB

00030000H 00040000H

Area 3 64KB Area 0

00040000H 0FFC0000H

Area 4 64KB

00050000H Area 2 256KB

Area 5 64KB

00060000H 10000000H

Area 0 Area 0

FFFFFFFFH FFFFFFFFH

136


4.5.2 Area Mode Register 0 (AMD 0)

Area Mode Register 0 (AMD 0) specifies the operation mode of Chip Select Area 0 (area other than those specified in ASRs 1 to 5 and AMRs 1 to 5). Upon reset, Area 0 is selected.

Configuration of Area Mode Register 0 (AMD 0)

Area Mode Register 0 (AMD 0) has the following register configuration:

Bit Functions of Area Mode Register 0 (AMD 0)

[bits 4 and 3] BWs 1 and 0 (Bus Width bit)

BWs 1 and 0 specify the bus width of Area 0.

Note

The initial values of BW1 and BW0 are both "0." If MODR is written when the register isread, the terminal levels of MD1 and MD0, not the value of the register, are read.

[bits 2 to 0] WTCs 2 to 0 (Wait Cycle bit)

WTCs 2 to 0 specify the automatic wait insertion count when the normal bus interface isused.

WTCs 2 to 0 of AMD 0 are set to "111" upon reset. Immediately after the reset is cleared, a

7 6 5 4 3 2 1 0AMD0

0000 0620H BW1 BW0 WTC2 WTC1 WTC0 ---00111H R/WAddress:


BW1 BW0 Bus width

0011

0101

8 bits16 bitsProhibitedProhibited

WTC2 WTC1 WTC0 Insertion wait cycle count

00001111

00110011

01010101

01234567

137


seven-cycle wait is automatically inserted in the bus access.

<Precaution>

Before the MODR is written to, set in BWs 1 and 0 of AMD 0 the same bus width as specified inpins MD 2, 1, and 0

The bus width of Area 0 is specified in pins MD 2, 1, and 0 upon reset. After the mode register(MODR) is set, the bus width set in AMD 0 becomes valid.

A malfunction occurs if Area 0 is set to the 16-bit width using pins MD 2, 1, and 0, and theMODR is written with this bus width being left and without setting AMD 0. This is because theBWs 1 and 0 of AMD 0 has the initial value "00" and the 8-bit bus width is newly selected.

MODR writeRSTX (reset)

CS0 bus width Pins MD 2, 1, and 0 AMD 0 register

138



Area Mode Register 1 (AMD 1) specifies the operation mode of Chip Select Area 1 (area specified in ASR 1 and AMR 1).




[bit 7] MPX (MultiPleX bit)

MPX controls the time sharing input-output interface for address and data input-output.

This product type does not support a time sharing input-output bus.

Always write "0" in this bit.


BWs 1 and 0 specify the bus width of Area 1.


The WTCs specify the automatic wait insertion count when the normal bus interface is used.The operation is the same as WTCs 2 to 0 of AMD 0. Upon reset, the WTCs are initializedto "000" and the insertion wait cycle count becomes 0.

7 6 5 4 3 2 1 0AMD1

0000 0621H MPX BW1 BW0 WTC2 WTC1 WTC0 0--00000 R/WAddress:


BW1 BW0 Bus width

0011

0101

8 bits16 bitsProhibitedreserved

139



Area Mode Register 32 (AMD 32) specifies the operation mode of Chip Select Area 2 (area specified in ASR 2 and AMR 2) and Chip Select Area 3 (area specified in ASR 3 and SMR 3).These areas allow only regular bus access and does not support a special interface of the DRAM interface.For Areas 2 and 3, the same bus width is set in BWs 1 and 0 bits. The automatic wait cycles can be set independently for each of these areas.





BWs 1 and 0 specify the bus width of Areas 2 and 3.

[bits 5 to 3] WTs 32 to 30 (Wait Cycle bit)

WTs 32 to 30 specify the automatic wait insertion count when Area 3 memory is accessed.

The operation is the same as WTCs 2 to 0 of AMD 0.

Upon reset, the WTs are initialized to "000" and the insertion wait cycle count becomes 0.

[bits 2 to 0] WTs 22 to 20 (Wait Cycle bit)

WTs 22 to 20 specify the automatic wait insertion count when the Area 2 memory isaccessed.

The operation is the same as WTCs 2 to 0 of AMD 0.

Upon reset, the WTs are initialized to "000" and the insertion wait cycle count becomes 0.

7 6 5 4 3 2 1 0AMD32

0000 0622H BW1 BW0 WT32 WT31 WT30 WT22 WT21 WT20 00000000 R/WAddress:


BW1 BW0 Bus width

0011

0101


140



Area Mode Register 4 (AMD 4) specifies the operation mode of Chip Select Area 4 (area specified in ASR 4 and AMR 4).Area 4 can use the DRAM interface.




[bit 7] DRME (DRaM Enable bit)

DRME selects either the normal bus interface or the DRAM interface for Area 4.

0: Normal bus interface

1: DRAM interface

To use the DRAM interface, set the DMCR (DRAM Control Register), described later, formore detailed control.


BWs 1 and 0 specify the bus width of Area 4. They have the same function as the BW bitsof other AMD registers. The bus width specified in these bits is valid when the DRAMinterface is used.


WTCs 2 to 0 specify the automatic wait insertion count when the Area 4 memory isaccessed.

WTCs 2 though 0 have the same function as the WTC bit of other AMD registers. Uponreset, the WTCs are initialized to "000" and the insertion wait cycle count becomes 0.

However, when the DRAM interface is used, the wait cycle is controlled in the DMCR. Thus,WTCs 2 to 0 become invalid.

7 6 5 4 3 2 1 0AMD4

0000 0623H DRME BW1 BW0 WTC2 WTC1 WTC0 0--00000 R/WAddress:


BW1 BW0 Bus width

0011

0101


141



Area Mode Register 5 (AMD 5) specifies the operation mode of Chip Select Area 5 (area specified in ASR 5 and AMR 5).Area 5 can use the DRAM interface. Each bit has the same meaning as AMD 4.




[bit 7] DRME (DRaM Enable bit)

DRME selects either the normal bus interface or the DRAM interface for Area 5.

0: Normal bus interface

1: DRAM interface

To use the DRAM interface, set the DMCR for more detailed control.


BWs 1 and 0 specify the bus width of Area 5. They have the same function as the BW bitsof other AMD registers. The bus width specified in these bits is valid when the DRAMinterface is used.


WTCs 2 to 0 specify the automatic wait insertion count when the Area 5 memory isaccessed.

WTCs 2 though 0 have the same function as the WTC bit of other AMD registers. Uponreset, the WTCs are initialized to "000" and the insertion wait cycle count becomes 0.

However, when the DRAM interface is used, the wait cycle is controlled in the DMCR. Thus,WTCs 2 to 0 become invalid.

7 6 5 4 3 2 1 0AMD5

0000 0624H DRME BW1 BW0 WTC2 WTC1 WTC0 0--00000 R/WAddress:


BW1 BW0 Bus width

0011

0101


142


4.5.7 DRAM Control Registers 4 and 5 (DMCRs 4 and 5)

DRAM Control Registers 4 and 5 (DMCRs 4 and 5) control the DRAM interface of Areas 4 and 5. These registers are valid only if the DRME bit of AMDs 4 and 5 is set to "1".

Configuration of DRAM Control Registers 4 and 5 (DMCRs 4 and 5)

DRAM Control Registers 4 and 5 (DMCRs 4 and 5) have the following register configurations:

Bit Functions of DRAM Control Registers 4 and 5 (DMCRs 4 and 5)

[bits 15 to 12] PGSs 3 to 0 (PaGe size Select bit)

PGSs 3 to 0 specify the page size of DRAM to be connected.

The bus interface unit determines the ROW size (page size) based on the values in PGSs 3 to 0and the specified bus width. If, when the register allows the page access mode, access occursin the same page, the fast page access is executed.

15 14 13 12 11 10 9 8DMCR4

0000 062CH PGS3 PGS2 PGS1 PGS0 Q1W Q4W DSAS HYPR 00000000 R/W

7 6 5 4 3 2 1 0

PAGE C/W SLFR REFE PAR PERR PEIE 0000000- R/W

15 14 13 12 11 10 9 8DMCR5

0000 062EH PGS3 PGS2 PGS1 PGS0 Q1W Q4W DSAS HYPR 00000000 R/W

7 6 5 4 3 2 1 0

PAGE C/W SLFR REFE PAR PERR PEIE 0000000- R/W

Address:


Address:




Table 4.5-1 Page Size of DRAM to be Connected

PGS3 to 0 Page size ROW Address Column address

Determining whether access occurs in the same

page

A31 to 16 A15 to 00 8-bit bus 16-bit bus

0000 256 A31 to 16 A23 to 08 A31 to 00 A31 to 08 A31 to 09




0100to1111

reserved

143


[bit 11] Q1W (Q1 wait bit)

Q1W specifies whether or not to automatically extend the Q1 cycle (RAS "H" period) duringDRAM access for one more cycle.

0: Not extending the Q1 cycle (initial value)

1: Extending the Q1 cycle

[bit 10] Q4W (Q4 wait bit)

Q4W specifies whether or not to automatically extend the Q4 cycle (CAS "L" period) duringDRAM access for one more cycle. The Q4W bit is valid only if the DSAS bit (bit 9) is set to"0".

0: Not extending the Q4 cycle (initial value)

1: Extending the Q4 cycle

[bit 9] DSAS (Double/Single cas Access cycle Select bit)

DSAS selects whether the CAS access should be performed in either two cycles (DoubleCAS access) or one cycle (Single CAS access) when the fast page mode is used in theDRAM access.

0: Double CAS access (initial value)

1: Single CAS access

[bit 8] HYPR (HYPeR page mode enable)

HYPR should be set when DRAM with a hyper page mode is externally connected.

The HYPR bit is valid only if the DSAS bit (bit 9) is set to "1".

0: Double/Single CAS DRAM (initial value)

1: DRAM with the hyper page mode

[bit 7] PAGE (PAGe Enable bit)

PAGE specifies whether or not to enable the fast page mode.

0: Disabling the fast page mode (always random-access operation; initial value)

1: Enabling the fast page mode (Performing the same page access specified in PGSs 3 to 0in the fast page mode)

[bit 6] C/W (1CAS-2WE/2CAS-1WE Select bit)

C/W specifies, when a bus width of 16 bits or more is used, whether to interface with 1CAS-2WE type memory or 2CAS-1WE type memory.

0: 1CAS-2WE interface (initial value)

1: 2CAS-1WE interface

[bit 5] SLFR (SeLF Refresh bit)

Writing "1" in SLFR puts the DRAM in the self refresh mode.

Writing "1" in this bit of DMCR 4 or 5 activates the self refresh mode regardless of Area 4 or5.

SLFR can be read from or written to at any timing. However, if the self refresh mode ofDRAM is terminated, sufficient RAS recovery time must be secured.

0: Terminating the self refresh (initial value)

1: Activating the self refresh

144


[bit 4] REFE (REFresh Enable bit)

REFE specifies whether or not to perform a periodical refresh operation in the CBR (CASBefore RAS) method. Writing "1" in this bit of DMCR 4 or 5 and writing the STR bit of RFCR(ReFresh Control Register) starts the refresh cycle regardless of Area 4 or 5.

0: Not performing refresh (initial value)

1: Performing refresh. Refresh is performed in the cycle specified in RFCR (ReFresh ControlRegister).

[bit 3] PAR (PARity select bit)

This device does not support the parity function.

Writing to this bit is meaningless.

[bit 2] PERR (Parity ERRor bit)


Writing to this bit is meaningless.

[bit 1] PEIE (Parity Error Interrupt Enable bit)

PEIE specifies whether or not to output an interrupt request if a parity error occurs.


Always write "0" in this bit.

Combinations of Bus Widths

The following table shows the combinations of bus widths that can be used in Areas 4 and 5.

Table 4.5-2 Combinations of Bus Widths that can be Used in Areas 4 and 5

Combination Area 4 Area 5

1 Normal: 16 or 8 bits Normal: 16 or 8 bits

2 Normal: 16 or 8 bits DRAM: 16 bits (C/W = 0, 1)

3 Normal: 16 or 8 bits DRAM: 8 bits (C/W = 0, 1)

4 DRAM: 16 bits (C/W = 0, 1) Normal: 16 or 8 bits

5 DRAM: 16 bits (C/W = 0, 1) DRAM: 16 bits (C/W = 0, 1)


7 DRAM: 8 bits (C/W = 0, 1) Normal: 16 or 8 bits



145


4.5.8 Refresh Control Register (RFCR)

Refresh Control Register (RFCR) controls the Cas Before Ras (CBR) refresh operation using the DRAM interface.There is a six-bit down counter that uses one-32nd division output of the time-base timer as the clock source. RFCR controls this reload value to specify a refresh interval.

Configuration of Refresh Control Register (RFCR)

Refresh Control Register (RFCR) has the following register configuration:

The time-base timer, a counter of oscillation stabilization wait intervals, etc., operates at half thefrequency of X0 if CHC = 1 in Gear Control Register (GCR) and at the same frequency as theinternal PLL oscillation frequency if CHC = 0. For example, if CHC = 0 and the PLL oscillationfrequency is 50 MHz, one cycle is 20 nanoseconds and one refresh interval is 20 x 32 = 64nanoseconds.

The refresh is counted based on the output of the time-base timer whether the clock doubler isturned on or off.

Bit Functions of Refresh Control Register (RFCR)

[bit 13 to 8] REL (REfresh intervaL bits)

The REL register sets the refresh interval.

During reading, a value is read from the down counter counting the refresh interval.

DRAM in Areas 4 and 5 is refreshed at the same time in the interval specified in REL.

[bit 7] R1W (Refresh 1 Wait)

R1W extends the first refresh cycle (R1) for one more cycle.

0: No wait (initial value)

1: Wait

[bit 6] R3W (Refresh 3 Wait)

R3W extends the third refresh cycle (R3) for one more cycle.

0: No wait (initial value)

1: Wait

15 14 13 12 11 10 9 8

RFCR REL5 REL4 REL3 REL2 REL1 REL0 --XXXXXX R/W0000 0626H

7 6 5 4 3 2 1 0

R1W R3W STR CKS1 CKS0 00---000 R/W

Address:



146


[bit 2] STR (STaRt bit)

STR controls start and stop of the down counter.

0: STOP (initial value)

1: START

Setting STR loads the REL value to the down counter at the same time.

Setting REFE of DMCR to "1" and STR to "1" performs CBR refresh.

[bit 1, 0] CKS (Clock Select bit)

CKS selects the clock source of the down counter.

The down counter uses the one-32nd division output ( of the time-base timer as the clock.

CKS1 CKS0 Source clock Max clock count

0 0 Φ (initial value) 26 (RELs 5 - 0: 6 bits) x 32 (one-32nd division) = 2048

0 1 Φ/8 26 (RELs 5 - 0: 6 bits) x 32 (one-32nd division) x 8 = 16384

1 0 reserved

1 1 reserved

147


4.5.9 External Pin Control Register 0 (EPCR 0)

External Pin Control Register 0 (EPCR 0) controls the output of each signal.If the output is allowed, the desired timing is output in each bus mode. If the input is enabled, an input signal from the outside is accepted.If the output is prohibited or the input is disabled, this register can be used as an I/O port.

Configuration of External Pin Control Register 0 (EPCR 0)

External Pin Control Register 0 (EPCR 0) has the following register configuration:

Bit Functions of External Pin Control Register 0 (EPCR 0)

[bit 11] WRE (WRite pulse output Enable bit)

WRE selects whether or not to output a write pulse WR0X-1X.

Upon reset, this bit is set to Output Allowed.

0: Output prohibited

1: Output allowed (initial value)

For this product type, always set the WRE bit to "1" because this bit is not used to control theWR0X-1X pin as an I/O port.

Even if the WRE bit is set to "1", the WR0X-1X pin can be used as an I/O port for a writepulse depending on the bus width set in AMD. (For example, WR1X is not output in theeight-bit mode and a corresponding pin can be used as an I/O port.)

[bit 10] RDXE (ReaDX pulse output Enable bit)

RDXE selects whether or not to output the read pulse RDX.

Upon reset, this bit is set to Output Allowed.

0: Output prohibited (setting prohibited)


For this product type, always set the RDXE bit to "1" because this bit is not used to controlthe RDX pin as an I/O port.

[bit 9] RDYE (ReaDY input Enable bit)

RDYE controls the RDY input as follows:

Upon reset, this bit is set to Input Disabled.

15 14 13 12 11 10 9 8EPCR0

0000 0628H WRE RDXE RDYE BRE ----1100 W

7 6 5 4 3 2 1 0

CKE COE5 COE4 COE3 COE2 COE1 COE0 -1111111 W

Address:



148


0: RDY input disabled (initial value)

1: RDY input enabled

[bit 8] BRE (Bus Request Enable bit)

BRE controls BRQ and BGRNTX as follows:

Upon reset, this bit is set to BRQ Input Disabled and BGRNTX Output Prohibited.

0: BRQ input disabled and BGRNTX output prohibited (The pin acts as an I/O port.) (initialvalue)

1: BRQ input enabled and BGRNTX output allowed

[bit 6] CKE (ClocK output Enable bit)

CKE enables the output of CLK (operating clock waveform of the external bus).



This bit is initialized to "1" upon reset, causing CLK to be output.

[bit 5] COE5 (Chip select Output Enable 5)

COE5 controls the output of CS5X. Upon reset, this bit is set to Output Allowed.









For this product type, the CS3X pin is also used for the E0P1 output of DMAC. Thus, theCS3X pin is controlled in combination with the EPSE1 and EPDE1 bits of DMAC ControlRegister (DATCR) as follows:








EPSE1 EPDE1 COE3

00011

00101

01XXX

PortCS3X output (initial value)E0P1 outputE0P1 outputE0P1 output

149





0: Output prohibited (setting prohibited)


For this product type, always set the COE0 bit to "1" because this bit is not used to controlthe CS0X pin as an I/O port.

150


4.5.10 External Pin Control Register 1 (EPCR 1)

External Pin Control Register 1 (EPCR 1) controls the output of an address signal.

Configuration of External Pin Control Register 1 (EPCR 1)

External Pin Control Register 1 (EPCR 1) has the following register configuration:

Bit Functions of External Pin Control Register 1 (EPCR 1)

[bit 7] AE23 (Address output Enable 23)

AE23 specifies whether or not to output Address 23.

If output is prohibited, the pin can be used as an I/O port.



AE23 also specifies whether or not to output Address 24 to the A24/E0P0 pin.

The Address 24 pin can be specified to output E0P0 of DMAC depending on the setting inEPSE0 and EPDE0 of DMAC Pin Control Register (DATCR).

The following shows the relationship between AE23 and EPSE0 and EPDE0.

*1 If one or both of EPSE0 and EPDE0 is set to 1

[bits 6 to 0] AEs 22 to 16 (Address output Enable 22 to 16)

AEs 22 to 16 specify whether or not to output a corresponding address.

If output is prohibited, this register can be used as an I/O port.



Upon reset, AEs 23 to 16 are initialized to "FFH".

EPCR10000 062BH

7 6 5 4 3 2 1 0

AE22 AE21 AE20 AE19 AE18 AE17 AE16 11111111 WAddress:


AE23

AE23 EPSE0 EPDE0 A24 pin

1 0 0 A24

0 0 0 "H" or "L"

- 1 (*1) 1 (*1) E0P0

151


4.5.11 DRAM Signal Control Register (DSCR)

DRAM Signal Control Register (DSCR) controls the output of each DRAM control signal. If output is prohibited, this register can be used as an I/O port.

Configuration of DRAM Signal Control Register (DSCR)

DRAM Signal Control Register (DSCR) has the following register configuration:

<Precaution>

For the MB91101, do not mix CAS output and output ports among the CAS0L, CAS0H, CAS1L,and CAS1H pins. To mix CAS output and input ports or DMAC pins, write "1" in PDRcorresponding to the input port or DMAC pin. For the MB91101A, this restriction does not exist.

Bit Functions of DRAM Signal Control Register (DSCR)

[bit 7] DW1E

DW1E controls the output of DW1X. Upon reset, this pin is set to Output Prohibited.

0: Output prohibited (initial value)

1: Output allowed

[bit 6] DW0E

DW0E controls the output of DW0X. Upon reset, this pin is set to Output Prohibited.


1: Output allowed

[bit 5] C1HE

C1HE controls the output of CS1H. Upon reset, this pin is set to Output Prohibited.

For this product type, the CS1H pin is also used for the DACK2 output of DMAC. Thus, theCS1H pin is controlled in combination with the AKSE2 and AKDE2 bits of DMAC ControlRegister (DATCR) as follows:

[bit 4] C1LE

C1LE controls the output of CS1L. Upon reset, this pin is set to Output Prohibited.


7 6 5 4 3 2 1 0DSCR

0000 0625H DW1E DW0E C1HE C1LE C0HE C0LE RS1E RS0E 00000000 WAddress:


AKSE2 AKDE2 C1HE

00011

00101

01XXX

Port (initial value)C1HE outputDACK2 outputDACK2 outputDACK2 output

152


1: Output allowed

[bit 3] C0HE

C0HE controls the output of CS0H. Upon reset, this pin is set to Output Prohibited.


1: Output allowed

[bit 2] C0LE

C0LE controls the output of CS0L. Upon reset, this pin is set to Output Prohibited.


1: Output allowed

[bit 1] RS1E

RS1E controls the output of RAS1. Upon reset, this pin is set to Output Prohibited.

For this product type, the RAS1 pin is also used for the EOP2 output of DMAC. Thus, theRAS1 pin is controlled in combination with the EPSE2 and EPDE2 bits of DMAC ControlRegister (DATCR) as follows:

[bit 0] RS0E

RS0E controls the output of RAS0. Upon reset, this pin is set to Output Prohibited.


1: Output allowed

EPSE2 EPDE2 RS1E

00011

00101

01XXX

Port (initial value)RAS1 outputEOP2 outputEOP2 outputEOP2 output

153


4.5.12 Little Endian Register (LER)

The bus access in the MB91101 is normally performed in the big endian method. Setting Little Endian Register (LER) allows the user to handle one of Areas 1 to 5 as a little endian area.This function is supported on all the bus modes regardless of the normal, time-sharing, or DRAM interface. However, Area 0 is not subject to the little endian method.

Configuration of Little Endian Register (LER)

Little Endian Register (LER) has the following register configuration:

Bit Function of Little Endian Register (LER)

As shown in the following table, specify a little endian area using the combination of LE2, LE1,and LE0 bits.

Data can be written to the LER register only once after the reset.

7 6 5 4 3 2 1 0LER

0000 07FEH LE2 LE1 LE0 -----000 WAddress:


Table 4.5-3 Mode Setting Using the Combination of Bits (LE2, LE1, and LE0)

LE2 LE1 LE0 Mode

0 0 0 Initial value after reset.No little endian area exists.

0 0 1 Area 1 is little endian.Areas 0 and 2 to 5 are big endian.

0 1 0 Area 2 is little endian.Areas 0, 1, and 3 to 5 are big endian.

0 1 1 Area 3 is little endian.Areas 0 to 2, 4, and 5 are big endian.

1 0 0 Area 4 is little endian.Areas 0 to 3 and 5 are big endian.

1 0 1 Area 5 is little endian.Areas 0 to 4 are big endian.

154


4.5.13 Mode Register (MODR)

Data that is written into "0000 07FFH" by CPU after the reset is called mode data.

What exists at "0000 07FFH" is a mode register (MODR). After this register is set,

operation proceeds in a mode that is set in this register.The mode register can be set only once by being written in following the reset.The setting by this register is enabled immediately after the write operation into this register.

Configuration of Mode Register (MODR)

Bus Mode Setting Bit (M1, M0)

This bit specifies the bus mode after the write operation into the mode register.

The following table lists the relations between bits and the functions.

Note:

For product types without internal ROM, set only "10" in the above table. Thus, only "10" canbe set for this product type.

Other Bits (*)

Set always "0" to these bits.

<Precautions>

Be sure to set AMD0 to AMD5 to determine the bus width of each CS (ChipSelect) area beforewriting into MODR. MODR has no bit to set its bus width.

The values of the mode pins MD2 to 0 determine the bus width before writing into MODR, andthe values set in BW1 and 0 of AMD0 to 5 determine the bus width after writing into MODR. Forexample, the external reset vector is normally done in the area 0 (area in which CS0X is active)and the bus width at this time is determined by the MD2 to 0 pins. If the bus width is set to 16

Initial value

MODR address:000007FFH M1 M0 * * * * * * XXXXXXXX W

Bus mode setting bit

Access

Table 4.5-4 Bus Mode Setting Bit and the function

M1 M0 Function Remarks

0 0 Single chip mode

0 1 Internal-ROM-external bus mode

1 0 External-ROM-external bus mode

1 1 - Setting prohibited

155


bits this time using MD2 to 0 and a write operation is performed to MODR without settinganything to AMD0, a malfunction will occur because the initial value of the bus width of AMD0 isset to 8 bits and the area 0 makes a transition to the 8-bit bus mode for bus operation after thewrite operation to MODR. To prevent such problems, set AMD0 to 5 before writing into MODR.

MODR write

RSTX (reset)

Bus width setting MD2,1,0 BW1, 0 of AMD0-5

156



Control signals in the data bus (WR0X-1X, CS0H, CS1L, CS1H, DW0X, and DW1X) always correspond to the byte locations in the data bus regardless of the big or little endian setting or the data bus width.

Relationship between Data Bus Widths and Control Signals

This section describes the byte locations in the data bus for the product type used in the databus width specified for each bus mode as well as the corresponding control signals.

Data bus widths and control signals in the normal bus interface

Figure 4.6-1 Data Bus Widths and Control Signals in the Normal Bus Interface

Data bus widths and control signals in the DRAM interface

Figure 4.6-2 Data Bus Widths and Control Signals in the DRAM Interface

Table 4.6-1 sums up the above data.

Data bus Control signal Control signal

D31 D31WR0X WR0X

D24WR1X

D16

(D23 to D16 are not used.)

Data bus

D31 D31CASL WEL CAS WE

D24CASH WEH

D16

Data bus Control signal Control signal

(D23 to D16 are not used.)

Data bus

157


Table 4.6-1 Relationship between Data Bus Widths and Control Signals

Bus width 16-bit bus width 8-bit bus width

Data bus WR 2CAS/1WE 1CAS/2WE WR 2CAS/1WE 1CAS/2WE

D31-D24 WR0X CASL WEL WR0X CAS WE

D23-D16 WRIX CASH WEH

158


4.6.1 Big Endian Bus Access

An area for which Little Endian Register (LER) is not set can be accessed via the external bus in the big endian method.The FR series is normally big endian.

Data Format

The following figures show the relationship between an internal register and an external databus.

Word access (when the LD or ST instruction is executed)

Figure 4.6-3 Relationship between an Internal Register and an External Data Bus in the Word Access

Half word access (when the LDUH or STH instruction is executed)

Figure 4.6-4 Relationship between an Internal Register and an External Data Bus in the Half Word Access

AA AA CC

BB BB DD

CC

DD

D31

D23

D15

D07

D31

D23

Internal register External bus

AA

BB

AA

BB

D31

D23

D15

D07

D31

D23


159


Byte access (when the LDUB or STB instruction is executed)

Figure 4.6-5 Relationship between an Internal Register and an External Data bus in the Byte Access

Data Bus Width

The following figures shows the relationship between an internal register and an external databus for each data bus width.

16-bit bus width

Figure 4.6-6 Relationship between an Internal Register and an External Data Bus for the 16-bit Bus Width

AA

AA

AA AA

D31

D23

D15

D07

D31

D23

D31

D23

D15

D07

D31

D23

Internal register External bus Internal register External bus

(a) Output address low-order "0" (b) Output address low-order "1"

"00" "10"

AA Read/Write AA CC

BB BB DD

CC

DD

D31

D23

D15

D07

D31

D23


Output address low-order

160


8-bit bus width


External Bus Access

Figures 4.6-8 and 4.6-9 show the external bus access (for the 16-bit and 8-bit bus width) in theword, half word, and byte access. These figures also show the following items:

• Access byte location

• Program address and output address

• Bus access count

<Precaution>

The MB91101 does not detect a misalign error. If, in the word access, an address specified in aprogram has the low-order two bits "00", "01", "10", or "11", the output address invariably hasthe low-order two bits "00". If, in the half word access, the former has "00" and "01" or "10" and"11", the latter has "00" or "10", respectively.

"00" "01" "10" "11"Read/Write

AA AA BB CC DD

BB

CC

DD

D31

D23

D15

D07

D31



161


16-bit bus width

Figure 4.6-8 External Bus Access for the 16-bit Bus Width

PA1/PA0= 00 PA1/PA0= 01 PA1/PA0= 10 PA1/PA0= 11

A1/A0= 00 A1/A0= 00 A1/A0= 00 A1/A0= 00

A1/A0= 10 A1/A0= 10 A1/A0= 10 A1/A0= 10

MSB LSB

00 01 00 01 00 01 00 01

10 11 10 11 10 11 10 11

16bit

PA1/PA0= 00 PA1/PA0= 01 PA1/PA0= 10 PA1/PA0= 11

A1/A0= 00 A1/A0= 00 A1/A0= 10 A1/A0= 10

00 01 00 01 00 01 00 01

10 11 10 11 10 11 10 11

PA1/PA0= 00 01 PA1/PA0= 10 PA1/PA0= 11

A1/A0= 00 A1/A0= 01 A1/A0= 10 A1/A0= 11

00 01 00 01 00 01 00 01

10 11 10 11 10 11 10 11

(a) (b) (c) (d)

(a) (b) (c) (d)

(a) (b) (c) (d)

PA1/PA0 : Low-order two bits of an address specified in a programOutput A1/A0 : Low-order two bits of an output address : Leading byte location of an output address : Data byte location to be accessed1) to 2) : Bus access count

Output Output Output OutputOutput Output Output Output

Output Output Output Output


(A) Word access

(B) Half word access

(C) Byte access

PA1/PA0=

162


8-bit bus width

Figure 4.6-9 External Bus Access for the 8-bit Bus Width

PA1/PA0= 00 PA1/PA0= 01 PA1/PA0= 10 PA1/PA0= 11A1/A0= 00 A1/A0= 00 A1/A0= 00 A1/A0= 00A1/A0= 01 A1/A0= 01 A1/A0= 01 A1/A0= 01A1/A0= 10 A1/A0= 10 A1/A0= 10 A1/A0= 10A1/A0= 11 A1/A0= 11 A1/A0= 11 A1/A0= 11

MSB LSB

00 00 00 00

01 01 01 01

10 10 10 10

11 11 11 11

8bit

PA1/PA0= 00 PA1/PA0= 01 PA1/PA0= 10 PA1/PA0= 11A1/A0= 00 A1/A0= 00 A1/A0= 10 A1/A0= 10A1/A0= 01 A1/A0= 01 A1/A0= 11 A1/A0= 11

00 00 00 00

01 01 01 01

10 10 10 10

11 11 11 11

PA1/PA0= 00 PA1/PA0= 01 PA1/PA0= 10 PA1/PA0= 11A1/A0= 00 A1/A0= 01 A1/A0= 10 A1/A0= 11

00 00 00 00

01 01 01 01

10 10 10 10

11 11 11 11

(a) (b) (c) (d)

(d)(c)(b)(a)

(a) (b) (c) (d)

PA1/PA0 : Low-order two bits of an address specified in a programOutput A1/A0 : Low-order two bits of an output address : Leading byte location of an output address : Data byte location to be accessed1) to 4) : Bus access count


(A) Word access

(B) Half word access

(C) Byte access

Output Output Output OutputOutput Output Output Output





163


Example of Connecting the MB91101 with an External Device

Figure 4.6-10 Example of the MB91101 being Connected to an External Device

This LSI

W WD31 R D23 R

0 1D24 X D16 X

0 1 X

D15 D08D07 D00 D07 D0016-bit device* 8-bit device*

* For a 16-bit or 8-bit device, the data bus on the MSB side of this LSI is used.("0"/"1" address low-order 1 bit, "X" means that the low-order 1 bit can be "0" or "1")

164


4.6.2 Little Endian Bus Access

An area for which Little Endian Register (LER) is set can be accessed via the external bus in the little endian method.

Overview of the Little Endian Bus Access

The little endian bus access of the MB91101 uses the same bus access operation as the bigendian. The little endian, basically using the same order of output addresses and the output ofthe same control signals as the big endian, only swaps the byte locations of the data busaccording to the bus width.

Ensure that the big endian and little endian areas are physically separated upon connection.

• The addresses are output in the same order both in the big endian and the little endian.

• Word access: The big endian MSB-side byte data corresponding to the address "00" is thelittle endian LSB-side byte data.

• Half word access: The big endian MSB-side byte data corresponding to the address "0" isthe little endian LSB-side byte data.

• Byte access: Both the big endian and little endian works in the same way.

• The data bus control signal to be used in the 16-bit or 8-bit bus width is the same for both thebig endian and the little endian.

Data Format

The following figures show the relationship between an internal register and an external databus.

In the word access, all four bytes in a word have opposite byte locations.

"00" --> "11", "01" --> "10", "10" -->"01", "11" --> "00"

In the half word access, the two bytes in a half word have opposite byte locations.

"0" --> "1", "1" --> "0"

165


Word access (when the LD or ST instruction is executed)

Figure 4.6-11 Relationship between an Internal Register and an External Data Bus in the Word Access

Half word access (when the LDUH or STH instruction is executed)

Figure 4.6-12 Relationship between an Internal Register and an External Data Bus in the Half Word Access

Byte access (when the LDUB or STB instruction is executed)

Figure 4.6-13 Relationship between an Internal Register and an External Data Bus in the Byte Access

AA DD BB

BB CC AA

CC

DD

D31

D23

D15

D07

D31

D23


BB

AA

AA

BB

D31

D23

D15

D07

D31

D23


AA

AA

AA AA

D31

D23

D15

D07

D31

D23

D31 D31

D23

D15

D07

D23

Internal register External busInternal register External bus

(a) Output address low-order "0" (b) Output address low-order "1"

166


Data Bus Width

The following figures shows the relationship between an internal register and an external databus for each data bus width.

16-bit bus width


8-bit bus width


00 10

AA read/Write DD BB

BB CC AA

CC

DD

D31

D23

D15

D07

D31

D23



00 01 10 11read/Write

AA DD CC BB AA

BB

CC

DD

D31 D31

D23

D15

D07



167


Example of the MB91101 being Connected to an External Device

16-bit bus width

Figure 4.6-16 Example of the MB91101 being Connected to an External Device (for the 16-bit Bus Width)

8-bit bus width

Figure 4.6-17 Example of the MB91101 being Connected to an External Device (for the 8-bit Bus Width)

This LSI CSnXCSmX

W WD31 R D23 R

0 1D24 X D16 X

Big endian area Little endian area

WR0X WR1X WR1X WR0XD31-24 D23-16 D23-16 D31-24

MSB LSB MSB LSB

D15 D08D07 D00 D15 D08D07 D00

This LSI CSnXCSmX

W WD31 R D23 R

0 1D24 X D16 X

Big endian area Little endian area

D07 D00 D07 D00

168


4.6.3 External Access

This section shows a list of external access patterns.

Word Access

Bus width

Big endian mode Little endian mode

16-bit bus width

8-bit bus width

Control pin

address: 0 2D31 D31

AA AA CC WR0X CASL WEL

BB BB DD WR1X CASH WEHD16

CC

DDD00

1) 2)

Internal register External pin

address: 0 2D31 D31

AA DD BB WR0X CASL WEL

BB CC AA WR1X CASH WEHD16

CC

DDD00

1) 2)

Control pinInternal register External pin

address: 0 1 2 3D31 D31

AAAA BB CC DD WR0X CAS WE

D24

BB

CC

DDD00

1) 2) 3) 4)


address: 0 1 2 3D31 D31

AA DD CC BB AA WR0XCAS WED24

BB

CC

DDD00

1) 2) 3) 4)


169


Half Word Access

Bus width


16-bit bus width

8-bit bus width

address: 0D31 D31

AA WR0X CASL WEL

BB WR1X CASH WEHD16

AA

BBD00

1)


address: 0D31 D31

BB WR0X CAS0 WEL

AA WR1X CAS1 WEHD16

AA

BBD00

1)


address: 2D31 D31

CC WR0X CASL WEL

DD WR1X CASH WEHD16

CC

DDD00

1)


address: 2D31 D31

DD WR0X CASL WEL

CC WR1X CASH WEHD16

CC

DDD00

1)


address: 0 1D31 D31

AA BB WR0X CAS WED24

AA

BBD00 D00

1) 2)


address: 0 1D31 D31

BB AA WR0X CAS WED24

AA

BBD00 D00

1) 2)


170


Byte Access

8-bit bus width

Bus width


address: 2 3D31 D31

CC DD WR0X CAS WED24

CC

DDD00 D00

1) 2)


address: 2 3D31 D31

DD CC WR0X CAS WED24

CC

DDD00 D00

1) 2)


Bus width


16-bit bus width

address: '0'D31 D31

AA WR0X CASL WEL

D16

AAD00

1)


address: '0'D31 D31

AA WR0X CASL WEL

D16

AAD00

1)


address: '1'D31 D31

BB WR1X CASH WEHD16

BBD00

1)


address: '1'D31 D31

BB WR1X CASH WEHD16

BBD00

1)


171


16-bit bus width

Bus width


8-bit bus width

Bus width


address: '2'D31 D31

CC WR0X CASL WEL

D16

CCD00

1)


address: '2'D31 D31

CC WR0X CASL WEL

D16

CCD00

1)


address: '3'D31 D31

DD WR1X CASH WEHD16

DDD00

1)


address: '3'D31 D31

DD WR1X CASH WEHD16

DDD00

1)


address:D31 D31

AA WR0X CAS WED24

AAD00

'0'

1)


address:D31 D31

AA WR0X CAS WED24

AAD00

'0'

1)


172


8-bit bus width

Bus width


address:D31 D31

BB WR0X CAS WED24

BBD00

'1'

1)


address:D31 D31

BB WR0X CAS WED24

BBD00

'1'

1)


address:D31 D31

CC WR0X CAS WED24

CCD00

'2'

1)


address:D31 D31

CC WR0X CAS WED24

CCD00

'2'

1)


address:D31 D31

DD WR0X CAS WED24

DDD00

'3'

1)


address:D31 D31

DD WR0X CAS WED24

DDD00

'3'

1)


173


4.6.4 DRAM

This section describes the DRAM control function.

DRAM Control Pin

Table 4.6-2 shows the relationship between the pin functions used for the DRAM interface andthe bus widths.

Row and Column Addresses

The DRAM interface generates an address according to the page size selection bit (PGSs 3 to0) of the DRAM control registers 4 and 5 (DMCRs 4 and 5). If the fast page mode is used, theMB91101 determines whether access occurs in the same page depending on PGSs 3 to 0 andthe data bus width.

Table 4.6-2 DRAM Control Pins and Bus Widths

Pin name Data bus 16-bit mode Data bus 16-bit mode

Remarks

2CAS/1WR mode

1CAS/2WR mode

-

RAS0 Area 4 RAS Area 4 RAS Area 4 RAS • Correspondence of "L" and "H" to the address low-order 1 bit (A0) in the data bus 16-bit mode• "L":"0"• "H":"1"

CASL: CAS corresponding to the area where A0 is "0"CASH: CAS corresponding to the area where A0 is "1"WEL: WE corresponding to the area where A0 is "0"WEH: WE corresponding to the area where A0 is "1"

RAS1 Area 5 RAS Area 5 RAS Area 5 RAS


CS0H Area 4 CASH

Area 4 WEL Area 4 CAS


CS1H Area 5 CASH

Area 5 WEL Area 5 CAS

DW0X Area 4 WE Area 4 WEH Area 4 WE

DW1X Area 5 WE Area 5 WEH Area 5 WE

174


To connect the MB91101 with DRAM, the address output must be shifted by this LSI deviceaccording to the bus width to be used.

The following figures show examples of the MB91101 being connected for the 8-bit and 16-bitbus widths when x8 bits and 256-page size are used. For the 16-bit bus width, the low-orderone bit from each output address is not connected.

8-bit data bus (using one DRAM device)

Figure 4.6-18 Example of Connecting the MB91101 and One DRAM Device with 8-Bit Output (8-Bit Data Bus)

Table 4.6-3 Page Size Selection Bit

PGS3 to 0 Page size

Row address Column address

Determining whether access occurs in the same

page

A31-16 A15-00 8-bit bus 16-bit bus

0000 256 A31-16 A23-08 A31-00 A31-08 A31-09

0001 512 A31-16 A24-09 A31-00 A31-09 A31-10

0010 1024 A31-16 A25-10 A31-00 A31-10 A31-11

0011 4096 A31-16 A27-12 A31-00 A31-12 A31-13

0100 to 1111 reserved - - - - -

This LSI device

COLUMN Address A07 A06 A05 A04 A03 A02 A01 A00

ROW Address A15 A14 A13 A12 A11 A10 A09 A08

External pin A07 A06 A05 A04 A03 A02 A01 A00

A07 A06 A05 A04 A03 A02 A01 A00 RAS,CAS,WE

One DRAM device D07-00 D31-24

175


16-bit data bus (using two DRAM devices)

Figure 4.6-19 Example of Connecting the MB91101 and Two DRAM Devices with 8-Bit Output (16-Bit Data Bus)

Example of Connecting DRAM Devices

• DRAM: 2CAS/1WE, page size 512, x16 bit product

• Bus width: 16 bits

• Number of banks: 2 (using Areas 4 and 5)

This LSI device

COLUMN Address A08 A07 A06 A05 A04 A03 A02 A01 A00

ROW Address A16 A15 A14 A13 A12 A11 A10 A09 A08

External pin A08 A07 A06 A05 A04 A03 A02 A01 A00

A07 A06 A05 A04 A03 A02 A01 A00 RAS,CASL,WE (RAS,CAS,WEL)

D07-00 D31-24

Two DRAM devices

A07 A06 A05 A04 A03 A02 A01 A00 RAS,CASH,WE (RAS,CAS,WEH)

D07-00 D23-16

( ): 1CAS/2WE

176


Figure 4.6-20 Example of Connecting the MB91101 and Two DRAM Devices with 16-Bit Output (16-Bit Data Bus)

(Area 4RAS) RAS0 RAS

( Area4CASL) CSOL UCAS

( Area4CASH)CS0H LCAS

( Area4WE) DW0X WE

( Area5RAS) RAS1 OE

( Area5CASL) CS1L A8-A0

( Area5CASH)CS1H D16-D1

( Area5WE) DW1X

Area 4

RAS

UCAS

LCAS

WE

RDX OE

A09-01 A8-A0

D31-16 D16-D1

This LSI device Area 4

(A00 not connected)

( Area4CS) CS4X

( Area5CS) CS5X

177

4.7 Bus Timing

4.7 Bus Timing

This section describes the bus access timing diagrams and operations in each mode for the following items:• Normal bus access• Wait cycle• DRAM interface• DRAM refresh• External bus request

Normal Bus Access

In the normal bus interface, "two clock cycles" are used as the basic bus cycle both in the readand write cycles. Throughout this manual, these two cycles are indicated as "BA1" and "BA2".

• Basic read cycle

• Basic write cycle

• Read cycle in each mode

• Write cycle in each mode

• Read/write mixed cycle

Wait Cycle

Two types of wait cycle are provided: An automatic wait cycle due to the WTC bit of the AMDregister and an external wait cycle using the RDY pin.

A wait cycle is a mode in which the previous cycle is continued. The "BA1 cycle" is repeateduntil the wait is cleared.

• Automatic wait cycle

• External wait cycle

DRAM Interface

Chip Select Areas 4 and 5 can be used as DRAM space. Set the DRME bit of AMD 4 or 5 andcontrol the operation using DMCRs 4 and 5.

The DRAM interface has, depending on the CAS output, the following three modes set in theDSAS and HYPR bits of DMCRs 4 and 5.

• Double CAS access (DSAS: 0, HYPR: 0): Normal DRAM interface in this manual

• Single CAS access (DSAS: 1, HYPR: 0): Single DRAM interface in this manua

• DRAM with the hyper page mode (DSAS: 1, HYPR: 1): Hyper DRAM interface in thismanual

Setting the C/W bit of DMCRs 4 and 5 allows you to select DRAM with 1CAS/2WE or 2CAS/1WE.

The row and column addresses are determined based on the page size specified in the PGSs 3to 0 bits of DMCR and the bus width specified in the BWs 1 and 0 bits of AMD 4 or 5.

178


Normal DRAM interface

The normal DRAM interface is a mode in which the CAS access is performed in two clockcycles. To execute this mode, set the DSAS and HYPR bits of DMCRs 4 and 5 to "0" and "0",respectively. In the normal DRM interface, "five clock cycles" are used as the basic bus cycleboth in the read and write cycles. Throughout this manual, these cycles are indicated as "Q1" to"Q5".

Use the PAGE bit of DMCRs 4 and 5 to set the fast page mode.

Fast page mode

The fast page mode refers to performing fast memory access through the control of columnaddresses and CAS in the same page space with a matching row address. To use this mode,set the PAGE bit of DMCRs 4 and 5 to "1".

Whether access occurs in the same page or is not determined by the PGSs 3 to 0 bits ofDMCRs 4 and 5 and the bus width.

The access in the fast page mode starts as soon as the normal access to Q1 to Q5 is complete.In the fast page mode, the cycle of Q4 to Q5 is repeated. Once the page mode starts, RASremains in the "L" level unless access out of the page or a refresh cycle occurs.

Even in the fast page mode, the Q1 and Q4 wait cycle can be set, in which case the Q4, Q4W,and Q5 cycle is repeated in the fast page mode.

• Normal DRAM interface: Read

• Normal DRAM interface: Write

• Normal DRAM read cycle

• Normal DRAM write cycle

• Automatic wait cycle in the normal DRAM interface

• DRAM interface in the fast page mode

Single DRAM interface

The Single DRAM interface is a mode in which the CAS access is performed in one clock cycle.To execute this mode, set the DSAS and HYPR bits of DMCRs 4 and 5 to "1" and "0",respectively. To use this mode, also set the PAGE bit of DMCRs 4 and 5 to "1" to use the fastpage mode.

The single DRAM interface starts in the cycle of Q1 to Q3 in the same way as for the normalDRAM interface. In the Q4 cycle, the CAS control occurs in one cycle and the read or writeoperation follows. Throughout this manual, the read and write Q4 cycles are indicated as"Q4SR" and "Q4SW", respectively. The page size, 1CAS/2WE or 2CAS/1WE setting and Q1cycle wait are the same as for the normal DRAM interface.

• Single DRAM interface: Read

• Single DRAM interface: Write

• Single DRAM interface

Hyper DRAM interface

The hyper DRAM interface is a mode in which CAS access is performed in one clock cycle andan address is read one cycle earlier than the data in the read cycles. Thus, fast DRAM accessis realized. To execute this mode, set the DSAS and HYPR bits of DMCRs 4 and 5 to "1" and"1", respectively. Also set the PAGE bit of DMCRs 4 and 5 to "1" to use the fast page mode.

The hyper DRAM interface starts in the cycle of Q1 to Q3 in the same way as for the normalDRAM interface. In the Q4 cycle, the CAS control occurs in one cycle and the read or write

179

4.7 Bus Timing

operation follows. Throughout this manual, the read and write Q4 cycles are indicated as"Q4HR" and "Q4HW", respectively. The page size, 1CAS/2WE or 2CAS/1WE setting and Q1cycle wait are the same as for the normal DRAM interface.

• Hyper DRAM interface: Read

• Hyper DRAM interface: Write

• Hyper DRAM interface

DRAM Refresh

• CAS before RAS (CBR) refresh

• Automatic wait cycle of the CBR refresh

• Self refresh

External Bus Request

• Releasing the bus right

• Obtaining the bus right

180


4.7.1 Basic Read Cycle

This section describes the basic read cycle timing.

Basic Read Cycle Timing

Bus width: 16 bits, Access: Word, Access to CS0 area

Figure 4.7-1 Basic Read Cycle Timing Example

[Description of operation]

• CLK outputs the operation clock of the external bus.

• A24 to A00 (Addresses 24 to 00) output the address of the leading byte location for the word,half word, or byte access in the read cycle when the bus cycle starts (BA1). In the aboveexample, since the word access is performed in the 16-bit bus width, the high-order 16-bitaddress for the word access (low-order two bits "0") is output in the first bus cycle, and thelow-order 16-bit address (low-order two bits "2") is output in the second bus cycle.

• D31 to D16 (Data 31 to 16) indicate the read data from the external memory or the I/O. Inthe read cycle, D31 to D16 are read on the rising edge of RDX. In the read cycle, all of D31

BA1 BA2 BA1 BA2CLK

A24-00 #0 #2D31-24 #0 #2D23-16 #1 #3

RDXWR0XWR1XCS0XCS1XCS2XCS3XCS4XCS5X(DACK0)(EOP0)

- "#" in A24-00 indicates the low-order

- "#" in D31-16 indicates a byte address

- indicates the timing to read the read data.

- (DACK0) and (E0P0) indicate the bus cycle

Half word access

low-order side

2 bits of an address.

of read data.

of DMAC.

on the address high-order side

Half word access on the address

If the clock doubler is turned off, the CPU system and the external bus system have the operation clock ratio of 1:1. Thus, CLK outputs the clock of the same frequency as the CPU system. If the clock doubler is turned on, the CPU system and the external bus system have the operation clock ratio of 1:1/2. Thus, CLK outputs half the clock frequency of the CPU. When the gear is used, the CLK frequency is lowered according to the gear ratio.

181

4.7 Bus Timing

to D16 are read on the rising edge of RDX regardless of the bus width or word, half word, orbyte access setting. Whether the read data is valid or not is determined inside the chip.

• RDX is a read strobe signal of the external data bus, being asserted on the falling edge ofBA1 and negated on the falling edge of BA2.

• In the read cycle, WR0X and WR1X are negated.

• The output of the CS0X to CS5X (area chip select) signals are asserted when the bus cyclestarts (BA1) at the same time as A24 to A00. CS0X to CS5X, being created by decoding theaddress output, are changed only if the chip select areas specified in ASR and AMR arechanged. One of CS0X to CS5X is always asserted.

• DACKs 0 to 2 and EOPs 0 to 2 are output in the external bus cycle of DMA. The DMACregister setting determines whether these signals are output. These signals are output at thesame time as RDX.

182


4.7.2 Basic Write Cycle

This section describes the basic write cycle timing.

Basic Write Cycle Timing


Figure 4.7-2 Basic Write Cycle Timing Example


• A24 to A00 (Addresses 24 to 00) output the address of the leading byte location for the word,half word, or byte access in the write cycle when the bus cycle starts (BA 1). In the aboveexample, since the word access is performed in the 8-bit bus width, first the address of theleading byte (address low-order "0") is output, then the addresses for the leading byteaddress +1 ("1"), +2 ("2") and +3 ("3") are output in this order.

• D31 to D16 (Data 31 to 16) indicate the write data to the external memory or the I/O. In thewrite cycle, write data is output when the bus cycle starts (BA1) and set to High-Z when thebus cycle ends (BA2 completion). In the above example, write data is output to D31 to D24because the 8-bit data bus width is used.

• RDX is negated in the write cycle.

• WR 0X and WR1X are the write strobe signals of the external data bus, being asserted on

BA1 BA2 BA1 BA2 BA1 BA2 BA1 BA2CLK

A24-00 #0 #1 #2 #3D31-24 #0 #1 #2 #3D23-16RDXWR0XWR1XCS0XCS1XCS2XCS3XCS4XCS5X(DACK0)(EOP0)

Byte access for address low-order two bits "0" two bits "1" two bits "2" two bits "3"

Byte access for address low-order



183

4.7 Bus Timing

the falling edge of BA1 and negated on the falling edge of BA2.

• If Chip Select Areas 0 to 5 have the maximum bus width of 8 bits, i.e., all the predefinedareas are set to 8 bits, D23 to D16 and WR1X automatically become I/O ports and set toHigh-Z.

• DACKs 0 to 2 and EOPs 0 to 2 are output in the external bus cycle of DMA. The DMACregister setting determines whether these signals are output. These signals are output at thesame time as WR0X and WR1X.

D31 to D24 and D23 to D16 are asserted according to the corresponding data bus, i.e., WR0X and WR1X respectively. In the above example, only WR0X is asserted because the 8-bit data bus width is used.

The above example shows a case in which D23 to D16 and WR1X are used as I/O ports. Note that if one or more of Chip Select Areas 0 to 5 is set to the bus width of 16 bits, D23 to D16 and WR1X cannot be used as I/O ports.

Pin D31-24WR0X

D23-16WRIX

Maximum bus width

16 bits D31-24WR0X

D23-16WRIX

8 bits D31-24WR0X

I/O port

184


4.7.3 Read Cycle in Each Mode

This section shows the read cycle timing in each mode.

Read Cycle Timing

Bus width: 16 bits, Access: Half word

Figure 4.7-3 Read Cycle Timing Example 1

Bus width: 16 bits, Access: Byte


Bus width: 8 bits, Access: Word


BA1 BA2 BA1 BA2CLK

A24-00 #0 #2D31-24 #0 #2D23-16 #1 #3RDX

BA1 BA2 BA1 BA2 BA1 BA2 BA1 BACLK

A24-00 #0 #1 #2 #3D31-24 #0 X #2 XD23-16 X #1 X #3RDX

X: Invalid data input


A24-00 #0 #1 #2 #3D31-24 #0 #1 #2 #3D23-16RDX

185

4.7 Bus Timing






A24-00 #0 #1 #2 #3D31-24 #0 #1 #2 #3D23-16RDX


A24-00 #0 #1 #2 #3D31-24 #0 #1 #2 #3D23-16RDX

186


4.7.4 Write Cycle in Each Mode

This section shows the write cycle timing in each mode.

Write Cycle Timing


Figure 4.7-8 Write Cycle Timing Example 1





BA1 BA2 BA1 BA2CLK

A24-00 #0 #2D31-24 #0 #2D23-16 #1 #3WR0XWR1X

BA1 BA2 BA1 BA2CLK

A24-00 #0 #2D31-24 #0 #2D23-16 #1 #3WR0XWR1X


A24-00 #0 #1 #2 #3D31-24 #0 X #2 XD23-16 X #1 X #3WR0XWR1X

X: Invalid data input

187

4.7 Bus Timing






A24-00 #0 #1 #2 #3D31-24 #0 #1 #2 #3D23-16WR0XWR1X


A24-00 #0 #1 #2 #3D31-24 #0 #1 #2 #3D23-16WR0XWR1X

188


4.7.5 Read/Write Mixed Cycle

This section shows the read/write mixed cycle timing.

Read/Write Mixed Cycle Timing

CS0 area: 16-bit bus width, word read

CS1 area: 8-bit bus width, word read

Figure 4.7-13 Read/Write Mixed Cycle Timing Example


• In the above figure, an idle cycle (where no bus cycle exists) is inserted when the chip selectarea is switched. If an idle cycle is inserted between bus cycles, the address of the previousbus cycle continues to be output until the next bus cycle starts. At the same time, CS0X toCS5X corresponding to the output address continues to be asserted.

• The above example shows the mixture of 16-bit and 8-bit buses.

BA1CLK

A24-00 #0 #2 #0 #1D31-24 #0 #2 #0 #1D23-16 #1 #3

RDXWR0XWR1XCS0XCS1X

Word read cycle Half word write cycleCS0 area CS1 area

BA2 BA1 BA1 BA1BA2 BA2 BAIdle Idle

Since the maximum bus width is 16 bits, D23 to D16 and WR1X do not act as I/O ports even in the 8-bit access area (CS1 area). D23 to D16 output undefined data and WR1X is negated.

189

4.7 Bus Timing

4.7.6 Automatic Wait Cycle

This section shows the automatic wait cycle timing.

Automatic Wait Cycle Timing

Bus width: 16 bits, Access: Half word read/write

Figure 4.7-14 Automatic Wait Cycle Timing Example


• You can insert an automatic wait cycle by setting the WTC bit of the AMD register in eachchip select area.

• In the above figure, the WTC bit is set to "001" and one wait bus cycle is inserted into anormal bus cycle. In this example, "two-clock normal bus cycle" plus "one-clock wait cycle"is "three-clock bus cycle in total". You can set an automatic wait cycle up to seven clocks(i.e., nine-clock normal bus cycle in total).

BA1 BA1 BA2 BA1 BA1 BA2CLK

A24-00 #0 #2D31-16 #0:1 #2,3RDXWR0X,1X(DACK0)(EOP0)

wait waitread write

190


4.7.7 External Wait Cycle

This section shows the external wait cycle timing.

External Wait Cycle Timing


Figure 4.7-15 External Wait Cycle Timing Example


• You can insert an external wait cycle by setting the RDYE bit of the EPCR 0 register toenable the input to the external RDY pin.

• If the external RDY is used, insert an automatic wait cycle of one clock or more, i.e., set theWTC bit of AMD to "001" or more. RDY is not detected in an automatic wait cycle butdetected after the automatic wait cycle.

• Input the external RDY in synchronization with the falling edge of the CLK pin output. If theexternal RDY is set to the "L" level on the falling edge of CLK, providing a wait cycle, thesame BA1 cycle is repeated. If the external RDY is set to the "H" level, a wait cycle isassumed to be completed, and the BA2 cycle starts.

BA1 BA1 BA1 BA1 BA1 BA2CLK

A24-00 #0#0:1

D31-16RDX

D31-16 #0,1WR0X,1X

wait wait wait RDYRDY

Automatic Wait due to RDY

Bus cycle

Read

Write

wait

191

4.7 Bus Timing

4.7.8 Normal DRAM Interface: Read

This section shows the normal DRAM interface read timing.

Normal DRAM Interface: Read Timing


Figure 4.7-16 Normal DRAM Interface Read Timing Example


• A24 to A00 (Addresses 24 to 00) output a row address in the Q2 rising edge cycle and acolumn address in the Q4 rising edge cycle for the read address specified in PCs 3 to 0 ofthe DMCR and the bus width. An address output in the Q1 cycle is undefined.

• D31 to D16 (Data 31 to 16) indicate the read data from the external memory and the I/O. Inthe read cycle, D31 to D16 are read on the rising edge of CAS if 1CAS/2WE is set or on therising edge of CASH if 2CAW/1WE is set. If 1CAS/2WE is set, CAS corresponds to D31 to

Q1 Q2 Q3 Q4 Q5 Q1 Q2 Q3 Q4 Q5CLK

1)1CAS/2WEA24-00 X #0 row.adr. #0 col.adr X #2 row.adr. #2 col.adrD31-24 #0 #2D23-16 #1 #3RASCASWELWEHRDXCS4X(DACK0)(EOP0)

2)2CAS/1WEA24-00 X #0 row.adr. #0 col.adr X #2 row.adr. #2 col.adrD31-24 #0 #2D23-16 #1 #3RASCASLCASHWERDXCS4X(DACK0)(EOP0)

Half word access on the address Half word access on the address high-order side low-order side

192


D16. If 2CAS/1WE is set, CASL and CASH correspond to D31 to D24 and D23 to D16,respectively. In the read cycle, all of D31 to D16 are read regardless of the bus width orword, half word, or byte access setting. Whether the read data is valid or not is determinedinside the chip.

• RAS is a row address strobe signal, being set to "H" on the rising edge of Q1 and "L" on therising edge of Q3. If the PAGE bit is set to "0" (in a mode other than the fast page mode),RAS is normally set to "H".

• CAS is a column address strobe signal. In 2CAS/1WE, CASL indicates the high-orderaddress (low-order 1 bit "0") CAS and CASH indicates the low-order address (low-order 1 bit"1") CAS. This signal is asserted on the falling edge of Q4 and negated on the falling edgeof Q5.

• In the read cycle, WE (including WEL and WEH) is negated.

• In the read cycle, RDX outputs the "L" level from the Q1 cycle.

• CS4X and CS5X are output on the rising edge of the Q1 cycle.

• DACKs 0 to 2 and EOPs 0 to 2 are output in the external bus cycle of DMA. The DMACregister setting determines whether these signals are output. These signals are output at thesame time as CAS.

193

4.7 Bus Timing

4.7.9 Normal DRAM Interface: Write

This section shows the normal DRAM interface write timing.

Normal DRAM Interface: Write Timing


Figure 4.7-17 Normal DRAM Interface Write Timing Example


• A24 to A00 (Addresses 24 to 00) output data in the same way as in the read cycle.

• D31 to D16 (Data 31 to 16) indicate the write data to the external memory and the I/O. In thewrite cycle, D31 to D16 output write data starting from the Q1 cycle and is set to High-Z afterthe Q5 cycle. If 1CAS/2WE is set, WEL and WEH correspond to D31 to D24 and D23 toD16, respectively. If 2CAS/1WE is set, WE corresponds to D31 to D16. Thus, valid data isoutput. For the 8-bit data bus width, write data is output to D31 to D24.

Q1CLK

X #0 row.adr. #0 col.adr X #2 row.adr. #2 col.adrD31-24 #0 #2D23-16 #1 #3RASCASWELWEHRDXCS4X(DACK0)(EOP0)

X #0 row.adr. #0 col.adr X #2 row.adr. #2 col.adrD31-24 #0 #2D23-16 #1 #3RASCASLCASHWERDXCS4X(DACK0)(EOP0)

Q2 Q3 Q4 Q5 Q1 Q2 Q3 Q4 Q5

A24-00

A24-00

Half word access on the address Half word access on the address high-order side low-order side

1)1CAS/2WE

2)2CAS/1WE

194


• RAS is the same as in the read cycle.

• CAS is the same as in the read cycle.

• WE is a DRAM write strobe signal. If 2CAS/1WE is set, WEL indicates the high-orderaddress (low-order 1 bit "0") WE and WEH indicates the low-order address (low-order 1 bit"1") WE . This signal is asserted on the rising edge of Q4 and negated on the rising edge ofthe cycle subsequent to Q5.

• In the write cycle, RDX outputs the "H" level.

• CS4X and CS5X are output on the rising edge of the Q1 cycle.

• DACKs 0 to 2 and EOPs 0 to 2 are output in the external bus cycle of DMA. The DMACregister setting determines whether these signals are output. These signals are output at thesame time as CAS.

195

4.7 Bus Timing

4.7.10 Normal DRAM Read Cycle

This section shows the normal DRAM read cycle timing.

Normal DRAM Read Cycle Timing


Figure 4.7-18 Normal DRAM Read Cycle Timing Example 1

Q1 Q2 Q3 Q4 Q5CLK

A24-00 X #0 row.adr. #0 col.adrD31-24 #0D23-16 #1RASCASWELWEH

A24-00 X #0 row.adr. #0 col.adrD31-24 #0D23-16 #1RASCASLCASHWE

1CAS/2WE)

2CAS/1WE2)

196







1)1CAS/2WEA24-00 X #0 row.adr. #0 col.adr X #1 row.adr. #1 col.adrD31-24 #0 XD23-16 X #1RASCASWELWEH

2)2CAS/1WEA24-00 X #0 row.adr. #0 col.adr X #1 row.adr. #1 col.adrD31-24 #0 XD23-16 X #1RASCASLCASHWE

Upper address bit

Lower address bit


A24-00 X #0 row.adr. #0 col.adr X #1 row.adr. #1 col.adrD31-24 #0 #1D23-16RASCASWE

197

4.7 Bus Timing

4.7.11 Normal DRAM Write Cycle

This section shows the normal DRAM write cycle timing.

Normal DRAM Write Cycle Timing


Figure 4.7-21 Normal DRAM Write Cycle Timing Example 1

Q1 Q2 Q3 Q4 Q5CLK

1CAS/2WEA24-00 X #0 row.adr. #0 col.adrD31-24 #0D23-16 #1RASCASWELWEH

2CAS/1WEA24-00 X #0 row.adr. #0 col.adrD31-24 #0D23-16 #1RASCASLCASHWE

1)

2)

198







1)1CAS/2WEA24-00 X #0 row.adr. #0 col.adr X #1 row.adr. #1 col.adrD31-24 #0 XD23-16 X #1RASCASWELWEH

2)2CAS/1WEA24-00 X #0 row.adr. #0 col.adr X #1 row.adr. #1 col.adrD31-24 #0 #1D23-16 X #1RASCASLCASHWE

Upper address bit

Lower address bit

Upper address bit

Lower address bit


A24-00 X #0 row.adr. #0 col.adr X #1 row.adr. #1 col.adrD31-24 #0 XD23-16RASCASWE

199

4.7 Bus Timing

4.7.12 Automatic Wait Cycle for the Normal DRAM Interface

This section shows the automatic wait cycle timing for the normal DRAM interface.

Automatic Wait Cycle Timing for the Normal DRAM Interface


Figure 4.7-24 Normal DRAM Interface Automatic Wait Cycle Timing Example


• You can insert a one-clock wait cycle into the Q1 or Q4 cycle by setting the Q1W or Q4W bitof DMCRs 4 and 5. These cycles are called the "Q1W or Q4W" cycle. The Q1W or Q4Wcycle executes the same cycle as the Q1 or Q4 cycle, respectively, to extend the "H" width ofRAS or the "L" width of CAS for one more cycle. Set these cycles according to the DRAMaccess time.

Q1 Q1W Q2 Q3 Q4 Q4W Q5CLK

1)ReadA24-00 X #0 row.adr. #0 col.adr.D31-24 #0D23-16RASCASWERDX

2)WriteA24-00 X #0 row.adr. #0 col.adr.D31-24 #0D23-16RASCASWERDX

Q1 wait Q4 waitNormal DRAM interface

200


4.7.13 DRAM Interface in the Fast Page Mode

This section shows the DRAM interface timing in the fast page mode.

DRAM Interface Timing in the Fast Page Mode

Read cycle, Bus width: 16 bits, Access: Word

Figure 4.7-25 Fast Page Mode DRAM Interface Timing Example 1


• With RAS set to "L", keep WE (including WEL and WEH) at "H" to perform read control usingonly CAS (including CASL and CASH).

• A column address is output in each Q4 or Q5 cycle.

Q1 Q2 Q3 Q4 Q5 Q4 Q5 Q4 Q5 Q4 Q5CLK

1CAS/2WEA24-00 X #0 row.adr. #0 col.adr #2 col.adr #4 col.adr #6 col.adrD31-24 #0 #2 #4 #6D23-16 #1 #3 #5 #7RASCASWELWEHRDX

1)

Normal DRAM bus cycle Fast page Fast page Fast page

201

4.7 Bus Timing

Write cycle, Bus width: 16 bits, Access: Word



• With RAS set to "L", keep WE (including WEL and WEH) at "L" to perform write control usingonly CAS (including CASL and CASH).

• A column address and output data are output in each Q4 or Q5 cycle.

CS area (CS4 or CS5) switching in the fast page mode, read/write mixed cycle, 2CAS/1WE



• In the fast page mode, RAS remains at the "L" level even if the CS area is switched.

• If a bus cycle starts in the fast page mode, RDX in the read cycle is set to the "L" level on therising edge of Q4 and negated after the Q5 cycle ends. In the write cycle, WE (including

Q1 Q2 Q3 Q4 Q5 Q4 Q5 Q4 Q5 Q4 Q5CLK

2CAS/1WEA24-00 X #0 row.adr. #0 col.adr #2 col.adr #4 col.adr #6 col.adrD31-24 #0 #2 #4 #6D23-16 #1 #3 #5 #7RASCASLCASHWERDX

2)

Normal DRAM bus cycle Fast page Fast page Fast page

Q4CLK

A24-00 CS5X col.adr CS5X col.adr CS5X col.adr CS4X col.adr CS4X col.adrD31-24 WriteD23-16 Read WriteCS4XCS5XRDX

CS4:RASCS4:CASLCS4:CASHCS4:WE


CS5 area

Q5 Q4 Q5 Q4 Q5 Q4 Q5 Q4 Q5

CS4 area

Idel

Read WriteWrite Read

ReadReadRead

202


WEL and WEH) is set to the "H" level on the rising edge of Q4 and negated after the Q5cycle ends.

• CS4X and CS5X change at the same time as an output address. If a bus cycle starts in thefast page mode, they change in the Q4 cycle in the same way as in a column address.

Mixture of the fast page mode and the basic bus cycle



• In the fast page mode, RAS remains at the "L" level even if the CS area is switched andanother CS area is being accessed.

Q4 IdleCLK

A24-00 CS4X col.adr CS2X basic bus CS2X basic bus CS4X col.adr CS4X col.adrD31-24D23-16CS2XCS4X

RDXWR0X


CS4 fast page CS2 basic bus

Q5 BA1 BA2 BA1 BA2 Q4 Q5 Q4 Q5

CS4 fast page

WriteRead WriteRead

ReadRead

ReadRead

ReadRead

203

4.7 Bus Timing

4.7.14 Single DRAM Interface: Read

This section shows the single DRAM interface read timing.

Single DRAM Interface: Read Timing


Figure 4.7-29 Single DRAM Interface Read Timing Example


• A column address is output in each Q4SR cycle.

• CAS is asserted on the falling edge of Q4SR and negated on the rising edge of Q4SR whenit ends.

• D31 to D16 are read on the rising edge of CAS (including CASL and CASH) in the same wayas for the normal DRAM interface.

• After a read cycle ends, at least a one-clock idle cycle is always inserted to prevent a buscontention of the external data bus.

• DACKs 0 to 2 and EOPs 0 to 2 are output at the same time as CAS.

Q1 Q2 Q3 Q4SR Q4SR Q4SR Q4SR Q1 Q2 Q3CLK

1)1CAS/2WEA24-00 X row.adr. col. col. col. col. X row.adr.D31-24D23-16RASCASWELWEHRDX(DACK0)(EOP0)

Out of the page

ReadRead

ReadRead

Idle

Fast page Fast page Fast page

ReadRead

ReadRead

204


4.7.15 Single DRAM Interface: Write

This section shows the single DRAM interface write timing.

Single DRAM Interface: Write Timing


Figure 4.7-30 Single DRAM Interface Write Timing Example


• A column address and write data are output in each Q4SW cycle.

• CAS is asserted on the falling edge of Q4SW and negated on the rising edge of Q4SW whenit ends.

• WE (including WEL and WEH) is asserted on the rising edge of the Q4SW cycle andnegated after Q4SW ends.

Q1 Q2 Q3 Q4SW Q4SW Q4SW Q4SW Q1 Q2 Q3 Q4SWCLK

2)2CAS/1WEA24-00 X row.adr. col. col. col. col. X row.adr. col.D31-24 W W W W WD23-16 W W W W WRASCASLCASHWERDX(DACK0)(EOP0)


205

4.7 Bus Timing

4.7.16 Single DRAM Interface

This section shows the single DRAM interface timing.

Single DRAM Interface Timing

Mixture of the single DRAM interface and the fast page mode, CS switching

Figure 4.7-31 Single DRAM Interface Timing Example


• If a bus cycle starts in the fast page mode, RDX in the read cycle is set to the "L" level on therising edge of QS4R and negated after the Q4SR cycle ends. In the write cycle, WE(including WEL and WEH) is set to the "H" level on the rising edge of Q4SW and negatedafter the Q4SW cycle ends.

• CS4X and CS5X change at the same time as an output address. If a bus cycle starts in thefast page mode, they change in the Q4SR or Q4SW cycle in the same way as in a columnaddress.

Q4SR BA1 BA2 Q1 Q2 Q3 Q4SW Q4SR Q4SRCLK

A24-00 col. CS2X basic bus X row.adr. col. col. col.D31-24D23-16CS2XCS4XCS5X

RDXWR0X



CS5 Single CS2 normal CS4 Single CS5

WriteRead Write


ReadReadRead

IdleIdle

206


4.7.17 Hyper DRAM Interface: Read

This section shows the hyper DRAM interface read timing.

Hyper DRAM Interface: Read Timing


Figure 4.7-32 Hyper DRAM Interface Read Timing Example


• A column address is output in each Q4HR cycle.

• CAS is asserted on the falling edge of Q4HR and negated on the rising edge of Q4HR whenit ends.

• D31 to D16 are read on the falling edge of CAS to be output in the Q4HR cycle subsequentto Q4HR in which a corresponding column address is output.

• After a read cycle ends, at least a one-clock idle cycle is always inserted to prevent a buscontention of the external data bus.

• DACKs 0 to 2 and EOPs 0 to 2 are output at the same time as CAS.

Q1 Q2 Q3 Q4HR Q4HR Q4HR Q4HR Q4HR Q1 Q3CLK

1CAS/2WEA24-00 X row.adr. col.0 col.2 col.4 col.6 X row.aD31-24 0 2 4 6D23-16 1 3 5 7RASCASWELWEHRDX(DACK0)(EOP0)

Out of the page

1)


Read

Read

Read

Read

Read

Read

Read

Read

Idle

Fast page

207

4.7 Bus Timing

4.7.18 Hyper DRAM Interface: Write

This section shows the hyper DRAM interface write timing.

Hyper DRAM Interface: Write Timing


Figure 4.7-33 Hyper DRAM Interface Write Timing Example


• A column address and write data are output in each Q4HW cycle.

• CAS is asserted on the falling edge of Q4HW and negated on the rising edge of Q4HWwhen it ends.

• WE (including WEL and WEH) is asserted on the rising edge of the Q4HW cycle andnegated after Q4HW ends.

Q1 Q2 Q3 Q4HW Q4HW Q4HW Q4HW Q1 Q2 Q3 Q4HWCLK

2)2CAS/1WEA24-00 X row.adr. col. col. col. col. X row.adr. col.D31-24 W W W W WD23-16 W W W W WRASCASLCASHWERDX(DACK0)(EOP0)

208


4.7.19 Hyper DRAM Interface

This section shows the hyper DRAM interface timing.

Hyper DRAM Interface Timing

Mixture of the hyper DRAM interface and the basic bus cycle, CS switching

Figure 4.7-34 Hyper DRAM Interface Timing Example


• If a bus cycle starts in the fast page mode, RDX in the read cycle is set to the "L" level on thefalling edge of Q4HR and negated after the Q4HR cycle ends. In the write cycle, WE(including WEL and WEH) is set to the "L" level on the rising edge of Q4HW and negatedafter the Q4HW cycle ends.

• CS4X and CS5X change at the same time as an output address. If a bus cycle starts in thefast page mode, they change in the Q4HR or Q4HW cycle in the same way as for a columnaddress.

BA1 BA2 Q1 Q2 Q3 Q4HR Q4HR Q4HW Q4HR Q4HRCLK

A24-00 CS2X basic bus X row.adr. col.adr. col. col. col.D31-24D23-16CS2XCS4XCS5X

RDXWR0X



CS2 nomal CS4 Hyper DRAM read CS5 Hyper DRAMwrite/read

WriteReadWrite


Read

Idle

209

4.7 Bus Timing

4.7.20 DRAM Refresh

This section shows the DRAM refresh timing.

CAS Before RAS (CBR) Refresh

Figure 4.7-35 CAS Before RAS (CBR) Refresh Timing Example


• You can execute the CBR refresh by setting both the REFE bit of DMCRs 4 and 5 and theSTR bit of RFCR.

• Throughout this manual, the CBR cycle is represented as "R1 to R4".

• If 1CAS/2WE or 2CAS/1WE is set, CAS or both CASL and CASH respectively are output inthe above timing.

• The CBR refresh gets a higher priority than the DRAM bus access.

• After the CBR refresh ends, the DRAM access always starts with the Q1 cycle that indicatesthe start of DRAM access even if the next bus access is within the same page, and a rowaddress is output first.

• The CBR refresh is periodically executed also if:

• The normal bus access other than DRAM is executed.

• The external bus is released (if BGRNTX is set to "L")

• The CPU is sleeping.

Q4 Q5 R1 R2 R3 R4 idle Q1 Q2 Q3CLK

CBR

RASCASWE

A24-00 col.adr. xx row.adr.D31-16

CAS is asserted on the falling edge of the R2 cycle and negated on the falling edge of the R4 cycle.RAS is asserted on the rising edge of the R3 cycle and negated on the falling edge of an idle cycle subsequent to R4. WE is negated during CBR.

However, the CBR refresh during the DRAM access is handled as follows: If word access is executed in the 8-bit bus width for example, four bus accesses are required. Even if a refresh request is issued in the first through third bus access, the refresh is executed only after the fourth bus access ends.In other words, the CBR refresh is always executed after one access unit is complete.

210


Automatic Wait Cycle in the CBR Refresh

Figure 4.7-36 CBR Refresh Automatic Wait Cycle Timing Example


• An automatic wait cycle can be inserted in the CBR refresh by setting the R1W and R3W bitsof RFCR.

Self Refresh

Figure 4.7-37 Self Refresh Timing Exampl


• The self refresh can be started by setting the SLFR bit of either DMCR 4 or 5 to "1". The selfrefresh is canceled by setting this bit to "0".

• An idle cycle of at least seven cycles is inserted after the self refresh ends.

• Throughout this manual, the self refresh is represented as "SRs 1 to 3".

R1 R1W R2 R3 R3W R4 idleCLKRASCAS

wait wait

SR1 SR2 SR3 SR3 SR3 idleCLKSLFRbitRASCAS

211

4.7 Bus Timing

4.7.21 External Bus Request

This section shows the external bus request timing.

Releasing the Bus Right

Figure 4.7-38 Bus Right Releasing Timing Example


• You can execute the bus arbitration according to BRQ and BGRNTX by setting the BRE bitof EPCR0 to "1".

• When the bus right is released, BGRNTX is asserted one cycle after the pin is set to High-Z.

Obtaining the Bus Right

Figure 4.7-39 Bus Right Obtaining Timing Example


• The bus arbitration can be executed according to BRQ and BGRNTX by setting the BRE bitof EPCR0 to "1".

• When the bus right is obtained, each pin is made active one clock after BGRNTX is negated.

CLKA24-00 #0:1 high ZD31-16 #0:1 high ZRDX high Z

BRQBGRNTX

One cycle

CLKA24-00 high ZD31-16 high ZRDX high Z

BRQBGRNTX

One cycle

212


4.7.22 Internal Clock Multiplication Operation (Clock Doubler)

Since the MB91101 has a clock multiplication circuit, the circuits inside the CPU operate either one or two times the frequency of the bus interface. Whichever clock is selected, the bus interface operates in synchronization with the CLK output pin. If the CPU issues an external access request, access to the outside starts only on the rising edge of the CLK output.

Selecting the Clock

For information on selecting either x2 or x1 clock, see Section 3.11 (Clock doubler of the clockgenerator).

The clock selection can be changed anytime during the chip operation. When the clockselection is switched, the bus operation is inhibited temporarily. Upon reset, the clock selectionis set automatically to x1.

Figures 4.7-40 and 4.7-41 show the x2 and x1 clock timing examples, respectively.

Figure 4.7-40 x2 Clock Timing Example (BW-16bit, Access-Word Read)

Figure 4.7-41 x1 Clock Timing Example (BW-16bit, Access-Word Read)

Internal clockInternal instruction

Internal instruction

CLK output

External address bus

External data bus

External RDX

PrefetchExternal access (instruction fetch)

address

data

Internal clock



CLK output

External address bus

External data bus

External RDX

PrefetchExternal access (instruction fetch)

address

data

213

4.7 Bus Timing

4.7.23 External Bus Operation Program Examples

This section shows simple program examples of operating the external bus.

External Bus Operation Program Examples

The following shows the register settings:

Areas

• Area 0 (AMD 0): 16 bits, normal bus, automatic wait - 0




• Area 4 (AMD 4): 16 bits, DRAM, page size 256, 1CAS/2WE, with wait, CBR refresh

• Area 5 (AMD 5): 16 bits, DRAM, page size 512, 2CAS/1WE, without wait, CBR refresh

Other buses

• Refresh (RFCR): Without wait, 1/8 setting

• External pin (EPCR 0): Accepts external RDY, arbitration of BRQ and BGRNTX

• External pin (DSCR): DRAM pin setting

• Little Endian (LER): Area 2

Note also the following points:

• Set MDs 2, 1, and 0 to "001" and the external vector to the 16-bit mode.

• Set Area 0 to the same bus width before setting the mode register (MODR)

• Set Areas 1 to 5 such that there is no overlap.

External Bus Operation Program Example

For the purpose of explanation, the following program writes data to byte registers in bytes andto half word registers in half words.

***** Program example *****

//Each register settings

init_epcr ldi:20 #0xffff,r0 // //

External pin settingsExternal RDY wait, BRQ and BGRNTX bus arbitration

ldi:20 #0x628,r1 // epcr0 register address setting

sth r0,@r1 // epcr0 register write

init_dscr ldi:8 #0xff,r0 ////

DRAM pin settingRAS,CAS,WE

214


ldi:20 #0x625,r1 // dscr register address setting

stb r0,@r1 dscr register write

init_amd0 ldi:8 #0x08,r0 // 16-bit bus, 0-wait

ldi:20 #0x620,r1 // amd0 register address setting

stb r0,@r1 // amd0 register write

init_amd1 ldi:8 #0x0a,r0 // 16-bit bus, 2-wait



init_amd32 ldi:8 #0x49,r0 // Normal, 16-bit bus, 1-wait



init_amd4 ldi:8 #0x88,r0 // DRAM, 16-bit bus



init_amd5 ldi:8 #0x88,r0 // DRAM, 16-bit bus



init_dmcr4 ldi:20 #0x0c90,r0 ////

page size=256,Q1/Q4-wait,Page1CAS-2WE, CBR, no parity

ldi:20 #0x62c,r1 // dmcr4 register address setting

sth r0,@r1 // dmcr4 regiser write

init_dmcr5 ldi:20 #0x10c0,r0 ////

page size=512, Q1/Q4-no wait, Page2CAS-1WE, CBR, no parity

ldi:20 #0x62e,r1 // dmcr5 register address setting

sth r0,@r1 // dmcr5 register write

init_rfcr ldi:20 #0x0205,r0 // REL=2, R1W/R3W-no wait, refresh, 1/8

ldi:20 #0x626,r1 // rfcr register address setting

215

4.7 Bus Timing

//External bus access

sth r0,@r1 // rfcr register write

init_asr ldi:32 #0x0013001,r0 // asr1, amr1 register setting values

ldi:32 #0x0015001,r1 // asr2, amr2 register setting values



ldi:32 #0x001b001,r4 // asr5, amr5 register setting values

ldi:20 #0x60c,r5 // asr1, amr1 register address settings

ldi:20 #0x610,r6 // asr2, amr2 register address settings



ldi:20 #0x61C,r9 // asr5, amr5 register address settings

st r0,@r5 // asr1, amr1 register write





init_ler ldi:8 #0x02,r0 // CS2 little endian

ldi:20 #0x7fe,r1 // ler register address setting

stb r0,@r1 // ler register write

init_modr ldi:8 #0x80,r0 // External ROM external bus

ldi:20 #0x7ff,r1 // modr register address setting

stb r0,@r1 // modr register write

adr_set ldi:32 #0x00136da0, r0 // CS1 address

ldi:32 #0x00151300, r1 // CS2 address

ldi:32 #0x00196434, r2 // CS4 address (within the page)

ldi:32 #0x0019657c, r3 // CS4 address (within the page)

ldi:32 #0x00196600, r4 // CS4 address (out of the page)

ldi:32 #0x001a6818, r5 // CS5 address (within the page)

ldi:32 #0x001a6b8c, r6 // CS5 address (within the page)

216


ldi:32 #0x001a6c00, r7 // CS5 address (out of the page)

bus_acc ld @r0,r8 // CS1 data word load

lduh @r1,r9 // CS2 data half word load

ld @r2,r10 // CS4 word load

ldub @r3,r11 // CS4 data byte load

st r8,@r4 // CS4 data word store

sth r9,@r5 // CS5 data half word store

st r10,@r6 // CS5 data word store

stb r11,@r7 // CS5 data byte store

217

CHAPTER 5 I/O PORTS

This chapter explains the outline of the I/O ports, the register configuration, and the conditions for using external pins as I/O.

5.1 Outline of the I/O Ports

5.2 Port Data Registers (PDRs)

5.3 Data Direction Registers (DDRs)

5.4 Relation Between External Pins and Switching Registers

218

CHAPTER 5 I/O PORTS

5.1 Outline of the I/O Ports

The MB91101 can be used as I/O ports when the resource corresponding to each pin does not use the pin as I/O.

Basic Block Diagram of I/O Ports

Figure 5.1-1 shows the basic configuration of the I/O ports.

Figure 5.1-1 Basic Configurataion of the I/O Ports

Registers of I/O Ports

The I/O ports consists of port data registers (PDRs) and data direction registers (DDRs).

Input mode (DDR = "0")

• In PDR read cycle, the level of the corresponding external pin is read.

• In PDR write cycle, the set value is written to the PDR.

Output mode (DDR = "1")

• In PDR read cycle, the value of the PDR is read.

• In PDR write cycle, the value of the PDR is output to the corresponding output pin.

Data Bus

0

1PDR read

0 pin

1

D D R

P D R

Resource input

Resource output

Resource output permission

PDR: Port Data RegisterDDR: Data Direction Register

219



The port data registers (PDR2 to F) are I/O data registers of the I/O ports. I/O is controlled by the corresponding data direction registers (DDR2 to F).

Configuration of Port Data Registers (PDRs)

The configuration of the port data registers (PDRs) is shown in the following.

7 6 5 4 3 2 1 0PDR2Address: 000001H P27 P26 P25 P24 P23 P22 P21 P20 XXXXXXXXB R/W

7 6 5 4 3 2 1 0PDR6Address: 000005H P67 P66 P65 P64 P63 P62 P61 P60 XXXXXXXXB R/W

7 6 5 4 3 2 1 0PDR8Address: 00000BH P85 P82 P81 P80 --XXXXXXB R/W

7 6 5 4 3 2 1 0PDRAAddress: 000009H PA6 PA5 PA4 PA3 PA2 PA1 -XXXXXXXB R/W

7 6 5 4 3 2 1 0PDRBAddress: 000008H PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 XXXXXXXXB R/W

7 6 5 4 3 2 1 0PDREAddress: 000012H PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 XXXXXXXXB R/W

7 6 5 4 3 2 1 0PDRFAddress: 000013H PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 XXXXXXXXB R/W

Ini t ia l value

Ini t ia l value

Ini t ia l value

Ini t ia l value

Ini t ia l value

Ini t ia l value

Ini t ia l value

Access

Access

Access

Access

Access

Access

Access

220

CHAPTER 5 I/O PORTS

5.3 Data Direction Registers (DDRs)

The data direction registers (DDR2 to F) control the I/O direction of the corresponding I/O ports in bit units.When 0 is written, the corresponding port is used as input. When 1 is written, the corresponding port is used as output.

Configuration of Data Direction Registers (DDRs)

The configuration of the data direction registers (DDRs) is shown in the following.

7 6 5 4 3 2 1 0PDR2Address: 000601H P27 P26 P25 P24 P23 P22 P21 P20 00000000B W

PDR6Address: 000605H P67 P66 P65 P64 P63 P62 P61 P60 00000000B W

7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

PDR8Address: 00060BH P85 P82 P81 P80 --0--000B W

7 6 5 4 3 2 1 0PDRAAddress: 000609H PA6 PA5 PA4 PA3 PA2 PA1 -000000-B W

7 6 5 4 3 2 1 0PDRBAddress: 000608H PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 00000000B W

7 6 5 4 3 2 1 0PDREAddress: 0000D2H PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 00000000B W

7 6 5 4 3 2 1 0PDRFAddress: 0000D3H PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 00000000B W

Ini t ia l value

Ini t ia l value

Ini t ia l value

Ini t ia l value

Ini t ia l value

Ini t ia l value

Ini t ia l value

Access

Access

Access

Access

Access

Access

Access

221



Table 5.4.1 shows the relationship between the initial value of each external pin and the register that switches between an I/O port and a control pin. The description "8 bits: . 16 bits: " indicates that the function changes depending on the width of the external bus used. Note that the following pin numbers are examples of the QFP and the pin numbers of the SQFP are different. Check the pin numbers in Section 1.5, "Pin Assignment" for the SQFP.

Selecting the Function (I/O Port or Control Pin) of External Pins.

Table 5.4-1 List of Function Choices of External Pins

Pin No. Pin code Initial value Switching registers

28 to 35 P20 to P27 8 bits: P20 to P2716 bits: D16 to D23

Switched automatically depending on the bus width selected in MD0 to 2 and AMD0 to 5. 8 bits: P20 to P27 16 bits: D16 to D23

D16 to D23

36 to 42. 44 D24 to D31 D24 to D31 -

45, 47 to 61 A00 to A15 A00 to A15 -

62 to 67,69,70

P60 to P67 A16 to A23 EPCR1 (AE16 to AE23 bits) 0: P60 to P67 1: A16 to A23A16 to A23

71 A24 A24 EPCR1 (AE24 bit) and DATCR (EPSE0 and EPDE0 bits)AE24, EPSE0, EPDE0 100: A24 Other: EOP0

E0P0

22 P80 P80 EPCR0 (RDYE bit) 0: P80 1: RDYRDY

23 P81 P81 EPCR0 (BRE bit) 0: P81 1: BGRNTXBGRNTX

24 P82 P82 EPCR0 (BRE bit) 0: P82 1: BRQBRQ

25 RDX RDX Always set the RDXE bit in EPCR0 to "1."

222

CHAPTER 5 I/O PORTS

26 WR0X WR0X Always set the WRE bit in EPCR0 to "1."Switched automatically depending on the bus width selected in MD0 to 2 and AMD0 to 5. 8 bits: P85 16 bits: WRIX

27 P85 8 bits: P85 16 bits: WRIX

WR1X

14 CS0X CS0X Always set the COE0 bit in EPCR0 to "1."



223




13 to 12 PA1 to PA2 CS1X to CS2X EPCR0 (COE1 to COE2 bits) 0: PA1 to PA2 1: CS1X to CS2XCS1X to CS2X

11 PA3 CS3X EPCR0 (COE3 bit) and DATCR (EPSE1, EPDE1 bits)COE3, EPSE1, EPDE1 000: PA3 100: CS3X Other: E0P1

CS3X

E0P1

10 to 9 PA4 to PA5 CS4X to CS5X EPCR0 (COE4 to COE5 bits) 0: PA4 to PA5 1: CS4X to CS5XCS4X to CS5X

8 PA6 CLK EPCR0 (CKE bit) 0: PA6 1: CLKCLK

99 to 1001 to 2

PB0 to PB3 PB0 to PB3 DSCR (RS0E to DW1E bits) 0: PB0 to PB7 1: RAS0 to DWOXRAS0

CS0LCS0HDW0X

3 PB4 PB4 DSCR (RS1E bit) and DATCR (EPSE2, EPDE2 bits)RS1E, EPSE2, EPDE2 000: PB4 100: RAS1 Other: E0P2

RAS1

E0P2

4 PB5 PB5/DREQ2 DSCR (C1LE) 0: PB5 1: CS1LThe value of the pin is always entered to DREQ2.

CS1L

DREQ2

5 PB6 PB DSCR (C1HE bit) and DATCR (AKSE2, AKDE2 bits)C1HE, AKSE2, AKDE2 000: PB6 100: CS1H Other: DACK2

CS1H

DACK2

6 PB7 PB7 DSCR(DW1E) 0: PB7 1: DW1XDW1X

19 to 21 MD0 to MD2 MD0 to MD2 -

16 HSIX HSIX -

15 NMIX NMIX -

75 to 78 AN0 to AN3 AN0 to AN3 -

224

CHAPTER 5 I/O PORTS

98 to 97 PE0 to PE1 PE0/INT0 to PE1/INT1

The values of the pins are always entered in INT0 and INT1.

INT0 to INT1

92 to 91 PE2 to PE3 PE2/INT2 to PE3/INT3

SMR (SCKE) 0: The values of the pins are entered in SC1 and SC2. 1: SC1, SC2 (output)

INT2 to INT3

SC1 to SC2



225




90 to 89 PE4 to PE5 PE4/DREQ0 to PE5/DREQ1

The values of the pins are always entered in DREQ0 and DREQ1.

DREQ0, DREQ1

88 to 87 PE6 to PE7 PE6 to PE7 DATCR (AKSE0/1, AKDE0/1 0: PE6, PE7 1: DACK0, DACK1DACK0, DACK1

79 PF0 PF0/SI0/TRG0 The value of the pin is always entered in SI0 and TRG0 (except when stopped)TRG0

SI0

80 PF1 PF1/TRG1 SMR (SOE) 0: PF1 1: S00 (output)The value of the pin is always entered in TRG1 (except when stopped).

TRG1

S00

81 PF2 PF2/SC0(input)

PCNL (POEN) 0: PF2 1: OPCA3SMR (SCKE) 0: The value of the pin is entered in SC0 (except when stopped). 1: SC0 (output)

OPCA3

SC0

82 PF3 PF3/SI1/TRG2 The value of the pin is always entered in SI1 and TRG2 (except when stopped)SI1

TRG2

83 PF4 PF4/TRG3 SMR (SOE) 0: PF4 1: S01 (output)The value of the pin is always entered in TRG3 (except when stopped).

S01

TRG3

84 PF5 PF5/SI2 PCNL (POEN) 0: PF5 1: OPCA1The value of the pin is always entered in SI2 (except when stopped).

OPCA1

SI2

85 PF6 PF6 PCNL (POEN) 0: PF5 1: OPCA1SMR (S0E) 0: PF6 1: S02 (output)

OPCA2

S02

86 PF7 PF7 PCNL (POEN) 0: PF6 1: OPCA2OPCA0

226

CHAPTER 5 I/O PORTS

72 AVCC AVCC -

73 AVRH AVRH -

74 AVSS(AVRL)

AVSS(AVRL)

-



227




17 RSTX RSTX -

95 X0 X0 -

94 X1 X1 -

96, 46 Vcc5 Vcc5 -

7 Vcc3 Vcc3 -

18, 43, 68, 93 Vss Vss -

228

CHAPTER 5 I/O PORTS

229

CHAPTER 6 U-TIMER

This chapter explains the outline of the U-TIMER, the configuration/functions of the registers, and the operation of the U-TIMER.

6.1 Outline of the U-TIMER

6.2 Registers of the U-TIMER

6.3 Operation of the U-TIMER

230

CHAPTER 6 U-TIMER

6.1 Outline of the U-TIMER

The U-TIMER is a 16-bit timer that generates the baud rate of the UART. By combining the operating frequency of the chip and the reload value of the U-TIMER, any baud rate can be set.Since an interrupt is generated by counting underflow, it can also be used as an interval timer.

The MB91101 contains three channels of this timer. Up to 216 x φφφφ intervals can be counted.

List of Registers in U-TIMER

Figure 6.1-1 provides a list of the registers in the U-TIMER

Figure 6.1-1 List of the Registers in the U-TIMER

Block Diagram of U-TIMER

Figure 6.1-2 shows the block diagram of the U-TIMER.

Figure 6.1-2 B lock Diagram of the U-TIMER

15 8 7 0

UTIM (R)

UTIMR (W)

UTIMC (R/W)

15 0

UTIMR(reload register)

15 load 0

UTIM(t imer)

clock underf lowcontrol

f . f . to UART

(Peripheral c lock)

231



The U-TIMER registers include the following.• U timer value register (UTIM)• Reload register (UTIMR)• U timer control register (UTIMIC)

U -TIMER Value Register: UTIM (U-TIMER)

The UTIM indicates the value of the timer. Access with a 16-bit transfer instruction.

Reload Register: UTIMR (Reload Register)

The UTIMR is a register for storing the value reloaded to the UTIM when underflow occurs inthe UTIM.

Access with a 16-bit transfer instruction.

U-Timer Control Register: UTIMIC (U-Timer Control Register)

The UTIMIC controls the operation of the U-TIMER.

[bit 7] UCC1 (U-timer Count Control 1)

The UCC1 bit controls the method of counting the U-TIMER.

n: Set value of the UTIMRα: Cycle of the output clock for the UART

15 14 2 1 0UTIMch0 Address:0000 0078H b15 b14 b2 b1 b0ch1 Address:0000 007CH

ch2 Address:0000 0080H R0

Access in i t ia l value

15 14 2 1 0UTIMRch0 Address:0000 0078H b15 b14 b2 b1 b0ch1 Address:0000 007CHch2 Address:0000 0080H W

0 ini t ia l valueAccess

7 6 5 4 3 2 1 0UTIMCch0 Address:0000 007BH UCC1 UTIE UNDR CLKS UTST UTCRch1 Address:0000 007FH

ch2 Address:0000 0083H R/W R/W R/W R/W R/W R/W0 0 0 0 0 1

AccessInitial value

0 Ordinary operation α = 2n+2 [initial value]

1 +1 mode α = 2n+3

232

CHAPTER 6 U-TIMER

The U-TIMER can provide an ordinary 2(n+1) cycle clock as well as an odd frequencydivision for the UART.

When UCC1 is set to 1, 2n+3 cycles are generated.

[Setting example]

UTIMR=5, UCC1=0 -> Generated cycles = 2n+2 = 12 cycles



When the U-TIMER is used as an interval timer, set UCC1 to 0.

[bits 6, 5] (Reserved)

[bit 4] UTIE (U-TIMER Interrupt Enable)

UTIE is an interrupt enable bit due to U-TIMER underflow.

1: Interrupt disabled [Initial value]

0: Interrupt enabled

[bit 3] UNDR (UNDeR flow flag)

UNDR is a flag indicating the occurrence of underflow. When UNDR is set when UTIE is "1,"underflow interrupt occurs.

UNDR is cleared when reset or "0" is written. During a reading in the read modify writeinstructions, "1" is always read.

Writing "1" to UNDR is invalid.

[bit 2] CLKS (clock select)

In this model, set "0."

[bit 1] UTST (U-TIMER STart]

U-TIMER operation enable bit.

0: Stop: Even during operation, the U-TIMER is stopped when "0" is written. [initial value]

1: Operate: Even if "1" is written during operation, the U-TIMER continues operation.

[bit 0] UTCR (UTIMER CleaR)

When "0" is written to UTCR, the U-TIMER is cleared to 0000H. (f.f. is also cleared to "0.")

Always "1" is read.

<Precautions>

• If the start bit UTST is asserted (started) from the stop state, reloading is performedautomatically.

• If the clear bit UTCR and the start bit UTST are asserted simultaneously from the stop state,the counter is cleared to "0" and underflow occurs in the countdown immediately thereafter.

• If the clear bit UTCR is asserted during operation, the counter is also cleared to "0."Therefore, a short impulse may be output in the output waveform that may cause the UARTto malfunction. When the output clock is used, do not clear the U-TIMER with the clear bitduring operation.

233



This section explains the calculation of the baud rate of the U-TIMER.

Baud Rate Calculation

The UART uses the under flip-flop (f.f. in the figure) of the corresponding U-TIMER (U-TIMERx -> UARTx, x = 0, 1, 2) as a clock source for the baud rate.

Asynchronous (start-stop synchronized) mode

The UART uses the output of the U-TIMER divided by 16.

CLK synchronous mode

n: UTIMR (Reload value)bps = When UCC1=0

(2n+2) 16 : Peripheral machine clock frequency (changed by gear)

bps = When UCC1=1(2n+3) 16

n: UTIMR (Reload value)bps = When UCC1=0

(2n+2)

bps = When UCC1=1(2n+3)

: Per ipheral machine clock f requency (changed by gear)

234

CHAPTER 6 U-TIMER

235

CHAPTER 7 16-BIT RELOAD TIMER

This chapter explains the outline of the 16-bit reload timer, the configuration and functions of the registers, and the operation of the 16-bit reload timer.

7.1 Outline of the 16-Bit Reload Timer

7.2 Control Status Register (TMCSR)

7.3 16-Bit Timer Register (TMR)/16-Bit Reload Register (TMRLR)

7.4 Operation of 16-Bit Reload Timer

7.5 Operating State of the Counter

236


7.1 Outline of the 16-bit Reload Timer

The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating the internal count clock, and a control register. The channel 2 TO output of the reload timer is connected to the A/D converter in the LSI. Therefore, A/D conversion can be activated in the cycles set in the reload register. The input clock can be selected from three types of internal clocks (2/8/32 divisions of the machine clock).DMA transfer can be activated by an interrupt.The MB91101 contains three channels of this timer.

List of 16-Bit Reload Timer

Figure 7.1 shows the list of the registers in the 16-bit reload timer.

Figure 7.1-1 List of Registers in 16-bit Reload Timer

15 14 13 12 11 10 9 8(TMCSR)

CSL1 CSL0 MOD2 MOD1

7 6 5 4 3 2 1 0

MOD0 OUTE OUTL RELD INTE UF CNTE TRG

15 0

(TMR)

15 0

(TMRLR)

Control status register

16-bi t t imer register

16-bi t re load register

237

7.1 Outline of the 16-bit Reload Timer

Block Diagram of 16-Bit Reload Timer

Figure 7.1-2 shows the block diagram of the 16-bit reload timer

Figure 7.1-2 Block Diagram of 16-bit Reload Timer

16/

/8

RELD

/ UF OUTE16

OUTL2/ OUT INTE

GATE CTL. /2 UF IRQ

CSL1CNTE

CSL0TRG

/2

IN CTL.EXCK PWM(ch.0,ch.1)

3 A/D (ch.2)

21 23 25 MOD2

MOD1

MOD0

/3

R

|

B

U

S

16-bi t re load register

Reload

16-bi t down counter

Clock selector

Retr igger

Prescaler c lear

Internal c lock

238



The control status register (TMCSR) controls the operation mode and interrupts of the 16-bit timer.Excepting the UF, CNTE, and TRG bits, bits can be rewritten only when CNTE = 0.Simultaneous writing is possible.

Configuration of Control Status Register (TMCSR)

Bit Functions of Control Status Register (TMCSR)

[bits 11, 10] CSL1, CSL2 (Count clock SLect)

Count clock select bit

The clock source selected is shown in Table 7.2-1.

[bits 9, 8, 7] MOD2, MOD1, MOD0 (MODe)

Bits for setting the operation mode

Set "0."

[bit 6] OUTE (OUTput Enable)

Set "0."

[bit 5] OUTL

Set "0."

[bit 4] RELD

A reload enable bit. When this bit is set to "1," the timer enters the reload mode. Theinstant the counter value underflows from 0000H to FFFFH, the contents of the reloadregister are loaded to the counter and the timer continues the count operation. The timerstops the count operation when this bit is "0" and the counter value underflows from 0000Hto FFFFH.

11 10 9 8 7 6 5 4 3 2 1 0TMCSR

Address:00002EH CSL1 CSL0 MOD2 MOD1 MOD0 OUTE OUTL RELD INTE UF CNTE TRG000036H -000H

000042H R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W

Ini t ia l value

Table 7.2-1 CSL Bit Setting Clock Source

CSL1 CSL0 Clock source (φφφφ machine clock)

0 0 φ/21

0 1 φ/23

1 0 φ/25

1 1 Setting prohibited

239


[bit 3] INTE

An interrupt request enable bit. When this bit is "1" and the UF bit is set to "1," an interruptrequest is generated. When this bit is set to "0," no interrupt request is generated.

[bit 2] UF

A timer interrupt request flag. When the counter value underflows from 0000H to FFFFH, thisbit is set to "1." This flag is cleared when "0" is written to this bit.

Writing "1" to this bit has no significance.

During a reading in read modify write instructions, "1" is read.

[bit 1] CNTE

A count enable bit of the timer. When "1" is written to this bit, the time enters the activatingtrigger wait state. The timer stops the counting operation when "0" is written.

[bit 0] TRG

A software trigger bit. When "1" is written, software is triggered and the contents of thereload register are loaded to the counter to start the counting operation.

Writing "0" to this bit has no significance. The read value is always "0." The trigger input bythis register is effective only when CNTE = "1." When CNTE = "0," no operation occurs.

240


7.3 16-Bit Timer Register (TMR)/16-Bit Reload Register (TMRLR)

The 16-bit timer register (TMR) can read the count value of the 16-bit timer.The 16-bit reload register (TMRLR) holds the initial value of the count.

16-Bit Timer Register (TMR)

The 16-bit timer register (TMR) can read the count value of the 16-bit timer. The initial value isundefined.

Read this register with a 16-bit data transfer instruction.

16-Bit Reload Register (TMRLR)

The 16-bit reload register (TMRLR) holds the initial value of the count. The initial value isundefined.

Read this register with a 16-bit data transfer instruction.

15 0TMR

:00002AH

000032H

00003EH

R R R R R R R R R

Address

Ini t ia l value

0

Address:000028H

000030H

00003CH

WWWW W W W W W

TMRLR15

Initial value

241



The 16-bit reload timer performs the following two operations.• Internal clock operation• Underflow operation

Internal Clock Operation

When operating the timer with the frequency-divided clock of the internal clock, the clock sourcecan be selected from the machine clocks divided by 2, 8, and 32.

To start count operation concurrently with the count permission, write "1" to both the CNTE andTRG bits in the control status register. The trigger input by the TRG bit is always effective whenthe timer is activated (CNTE = "1") regardless of the operation mode.

Activation and operation of the counter are shown in Figure 7.4-1.

From the point at which the counter start trigger is entered until the point at which the data in thereload register is loaded to the counter, the time period T (T: machine cycle of the peripheralclock) is required.

Figure 7.4-1 Timing of Counter Activation and Operation

Underflow Operation

The point at which the counter value is changed from 0000H to FFFFH is defined as underflow.Therefore, underflow occurs at [reload register set value + 1].

When the RELD bit in the control register is "1" at the occurrence of underflow, the contents ofthe reload register are loaded and the timer continues the counting operation. When the RELDbit is "0," the counter stops at FFFFH.

If the UF bit in the control register is set by underflow when the INTE bit is "1," an interruptrequest is generated.

Figure 7.4-2 shows the underflow operation.

T

- 1 - 1 - 1

Count clock

Counter

Data load

CNTE (register)

TRG (register)

Reload data

242


Figure 7.4-2 Timing of the Underflow Operation.

0000H

(RELD=1)

0000H FFFFH

(RELD=0)

-1 -1 -1

Count clock

Counter

Data load

Underflow set

Underflow set

Counter

Count clock

243



The state of the counter is determined by the CNTE bit in the control register and the internal WAIT signal. The following states can be set: the stop state with CNTE = "0" and WAIT = "1" (STOP state), the activation trigger wait state with CNTE = "1" and WAIT = "1" (WAIT state), and the operating state with CNTE = "1" and WAIT = "0" (RUN state). The transition of these states is shown in Figure 7.5-1.

Operating State of Counter

Figure 7.5-1 State Transition of the Counter

The channel 2 TO output of the reload timer is connected to the A/D converter in the LSI.Therefore, A/D conversion can be activated in the cycles set in the reload register.

CNTE=0,WAIT=1

CNTE='0'' CNTE='0'

CNTE='1' CNTE='1'

TRG='0' TRG='1'

CNTE=1,WAIT=1 CNTE=1,WAIT=0

RELD

TRG='1' TRG='1'

RELD UFCNTE=1,WAIT=0

STOP

RESET

WAIT

UF

LOAD

RUN

State transition by hardware

State transition by register access

Counter: Holds the value at stop. Undefined immediately after reset.

Counter: Holds the value at stop. Undefined from immediately after reset to loading.

Counter: Operates

The contents of the reload registerare loaded to the counter.

Loading is completed.

244


245

CHAPTER 8 PWM TIMER

This chapter explains the outline of the PWM timer, the configuration and functions of the registers, and the operation of the PWM timer.

8.1 Outline of the PWM Timer

8.2 Block Diagram of the PWM Timer

8.3 Control Status Registers (PCNH, PCNL)

8.4 PWM Cycle Setting Register (PCSR)

8.5 PWM Duty Setting Register (PDUT)

8.6 PWM Timer Register (PTMR)

8.7 General Control Register 1 (GCN1)


8.9 PWM Operation

8.10 One-Shot Operation

8.11 Interrupt

8.12 PWM Output All "L" and All "H"

8.13 Activating Two or More Channels of the PWM Timer

246

CHAPTER 8 PWM TIMER


The PWM timer can output very precise PWM waveforms efficiently. The MB91101 contains four channels of the PWM timer.Each channel consists of a 16-bit down counter, a 16-bit data register with a cycle setting buffer, a 16-bit compare register with a duty setting buffer, and a pin control section.

Features of PWM Timer

• The count clock of the 16-bit counter can be selected from four types of internal clocks.

• Internal clock: φ, φ/4, φ/16, φ/64

• The counter value can be initialized to "FFFFH" with reset and counter borrow.

• Each channel has PWM output.

• Registers

• Cycle setting register: Reload data register with a buffer

• Duty setting register: Compare register with a buffer

• Transfer from the buffer is performed with counter borrow.

• Pin control

• Set to "1" at duty matching (having the priority).

• Reset to "0" at counter borrow.

• The output value fixing mode is provided and all "L" (or "H") can be output easily.

• The polarity can also be specified.

• An interrupt request can be generated by selecting one from the following combinations.

• Activation of the PWM timer.

• Generation of counter borrow (cycle matching).

• Generation of duty matching.

• Generation of counter borrow (cycle matching) or generation of duty matching.

DMA transfer can be activated from the above interrupt request.

• imultaneous activation of two or more channels can be set with software or another intervaltimer. Reactivation during operation can also be set.

247


List of Registers of PWM Timer

Figure 8.1-1 shows the list of the registers of the PWM timer.

Figure 8.1-1 List of the Registers of the PWM Timer.

15 0

000000DCH R/W

000000DFH R/W

000000E0H R

000000E2H W

000000E4H W

000000E6H R/W

000000E8H R

000000EAH W

000000ECH W

000000EEH R/W

000000F0H R

000000F2H W

000000F4H W

000000F6H R/W

000000F8H R

000000FAH W

000000FCH W

000000FEH R/W

Address

GCN1

GCN2

PTMR

PCSR

PDUT

PCNH PCNL

PTMR

PTMR

PTMR

PCSR

PCSR

PCSR

PDUT

PDUT

PDUT

PCNH

PCNH

PCNH

PCNL

PCNL

PCNL

General control register 1


ch0 timer register

ch0 cycle setting register

ch0 duty setting register

ch0 control status register

ch1 timer register




ch2 timer register




ch3 timer register




248

CHAPTER 8 PWM TIMER


Figures 8.2-1 and 8.2-2 show the general block diagram of the PWM timer and the block diagram of one channel of the PWM timer, respectively.

General Block Diagram of PWM Timer

Figure 8.2-1 General Block Diagram of the PWM Timer

PWM0

PWM1

4

PWM2

PWM3

4

16-bit reload timer ch0

16-bit reload timer ch1


External TRGs 0 to 3

Gen

eral

con

trol

reg

iste

r 1

(sou

rce

sele

ctio

n)

TRG input PWM timer ch0




249


Block Diagram of One Channel of PWM Timer

Figure 8.2-2 Block Diagram of One Channel of the PWM Timer

1/1 cmp

1/4 ck

1/16

1/64

S Q

R

IRQ

PCSR PDUT

Prescaler

Peripheral clock

Load

16-bi t down counter

Start Borrow

PPG mask

PWM output

Inverted bi t

TRG input

Enable

Edgedetect ion

Software t r igger

inte

rru

pt

se

lec

tio

n

250

CHAPTER 8 PWM TIMER


The control status registers (PCNH, PCNL) control the PWM timer and display its status. Note that there are bits that cannot be rewritten during PWM timer operation.

Configuration of Control Status Registers (PCNH, PCNL)

The register configuration of the control status registers (PCNH, PCNL) is shown in thefollowing.

Bit Functions of Control Status Registers (PCNH, PCNL)

[bit 15] CNTE: Timer enable bit

A bit for allowing a 16-bit down counter operation.

[bit 14] STGR: Software trigger bit

Writing "1" to this bit, triggers the software.

The read value of the STGR bit is always "0."

[bit 13] MDSE: Mode selection bit

A bit for selecting either a PWM operation that outputs pulses continuously or a one-shotoperation that outputs a single pulse.

PCNH bit 15 14 13 12 11 10 9 8Address: ch0 0000E6H

ch1 0000EEH CNTE STGR MDSE RTRG CKS1 CKS0 PGMSch2 0000F6H

ch3 0000FEH R/W R/W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0

PCNL bit 7 6 5 4 3 2 1 0Address: ch0 0000E7H

ch1 0000EFH EGS1 EGS0 IREN IRQF IRS1 IRS0 POEN OSELch2 0000F7H

ch3 0000FFH R/W R/W R/W R/W R/W R/W R/W R/W

0 0 0 0 0 0 0 0

Attr ibute

Attr ibute

Ini t ia l value

Ini t ia l value

Rewri t ing dur ing operat ion

Rewri t ing dur ing operat ion

0 Stop (initial value)

1 Permission

0 PWM operation (initial value)

1 One-shot operation

251


[bit 12] RTRG: Restart enable bit

A bit for allowing a restart by software trigger or trigger input.

[bits 11, 10] CKS1, CKS0: Counter clock selection bit

Bits for selecting the count clock of the 16-bit counter

φ: Peripheral system machine clock

[bit 9] PGMS: PWM output mask selection bit

Writing "1" to this bit, masks the PWM output to "0" or "1" regardless of the mode setting,cycle setting, or duty setting.

To output all "H" in normal polarity or to output all "L" in inverted polarity, write the abovevalue to the cycle setting register and the duty setting register. The inversion of the abovemasked value can be output.

[bit 8]: Unused bit

[bits 7, 6] EGS1, SGS0: Trigger input edge selection bits

Select the effective edge of the activation source selected in the general control register 1.

Regardless of which mode is selected, the software trigger becomes valid when "1" is writtento the bit of the software trigger.

0 Restart prohibited (initial value)

1 Restart allowed

Table 8.3-1 Selection of the Count Clock

CKS1 CKS0 Cycle

0 0 φ (Initial value)

0 1 φ/4

1 0 φ/16

1 1 φ/64

Table 8.3-2 PWM Output When "1" is Written to PGMS

Polarity PWM output

Normal polarity L output

Inverted polarity H output

Table 8.3-3 Selection of the Trigger Input Edge

EGS1 EGS0 Edge selection

0 0 Invalid (initial value)

0 1 Rising edge

1 0 Falling edge

1 1 Both edges

252

CHAPTER 8 PWM TIMER

[bit 5] IREN: Interrupt request enable bit

A bit for enabling an interrupt request.

[bit 4] IRQF: Interrupt request flag

When bit 5 (IREN) is enabled and the interrupt source selected in bits 3 and 2 (IRS1, IRS0)is generated, this bit is set and an interrupt request is generated to the CPU. Whenactivation of DMA transfer is selected, DMA transfer is activated.

This bit is cleared by writing "0" or a clear signal from the DMAC.

Even if "1" is written, the bit value is not changed.

The read value in the read modify write instruction is "1" regardless of the bit value.

[bits 3, 2] IRS1, IRS0: Interrupt source selection bit

A bit for selecting the source that sets bit 4 (IRQF).

[bit 1] POEN: PWM output enable bit

When "1" is set, the PWM output is output from the pin.

0 Disabled (initial value)

1 Enabled

Table 8.3-4 Selection of the Interrupt Source

IRS1 IRS0 Interrupt source

0 0 Software trigger or trigger input present (initial value)

0 1 Counter borrow (cycle matching) is generated

1 0 Duty matching is generated

1 1 Counter borrow (cycle matching) or duty matching is generated

0 General-purpose port (initial value)

1 PWM output pin

253


[bit 0] OSEL: PWM output polarity specification bit

A bit for setting the polarity of the PWM output.

By combining with bit 9 (PWMS), the PWM output becomes as shown in the following

Table 8.3-5 Specification of the Polarity of the PWM Output and the Edge

PGMS OSEL PWM output

0 0 Normal polarity (initial value)

0 1 Inverted polarity

1 0 Output is fixed to "L"

1 1 Output is fixed to "H"

Polarity After reset Duty matching Counter borrow

Normal polarity

"L" is output

Inverted polarity

"H" is output

254

CHAPTER 8 PWM TIMER

8.4 PWM Cycle Setting Register (PCSR)

The PWM cycle setting register (PCSR) is a register with a buffer for setting the cycle. The transfer from the buffer is performed with counter borrow.

PWM Cycle Setting Register (PCSR)

The register configuration of the PWM cycle setting register (PCSR) is shown in the following.

When setting or rewriting the initial value to the cycle setting register, write to the duty settingregister after writing the cycle setting register.

Access this register with 16-bit data.

PCSR bit 15 14 13 12 11 10 9 8Address: ch0 0000E2H

ch1 0000EAH

ch2 0000F2H

ch3 0000FAH 7 6 5 4 3 2 1 0

Attr ibute Wri te onlyIni t ia l value Undef ined

255



The PWM duty setting register (PDUT) is a register with a buffer for setting the duty. The transfer from the buffer is performed with counter borrow.

PWM Duty Setting Register (PDUT)

The register configuration of the PWM duty setting register (PDUT) is shown in the following.

When the same value is entered to the cycle setting register and the duty setting register, all "H"is output in normal polarity and all "L" is output in inverted polarity.

The value set in the PDUT should be equal to or less than the value set in the PCSR; otherwisethe output of the PWM will be undefined.


PDUT bit 15 14 13 12 11 10 9 8Address: ch0 0000E4H

ch1 0000ECH

ch2 0000F4H

ch3 0000FCH 7 6 5 4 3 2 1 0

Attr ibute Wri te onlyIni t ia l value Undef ined

256

CHAPTER 8 PWM TIMER

8.6 PWM Timer Register (PTMR)

The PWM timer register (PTMR) can read the value of the 16-bit down counter.

PWM Timer Register (PTMR)

The register configuration of the PWM timer register (PTMR) is shown in the following.


PTMR bit 15 14 13 12 11 10 9 8Address: ch0 0000E0H

ch1 0000E8H

ch2 0000F0H

ch3 0000F8H 7 6 5 4 3 2 1 0

FFFFH

Attr ibute Read onlyIni t ia l value

257



The general control register 1 (GCN1) selects the source of the trigger input of the PWM timer.

Configuration of General Control Register 1 (GCN1)

The configuration of the general control register 1 (GCN1) is shown in the following.

GCN1 bit 15 14 13 12 11 10 9 8Address: 0000DCH

TSEL33:30 TSEL23:20

R/W R/W R/W R/W R/W R/W R/W R/W

0 0 1 1 0 0 1 0

bit 7 6 5 4 3 2 1 0

TSEL13:10 TSEL03:00


0 0 0 1 0 0 0 0

Attr ibute

Attr ibute

Ini t ia l value

Ini t ia l value

258

CHAPTER 8 PWM TIMER

Bit Functions of General Control Register 1 (GCN1)

[bits 15-12] TSEL 33-30: ch3 trigger input selection bits


Table 8.7-1 Selection of Ch3 Trigger Input

TSEL33-30 ch3 trigger input

15 14 13 12

0 0 0 0 EN0 bit of GCN2



0 0 1 1 EN3 bit of GCN2 (initial value)

0 1 0 0 16-bit reload timer ch0


0 1 1 X Setting prohibited

1 0 0 0 External TRG0




1 1 X X Setting prohibited



11 10 9 8













259






7 6 5 4















3 2 1 0













260

CHAPTER 8 PWM TIMER


The general control register 2 (GCN2) generates an activation trigger using software.

General Control Register 2 (GCN2)

The register configuration of the general control register 2 (GCN2) is shown in the following.

When the EN bit in this register is selected with the general control register 1 (GCN1), the valueof the register is transferred to the trigger input of the PWM timer as it is.

By generating the edge selected with the EGS1 and 0 bits in the control status register, thePWM timers of two or more channels can be started simultaneously.

Write "0" to bits 7 to 4 in this register.

GCN2 bit 7 6 5 4 3 2 1 0Address: 0000DFH

EN3 EN2 EN1 EN0


0 0 0 0 0 0 0 0

Attr ibute

Ini t ia l value

261

8.9 PWM Operation

8.9 PWM Operation

The PWM operation outputs pulses continuously.

PWM Operation.

In PWM operation, pulses can be output continuously after the activation trigger is detected.

The cycle of the output pulse can be controlled by changing the PCSR value and the duty ratiocan be controlled by changing the PDUT value.

After writing data to the PCSR, write data to the PDUT.

<Precautions>

When the external TRG input is selected as an activation trigger, enter a pulse above thefollowing minimum pulse width.

Pulse width: 5 machine cycles or more (cycles of the peripheral clock)

Even if a pulse below the above is entered, it may be recognized as an effective pulse. Sincethis model does not have a filter function in the external TRG input, add an external filter ifrequired.

Figures 8.9-1 and 8.9-2 show the timing charts of the PWM operation when trigger re-activationis prohibited and allowed, respectively.

262

CHAPTER 8 PWM TIMER

When re-activation is prohibited

Figure 8.9-1 PWM Operation Timing Chart (Trigger Re-activation Prohibited)

When re-activation is allowed

Figure 8.9-2 PWM Operation Timing Chart (Trigger Re-activation Allowed)

m

n

0

PWM

Activat ion t r igger

The r is ing edge is detected. Tr igger is ignored.

T: Count c lock cycle

m: PCSR value

n: PDUT value

= T (n + 1)

= T (m + 1)

m

n

0

PWM


The r is ing edge is detected. Re-act ivated by t r igger.

T: Count c lock cyclem: PCSR valuen: PDUT value

= T (n + 1)

= T (m + 1)

263



The one-shot operation outputs a single pulse.

One-Shot Operation

In a one-shot operation, a single pulse of any width can be output by a trigger.

When re-activation is allowed, the counter is reloaded when an edge is detected duringoperation.

Figures 8.10-1 and 8.10-2 show the timing charge of the one-shot operation when re-activationof a trigger is prohibited and allowed, respectively.

When re-activation is prohibited

Figure 8.10-1 One-shot Operation Timing Chart (Trigger Re-activation Prohibited)

m

n

0

PWM


The r is ing edge is detected. Tr igger is ignored.


= T (n + 1)

= T (m + 1)

264

CHAPTER 8 PWM TIMER

When re-activation is allowed

Figure 8.10-2 One-shot Operation Timing Chart (Trigger Re-activation Allowed)

m

n

0

PWM


The r is ing edge is detected. Re-act ivated by t r igger.


= T (n + 1)

= T (m + 1)

265

8.11 Interrupt

8.11 Interrupt

Figure 8.11 shows the timing chart of an interrupt source

Interrupt

Figure 8.11-1 Timing Chart of the Interrupt Source (PWM Output: Normal Polarity)

0003 0002 0001 0000 0003

PWM


2.5T max.

Load

Clock

Count value

InterruptEffect ive edge Duty matching Counter borrow

*: From the act ivat ion t r igger to the load of the count value, a maximum per iod of 2.5T (T: count c lock cycle) is required.

266

CHAPTER 8 PWM TIMER

8.12 PWM Output All "L" and All "H"

Figures 8.12-1 and 8.12-2 show the output method for setting the PWM output to all "L" and all "H."

PWM Output All "L" and All "H"

Example of setting all PWM output to level "L".

Figure 8.12-1 Example of Setting all PWM Output to Level "L"

Example of setting all PWM output to level "H"

Figure 8.12-2 Example of Setting all PWM Output to Level "H"

PWM

Gradual ly decrease the duty value.

Wri te "1" to PGMS (mask bi t ) wi th a borrow interrupt.I f "0" is wr i t ten to PGMS (mask bi t ) in a borrow interrupt, a PWM waveform can be output wi thout outputt ing an impulse noise.

PWM

Gradual ly increase the duty value.

Wri te the same value in the cycle set t ing register and the duty set t ing register wi th a compare matching interrupt.

267



By using the general control registers 1 and 2 (GCN1, GCN2), two or more channels of the PWM timer can be activated.By selecting the activation trigger in the GCN1 register, two or more channels can be activated simultaneously.This section shows examples of activating two or more channels of the PWM timer by software activation using the GCN2 register and by the 16-bit reload timer.

Activating Two or More Channels of PWM Timer with Software

The setting procedure is shown in the following.

1. Set the cycle in the PCSR.

2. Set the duty in the PDUT.

• Write a value to the PSCR first, and then write a value to the PDUT.

3. In the GCN1, determine the trigger input source of the channel to be activated.

• Since the GCN2 is used here, the initial setting is used. (ch0 -> EN0, ch1 -> EN1, ch2 -> EN2, ch3 -> EN3)

4. Set the control status register of the channel to be activated.

• CNTE: 1 -> Allows timer operation.

• STGR: 0 -> It is not activated here because it is activated in the GCN2.

• MDSE: 0 -> PWM operation

• RTRG: 0 -> Re-activation is prohibited.

• CSK1, 0: 00 -> Count clock = φ

• PGMS: 0 -> Output is not masked.(bit 8: 0 -> Unused bit. Any value may be set.)

• EGS11, 0: 01 -> Activates the rising edge.

• IREN: 1 -> Interrupt requests are enabled.

• IRQF: 0 -> Interrupt sources are cleared.

• IRS1, 0: 01 -> An interrupt request is generated due to the occurrence of counter borrow.

• POEN: 1 -> PWM output is allowed.

• OSEL: 0 -> Normal polarity

5. Writing data to GCN2 generates an activation trigger.

• To activate ch0 and ch1 simultaneously in the above setting, write "1" to EN0 and EN1 inthe GCN2. A rising edge is generated and pulses are output from PWM0 and PWM1.

268

CHAPTER 8 PWM TIMER

Activating by Using 16-Bit Reload Timer

Select the 16-bit reload timer as the source in GCN1 in Step 3) in the previous section andactivate the 16-bit reload timer instead of the GCN2 in Step 5).

In addition, set the control status register as shown in the following.RTRG: 1 -> Re-activation is allowed.EGS1, 0: 11 -> Activates both edges.

The PWM timer can also be reactivated at certain intervals by setting the 16-bit reload timeroutput to toggle output.

269

CHAPTER 9 EXTERNAL INTERRUPT/NMI CONTROL

This chapter explains the general outlines of the external interrupt/NMI controller, configuration/functions of registers, and operations of the external interrupt/NMI controller.

9.1 Overview of the External Interrupts/NMI Controller

9.2 Enable Interrupt Request Register (ENIR)

9.3 External Interrupt Request Register (EIRR)

9.4 External Level Register (ELVR)

9.5 External Interrupt Operation

9.6 External Interrupt Level

9.7 NMI (Non Maskable Interrupt) Operations

270


9.1 Overview of the External Interrupts/NMI Controller

The external interrupt/NMI controller is a block to control external interrupt requests input into NMI and INT0 to 3."H", "L", "rising edge", and "falling edge" can be selected as a request level to be detected (excepting NMI).

Register List of the External Interrupt/NMI Controller

Figure 9.1-1 shows a register list of the external interrupt/NMI controller.

Figure 9.1-1 Register List of the External Interrupt/NMI Controller

Block Diagram of the External Interrupt/NMI Controller

Figure 9.1-2 shows a block diagram of the external interrupt/NMI controller.

Figure 9.1-2 Block Diagram of the External Interrupt/NMI Controller

bit 7 6 5 4 3 2 1 0

EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0

bit 15 14 13 12 11 10 9 8

ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0

bit 7 6 5 4 3 2 1 0

LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0

Enable interrupt request register (ENIR)

External interrupt request register (EIRR)

External level register (ELVR)

R BUS

INT0 3

NMIX

8

9

8

8

5

Enable interrupt request register

Request level

Gate Factor F/F Edge detect ion c i rcui t

External interrupt request register

External level register

271



The enable interrupt request register (ENIR) performs the mask control of external interrupt request output.

Enable Interrupt Request Register (ENIR)

The register configuration of the enable interrupt request register (ENIR) is as follows:

The enable interrupt request register (ENIR) performs the mask control of external interruptrequest output.

Request level output corresponding to the bit of this register to which is set "1" is allowed (Thepermission of INT0 is controlled by EN0) and a request is output to the interrupt controller. Pinscorresponding to the bits to which is set "0" retain interrupt sources but do not sent a request tothe interrupt controller.

A write operation to bits EN4 to EN7 has no significance in this device.

Write "0" into bits EN4 to EN7.

<Precautions>

There is no mask bit for NMI (Non Maskable Interrupt).

7 6 5 4 3 2 1 0ENIRAddress:000095H EN7 EN6 EN5 EN4 EN3 EN2 EN1 EN0 00000000 R/W

Ini t ia l value Access

272


9.3 External Interrupt Request Register (EIRR)

The external interrupt request register (EIRR) indicates that there is a corresponding external interrupt request during a read operation. EIRR is used to clear the flip-flop content of this request during a write operation.

External Interrupt Request Register (EIRR)

The register configuration of the external interrupt request register (EIRR) is as follows:

The external interrupt request register (EIRR) indicates that there is a corresponding externalinterrupt request during a read operation. EIRR is used to clear the flip-flop content of thisrequest during a write operation.

When "1" is read from this register, there is an external interrupt request at the pincorresponding to this bit.

If "0" is written into this register, the request flip-flop of the corresponding bit is cleared. Writing"1" to this register is invalid.

"1" is read during a read operation of the read/modify/write.

<Precautions>

The NMI flag cannot be read/written by the user.

15 14 13 12 11 10 9 8EIRRAddress:000094H ER7 ER6 ER5 ER4 ER3 ER2 ER1 ER0 00000000 R/W

AccessIni t ia l value

273



The external level register (ELVR) is used to make a selection for request detection.

External Level Register (ELVR)

The register configuration of the external level register (ELVR) is as follows:

The external level register (ELVR) is used to make a selection for request detection.

Two bits each are allocated to INT0 to 3 as listed in Table 9.4-1.

If the request input is a level detection and the input is at an active level after clearing each bit ofEIRR, the relevant bit is set again.

<Precautions>

NMI is always detected by its falling edges (except when stopped). When stopped, it isdetected by level L.

To use an external interrupt for returning from the clock stop mode, set the input request to theH level.

7 6 5 4 3 2 1 0ELVRAddress:000099H LB3 LA3 LB2 LA2 LB1 LA1 LB0 LA0 00000000 R/W

Ini t ia l value Access

Table 9.4-1 Allocation of the External Interrupt Request Levels

LBx LAx Operation

0 0 Request with the L level

0 1 Request with the H level

1 0 Request with the rising edge

1 1 Request with the falling edge

274


9.5 External Interrupt Operation

If the external level register (ELVR) and enable interrupt request register (ENIR) are set and a request is then input into the corresponding pin specified by the ELVR register, this module sends an interrupt request signal to the interrupt controller.

External Interrupt Operations

If the priority of an interrupt from this resource is the highest as a result of priority analyses inthe interrupt controller of interrupts occurring simultaneously, the relevant interrupt is generated.

Figure 9.5-1 shows an external interrupt operation.

Figure 9.5-1 External Interrupt Operation

Returning from the Stop State

To use an external interrupt to return from the stop state in clock stop mode, the input requestmust be the H level request. If it is the L level request, malfunctioning may be caused.

If the input request is an edge request, returning from the stop state in clock stop mode is notpossible.

Procedure for an External Interrupt Operation

To set a register in the external interrupt section, proceed as follows:

1. Disable the bits for the enable interrupt request register (ENIR).

2. Set the bits for the external level register (ELVR).

3. Clear the bits for the external interrupt request register (EIRR).

4. Enable the bits for the enable interrupt request register (ENIR).

3) and 4) can be performed simultaneously using 16-bit data.

Before setting a register in this module, the enable interrupt request register (ENIR) must bedisabled. Before enabling the enable interrupt request register (ENIR), the external interruptrequest register (EIRR) must be cleared to prevent the occurrence of false interrupt sourceswhen a register is set or interrupts allowed.

CPU

ELVR ICR yy IL

EIRR CMP CMP

ENIR ICR xx ILM

External interrupt

Resource request

Interrupt control ler

275



To detect the occurrence of an edge when the request level is an edge request, the pulse width requires at least three machine cycles (peripheral system clock machine cycle).If the request input level is a level setting, the request to the interrupt controller remains active even if a request entered from outside is canceled because a request source holding circuit exists inside.To cancel a request to the interrupt controller, the external interrupt request register (EIRR) must be cleared.

External Interrupt Level

Figure 9.6-1 shows a clear operation of the request source holding circuit during a level setting,and Figure 9.6-2 shows an interrupt source and an interrupt request to the interrupt controllerwhen interrupts are allowed.

Figure 9.6-1 Clear Operation of the Request Source Holding Circuit During Level Setting

Figure 9.6-2 Clear Operation of the Request Source Holding Circuit During Level Setting

Interrupt input Level detect ion

Factor F/F (request source

holding ci rcui t )

Enabl ing gate

To interrupt control ler

Factors are held i f not c leared

Interrupt inputH level

Interrupt request to interrupt control ler

Inact ive af ter c lear ing the request source F/F

276


9.7 NMI (Non Maskable Interrupt) Operations

NMI is the top interrupt among user interrupts and cannot be masked. As an exception, NMI can be masked just after a reset before ILM is set.

NMI Operation

NMI is accepted as follows:

• Normal: falling edge

• Stopped: "L" level

The stop mode can be released by NMI. If the "L" level is entered in the stop state, the stopstate is released and the oscillation stabilization wait time is taken.

If the NMIX pin is returned to the "H" level in this oscillation stabilization wait time, no NMIrequest source exists and so NMI processing is not performed after the operation is restarted.To perform NMI processing after releasing the stop state, keep the NMIX pin at the "L" level andreturn it to the "H" level in the NMI processing routine.

The NMI bit is in the NMI request detection section and is set by an NMI request. The bit canonly be cleared by the acceptance of an NMI interrupt or a reset and cannot be read or writtento.

Figure 9.7-1 shows the request detection section of NMI.

Figure 9.7-1 Request Detection Section of NMI

0Q SX NMIX

R1

STOP

clear (RST, interrupt acknowledge)

NMI request (stop release)

Falling edge detection

277

CHAPTER 10 DELAYED INTERRUPT MODULE

This chapter explains the general outlines of the delayed interrupt module, configuration/functions of registers, and operations of the delayed interrupt module

10.1 Overview of the Delayed Interrupt Module

10.2 Delayed Interrupt Control Register (DICR)

10.3 Operations of the Delayed Interrupt Module

278


10.1 Overview of the Delayed Interrupt Module

The delayed interrupt module is a module for generating an interrupt for switching tasks.Using this module, interrupt requests to CPU can be generated/canceled by software.

Register List of the Delayed Interrupt Module

Figure 10.1-1 shows a register list of the delayed interrupt module.

Figure 10.1-1 Register List of the Delayed Interrupt Module

Block Diagram of the Delayed Interrupt Module

Figure 10.1-2 Block Diagram of the Delayed Interrupt Module

bit7 6 5 4 3 2 1 0

Address:00000430H DLYI

R/W

DICR

CPU

ICR IL

CMP CMP

DICR ICR ILM

W R I T E

Interrupt control lerDelayed interrupt

Resource request

279



The delayed interrupt control register (DICR) is a register to control delayed interrupts.

Configuration of the Delayed Interrupt Control Register (DICR)

The configuration of the delayed interrupt control register (DICR) is as follows:

Bit Function of the Delayed Interrupt Control Register (DICR)

[bit0] DLYI

This bit controls the generation/release of the applicable interrupt source.

bit7 6 5 4 3 2 1 0

DLYI -------0

R/W

Address 00000430H (Ini t ia l value)

0 Release a delayed interrupt source/no request [initial value]

1 Generate a delayed interrupt source

280


10.3 Operations of the Delayed Interrupt Module

The delayed interrupt is used to generate an interrupt for switching tasks. By using this function, interrupt requests to CPU can be generated/canceled by software.

Interrupt Number

The delayed interrupt is allocated to an interrupt source with the largest interrupt No.

In this part number, the delayed interrupt is allocated to the interrupt No. 63 (3F11).

DLYI Bit of DICR

By writing "1" into this bit, a relayed interrupt source is generated. By writing "0", a relayedinterrupt request is released.

This bit is the same as the interrupt source flag in a general interrupt. Clear this bit in aninterrupt routine simultaneously with task switching.

281

CHAPTER 11 INTERRUPT CONTROLLER

This chapter explains the general outlines of the interrupt controller, configuration/functions of registers, operations of the interrupt controller, and some examples of the hold request cancel request functions.

11.1 Overview of the Interrupt Controller

11.2 Block Diagram of the Interrupt Controller

11.3 Interrupt Control Register (ICR)

11.4 Hold Request Cancel Request/Level Setting Register (HRCL)

11.5 Priority Determination

11.6 Returning from the Standby Mode (Stop/Sleep)

11.7 Hold Request Cancel Request

11.8 Examples of the Hold Request Cancel Request Function (HRCR)

282



The interrupt controller controls interrupt acceptance and arbitration.

Hardware Configuration of the Interrupt Controller

This module is made up of the following:

• ICR register

• Interrupt criteria circuit

• Generator of the interrupt level and interrupt number (vector)

• HOLD request cancel request generator

Main Functions of the Interrupt Controller

The interrupt controller mainly provides the following functions:

• Detection of NMI requests/ interrupt requests

• Priority determination (by level and number)

• Transmission of the interrupt level of a request source as a result of priority determination (toCPU)

• Transmission of the interrupt No. of a request source as a result of priority determination (toCPU)

• Return instruction from the stop mode by NMI/an interrupt

• Hold request cancel request generation to the bus master

Register List of the Interrupt Controller

Figure 11.1-1 shows a register list of the interrupt controller.

283


Figure 11.1-1 Register List of the Interrupt Controller (1/2)

bit7 6 5 4 3 2 1 0

Address:00000400H ICR4 ICR3 ICR2 ICR1 ICR0










Address:0000040AH ICR4 ICR3 ICR2 ICR1 ICR0

Address:0000040BH ICR4 ICR3 ICR2 ICR1 ICR0

Address:0000040CH ICR4 ICR3 ICR2 ICR1 ICR0

Address:0000040DH ICR4 ICR3 ICR2 ICR1 ICR0

Address:0000040EH ICR4 ICR3 ICR2 ICR1 ICR0

Address:0000040FH ICR4 ICR3 ICR2 ICR1 ICR0











Address:0000041AH ICR4 ICR3 ICR2 ICR1 ICR0

Address:0000041BH ICR4 ICR3 ICR2 ICR1 ICR0

Address:0000041CH ICR4 ICR3 ICR2 ICR1 ICR0

Address:0000041DH ICR4 ICR3 ICR2 ICR1 ICR0

Address:0000041EH ICR4 ICR3 ICR2 ICR1 ICR0


R R/W R/W R/W R/W

I C R 0 0

I C R 0 1

I C R 0 2

I C R 0 3

I C R 0 4

I C R 0 5

I C R 0 6

I C R 0 7

I C R 0 8

I C R 0 9

I C R 1 0

I C R 1 1

I C R 1 2

I C R 1 3

I C R 1 4

I C R 1 5

I C R 1 6

I C R 1 7

I C R 1 8

I C R 1 9

I C R 2 0

I C R 2 1

I C R 2 2

I C R 2 3

I C R 2 4

I C R 2 5

I C R 2 6

I C R 2 7

I C R 2 8

I C R 2 9

I C R 3 0

I C R 3 1

284


Figure 11.1-2 Register List of the Interrupt Controller (2/2)

bit7 6 5 4 3 2 1 0

Address:00000420H

Address:00000421H

Address:00000422H

Address:00000423H

Address:00000424H

Address:00000425H

Address:00000426H

Address:00000427H

Address:00000428H

Address:00000429H

Address:0000042AH

Address:0000042BH

Address:0000042CH

Address:0000042DH

Address:0000042EH


R R/W R/W R/W R/W

Address:00000431H LVL4 LVL3 LVL2 LVL1 LVL0

R R/W R/W R/W R/W

I C R 3 2

I C R 3 3

I C R 3 4

I C R 3 5

I C R 3 6

I C R 3 7

I C R 3 8

I C R 3 9

I C R 4 0

I C R 4 1

I C R 4 2

I C R 4 3

I C R 4 4

I C R 4 5

I C R 4 6

I C R 4 7

HRCL

285



Figure 11.2-1 shows a block diagram of the interrupt controller.

Block Diagram of the Interrupt Controller

Figure 11.2-1 Block Diagram of the Interrupt Controller

INTO

OR5

NMI / LEVEL4 to 0

4HLDCAN

ICR00RI00 6

/ VCT5 to 0

ICR47RI47

(DLYIRQ) DLYI*1

*2

*3

IM

R-BUS

Prior i ty determinat ion

NMI processing

LEVEL determinat ion

VECTOR determinat ion

LE

VE

L a

nd

VE

CT

OR

g

en

era

tio

n

HLDREQ cancel

request

*1: DLYI means the delayed interrupt sect ion (For detai ls ,see the chapter of the delayed interrupt module).

*2: INT0 is the wakeup signal to the c lock control ler in s leep or stop mode.

*3: HLDCAN is the bus request s ignal to a bus master other than CPU.

286



One interrupt control register is available for each interrupt input to set the interrupt level of the corresponding interrupt request.

Configuration of the Interrupt Control Register (ICR)

The register configuration of the interrupt control register (ICR) is as follows:

Bit Function of the Interrupt Control Register (ICR)

[bit4 to 0] ICR4 to 0

Interrupt level bits to specify the interrupt level of the corresponding interrupt request.

If the interrupt level set to this register is equal to or higher than the level mask value set onthe ILM register of CPU, the interrupt request is masked by the CPU side.

These bits are initialized to 11111B by a reset.

Table 11.3-1 lists the correspondence between the interrupt level bits that can be set and theinterrupt level.

bit7 6 5 4 3 2 1 0

ICR4 ICR3 ICR2 ICR1 ICR0 ---11111

R R/W R/W R/W R/W

(Ini t ia l value)

287


ICR4 is fixed to "1" and "0" cannot be written into it.

Table 11.3-1 Correspondence Between the Interrupt Level Bits and the Interrupt Level

ICR4 ICR3 ICR2 ICR1 ICR0 Interrupt level

0 0 0 0 0 0System reserved

0 1 1 1 0 14

0 1 1 1 1 15 NMI

1 0 0 0 0 16 Highest level that can be set

1 0 0 0 1 17(High)

(Low)

1 0 0 1 0 18

1 0 0 1 1 19

1 0 1 0 0 20

1 0 1 0 1 21

1 0 1 1 0 22

1 0 1 1 1 23

1 1 0 0 0 24

1 1 0 0 1 25

1 1 0 1 0 26

1 1 0 1 1 27

1 1 1 0 0 28

1 1 1 0 1 29

1 1 1 1 0 30

1 1 1 1 1 31 Interrupt prohibited

288


11.4 Hold Request Cancel Request/Level Setting Register (HRCL)

This is a register to set the level when a hold request cancel request occurs.

Configuration of the Hold Request Cancel Request/Level Setting Register (HRCL)

The register configuration of the hold request cancel request/level setting register (HRCL) is asfollows:

Bit Function of the Hold Request Cancel Request/Level Setting Register (HRCL)

[bit4 to 0] LVL4 to 0

The interrupt level to issue a hold request cancel request to the bus master is set.

If an interrupt request with an interrupt level higher than that set to this register occurs, ahold request cancel request is issued to the bus master.

LVL4 is fixed to "1" and "0" cannot be written into it.

bit7 6 5 4 3 2 1 0

00000431H LVL4 LVL3 LVL2 LVL1 LVL0 ---11111

R R/W R/W R/W R/W

Address ( In i t ia l value)

289



In this module, an interrupt source with the highest priority is selected from those interrupt sources occurring simultaneously, and the interrupt level and interrupt source No. are then output to CPU.NMI has the highest priority among the interrupt sources handled by this module.

Priority Determination

The criteria for determining priorities of the interrupt sources are as follows:

1. NMI

2. Factors that satisfy the following conditions

• The interrupt level value is a value other than 31 (31 is intended for interrupt prohibition)

• The request sources with the smallest interrupt level value

• The request source with the smallest interrupt No. from them.

Table 11.5-1 lists the relations of the interrupt sources, interrupt No. and interrupt levels.

290


Table 11.5-1 Relations of the Interrupt Sources, Interrupt No. and Interrupt Levels

Interrupt source Interrupt No. Interrupt level

Offset TBR default address

Decimal Hexadecimal

NMI request 15 0F 15(FH) fixed 3C0H 000FFFC0H

External interrupt 0 16 10 ICR00 3BCH 000FFFBCH

External interrupt 1 17 11 ICR01 3B8H 000FFFB8H



UART 0 receipt complete 20 14 ICR04 3ACH 000FFFACH

UART 1 receipt complete 21 15 ICR05 3A8H 000FFFA8H

UART 2 receipt complete 22 16 ICR06 3A4H 000FFFA4H

UART 0 transmit complete 23 17 ICR07 3A0H 000FFFA0H

UART 1 transmit complete 24 18 ICR08 39CH 000FFF9CH

UART 2 transmit complete 25 19 ICR09 398H 000FFF98H

DMAC 0 (Termination, error) 26 1A ICR10 394H 000FFF94H

DMAC 1 (Termination, error) 27 1B ICR11 390H 000FFF90H

DMAC 2 (Termination, error) 28 1C ICR12 38CH 000FFF8CH

DMAC 3 (Termination, error) 29 1D ICR13 388H 000FFF88H

DMAC 4 (Termination, error) 30 1E ICR14 384H 000FFF84H

DMAC 5 (Termination, error) 31 1F ICR15 380H 000FFF80H

DMAC 6 (Termination, error) 32 20 ICR16 37CH 000FFF7CH

DMAC 7 (Termination, error) 33 21 ICR17 378H 000FFF78H

A/D 34 22 ICR18 374H 000FFF74H

Reload timer 0 35 23 ICR19 370H 000FFF70H

Reload timer 1 36 24 ICR20 36CH 000FFF6CH


PWM 0 38 26 ICR22 364H 000FFF64H

PWM 1 39 27 ICR23 360H 000FFF60H

PWM 2 40 28 ICR24 35CH 000FFF5CH

PWM 3 41 29 ICR25 358H 000FFF58H

291


Table 11.5-2 Relations of the Interrupt Sources, Interrupt No. and Interrupt Levels

Interrupt source Interrupt No. Interrupt level

Offset TBR default address

Decimal Hexadecimal

U-TIMER 0 42 2A ICR26 354H 000FFF54H

U-TIMER 1 43 2B ICR27 350H 000FFF50H

U-TIMER 2 44 2C ICR28 34CH 000FFF4CH

System reserved 45 2D ICR29 348H 000FFF48H

System reserved 46 2E ICR30 344H 000FFF44H

System reserved 47 2F ICR31 340H 000FFF40H

System reserved 48 30 ICR32 33CH 000FFF3CH

System reserved 49 31 ICR33 338H 000FFF38H









System reserved 58 3A ICR42 314H 000FFF14H

System reserved 59 3B ICR43 310H 000FFF10H

System reserved 60 3C ICR44 30CH 000FFF0CH

System reserved 61 3D ICR45 308H 000FFF08H

System reserved 62 3E ICR46 304H 000FFF04H

Delayed interrupt source bit 63 3F ICR47 300H 000FFF00H

292


NMI (Non Maskable Interrupt)

Since NMI has the highest priority among the interrupt sources handled by this module, NMI isalways selected if other interrupt sources occur simultaneously.

If NMI occurs, the following information is transferred to CPU

• Interrupt level: 15 (01111B)

• Interrupt No.: 15 (00111B)

NMI detection

NMI is set and detected in the external interrupt/NMI module. In this module, only thegeneration of the interrupt levels/interrupt No. is performed based on NMI requests.

Release of Interrupt Sources

There is no restriction between an instruction to release an interrupt source and the RETIinstruction in an interrupt routine. For details, see "Chapter 3 CPU and Controllers".

293



The function to return from the stop mode triggered by the generation of an interrupt request is implemented by this module.

Returning from the Standby Mode (Stop/Sleep)

If an interrupt request, including NMI from the peripheral functions, is generated, a returnrequest from the stop mode is generated for the clock controller.

The priority determination section restarts the operation when the clock is supplied afterreturning from the stop state, and CPU executes instructions until a result is output from thepriority determination section.

The return operation from the sleep state is the same.

Registers in this module can be accessed in the sleep state using DMAC.

<Precautions>

• The return from the stop mode is also performed when an NMI request occurs.The returnfrom the stop mode is also performed when an NMI request occurs.

• If an interrupt source should not be a return source from the stop or sleep mode, prohibit theinterrupt request output using the corresponding control register of the peripheral functions.Since the request signal to return from the standby mode is simply a logical sum output of allinterrupt requests, the contents of the interrupt level set to ICR are not added.

294


11.7 Hold Request Cancel Request

To perform processing of interrupts with high priorities while CPU is on hold, it is necessary to ask the hold request generator to cancel requests. The interrupt level standard to be for this cancellation request generation is set to the HRCL register.

Generation Standard for the Hold Request Cancel Requests

If an interrupt source with a level higher than the interrupt level set to the HRCL register, a holdrequest cancel request is generated.

This cancel request is valid and as a result, no DMA transfer occurs provided the interruptsource causing the cancel request generation is not cleared. The corresponding interruptrequest must be cleared.

Levels that Can Be Set for the Hold Request Cancel Requests

The values that can be set to the HRCL register are, like those of ICR, 10000B to 11111B.

If 11111B is set, a cancel request is generated for all interrupt levels. If 10000B is set, a cancelrequest is generated for NMI only.

Table 11.7-1 lists the settings of the interrupt levels that cause a hold request cancel request.

After a reset, the DMA transfer is inhibited for all interrupt levels.

That is, since no DMA transfer is performed when an interrupt occurs, set a required value tothe HRCL register.

Interrupt level on the HRCL register @ Interrupt level after priority determination Cancel request generation

Interrupt level on the HRCL register @ Interrupt level after priority determination No cancel request

Table 11.7-1 Settings of the Interrupt Levels that Generate a Hold Request Cancel Request

HRCL register

Interrupt levels that generate a hold request cancel request

16 NMI only

17 NMI, interrupt level 16

18 NMI, interrupt level 16 to 17

31 NMI, interrupt level 16 to 30 [initial value]

295



To enable CPU to perform processing with high priorities during DMA transfer, it is necessary to ask DMA to cancel a hold request to release the hold state, implemented as follows:

Control Register

Hold request cancel request/level setting register (HRCL): this module

If an interrupt with a level higher than the interrupt level set to this register occurs, a holdrequest cancel request is issued to DMA. The standard level for this request is set here.

Interrupt control register (ICR): this module

Set a level higher than the level of the HRCL register to ICR corresponding to the interruptsource to be used.

DMA request inhibit register (PDRR): clock controller

This register is used to temporarily inhibit the hold requests from DMA. By clearing interruptsources, a return to the hold state is prevented. A hold request from DMA is transferred to CPUonly if the value of this register is 0000B. This register is normally used by incrementing it at thestart of an interrupt routine and decrementing it at the end of a routine.

296


Hardware Configuration

The flow of each signal is as follows:

Figure 11.8-1 Hardware Configuration to Use the Hold Request Cancel Request Function

Sequence of a Hold Request Cancel Request

Example of the interrupt routine

Figure 11.8-2 Timing Example of a Hold Request Cancel Request Sequence (Interrupt Level: HRCL > a)

When an interrupt request occurs, the interrupt level changes. If this level is higher than thelevel set to the HRCL register, HRCR is activated for DMA. This triggers DMA to cancel holdrequests and CPU to return from the hold state to perform interrupt processing. In the interruptroutine, PDRR is incremented ((1)) and the interrupt sources are then cleared ((2)). Thischanges the interrupt level and inactivates HRCR, enabling DMA to issue a hold request again.However, because PDRR is not 0, this hold request is interrupted. Only when PDRR isdecremented ((3)) is the hold request transferred to CPU, thereby enabling the DMA transferagain.

IRQ (ICR) DMA CPU

(HRCL) HRCR DHRQ (PDRR) HRQ

This module Clock controller

DHRQ: DMA hold requestHRQ: hold requestIRQ: interrupt requestHRCR: hold request cancel request

RUN

CPU

DHRQ

HRQ

HACK

IRQ

LEVEL a RETI

HRCR

PDRR 0000 0001 0000

Bus hold Interrupt processing Bus hold (DMA transfer)

Interrupt routine example

PDRR increment

Interrupt source clear

PDRR decrement

297


Example of the multi-interrupt routine

Figure 11.8-3 Timing Example of a Hold Request Cancel Request Sequence (Interrupt Level: HRCL > a > b)

Example of the interrupt routine

The above example shows that an interrupt with a higher priority occurred when the interruptroutine I was being executed. By also incrementing PDRR at the start of each interrupt routineand decrementing it at the end of each interrupt routine, the accidental generation of a holdrequest can be prevented.

<Precautions>

• Increment/decrement PDRR at the start and end of an interrupt routine to be processedduring DMA transfer (When CPU is on hold). Or the DMA transfer is performed again duringexecution of the interrupt routine.

• Conversely, incrementing/decrementing PDRR in a normal interrupt routine will prevent aDMA transfer during execution of an interrupt routine, thereby leading to performancedegradation.

• Note the relations between the HRCL register and the interrupt level set to ICR.

RUN

CPU

DHRQ

HRQ

HACK

IRQ1

IRQ2

LEVEL a b a

HRCR

PDRR 0000 0001 0002 0001 0000

Bus hold Bus holdInterrupt Interrupt processing Interrupt processing

PDRR incrementInterrupt source clear

PDRR decrement

RETI

298


299

CHAPTER 12 A/D CONVERTER (Successive approximation type)

This chapter explains the general outlines of the A/D converter, configuration/functions of registers, and operations of the A/D converter.

12.1 Overview of the A/D Converter (Successive Approximation Type)

12.2 Control Status Register (ADCS)

12.3 Data Register (ADCR)

12.4 Operations of the A/D Converter

12.5 Conversion Data Protection Function

12.6 Precautions when Using the A/D Converter

300



The A/D converter is a module for converting the analog input voltage into digital values.

Features of the A/D Converter

• Minimal conversion time: 5.6 µs/ch (when the system clock is 25 MHz)

• The sample & hold circuit is contained.

• Resolution: 10 bits

• The analog input can be selected from four channels using a program:

• Single conversion mode: One channel can be selected for conversion.

• Scan conversion mode: Multiple continuous channels are converted. Up to four channelscan be converted.

• Continuous conversion mode: The specified channel is converted repeatedly.

• Stop conversion mode: Conversion stops temporarily after converting one channel to waitfor the next activation (The conversion start can be synchronized).

• The DMA transfer can be activated by an interrupt.

• The activation source can be selected from software, an external trigger (falling edge), and areload timer (rising timer).

301


Register List of the A/D Converter

Figure 12.1-1 shows a register list of the A/D converter.

Figure 12.1-1 Register List of the A/D Converter

15 0

ADCS

ADCR

16bit

bi t 15 14 13 12 11 10 9 8

BUSY INT INTE PAUS STS1 STS0 STRT

bit 7 6 5 4 3 2 1 0

MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

bi t 15 14 13 12 11 10 9 8

bit 7 6 5 4 3 2 1 0

7 6 5 4 3 2 1 0

9 8

Control status register (ADCS)

Data register (ADCR)

302


Block Diagram of the A/D Converter

Figure 12.1-2 shows a block diagram of the A/D converter.

Figure 12.1-2 Block Diagram of the A/D Converter.

AVCCAVR

AVSS

MPX

AN0AN1AN2AN3

ADCR

ADCSATGX

R|

BUS

Inp

ut

cir

cu

it

In ternal vol tage generator

Sample & hold c i rcui t

Comparator

Successive approximat ion

registerD

ec

od

er Data register

Tr igger act ivat ion

A/D control register

TIMO ( internal ly connected) [ re load t imer channel 2]

Timer act ivat ion Operat ing c lock

(Per ipheral system clock)Prescaler

303



The control status register (ADCS) performs the A/D converter control and status display.

Configuration of the Control Status Register (ADCS)

The register configuration of the control status register (ADCS) is as follows:

<Precautions>

Do not rewrite ADCS while the A/D converter is working.

Access by the read/modify/write set instructions is prohibited.

Bit Function of the Control Status Register (ADCS)

[bit15] BUSY (BUSY flag and stop)

Read: Bit to indicate the A/D converter operation. This bit is set when the A/D converter is activated and is cleared when it is terminated.

Write: If "0" is written into this bit when the A/D converter is working, the converter is forced to stop its operation. This operation is used for the forced stop in continuous/stop mode.

It is not possible to write "1" into the bit to indicate the operation. "1" is read by the RMW setinstructions.

In single mode, this bit is cleared when the A/D converter is terminated.

In continuous/stop mode, on the other hand, this bit is not cleared until the A/D converter isstopped by writing "0".

This bit is initialized to "0" by a reset.

Do not perform the forced stop and software activation simultaneously (BUSY=0, STRT=1).

[bit14] INT (INTerrupt)

Data indication bit. This bit is set when conversion data is written into ADCR.

If this bit is set when INTE (bit13) is "1", an interrupt request is generated. If the activation ofDMA transfer is selected, DMA is activated.

Writing "1" into this bit has no significance.

This bit is cleared by writing "0" or the clear signal from DMAC.

bit 15 14 13 12 11 10 9 8ADCSAddress:00003AH BUSY INT INTE PAUS STS1 STS0 STRT

0 0 0 0 0 0 0 0R/W R/W R/W R/W R/W R/W W R/W

bit 7 6 5 4 3 2 1 0

MD1 MD0 ANS2 ANS1 ANS0 ANE2 ANE1 ANE0

0 0 0 0 0 0 0 0R/W R/W R/W R/W R/W R/W R/W R/W

Ini t ia l value

Ini t ia l value

Bit at t r ibute

Bit at t r ibute

304


<Precautions>

Write "0" into this bit to clear it while the A/D converter is stopped.


"1" is read by the read operation of the read/modify/write set instructions.

[bit13] INTE (INTerrupt Enable)

This bit specifies whether to allow interrupts when conversion is completed.

0: Interrupt prohibited

1: Interrupt allowed

To activate the DMA transfer by an interrupt request, set this bit.


[bit12] PAUS (A/D converter PAUSe)

This bit is set when the A/D conversion operation is stopped temporarily.

Since only one register is available for storing the A/D conversion results, the previous datawill be corrupted if conversion results are not transferred by DMA when data is convertedcontinuously.

To protect data from such corruption, the next conversion data will not be stored unless thedata register contents are transferred by DMA. In the meantime, the A/D conversionoperation is stopped.

The A/D converter restarts its operation when the transfer of data register contents by DMAis completed.

This bit is valid only when DMA is used.

For details, see Section 12.5, "Conversion Data Protection Function."


[bit11, 10] STS1, STS0 (STart Source select)

These bits are initialized to "00" by a reset.

The A/D activation source is selected by setting these bits.

In a mode in which multiple types of activation are allowed, the A/D converter is activatedwith the activation source coming first.

Since the activation source changes when these bits are rewritten, care must be taken ifrewritten during A/D operation.

Table 12.2-1 Selection of the A/D Activation Source

STS1 STS0 Function

0 0 Software activation

0 1 Activation by an external pin trigger and software activation

1 0 Activation by a timer and software activation

1 1 Activation by an external pin trigger/timer and software activation

305


<Precautions>

An external pin edge detects a falling edge.

If the external trigger activation is set by rewriting these bits when the external trigger input levelis "L", the A/D converter may be activated.

If activation by a timer is selected, channel 2 of the reload timer is selected. If activation by atimer is set by rewriting these bits when the output level of the reload timer is "H", the A/Dconverter may be activated.

[bit9] STRT (STaRT)

The A/D converter is activated by writing "1" into this bit.

To restart the A/D converter, write "1" again.

In stop mode, the A/D converter cannot be restarted from an operational viewpoint.


Do not perform a forced stop and software activation simultaneously (BUSY=0, STRT=1).

"0" is read by the read/modify/write set instructions.

[bit8]

Bit for testing. Write "0" during a write operation.

[bit7, 6] MD1, MD0 (A/D converter MoDe set)

Select the operating mode.


<Precautions>

If the A/D converter is activated in continuous mode or stop mode, the conversion operation willcontinue until the converter is stopped by the BUSY bit.

The A/D converter is stopped by writing "0" into the BUSY bit.

The impossibility of a restart in single/continuous/stop mode applies to the activation of all types(activation by a timer, an external trigger, and software).

Table 12.2-2 Selection of the A/D Converter Operating Mode

MD1 MD0 Operating mode

0 0 Single mode, restarting during operations is always possible.

0 1 Single mode, restarting during operations is not possible.

1 0 Continuous mode, restarting during operations is not possible.

1 1 Stop mode, restarting during operations is not possible.

Single mode: Performs A/D conversion from the setting channels of ANS2 to ANS0 to those of ANE2 to ANE0 once before stopping.

Continuous mode: Repeats A/D conversion from the setting channels of ANS2 to ANS0 to those of ANE2 to ANE0.

Stop mode: Performs A/D conversion of one channel from the setting channels of ANS2 to ANS0 to those of ANE2 to ANE0 before each temporary stop.

306


[bit5, 4, 3] ANS2, ANS1, ANS0 (ANalog Start channel set)

The start channel of A/D conversion is set by these bits.

When the A/D converter is activated, the A/D conversion starts with the channel selected bythese bits.

The conversion channel is read during A/D conversion from these bits in read operation.

The previous channel is read while stopped in stop mode.


[bit2, 1, 0] ANE2, ANE1, ANE0 (ANalog End channel set)

The end channel of A/D conversion is set by these bits.

If the same channel as that of ANS2 to ANS0 is set, one channel conversion is adopted(single conversion).

If the continuous mode or stop mode is set, the start channel set by ANS2 to ANS0 isreturned after the conversion of the channel set by these bits is completed.

Set the channels in such a way that ANS is equal to or less than ANE.

Table 12.2-3 Settings of the A/D Conversion Start Channels

ANS2 ANS1 ANS0 Start channel

0 0 0 AN0

0 0 1 AN1

0 1 0 AN2

0 1 1 AN3

1 0 0 Setting prohibited




Table 12.2-4 Settings of the A/D Cconversion End Channels

ANE2 ANE1 ANE0 Start channel

0 0 0 AN0

0 0 1 AN1

0 1 0 AN2

0 1 1 AN3





307


[Example]

Operation in single mode with the channel settings: ANS=1ch and ANE=3ch

Conversion channel: 1ch --> 2ch --> 3ch


308


12.3 Data Register (ADCR)

The data register (ADCR) is a conversion storage register in which a digital value is stored as a result of conversion.

Configuration of the Data Register (ADCR)

The register configuration of the data register (ADCR) is as follows:

The value of this register is updated each time one conversion is completed. Normally, the finalconversion value is stored.

This register is undefined for a reset.

"0" is read from the higher 15 to 10 bits in read operation.

The conversion data protection function is available. For details, see "12.5 Conversion DataProtection Function".

bit 15 14 13 12 11 10 9 8ADCRAddress:000038H

0 0 0 0 0 0 X XR R R R R R R R

bit 7 6 5 4 3 2 1 0

X X X X X X X XR R R R R R R R

9 8

7 6 5 4 3 2 1 0

Bit at t r ibute

Bit at t r ibute

Ini t ia l value

Ini t ia l value

309



The A/D converter operates in successive approximation mode and has the resolution of 10 bits.Since this A/D converter has only one register (16 bits) for conversion result storage, the conversion data register (ADCR) is updated when one conversion is completed. When conversion is performed continuously, the DMA transfer can be used.

Operating Mode of the A/D Converter

A single mode, continuous mode, and stop mode are available for the A/D converter.

Single mode

In single mode, analog input set by the ANS bit and ANE bit of ADCS is converted in order.When the conversion of the end channel set by the ANE bit is completed, the A/D converterstops its operation.

If the start channel and the end channel are the same (ANS=ANE), one channel conversion isadopted.

Example:

If ANS=000 and ANE=011,

Start --> AN0 --> AN1 --> AN2 --> AN3 --> end


Start --> AN2 --> end

Continuous mode

In continuous mode, analog input set by the ANS bit and ANE bit of ADCS is converted in order.When the conversion of the end channel set by the ANE bit is completed, the analog input ofANS is returned to continue the A/D conversion.

If the start channel and the end channel are the same (ANS=ANE), one channel conversion iscontinued.

Example:


Start --> AN0 --> AN1 --> AN2 --> AN3 --> AN0 ... --> repeat


Start --> AN2 --> AN2 --> AN2 ... --> repeat

If conversion in continuous mode starts, the conversion is repeated until "0" is written into theBUSY bit. When "0" is written into the BUSY bit, the conversion is forced to stop.

Care must be taken when applying the forced operation stop because the conversion of databeing performed is stopped during the process.

If the forced operation stop is applied, the previous data whose conversion has been completedis stored in the conversion register.

310


Stop mode

In stop mode, analog input set by the ANS bit and ANE bit of ADCS is converted in order.However, the conversion operation stops temporarily each time one channel is converted. Torelease the temporary stop, the A/D converter must be activated again.

When the conversion of the end channel set by the ANE bit is completed, the analog input ofANS is returned to continue the A/D conversion.

If the start channel and the end channel are the same (ANS=ANE), one channel conversion isadopted.

Example:


Start --> AN0 --> stop --> start --> AN1 --> stop --> start --> AN2 --> stop --> start -->AN3 --> stop --> start --> AN0 ... --> repeat


Start --> AN2 --> stop --> start --> AN2 --> stop --> start --> AN2 ... --> repeat

The activation sources at this time are only those set by the STS1, 0 bits.

By using this mode, the conversion start can be synchronized.

311



The A/D converter of MB91101 has the conversion data protection function and provides the features of continuous conversion and allocation of multiple pieces of data using DMAC.

Conversion Data Protection Function

Since only one conversion data register is available, the previous data is lost by storing theconversion data after one conversion operation is completed when the A/D conversion isperformed continuously. To protect from such losses, this A/D converter has the function oftemporarily stopping after conversion without storing conversion data in the register if theprevious data has not been transferred to memory using DMAC.

The temporary stop is released after the previous data is transferred to memory using the DMAtransfer.

If the previous data has been transferred, the A/D conversion continues without stoppingtemporarily.

<Precautions>

This function is related to the INT and INTE bits of ADCS.

The data protection function is designed so that it operates only if interrupts are allowed(INTE=1).

If the interrupts are prohibited (INTE=0), this function does not work, and if the A/D conversionis performed continuously, conversion data is stored in the register successively and old datawill be lost.

If the interrupts are allowed (INTE=0) and the DMA transfer is not used, the INT bit will not becleared, the data protection function will work, and conversion will be stopped temporarily by theA/D converter. In this case, the stop state can be released by clearing the INT bit in an interruptsequence.

If the interrupts are prohibited when DMA is working and the A/D is stopped temporarily, the A/Dconverter may operate, changing the contents of the conversion data register before the datatransfer.

If the A/D converter is restarted when it is temporarily stopped, standby data is corrupted.

Figure 12.5-1 shows the flow of the data protection function when the DMA transfer is used.

312


Figure 12.5-1 Flow of the Data Protection Function When the DMA Transfer is Used

NO

YESYES NO

*

DMAC sett ing The f low when the A/D converter operat ion is stopped is omit ted.

Cont inuous A/D conversion act ivat ion

End of the 1st conversion

Storage in the data register

End of the 2nd conversion DMAC act ivat ion

Transfer end Temporary A/D converter stop

Storage in the data register

End of the 3rd conversion

Cont inued

End of a l l conversion

DMAC act ivat ion/ t ransfer

End

DMAC end interrupt rout ine

A/D converter stop

Transfer end

DMAC act ivat ion

*: I f the A/D converter is restarted when i t is temporar i ly stopped, standby conversion data is corrupted.

313



This section shows precautions when using the A/D converter.

Precautions When Using the A/D Converter

If the A/D converter is activated by an external trigger or internal timer

To activate the A/D converter by an external trigger or internal timer, the A/D activation bitsSTS1 and STS0 of the ADCS register are set. At this time, switch the input values of theexternal trigger and internal timer to the inactive side. Maintaining the values in the active sidemay lead to a malfunction.

When setting the STS1 and STS0 bits, set ATGX="1" input and reload timer (channel 2)="0"output.

Other Precautions for the A/D Converter

If the external impedance becomes higher than the specified value, analog input values cannotbe sampled within the defined sampling time, leading to incorrect conversion results.

314


315

CHAPTER 13 UART

This chapter explains the general outlines of UART, configuration/functions of registers, and operations of UART.

13.1 Overview of UART

13.2 Serial Mode Register (SMR)

13.3 Serial Control Register (SCR)

13.4 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

13.5 Serial Status Register (SSR)

13.6 Operations of UART

13.7 Asynchronous (Start-stop transmission) Mode

13.8 CLK Synchronous Mode

13.9 Interrupt Occurrence of UART and Flag Set Timing

13.10 Precautions for Using UART and an Application Example

13.11 Example of Settings of the Baud Rate and U-TIMER Reload Value

316

CHAPTER 13 UART


UART is a serial I/O port for asynchronous (start-stop transmission) communication or CLK synchronous communication.MB91101 contains three channels of UART.

Features of UART

• Full duplex double buffer

• Asynchronous (start-stop transmission) and CLK synchronous communications are possible.

• Multi-processor mode support

• Complete programmable baud rate

• Any baud rate can be set by the internal timer (See "Chapter 6 U-TIMER").

• The baud rate can freely be set by an external clock.

• Error detection function (parity, framing, and overrun)

• The NRZ code is used as the transfer signal.

• The DMA transfer can be activated by an interrupt.

Register List of UART

Figure 13-1-1 shows a register list of UART.

Figure 13.1-1 Register List of UART

15 8 7 0

SCR SMR (R/W)

SSR SIDR(R)/SODR(W) (R/W)

8 bi t 8 bi t

7 6 5 4 3 2 1 0

D7 D6 D5 D4 D3 D2 D1 D0(SIDR / SODR)

7 6 5 4 3 2 1 0

PE ORE FRE RDRF TDRE RIE TIE (SSR)

7 6 5 4 3 2 1 0

MD1 MD0 CS0 SCKE SOE (SMR)

7 6 5 4 3 2 1 0

PEN P SBL CL A/D REC RXE TXE (SCR)

Serial input register/ ser ia l output register

Ser ia l status register

Ser ia l mode register

Ser ia l control register

317


Block Diagram of UART

Figure 13-1-2 shows a block diagram of UART.

Figure 13.1-2 Block Diagram of UART

SC

SI

SO

SIDR SODR

MD1 PEN PEMD0 P ORE

SBL FRESMR SCR CL SSR RDRFCS0 A/D TDRE

RECSCKE RXE RIESOE TXE TIE

R - BUS

Control s ignalReceive interrupt

( to CPU)

From U-TIMER

External c lock

Clock

select ing

c i rcui t

Receive c lock

Send clock

SC (clock)

Send interrupt( to CPU)

(received data)

Receive control c i rcui t

Start b i t detect ing c i rcui t

Receive bi t counter

Receive par i ty counter

Send control c i rcui t

Send start c i rcui t

Send bi t counter

Send par i ty counter

(send data)

Receiptdeterminat ion

circui tReceive shi f ter

Receipt end

Send shi f ter

Transmission start

Receive error generat ion s ignal for DMA (to DMAC)

register register register

Control s ignal

318

CHAPTER 13 UART


The serial mode register (SMR) specifies the operating mode of UART.The operating mode must be set when operations are stopped. Do not write to this register during operation.

Configuration of the Serial Mode Register (SMR)

The register configuration of the serial mode register (SMR) is as follows:

Bit Function of the Serial Mode Register (SMR)

[bit7, 6] MD1, MD0 (MoDe select)

Select the operating mode of UART.

<Precautions>

In CLK asynchronous mode (multi-processor) of mode 1, several slave CPUs are connected toone host CPU. In this resource, the data format of received data cannot be identified.Therefore, only the master in the multi-processor is supported.

Since the parity check function cannot be used, set "0" to PEN of the SCR register.

[bit5, 4] (reserved)

Write always "1".

[bit3] CS0 (Clock Select)

Select the operating clock of UART.

0: Built-in timer (U-TIMER) [initial value]1: External clock

[bit2] (reserved)

Write always "0".

7 6 5 4 3 2 1 0SMR 00001FH

Address:000023H MD1 MD0 CS0 SCKE SOE 00--0-00B

000027H

R/W R/W W R/W R/W

Ini t ia l value

Table 13.2-1 Selection of the Operating Mode of UART

Mode MD1 MD0 Operating mode

0 0 0 Asynchronous (start-stop transmission) normal mode [initial value]

1 0 1 Asynchronous (start-stop transmission) multi-processor mode

2 1 0 CLK synchronous mode

– 1 1 Setting prohibited

319


[bit1] SCKE (SCLK Enable)

To conduct communication in CLK synchronous mode (mode 2), specify whether the SC pinshould be used as a clock input pin or clock output pin.

In CLK asynchronous mode or external clock mode, set "0" to this bit.

0: Functions as an input pin. [initial value]

1: Functions as an output pin.

<Precautions>

Before using the SC pin as a clock input pin, "1" must be set to the CS0 bit and an externalclock must be selected.

[bit0] SOE (Serial Output Enable)

Specifies whether the external pin (SO), which also serves as a general-purpose I/O port pin,is a serial output pin or an I/O port pin.

0: Functions as a general-purpose I/O port pin [initial value]

1: Functions as a serial data output pin (SO).

320

CHAPTER 13 UART

13.3 Serial Control Register (SSR)

The serial control register (SSR) controls the transfer protocol for serial communication.

Configuration of the Serial Control Register (SSR)

The register configuration of the serial control register (SSR) is as follows:

Bit Function of the Serial Control Register (SSR)

[bit7] PEN (Parity Enable)

Specifies whether to add the parity in serial communication to conduct data communication.

0: No parity [initial value]

1: Parity added

<Precautions>

Parity can be added in normal mode (mode 0) of the asynchronous (start-stop transmission)communication mode but cannot be added in multi-processor mode (mode 1) or CLKsynchronous communication mode (mode 2).

[bit6] P (Parity)

Specifies even/odd parity when data communication is performed with parity.

0: Even parity [initial value]

1: Odd parity

[bit5] SBL (Stop Bit Length)

Specifies the bit length of the stop bit that functions as the frame end mark whenasynchronous (start-stop transmission) communication is performed.

0: 1 stop bit [initial value]

1: 2 stop bits

[bit4] CL (Character Length)

Specifies the data length of one frame to be sent/received.

0: 7-bit data

1: 8-bit data

<Precautions>

Only the normal mode (mode 0) in the asynchronous (start-stop transmission) communicationcan handle 7-bit data. In multi-processor mode (mode 1) and CLK synchronous communication(mode 2), use 8-bit data.

7 6 5 4 3 2 1 0SCR 00001EH

Address:000022H PEN P SBL CL A/D REC RXE TXE 00000100B

000026H

R/W R/W R/W R/W R/W W R/W R/W

Ini t ia l value

321

13.3 Serial Control Register (SSR)

[bit3] A/D (Address/Data)

Specifies the data format of frames sent/received in multi-processor mode (mode 1) ofasynchronous (start-stop transmission) communication.

0: Data frame [initial value]

1: Address frame

[bit2] REC (Receive Error Clear)

By writing "0" into this bit, the error flag (PE, ORE, FRE) of the SSR register can be cleared.

Writing "1" into this bit is invalid and "1" is always read from this bit.

[bit1] RXE (Receiver Enable)

Controls the receive operation of UART.

0: Prohibit the receive operation. [initial value]

1: Allow the receive operation.

<Precaution:>

If the receive operation is prohibited when receiving (when data is input into the receive shiftregister), the receive operation stops when data receipt of the frame is completed and thereceived data is stored in the SIDR register of the received data buffer.

[bit0] TXE (Transmitter Enable)

Controls the send operation of UART.

0: Prohibit the send operation. [initial value]

1: Allow the send operation.

<Precautions>

If the send operation is prohibited when sending (when data is output from the send register),the send operation stops when there is no data in the SODR register of the send data buffer.

The send operation starts in synchronization with the internal serial clock after writing data intothe send data buffer (SODR4 to 0). The prohibition (TXE=0) of the send operation is invalid ifthe TDRE flag is "0".

322

CHAPTER 13 UART

13.4 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

The serial input data register (SIDR)/serial output data register (SODR) are the send/received data buffer registers.If the data length is 7 bits, bit7 (D7) becomes invalid data. Write data into the SODR register when TDRE of the SSR register is "1".

Configuration of the Serial Input Data Register (SIDR)/Serial Output Data Register (SODR)

The register configuration of the serial input data register (SIDR)/serial output data register(SODR) is as follows:

<Precautions>

The write operation into this address means writing into the SIDR register. The read operationof this address means reading from the SIDR register.

7 6 5 4 3 2 1 0SIDR 00001DH

Address: 000021H D7 D6 D5 D4 D3 D2 D1 D0000025H

R R R R R R R R

7 6 5 4 3 2 1 0SODR

D7 D6 D5 D4 D3 D2 D1 D0

W W W W W W W W

Init ia l value

Undef ined

Undef inedAddress: same as above

323



The serial status register (SSR) is made up of the flags indicating the operating state of UART.

Configuration of the Serial Status Register (SSR)

The register configuration of the serial status register (SSR) is as follows:

Bit Function of the Serial Status Register (SSR)

[bit7] PE (Parity Error)

Interrupt request flag set if a parity error occurs when receiving.

To clear the flag set once, write "0" into the REC bit (bit10) of the SCR register.

If this bit is set, data of SIDR becomes invalid.

0: No parity error [initial value]

1: Parity error occurred

[bit6] ORE (Over Run Error)

Interrupt request flag set if an over-run error occurs when receiving.

To clear the flag set once, write "0" into the REC bit of the SCR register.


0: No over-run error [initial value]

1: Over-run error occurred

[bit5] FRE (FRaming Error)

Interrupt request flag set if a framing error occurs when receiving.

To clear the flag set once, write "0" into the REC bit of the SCR register.


0: No framing error [initial value]

1: Framing error occurred

[bit4] RDRF (Receive Data Register Full)

Interrupt request flag indicating that received data is in the SIDR register.

This bit is set when received data is loaded into the SIDR register and is cleared when theSIDR register is read.

0: No received data [initial value]

1: Received data present

7 6 5 4 3 2 1 0SSR 00001CH

Address:000020H PE ORE FRE RDRF TDRE RIE TIE 00001-00B

000024H

R R R R R R/W R/W

Ini t ia l value

324

CHAPTER 13 UART

[bit3] TDRE (Transmitter Data Register Empty)

Interrupt request flag indicating that send data can be written into the SODR register.

This bit is cleared when send data is written into the SODR register. It is set again when thetransfer of written data starts after being loaded into the send shifter, thereby indicating thatthe next send data can now be written.

0: Prohibit the write operation of send data [initial value]

1: Allow the write operation of send data

[bit2] (reserved)

[bit1] RIE (Receiver Interrupt Enable)

This bit controls the receive interrupts.

0: Prohibit interrupts [initial value]

1: Allow interrupts

<Precautions>

In addition to the errors of PE, ORE, and FRE, normal receipt by RDRF is available as a receiveinterrupt source.

[bit0] TIE (Transmitter Interrupt Enable)

This bit controls the send interrupts.

0: Prohibit interrupts [initial value]

1: Allow interrupts

<Precautions>

A send request by TDRE is available as a send interrupt source.

325



UART has the following three operating modes and these modes can be switched by setting values to the SMR register and SCR register.• Asynchronous (start-stop transmission) normal mode• Asynchronous (start-stop transmission) multi-processor mode• CLK synchronous mode

Operating Mode of UART

Table 13-6-1 lists the operating modes of UART.

The stop bit length in asynchronous (start-stop transmission) mode can be specified only for thesend operation. The stop bit length for the receive operation is always 1 bit. Do not set anymodes other than those listed below because UART does not work.

<Precautions> (The following precautions apply to MB91101 but do not apply toMB91101A)

Do not write into SODR at the same time when sending terminates (the RDRF bit becomes "1")in CLK synchronous mode. Use the receipt detection flag RDRF to detect write timing intoSODR. Since transmission and reception occur at the same time in synchronous mode, the endof transmission can be detected by the RDRF flag.

When the CLK synchronous mode is used, use the RDRF polling or a receive interrupt fortransmission.

Selection of the Clock for UART

Internal timer

If U-TIMER is selected after setting "0" to CS0, the baud rate is determined by the reload valueset to U-TIMER. The formula for calculating the baud rate at this time is as follows:

• Asynchronous (start-stop transmission): φ / (16 × β)

• CLK synchronous: φ / β

φ: Frequency of the peripheral system machine clock

β: Frequency set by U-TIMER (2n+2 or 2n+3, n is the reload value)

The baud rate in asynchronous mode (start-stop transmission) can be used for transfer in therange of -1% to +1% of the specified baud rate.

Table 13.6-1 Operating Modes of UART

Mode Parity Data length Operating mode Stop bit length

0 Yes/No 7 Asynchronous (start-stop transmission) normal mode

1 bit or 2 bits

Yes/No 8

1 No 8 + 1 Asynchronous (start-stop transmission) multi-processor mode

2 No 8 CLK synchronous mode No

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CHAPTER 13 UART

External clock

The baud rate when an external clock is selected after setting "1" to CS0 is given as follows withthe frequency of the external clock equal to f:

• Asynchronous (start-stop transmission): f/16

• CLK synchronous: f

However, f is allowed up to "frequency of the peripheral system operating clock"/8.

(Example: f is up to 3.125 MHz when the peripheral system is operating at 25 MHz)

327



Transfer data always starts with the start bit ("L" level data) and ends with the stop bit ("H" level data) after transfer of the data bit length specified by the LSB first. If an external clock is selected, always enter a clock.

Transfer Data Format in Asynchronous (Start-Stop Transmission) Mode

Figure 13.7-1 shows the transfer data format in asynchronous (start-stop transmission) mode.

In normal mode (mode 0), the data length can be set as 7 bits or 8 bits, but in multi-processormode (mode 1), the data length must always be 8 bits. Also, no parity can be added in multi-processor mode, but the A/D bit is always added.

Figure 13.7-1 Transfer Data Format in Asynchronous (Start-Stop Transmission) Mode (Mode 0 and Mode 1)

Receive operation

If the RXE bit (bit1) of the SCR register is "1", the receive operation is always performed.

If the start bit appears in the receive line, one frame data is received according to the dataformat specified by the SCR register. If an error occurs after receiving one frame data, the errorflag is set and then the RDRF flag (bit4 of the SSR register) is set. If, at this time, the RIE bit(bit1) of the same SSR register is set to "1", a receive interrupt occurs to CPU. Check each flagof the SSR register, and if data has been received normally, read the SIDR register. If an errorhas occurred, respond accordingly.

The RDRF flag is cleared when the SIDR register is read.

Send operation

If the TDRE bit (bit11) of the SSR register is "1", send data is written into the SODR register. If,at this point, the TXE bit (bit0) of the SCR register is "1", the data is sent.

When the send operation of data set to the SODR register starts after loading it into the sendshift register, the TDRE flag is set again and so the next send data can be set. If, at this time,the TIE bit (bit0) of the same SSR register is "1", a send interrupt occurs to CPU, requesting it toset send data to the SODR register.

The TDRE flag is cleared temporarily when data is set to the SODR register.

SI,SO

Start LSB MSBStopA/D Stop

Transferred data is 01001101B

(Mode 0)(Mode 1)

328

CHAPTER 13 UART


UART handles only data in the NRZ (Non Return to Zero) format. Figure 13.8-1 shows the relations between the send/receive clock and data.

Transfer Data Format in CLK Synchronous Mode

Figure 13.8-1 Transfer Data Format in CLK Synchronous Mode (Mode 2)

If "0" is set to CS0 and the output from U-TIMER is selected, a synchronous clock for receivingdata is automatically created when data is sent.

If the external clock is selected, the clock must be supplied for just one byte after checking thatdata is stored (The TDRE flag is "0") in the SODR register of the send data buffer of the sendingUART. Also, the mark level must be set before and after sending data.

The data length is 8 bits only and no parity can be added. Since there are no start/end bits,errors other than over-run errors are not detected.

SC

RXE,TXE

SI,SO

LSB MSB

SODR wri te

Mark

(Mode 2)

Transferred data is 01001101B

329


Initialization

Indicates the setting values of each control register when in CLK synchronous mode.

• SMR register

• MD1, MD0: 10

• CS: Specifies the clock input

• SCKE: 1 for the internal timer and 0 for an external clock

• SOE: 1 for sending and 0 for receiving

• CR register

• PEN: 0

• P, SBL, A/D: These bits have no significance.

• CL: 1

• REC: 0 (for initialization)

• RXE, TXE: At least one of them must be 1

• SSR register

• RIE: 1 if interrupts are used and 0 if interrupts are not used.

• TIE: 0

Communication start

Communication is started by writing data into the SODR register. Also for receive-onlyoperations, temporary send data must be written into the SODR register.

Communication end

The communication end can be identified by checking that the RDRF flag of the SSR registerhas changed to "1". Determine whether communication has been effected normally based onthe ORE bit of the SSR register.

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CHAPTER 13 UART


UART has five flags and tow interrupt sources.Theses five flags are: PE/ORE/FRE/RDRF/TDRETwo interrupt sources are: interrupt source for receipt and for transmission.

Interrupt Occurrence and Flags

PE is the code for a parity error; ORE is the code for an over-run error; and FRE is the code fora framing error, all of which are set when receive errors occur and cleared if "0" is written intoREC of the SCR register.

RDRF is set when received data is loaded into the SIDR register and cleared by reading theSIDR register. However, the parity detection function is not available in mode 1, and the paritydetection and framing error detection functions are not available in mode 2.

TDRE is set if the SODR register is empty and data can be written therein and cleared bywriting data into the SODR register.

An interrupt is requested by PE/ORE/FRE/RDRF during a receive operation.

An interrupt is requested by TDRE during a send operation.

Set Timing of the Interrupt Flag During a Receive Operation in Mode 0

PE, ORE, FRE, and RDRF are set when the last stop bit is detected after completing a receivetransfer, thereby generating an interrupt request to CPU. When PE, ORE, or FRE is active,data of SIDR is invalid.

Figure 13.9-1 Set Timing of ORE, FRE, and RDRF (Mode 0)

D6 D7 Stop

PE,ORE,FRE

RDRF

Data

Receive interrupt

331


Set Timing of the Interrupt Flag During a Receive Operation in Mode 1

ORE, FRE, and RDRF are set when the last stop bit is detected after completing a receivetransfer, thereby generating an interrupt request to CPU. Since the length of data that can bereceived is 8 bits, the last 9th bit indicating the address/data becomes invalid. When ORE orFRE is active, data of SIDR is invalid.

Figure 13.9-2 Set Timing of ORE, FRE, and RDRF (Mode 1)

Set Timing of the Interrupt Flag During Receive Operation in Mode 2

ORE and RDRF are set when the last data (D7) is detected after completing receive transfer,generating an interrupt request to CPU. When ORE is active, data of SIDR is invalid.

Figure 13.9-3 Set Timing of ORE and RDRF (Mode 2)

D7 Stop

ORE,FRE

RDRF

Receive interrupt

Data A/D

D5 D6 D7

ORE

RDRF

Receive interrupt

Data

332

CHAPTER 13 UART

Set Timing of the Interrupt Flag During Send Operation in Mode 0, Mode 1, and Mode 2

TDRE is cleared when data is written into the SODR register and the data is transferred to theinternal shift register. TDRE is then set again when the next data can be written, therebygenerating an interrupt request to CPU.

If "0" is written into TXE (RXE is included in mode 2) of the SCR register during send operation,TDRE of the SSR register becomes "1", thereby prohibiting the send operation of UART afterthe send shifter stops. Data written into the SODR register after "0" is written into TXE (RXE isincluded in mode 2) of the SCR register during a send operation and before the transmissionstop is sent.

Figure 13.9-4 Setting Timing of TDRE (Mode 0 and Mode 1)

Figure 13.9-5 Setting Timing of TDRE (Mode 2)

TDRE

ST D0 D1 D2 D3 D4 D5 D6 D7 SP SP ST D0 D1 D2 D3A/D

SODR wri te

SO interrupt

Interrupt request f rom CPU

SO output

ST: Starter bi t D0 to D7: Data bi t SP: Stop bi t A/D: Address/data mult ip lexer

TDRE

D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7

SODR wri te

SO interrupt

Interrupt request f rom CPU

SO output

D0 to D7: Data bi t

333



This section explains precautions for using UART and an application example.

Precautions for Using UART on the MB91101 only (Not on the MB91101A)

Set the communication mode when the operation is stopped. Data sent and received while themode is set cannot be guaranteed (This applies to MB91101 but does not apply to MB91101A).

When UART is used in synchronous transfer mode (mode 2), because the communicationcontrol circuit may stop if the timing of a write operation to data register (SODR) matches withthe timing of a receive interrupt request (RDRF=1), a write operation must be performed inSODR after the data transfer is completed or just after the start of transmission.

Application Example of UART

The mode 1 is used when several slave CPUs are connected to one host CPU (See Figure13.10-1).

This resource supports only the communication interface on the host side.

Figure 13.10-1 Example of System Construction Using Mode 1

Communication is started by the host CPU with the transfer of address data.

The address data is data when the A/D bit of the SCR register is "1". The slave CPU to be thecommunication destination is selected by this data, thereby enabling communication with thehost CPU.

Normal data is data when the A/D bit of the SCR register is "0".

Figure 13.10-2 shows the flow chart of this communication.

Since the parity check function cannot be used in this mode, set "0" to the PEN bit of the SCRregister.

SO

SO SI SO SIHost CPU

Slave CPU#0 Slave CPU#1

SI

334

CHAPTER 13 UART

Figure 13.10-2 Communication Flow Chart in Mode 1

END

Yes

No

Yes

No

START

(Host CPU)

Set mode 1 as the t ransfer mode

Set data to select s lave CPU to D0 to D7 and "1"to A/D, and transfer 1 byte

Set "0" to A/D

Receive operat ion al lowed

Communicat ion wi th s lave CPU

Communicat ion end?

Communicat ion wi th other s lave

CPUs

Receive operat ion prohibi ted

335



Table 13.11-1 and Table 13.11-2 list some examples of the baud rate and U-TIMER reload value settings.Frequencies in the tables represent those of the peripheral system machine clock. UCC1 is the value to be set to the UCC1 bit of the U timer control register (UTIMC)."-" in the tables indicates that the corresponding frequencies cannot be used because the error exceeds plus or minus 1%.

Example of Baud Rate and U-TIMER Reload Value Settings

Asynchronous (start-stop transmission) mode

CLK synchronous mode

*: Error equal to or exceeding plus or minus 1%

Table 13.11-1 Baud Rate and U-TIMER Reload Value in Asynchronous (Start-Stop Transmission) Mode

Baud rate µµµµs 25 MHz 20 MHz 12.5 MHz 10 MHz

1200 833.33 650 (UCC1=0) 520 (UCC1=0) 324 (UCC1=1) 259 (UCC1=1)

2400 416.67 324 (UCC1=1) 259 (UCC1=1) 162 (UCC1=0) 129 (UCC1=0)

4800 208.33 162 (UCC1=0) 129 (UCC1=0) 80 (UCC1=1) 64 (UCC1=0)

9600 104.17 80 (UCC1=1) 64 (UCC1=0) 39 (UCC1=1) 31 (UCC1=1)

19200 52.08 39 (UCC1=1) 31 (UCC1=1) 19 (UCC1=1) -

38400 26.04 19 (UCC1=1) - 12 (UCC1=1) -

57600 17.36 12 (UCC1=1) - - -

10400 96.15 74 (UCC1=0) 59 (UCC1=0) 36 (UCC1=1) 29 (UCC1=0)

31250 32.00 24 (UCC1=0) 19 (UCC1=0) 11 (UCC1=1) 9 (UCC1=0)

62500 16.00 11 (UCC1=1) 9 (UCC1=0) - 4 (UCC1=0)

Table 13.11-2 Baud Rate and U-TIMER Reload Value in CLK Synchronous Mode

Baud rate µµµµs 25 MHz 20 MHz 12.5 MHz 10 MHz

250 K 4.00 49 (UCC1=0) 39 (UCC1=0) 24 (UCC1=0) 19 (UCC1=0)

500 K 2.00 24 (UCC1=0) 19 (UCC1=0) 11 (UCC1=1) 9 (UCC1=0)

1 M 1.00 11 (UCC1=1) 9 (UCC1=0) 5 (UCC1=0)* 4 (UCC1=0)

336

CHAPTER 13 UART

337

CHAPTER 14 DMAC

This chapter provides an overview of the DMAC, configuration and functions of registers, and operations of the DMAC.

14.1 Overview of the DMAC

14.2 DMAC Parameter Descriptor Pointer (DPDP)

14.3 DMAC Control Status Register (DACSR)

14.4 DMAC Pin Control Register (DATCR)

14.5 Registers in Descriptors on the RAM

14.6 Transfer Modes of the DMAC

14.7 Transfer Acceptance Signal Output and Transfer Completion Signal Output

14.8 Precautions on the DMAC

14.9 DMAC Timing Charts

338

CHAPTER 14 DMAC


The DMAC, a module contained in the MB91101, performs the direct memory access (DMA) transfer.

Features of the DMAC

• Eight channels

• Three modes: Single/block transfer, burst transfer, and continuous transfer

• Transfer between an address area and another area

• A maximum transfer count of 65,536

• Issuing an interrupt when the transfer is complete

• Transfer address increment or decrement can be selected using software

• Three external transfer request input pins, three external transfer request acceptance outputpins, and three external transfer completion output pins

339


List of DMAC Registers

Figure 14.1-1 shows a list of DMAC registers.

Figure 14.1-1 List of DMAC Registers

31 0

00000200H DPDP

00000204H DACSR

00000208H DATCR

31 0

DPDP + 0H DMA

ch-0

DPDP + 0CH DMA

ch-1

:

:

DPDP + 54H DMA

ch-7

[Inside DMAC: DMAC internal registers]

[On RAM: DMA descriptors]

descriptor

descriptor

descriptor

340

CHAPTER 14 DMAC

Block Diagram of the DMAC

Figure 14.1-2 shows a block diagram of the DMAC.

Figure 14.1-2 Block Diagram of the DMA

DPDP

DACSR

SADR

DADR

DATCR

DACK0-2EOP0-23 3

3

3

8

DREQ0-2

5

BLK DEC BLK

DMACT

INC/DEC

Edge/level detect circuit

Sequencer

Internal resource transfer request

Interrupt request

Data buffer Switcher

Mode Data bus

341



The DMAC parameter descriptor pointer (DPDP), a DMAC internal register, stores the leading address of the DMAC descriptor table on the RAM.Bits 6 through 0 of the DPDP are always set to 0. The leading address of a descriptor can be defined in 128-byte units.

DMAC Parameter Descriptor Pointer (DPDP)

The DMAC parameter descriptor pointer (DPDP) has the following register configuration:

The DPDP is not initialized upon reset.

The DPDP can be read and written.

Use a 32-bit transfer request to access this register.

The descriptor that specifies the operation mode of each channel is placed at the addressspecified in the DPDP as shown in Table 14.2-1.

31 7 6 0

00000200H 0000000

Initial value: 0000000

Initial value: Undefined

Table 14.2-1 Descriptor Address of Each Channel

DMA channel

Descriptor address DMA channel

Descriptor address

0 DPDP + 0 (00H) 4 DPDP + 48 (30H)

1 DPDP + 12 (0CH) 5 DPDP + 60 (3CH)

2 DPDP + 24 (18CH) 6 DPDP + 72 (48H)

3 DPDP + 36 (24H) 7 DPDP + 84 (54H)

342

CHAPTER 14 DMAC


The DMAC control status register (DACSR), a DMAC internal register, indicates the control and status of the entire DMAC.

Configuration of the DMAC Control Status Register (DACSR)

The DMAC control status register (DACSR) has the following register configuration:

31 30 29 28 27 26 25 24

00000204H


23 22 21 20 19 18 17 16


15 14 13 12 11 10 9 8


7 6 5 4 3 2 1 0


DER7 DED7 DIE7 DOE7

DOE5DIE5DED5DER5

DOE3DIE3DER3 DED3

DOE1DIE1DER1 DED1

DED6

DED4

DED2

DED0

DIE6

DIE4

DIE2

DIE0

DER6

DER4

DER2

DER0

DOE6

DOE4

DOE2

DOE0

Initial value: 00000000H

343


Bit Functions of the DMAC Control Status Register (DACSR)

[bit 31, 27, 23, 19, 15, 11, 7, 3] DERn (DMA ERror)

These bits indicate that an error occurring in the DMA request occurrence source of Channeln stopped the DMA transfer processing.

• 0: No error occurred.

• 1: An error occurred.

An error may or may not occur depending on the DMA request occurrence source(resource). No error occurs in some DMA request occurrence sources.

These bits are initialized to "0" upon reset.

Although these bits can be read and written, only "0" written into these bits is valid.

If these bits are read using a read/modify/write instruction, "1" is read.

[bit 30, 26, 22, 18, 14, 10, 6, 2] DEDn (DMA EnD)

These bits indicate that the DMA transfer of Channel n is complete.

• 0: DMA transfer operation is not complete.

• 1: Either the counter became 0 or an error occurred in the transfer request occurrencesource.


Although these bits can be read and written, only "0" written into these bits is valid.

If these bits are read using a read/modify/write instruction, "1" is read.

[bit 29, 25, 21, 17, 13, 9, 5, 1] DIEn (DMA Operation Enable)

These bits indicate that whether an interrupt request should occur if the DMA transfer ofChannel n is complete (if DEDn is set to 1).

• 0: Interrupt disabled

• 1: Interrupt enabled


These bits can be read and written.

[bit 28, 24, 20, 16, 12. 8, 4. 0] DOEn (DMA Operation Enable)

These bits enable the DMA transfer operation of Channel n.

• 0: Operation disabled

• 1: Operation enabled

DOEn is cleared to 0 if the DMA transfer of the concerned channel n is complete (if DEDn isset to 1).

If DOEn is at the same time cleared because of transfer completion and set because of awrite operation from the bus, the setting operation is prioritized.



344

CHAPTER 14 DMAC


The DMAC pin control register (DATCR), a DMAC internal register, controls the external transfer request input pins, external transfer request acceptance output pins, and external transfer completion output pins.

Configuration of the DMAC Pin Control Register (DATCR)

The DMAC pin control register (DATCR) has the following register configuration:

31 24

00000208H

23 22 21 20 19 18 17 16

R/W R/W R/W R/W R/W R/W

15 14 13 12 11 10 9 8


7 6 5 4 3 2 1 0


LS20LS21

LS10LS11

LS00LS01

AKDE2

AKDE1

AKDE0

EPSE2

EPSE1

EPSE0

AKSE2

AKSE1

AKSE0

EPDE2

EPDE1

EPDE0

Initial value: XXXX0X0X0H

345


Bit Functions of the DMAC Pin Control Register (DATCR)

[bit 21,20, 13, 12, 5, 4] LSn1, LSn0: Transfer request input detect level select

These bits select the detect level of the concerned external transfer request input pinDREQn as shown in Table 14.4-1.

These bits are undefined upon reset.


Set either "H" or "L" Level Detected to use the continuous transfer mode.

[bit 19, 11, 3] AKSEn

[bit 18, 10, 2] AKDEn

These bits specify the timing at which to issue a transfer request acceptance output signal.These bits also specify whether to enable or disable the output function from a transferrequest acceptance output signal pin.



[bit 17, 9, 1] EPSEn

Table 14.4-1 Selecting a Transfer Request Input Detect Level

LSn1 LSn0 Operation control function

0 0 Rising edge detected

0 1 Falling edge detected

1 0 "H" level detected

1 1 "L" level detected

Table 14.4-2 Specifying the Transfer Request Acceptance Output

AKSEn AKDEn Operation control function

0 0 Transfer acceptance output disabled

0 1 Transfer acceptance output enabled; output when accessing the transfer destination data access

1 0 Transfer acceptance output enabled; output when accessing the transfer source data access

1 1 Transfer acceptance output enabled; output when accessing the transfer source data and transfer destination data access

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CHAPTER 14 DMAC

[bit 16, 8, 0] EPDEn

These bits specify the timing at which to issue a transfer completion output signal. Thesebits also specify whether to enable or disable the output function from a transfer completionoutput signal pin.



Table 14.4-3 Specifying the Transfer Completion Output

EPSEn EPDEn Operation control function

0 0 Transfer completion output disabled

0 1 Transfer completion output enabled; output when accessing the transfer destination data access

1 0 Transfer completion output enabled; output when accessing the transfer source data access

1 1 Transfer completion output enabled; output when accessing the transfer source and destination data access

347



The register in the descriptors on the RAM store the channel-by-channel setting information in the DMA transfer.For these registers having 12 bits per channel, memory at the address indicated in the DPDP is used.For the leading address of the descriptor for each channel, see Table 14.2-1, "Descriptor address for each channel".

First Word of the Descriptor

The first word of the descriptor has the following register configuration:

[bits 31 to 16] DMACT: Transfer count specification

These bits specify how many times the DMA transfer should be performed. Specifying0000H performs the transfer 65536 times.

Every time the transfer is performed, the value is decremented by one.

[bits 15 to 12] Reserved

[bits 11 to 8] BLK: Block size specification

These bits specify the transfer block size used in the single/block transfer mode.

Specifying 0 specifies 16 as the block size.Specify 1 to perform single transfer.

[bits 7, 6] SCS1, SCS0: Transfer source address update mode specification

31 16

R/W

15 14 13 12 11 10 9 8

R/W

7 6 5 4 3 2 1 0


DMACT

DCS0DCS1SCS0SCS1 WS0 MOD1WS1

BLK

MOD0

Initial value: undefined

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CHAPTER 14 DMAC

[bits 5, 4] DCS1, DCS0: Transfer destination address update mode specification

These bits specify the update mode for each transfer of the transfer source and destinationaddresses.

The combinations of specifications shown in Table 14.5-1 are allowed.

In the address update mode, an address is incremented or decremented in the followingunits according to the transfer data size specification.

[bits 3,2] WS1, WS0

These bits specify the transfer data size.

Table 14.5-1 Transfer Source and Destination Address Update Mode Specification

SCS1 SCS0 DCS1 DCS0 Transfer source address

Transfer destination address

0 0 0 0 Address incremented Address incremented

0 0 0 1 Address incremented Address decremented

0 0 1 0 Address incremented Address fixed

0 1 0 0 Address decremented Address incremented

0 1 0 1 Address decremented Address decremented

0 1 1 0 Address decremented Address fixed

1 0 0 0 Address fixed Address incremented

1 0 0 1 Address fixed Address decremented

1 0 1 0 Address fixed Address fixed

Other Setting disabled

Table 14.5-2 Address Increment/Decrement Unit

Transfer data size Address increment/decrement unit

byte (8bit) plus or minus 1 byte

halfword (16bit) plus or minus 2 byte

word (32bit) plus or minus 4 byte

Table 14.5-3 Transfer Data Size Specification

WS1 WS0 Transfer data size

0 0 byte

0 1 halfword

1 0 word

1 1 Setting disabled

349


[bits 1, 0] MOD1, MOD0: Transfer mode specification

These bits specify the transfer mode.

The continuos transfer mode can be used only for Channels 0 through 2.

Second Word of Descriptor

This word stores the transfer source address.

The value is updated based on the address update mode specification (SCS1 and SCS0 bits)according to the transfer operation.

Specify a multiple of 2 if the transfer data size is a half word lenght or a multiple of 4 if thetransfer data size is a word length.

Third Word of Descriptor

This word stores the transfer destination address.

The value is updated based on the address update mode specification (DCS1 and DCS0 bits)according to the transfer operation.

Specify a multiple of 2 if the transfer data size is a half word length or a multiple of 4 if thetransfer data size is a word length.

Table 14.5-4 Transfer Mode Specification

MOD1 MOD0 Operation mode

0 0 Single/block mode

0 1 Burst mode

1 0 Continuos transfer mode

1 1 Setting disabled

31 0

R/W

SADR

31 0

R/W

DADR

350

CHAPTER 14 DMAC


The DMAC has the following three transfer modes. This section describes the operation procedures of these transfer modes.• Single/block transfer mode• Continuous transfer mode• Burst transfer mode

Single/Block Transfer Mode

1. The initialization routine sets a descriptor.

2. The program initializes the DMA transfer request occurrence source. If an internal peripheralcircuit is the transfer request occurrence source, enable the interrupt request. At the sametime, disable the interrupt in the ICR of the interrupt controller.

3. The program writes 1 into the DOEn bit of the desired DACSR.--- At this point, the settings of the DMA are complete. ---

4. The DMAC, upon detecting DMA transfer request input, asks the CPU to secure the busprivilege.

5. If the CPU transfers the bus privilege, the DMAC accesses the three-word information in thedescriptor via the bus.

6. The DMACT is subtracted and data is then transferred according to the information in thedescriptor as often as specified in BLK or until the DMACT becomes 0. While data istransferred, a transfer request acceptance output signal is output (if the external transferrequest input is used). If the DMACT becomes 0 due to subtraction, a transfer completionoutput signal is output during data transfer.

7. The transfer request input is cleared.

8. The SADR or DADR is incremented or decremented and written back into the descriptortogether with the DMACT value.

9. The bus privilege is returned to the CPU.

10.If the DMACT value is 0, DEDn of the DACSR is set to 1. At the same time, an interrupt, ifenabled, occurs in the CPU.

The minimum required cycle count per transfer is as follows if the descriptor is stored in theinternal RAM and the data with length in bytes is transferred between external buses.

• If both the transfer source and destination addresses are fixed: (6+5 x BLK) cycles

• If one of the transfer source and destination addresses is fixed: (7+5 x BLK) cycles

• If both the transfer source and destination addresses are incremented or decremented: (8+5x BLK) cycles

351


Continuous Transfer Mode


2. The program initializes the DMA transfer request occurrence source. Set the externaltransfer request input pin to the H or L level detected.

3. The program writes 1 into the DOEn bit of the desired DACSR.--- At this point, the settings of the DMA are completed. ---



6. The DMACT is subtracted and data is then transferred once according to the information inthe descriptor. While data is transferred, a transfer request acceptance output signal isoutput. If the DMACT becomes 0 due to subtraction, a transfer completion output signal isoutput during data transfer.

7. If the DMACT value is not 0 and a DMA request from a peripheral device still exists, Steps 6)is repeated and the subsequent steps are performed thereafter. (Depending on the busstatus, Step 8) is also included.)

8. If the DMACT value is 0 or if DMA requests from peripheral devices are cleared, the SADRor DADR is incremented or decremented and written back into the descriptor together withthe DMACT value.


10.If the counter value is 0, DEDn of the DACSR is set to 1. At the same time, an interrupt, ifenabled, occurs in the CPU.

The minimum required cycle count per transfer is as follows if the descriptor is stored in theinternal RAM and the data with length in bytes is transferred between the external buses.

• If both the transfer source and destination addresses are fixed: (6+5×n) cycles

• If one of the transfer source and destination addresses is fixed: (7+5×n) cycles

• If both the transfer source and destination addresses are incremented or decremented:(8+5×n) cycles

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CHAPTER 14 DMAC

Burst Transfer Mode


2. The program initializes the DMA transfer request occurrence source. If the internalperipheral circuit is to be the transfer request source, enable the interrupt request. At thesame time, disable the interrupt in the ICR of the interrupt controller.

3. The program writes 1 into the DOEn bit of the desired DACSR.--- At this point, the settings of the DMA are complete. ---



6. The DMACT is subtracted and data is then transferred according to the information in thedescriptor as often as specified in DMACT. While data is transferred, a transfer requestacceptance output signal is output (if the external transfer request input is used). If theDMACT becomes 0 due to subtraction, a transfer completion output signal is output duringdata transfer.

7. The SADR or DADR is incremented or decremented and written back into the descriptortogether with the DMACT value.


9. DEDn of the DACSR is set to 1. At the same time, an interrupt, if enabled, occurs in theCPU.

The minimum required cycle count per transfer is as follows if the descriptor is stored in theinternal RAM and the data with length in bytes is transferred between the external buses.

• If both the transfer source and destination addresses are fixed: (6+5×n) cycles

• If one of the transfer source and destination addresses is fixed: (7+5×n) cycles

• If both the transfer source and destination addresses are incremented or decremented:(8+5×n) cycles

353


Combinations of Request Senses and Transfer Modes

Figure 14.6-1 shows combinations of request senses and transfer modes.

Figure 14.6-1 Combinations of Request Senses and Transfer Modes

Sense Modes of the DREQ Signal

Edge sense

The edge sense can be used in a step transfer (single/block) and a burst transfer.

A DMA request is detected using an (active) edge.

Since the input of an external DREQ is masked during the DMAC transfer, an active edge forthe next transfer must be later than an active edge for the transfer destination DACK in theimmediately preceding DMA transfer. Note this during the step transfer.

Level sense

The level sense can be used in step transfer (single/block) and continuous and burst transfer.

A DMA request is detected using the (active) level.

<Precaution>

Both for level and edge senses, the DAC signal has the electrical characteristic of min 2tCYC[ns].

For an edge sense, the DACK has also the negate period of min 2tCYC [ns].

Request sense

Edge sense

Level sense

Transfer mode

Step operation mode

Burst transfer mode

Continuos operation mode

Transfer unit

Single transfer

Block transfer

354

CHAPTER 14 DMAC

14.6.1 Step Transfer (Single/Block Transfer)

DMA transfer is performed once for one transfer request (an edge or level sense can be selected for the DREQ input). Each time a DMA transfer is performed, the bus privilege is passed to the CPU (the cycle-stealing is used to perform a transfer).The transfer unit is determined by block size. The larger the block, the higher the DMAC transfer rate but the lower the CPU throughput.

Step Transfer [CLK Doubler Used, Internal Descriptor, Block Size = 1]

Figure 14.6-2 Step Transfer [CLK Doubler Used, Internal Descriptor, Block Size = 1]

CLK

DREQ

-DACK

InternalD-Abus

external

Abus

Descriptor access

Transfer source Transfer destination Transfer destinationTransfer source

Period during which the CPU can use the data bus

355


14.6.2 Continuous Transfer

DMA transfer is performed while the transfer request [DREQ] maintains an active level (only the level sense can be selected for the DREQ input).If the transfer count register becomes "0" or the DREQ input is negated, the bus privilege is passed to the CPU.

Continuous Transfer [CLK Doubler Used, Internal Descriptor]

Figure 14.6-3 Continuous Transfer [CLK Doubler Used, Internal Descriptor]

CLK

DREQ

-DACK

Internal

D-Abus

external

Abus

Descriptor access


Transfer source Transfer sourceTransfer destination

Transfer destination

356

CHAPTER 14 DMAC

14.6.3 Burst Transfer

DMA transfer is performed as often as the specified transfer count for one transfer request [DREQ] (Either the level or edge sense can be selected for the DREQ input).If the transfer count register becomes "0", the DMA transfer is completed and the bus privilege is passed to the CPU.

Burst Transfer [CLK Doubler Used, Internal Descriptor]

Figure 14.6-4 Burst Transfer [CLK Doubler Used, Internal Descriptor]

CLK

DREQ

- DACK

Internal

D-Abus

external

Abus

DMACT=1 DMACT=0

-EOP

Descriptor access


Transfer source Transfer sourceTransfer destination Transfer destination

357


14.6.4 Differences Depending on the DREQ Sense Modes (Precaution on the Edge Mode)

If the edge mode is used, the next DREQ edge must be entered when or after the DMAC request flag is cleared. Note that an edge entered before this point is ignored.For an edge to be recognized, a negate period of min 2tCYC [ns] is required.During the transfer destination access, enter the next DREQ at or after the DACK falls.

Figure 14.6-5 Precaution on Timing in the Edge Mode

CLK

DREQ

-DACK

external

A bus

A B

DREQ(NG)

DREQ(NG)

DREQ(NG)

Premature active edge

Not meeting min 2tCYC [ns]

Internal D-A bus

Destination write

Descriptor write

Transfer source Transfer destination

A: Point at which the request flag is cleared Point at which the next DREQ is sensed in the edge sense mode Point at which the next DREQ is sensed in the continuos transfer modeB: Point at which the next DREQ is sensed in single/block transfer in the level sense mode

358

CHAPTER 14 DMAC

14.6.5 Differences Depending on the DREQ Sense Modes (Precaution on the Level Mode)

If the level sense mode is used, be careful of a DMA transfer overrun.During the transfer destination access, negate the DREQ before the DACK rises.

Figure 14.6-6 Precaution on Timing in the Level Mode

CLK

DREQ

-DACK

externalA bus

A B

DREQ

DREQ(NG)

1 CYC at the maximum

Data is transferred twice by mistake for one transfer request.

Internal D-A bus

Source read Destination write

Descriptor read Descriptor write

Transfer source Transfer destination

A: Point at which the request flag is cleared Point at which the next DREQ is sensed in the edge sense mode Point at which the next DREQ is sensed in the continuos transfer modeB: Point at which the next DREQ is sensed in single/block transfer in the level sense mode

This figure shows the shortest approximate time from the DREQ to DMA activation.

359



Channels 0, 1, and 2 function to output transfer acceptance and transfer completion signals.The DMAC outputs a transfer acceptance signal when performing the DMA transfer after accepting a transfer request input from a pin.The DMAC outputs a transfer completion signal when completing the transfer because the DMACT counter becomes 0 after performing the DMA transfer after accepting a transfer request input from a pin.

Transfer Acceptance Signal Output

A transfer acceptance signal is output using an active-low pulse when the transfer data isaccessed. The AKSn and AKDn bits in the DATCR can specify whether to output a transferacceptance signal in synchronization with transfer source access or transfer destination accessor both.

Transfer Completion Signal Output

A transfer completion signal is output using an active-low pulse when the final transfer data isaccessed. The EPSn and EPDn bits in the DATCR can specify whether to output a transfercompletion signal in synchronization with transfer source access or transfer destination accessor both.

360

CHAPTER 14 DMAC


This section describes the precautions on using the DMAC

Priority of Channels

Once this DMAC is activated by a DMA transfer request for one channel, a DMA transferrequest occurring for another channel is suspended until the transfer in progress is completed.

If, when the DMAC detects a DMA transfer request, requests for multiple channels aresimultaneously active, the channel to be accepted is determined according to the followingpriority.

(High) ch0 > ch1 > ch2 > ch3 > ch4 > ch5 > ch6 > ch7 (Low)

If requests for multiple channels occur simultaneously, the DMA transfer for one channel isperformed and the bus control is then returned to the CPU before performing the DMA transferfor another channel.

Using a Resource Interrupt Request as a DMA Transfer Request

If the DMAC transfer is to be used, the interrupt level in the interrupt controller for the concernedinterrupt must be set to Interrupt Disabled.

On the contrary, if the DMAC transfer is not to be used, the DMAC operation enable bit in theDMAC must be set to disabled and the interrupt level must be set to an appropriate value.

Inhibiting the DMA Transfer if an Interrupt with a High Priority Occurs

The MB91101 has the function of stopping the DMA transfer if, while the DMA transfer is inprogress according to a DMA transfer request, an interrupt with a higher priority occurs.

HRCL register

Manipulate the Hold Request Cancel Level (HRCL) register of the interrupt controller to stop theDMA transfer operation if an interrupt request occurs.

If an interrupt request with an interrupt level higher than that of the HRCL occurs from aperipheral circuit, the DMA transfer operation of the DMAC is inhibited. While executing theDMA transfer operation, the DMA transfer operation is stopped at a transfer operation intervaland the bus privilege is passed to the CPU. While waiting for a DMA transfer request, a DMAtransfer request is suspended.

After reset, the HRCL is set to the lowest level (31), i.e., the DMA transfer operation is inhibitedagainst any interrupt request. If a DMA transfer is to be performed while an interrupt requestexists, set the HRCL register to an appropriate value.

361


PDRR register

The function of inhibiting the DMA transfer operation as specified in the HRCL register isenabled only if an interrupt request with a higher priority is active. In an interrupt handlerprogram, for example, clearing an interrupt request cancels the inhibition of the DMA transferaccording to the HRCL register and may result in the CPU losing the bus privilege.

The PDRR register in the clock control section is provided to clear an interrupt request andaccept other interrupt requests as well as to inhibit the DMA transfer operation.

In an interrupt handler, writing any value other than 0 in the PDRR inhibits the DMA transferoperation. Write 0 into the PDRR to cancel the inhibition of the DMA transfer operation.

DMA cannot be used in sleep mode. Disable DMA before entering the sleep mode.

DMA transfer in sleep mode

DMA cannot be used in sleep mode. Disable DMA before entering the sleep mode.

Transfer to a DMAC Internal Register

Do not specify a DMAC internal register as the transfer destination address.

Continuos Transfer

In continuous transfer mode, rewriting of descriptor may occur even during transfer, dependingon the state of the bus buffer in the device. In this case, transfer will resume after rewriting.

Precautions on the MB91101 Only (Not on the MB91101A)

Under the following conditions, the DMA transfer is performed one extra time (one transfer sizein single transfer and one block size in block transfer) even if the DREQ is set to a lower priority.

[Conditions]

• DMA transfer destination: External and:

• Level mode and:

• DREQ-DACK handshake makes a DREQ request in synchronization with the DACKoccurring when the transfer destination is accessed

(No problem occurs if the DMAC transfer is performed according to a request from an internalresource or if the DREQ is negated before a rising edge of the transfer source DACK.)

[Solution]

Set a descriptor in external memory unless both the transfer source and the destination arefixed addresses.

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CHAPTER 14 DMAC

DMA for the MB9110: Negate DREQ before DACK rises during access to the transferdestination

DMA for the MB91101A: Negate DREQ before DACK rises during access to the transfer source

Figure 14.8-1 Restriction of DMAC

Under the following conditions, the DMA transfer is performed twice inadvertently for onetransfer request if the DMAC transfer is performed due to the send operation of the internalUART.

[Conditions]

• DMA transfer source: External memory and:

• DMA transfer destination: UART send register and:

• The CPU has a higher operation frequency than the peripheral resource.

(For details, see Table 14.8-1.)

Y: Normal operation, N: Faulty, X: Faulty

[Solutions]

• Use a gear ratio indicated with Y in the above table or:

• Only if a gear ratio with CPU is selected: Peripheral = 2: 1 (indicated with N in Table 14.8-1), place the descriptor in external memory. [Example: CPU 50 MHz, Peripheral 25 MHz]

CLK

DACK

externalAbus

B

DREQ MB91101(NG) MB91101A(OK)

A:MB91101B:MB91101A

A

DREQ MB91101(OK) MB91101A(OK)

Internal D-ASource read Destination write

Descripter read Descriptor write

Period in which the DATA bus of the CPU can be used

Transfer source Transfer destination Sense starting point of the next DREQ atsingle block transfer in level sense mode

The timing from DREQ to DMA start, as described here, indicates almost the fastest timing possible.

Table 14.8-1 Combinations of Clock Gears

Peripheral

CPU 1/1 1/2 1/4 1/8

1/1 Y N X X

1/2 Y Y N X

1/4 Y Y Y N

1/8 Y Y Y Y

363


DMA Transfer Request Causes

Table 14.8-2 lists the DMA transfer request causes.

DMAC transfer request source error statuses

Only ch4 can report the occurrence of an error to the DMA request occurrence source in theDERn bit of the DACSR.

If the UART ch0 receive interrupt is used as a DMA transfer request, the occurrence of any ofthe following errors sets the DER4 bit to "1".

• Parity error

• Overrun error

• Framing error

DREQ2

If the external transfer request input pin DREQ2 is to be used, disable the CS1L function forwhich this pin is also used (set the C1LE bit of the DSCR register to "0").

If the CS1L output is enabled, a change in the CS1L signal causes a malfunction.

Table 14.8-2 DMA Transfer Request Causes

Channel number Transfer request cause

0 External transfer request input pin DREQ0



3 PWM ch0

4 UART ch0 received

5 UART ch0 sent

6 16-bit reload timer ch0

7 A/D converter

364

CHAPTER 14 DMAC


This section provides the DMAC operation timing charts:• Timing chart of the descriptor access section• Timing chart of the data transfer section• Transfer stop timing chart in the continuous transfer mode• Transfer completion operation timing chart

Description of Symbols Used in the Timing Charts

Table 14.9-1 Description of Symbols Used in the Timing Charts

Symbol Meaning of symbol

#0 Descriptor No.0

#0H Bits 31 to 16 of Descriptor No.0

#0L Bits 15 to 0 of Descriptor No.0

#1 Descriptor No.1



#2 Descriptor No.2



#1/2 Descriptor No.1 or 2 (determined by SCS1, 0, DCS1, 0)

#1/2H Bits 31 to 16 of Descriptor No.1 or 2

#1/2L Bits 15 to 0 of Descriptor No.1 or 2

S Transfer source

SH Bits 31 to 16 of transfer source

SL Bits 15 to 0 of transfer source

D Transfer destination

DH Bits 31 to 16 of transfer destination

DL Bits 15 to 0 of transfer destination

365


14.9.1 Timing Chart of the Descriptor Access Section

This section shows the timing chart of the descriptor access section.

Descriptor Access Section

Request pin input mode: level, descriptor address: external

Request pin input mode: level, descriptor address: internal

(A)

CLK

DREQn

RDXD

WRnX

DACK

EOP

#2H

#2H

S

S

#1H

#1L#1H

#1L#0L#0H

#0L#0H #2L

#2LAddr pin

Data pin

(A)

Interanl KB

CLK

DREQn

Addr pin

Data pin

RDXD

WRnX

DACK

EOP

S

S

366

CHAPTER 14 DMAC

Request pin input mode: edge, descriptor address: external

Request pin input mode: edge, descriptor address: internal

<Precaution>

This figure shows the shortest time from the DREQn occurrence to the DMAC operation start.

In actual operation, the DMAC operation start may be delayed because of bus contention due toinstruction fetch and data access of the CPU.

(A)

CLK

DREQn

RDXD

WRnX

DACK

EOP

#2H

#2H

S

S

#1H

#1L#1H

#1L#0L#0H

#0L#0H #2L

#2L

Data pin

Addr pin

(A)

CLK

DREQn

RDXD

WRnX

DACK

EOP

S

S

Addr pin

Data pin

367


14.9.2 Timing Chart of the Data Transfer Section

This section shows the timing chart of the data transfer section.

Data Transfer Section, 16/8-Bit Data

Transfer source area: external, transfer destination area: external

Transfer source area: external, transfer destination area: internal RAM

CLK

DREQn

Addr pin

Data pin

RDXD

WRnX

DACK

EOP

(A)

W

D

DS#2

S#2

D

DS

S

W

D

DS

S

W

D

DS

S

(A)

CLK

DREQn

Addr pin

Data pin

RDXD

WRnX

DACK

EOP

S#2

S#2 S

S

S

S

S

S

368

CHAPTER 14 DMAC

Transfer source area: internal RAM, transfer destination area: external

(A)

CLK

DREQn

Addr pin

Data pin

RDXD

WRnX

DACK

EOP

#2

#2

W

D

D D D D

DD

WW

D

W

369


14.9.3 Transfer Stop Timing Chart in the Continuous Transfer Mode

This section shows the transfer stop timing chart in the continuous transfer mode.

Transfer Stop Timing Chart in the Continuous Transfer Mode (If One of the Addresses is Fixed), 16/8-Bit Data




CLK

DREQn

Addr pin

Data pin

RDXD

WRnX

DACK

EOP

W

D

D

S

S

W

#1/2L

#1/2L

#1/2H

#1/2H

W

D

D

W W

#0H

#0H

CLK

DREQn

Addr pin

Data pin

RDXD

WRnX

DACK

EOP

S

S

W

#0H

#0HS

S

W

#1/2L#1/2H

#1/2L#1/2H

W

CLK

DREQn

Addr pin

Data pin

RDXD

WRnX

DACK

EOP

W

D

D D D

DD

WW W

#0H

#0H

W

#1/2L#1/2H

#1/2L#1/2H

W

370

CHAPTER 14 DMAC




CLK

DREQn

Addr pin

Data pin

RDXD

WRnX

DACK

EOP

W

D

D

S

S

W

#2L

#2L

#2H

#2H

W W

D

D

W

#0H

#0H

W

#1L

#1L

#1H

#1H

W

CLK

DREQn

Addr pin

Data pin

RDXD

WRnX

DACK

EOP

S

S #0H

#0HS

S

W W

#2L

#2L

#2H

#2H

WW

#1L

#1L

#1H

#1H

W

CLK

DREQn

Addr pin

Data pin

RDXD

WRnX

DACK

EOP

W

D

D D D

DD

WW

#0H

#0H

W W

#2L

#2L

#2H

#2H

WW

#1L

#1L

#1H

#1H

W

371


14.9.4 Transfer Completion Operation Timing Chart

This section shows the transfer completion operation timing chart.

Transfer Completion Operation (If One of the Addresses is Fixed)

Bus width: 16 bits, data length: 8/16 bits

Bus width: 16 bits, data length: 32 bits

CLK

Addr pin

Data pin

RDXD

WRnX

AKSE=1

DACK AKDE=1

EPSE=1

EOP EPDE=1

W

D

D

S

S

W

#1/2L

#1/2L

#1/2H

#1/2H

W

D

D

W W

#0H

#0HS

S

W

D

D

Both set to 1

Both set to 1

CLK

Addr pin

Data pin

RDXD

WRnX

AKSE=1

DACK AKDE=1

EPSE=1

EOP EPDE=1

SLSH

SLSH

W

#1/2L

#1/2L

#1/2H

#1/2H

W

DH

DH

W W

#0H

#0H

DL

DL

W

SLSH

SLSH DH

DH

W

DL

DL

W

Both set to 1

Both set to 1

372

CHAPTER 14 DMAC

Bus width: 16 bits, data length: 8/16 bits

Bus width: 16 bits, data length: 32 bits

CLK

Addr pin

Data pin

RDXD

WRnX

AKSE=1

DACK AKDE=1

EPSE=1

EOP EPDE=1

W

D

D

S

S

W

#2L

#2L

#1H

#1H

W

D

D

W W

#0H

#0HS

S

W

D

D

W

#1L

#1L

#2H

#2H

W

Both set to 1

Both set to 1

CLK

Addr pin

Data pin

RDXD

WRnX

AKSE=1

DACK AKDE=1

EPSE=1

EOP EPDE=1

CLK

Addr pin

Data pin

RDXD

WRnX

SLSH

SLSH

W

#1L

#1L

#1H

#1H

W

DH

DH

W W

#0H

#0H

DL

DL

W

SLSH

SLSH DH

DH

W

DL

DL

W

W

#2L

#2L

#2H

#2H

W

Both set to 1

Both set to 1

373

CHAPTER 15 BIT SEARCH MODULE

This chapter describes the overview of the bit search module, configuration and functions of registers, operations of the bit search module, and save and restore processing.

15.1 Overview of the Bit Search Module

15.2 Registers of the Bit Search Module

15.3 Operations of the Bit Search Module and Save and Restore Processing

374


15.1 Overview of the Bit Search Module

The bit search module searches the data written into the input registers for 0, 1, or a variation point and returns a detected bit position.

List of Bit Search Module Registers

Figure 15.1-1 show the list of bit search module registers.

Figure 15.1-1 List of Bit Search Module Registers

Block Diagram of the Bit Search Module

Figure 15.1-2 shows the block diagram of the bit search module

Figure 15.1-2 Block Diagram of the Bit Search Module

31 0

Address: 000003F0H

Address: 000003F4H

Address: 000003F8H

Address: 000003FCH

BSD0

BSD1

BSDC

BSRR

0-detection data register

1-detection data register

Variation point detection data register

Detection result register

D-BUS

Input latch

Address decoder

Detection mode

Detecting 1 and creating data

Bit search circuit

Search result

375



The bit search module has the following four registers:• 0-detection data register (BSD0)• 1-detection data register (BSD1)• Variation point detection data register (BSDC)• Detection result register (BSRR)

0-Detection Data Register (BSD0)

Used to detect 0 in a written value.

Upon reset, this register has an undefined initial value.

Reading this register reads an undefined value.

To transfer data, use a 32-bit long data transfer instruction (do not use an 8-bit or 16-bit longdata transfer instruction).

1-Detection Data Register (BSD1)

31 0

000003F0H

WRead/writeInitial value Undefined

31 0

000003F4H

R/WUndefinedInitial value

Read/write

376



When writing

Used to detect 1 in a written value

When reading

Used to read save data of the internal status of the bit search module. Used to save andrestore the original status of the bit search module when the interrupt handler, etc. uses the bitsearch module. Even if data is written to the 0 detection and variation point detection dataregisters, manipulating only the 1-detection data register allows the original status to be savedand restored.


Variation Point Detection Data Register (BSDC)

Used to detect a variation point in a written value.


Reading this register reads an undefined value.


Detection Result Register (BSRR)

Reading this register reads the result of detecting 0, 1, or a variation detection.

The last written data register determines which detection result is read.

31 0

000003F8H

WRead/writeInitial value Undefined

31 0

000003FCH

RUndefinedInitial value

Read/write

377



This section describes the 0-detection, 1-detection, and variation point detection operations of the bit search module as well as save and restore processing.

0 Detection

The bit search module scans data written into the 0-detection data register from the MSB to theLSB and returns the position where "0" is detected for the first time.

To obtain the detection result, read the detection result register.

Table 15.3-1 shows the correspondence between detected positions and returned values.

If no "0" exists (i.e., the value is FFFFFFFFH), the value 32 is returned as the search result.

[Example execution]

Write data Read value (decimal)

11111111 11111111 11110000 00000000B (FFFFF000H) ==> 20

11111000 01001001 11100000 10101010B (F849E0AAH) ==> 5

10000000 00000010 10101010 10101010B (8002AAAAH) ==> 1

11111111 11111111 11111111 11111111B (FFFFFFFFH) ==> 32

1 Detection

The bit search module scans data written into the 1-detection data register from the MSB to theLSB and returns the position where "1" is detected for the first time.



If no "1" exists (i.e., the value is 00000000H), the value 32 is returned as the search result.

[Example execution]


00100000 00000000 00000000 00000000B (20000000H) ==> 2

00000001 00100011 01000101 01100111B (01234567H) ==> 7

00000000 00000011 11111111 11111111B (0003FFFFH) ==> 14

00000000 00000000 00000000 00000001B (00000001H) ==> 31

00000000 00000000 00000000 00000000B (00000000H) ==> 32

378


Variation Point Detection

The bit search module scans data written into the variation point detection data register from Bit30 to the LSB, compares the data with the MSB value, and returns the position where a valuedifferent than the MSB is detected for the first time.



If no variation point exists, the value 32 is returned.

The variation point detection does not return 0 as a result.

[Example execution]


00100000 00000000 00000000 00000000B (20000000H) ==> 2

00000001 00100011 01000101 01100111B (01234567H) ==> 7

00000000 00000011 11111111 11111111B (0003FFFFH) ==> 14

00000000 00000000 00000000 00000001B (00000001H) ==> 31

00000000 00000000 00000000 00000000B (00000000H) ==> 32

11111111 11111111 11110000 00000000B (FFFFF000H) ==> 20

11111000 01001001 11100000 10101010B (F849E0AAH) ==> 5

10000000 00000010 10101010 10101010B (8002AAAAH) ==> 1

11111111 11111111 11111111 11111111B (FFFFFFFFH) ==> 32

Table 15.3-1 Bit Positions and Returned Values (Decimal)

Detected bit

position

Returned value

Detected bit

position

Returned value

Detected bit

position

Returned value

Detected bit

position

Returned value

31 0 23 8 15 16 7 24

30 1 22 9 14 17 6 25

29 2 21 10 13 18 5 26

28 3 20 11 12 19 4 27

27 4 19 12 11 20 3 28

26 5 18 13 10 21 2 29

25 6 17 14 9 22 1 30

24 7 16 15 8 23 0 31

No variation

point

32

379


Save and Restore Processing

To save and restore the internal status of the bit search module when, for example, the bitsearch module is used in the interrupt handler, proceed as follows:

1. Read the 1-detection data register and store the contents (saving).

2. Use the bit search module.

3. Write the data saved in Step 1) into the 1-detection data register (restoring).

After proceeding as above, the value that can be obtained by reading the detection resultregister is the same as the content written into the bit search module before Step 1).

The above procedure properly restores the original content even if data is last written to the 0-detection or variation point detection data register.

380


381

APPENDIX

The appendices provide more details and programming references concerning the I/O maps, interrupt vectors, pin statuses in CPU states, precautions on using the little endian area, and instructions.

A I/O Maps

B Interrupt Vectors

C Pin Statuses in CPU States

D Precautions on Using the Little Endian Area

E. Instruction List

382

APPENDIX A I/O Maps

APPENDIX A I/O Maps

Addresses shown in Tables A-1 through A-6 are assigned to the registers of peripheral functions contained in the MB91101.

Reading an I/O Map

<Precautions>

The register bit value has one of the following initial values:

"1": Initial value "1"

"0": Initial value "0"

"X": Initial value "X"

"– ": No register actually exists at this position.

AddressRegister

Internal resource

Port data register

+0 +1 +2 +3

000000H PDR3 [R/W]XXXXXXXX

PDR2 [R/W]XXXXXXXX

Read/write attribute

Register initial value after reset

Register name (The registers in the first, second, ... columns have the addresses 4n, 2n+1, ...)

Leftmost register address (The register in the first column is the MSB of data if accessed in words.)

383

APPENDIX A I/O Maps

I/O Mapping

Table A-1 I/O MAP

Address Register name (abbreviated)

Register name Read/write Intitial value

0000H (Vacancy)

0001H PDR2 Port 2 data register R/W XXXXXXXXB

0002H to

0004H

(Vacancy)

0005H PDR6 Port 6 data register R/W XXXXXXXXB

0006H (Vacancy)

0007H

0008H PDRB Port B data register R/W XXXXXXXXB

0009H PDRA Port A data register R/W -XXXXXX-B

000AH (Vacancy)

000BH PDR8 Port 8 data register R/W --X--XXXB

000CH to

0011 H

(Vacancy)

0012H PDRE Port E data register R/W XXXXXXXXB

0013H PDRF Port F data register R/W XXXXXXXXB

0014H to

001BH

(Vacancy)

001CH SSR0 Serial status register 0 R/W 00001-00B

001DH SIDR0/SODR0 Serial input register 0/ serial output register 0

R/W XXXXXXXXB

001EH SCR0 Serial control register 0 R/W 00000100B

001FH SMR0 Serial mode register 0 R/W 00--0-00B

0020H SSR1 Serial status register 1 R/W 00001-00B

0021H SIDR1/SODR1 Serial input register 0/ serial output register 0

R/W XXXXXXXXB

0022H SCR1 Serial control register 1 R/W 00000100B

0023H SMR2 Serial mode register 2 R/W 00--0-00B

0024H SSR2 Serial status register 2 R/W 00001-00B

0025H SIDR2/SODR2 Serial input register 2/ serial output register 2

R/WXXXXXXXXB

384

APPENDIX A I/O Maps

0026H SCR2 Serial control register 2 R/W 00000100B

0027H SMR2 Serial mode register 2 R/W 00--0-00B

0028H TMRLR0 16-bit reload register ch. 0 W XXXXXXXXB

0029H XXXXXXXXB

002AH TMR0 16-bit timer register ch.0 R XXXXXXXXB

002BH XXXXXXXXB

002CH (Vacancy)

002DH

002EH TMCSR0 16-bit reload timer control status register ch. 0

R/W ----0000B

002FH 00000000B

0030H TMRLR1 16-bit reload register ch. 1 W XXXXXXXXB

0031H XXXXXXXXB

0032H TMR1 16-bit timer register ch. 1 R XXXXXXXXB

0033H XXXXXXXXB

0034H (Vacancy)

0035H

0036H TMCSR1 16-bit reload timer control status register ch. 1

R/W ----0000B

0037H 00000000B

0038H ADCR A/D converter data register R ------XXB

0039H XXXXXXXXB

003AH ADCS A/D converter control status register R/W 00000000B

003BH 00000000B

003CH TMRLR2 16-bit reload register ch. 2 W XXXXXXXXB

003DH XXXXXXXXB

003EH TMR2 16-bit timer register ch. 2 R XXXXXXXXB

003FH XXXXXXXXB

0040H (Vacancy)

0041H

0042H TMCSR2 16-bit reload timer control status register ch. 2

R/W ----0000B

0043H 00000000B

Table A-1 I/O MAP



385

APPENDIX A I/O Maps

0044H to

0077H

(Vacancy)

0078H UTIM0/UTIMR0 U-TIMER register ch. 0/ reload register ch. 0

R/W 00000000B

0079H 00000000B

007AH (Vacancy)

007BH UTIMC0 U-TIMER control register ch. 0 R/W 0--00000B

007CH UTIM1/UTIMR1 U-TIMER register ch.1/ reload register ch. 1

R/W 00000000B

007DH 00000000B

007EH (Vacancy)

007FH UTIMC1 U-TIMER control register ch. 1 R/W 0--00000B

0080H UTIM2/UTIMR2 U-TIMER register ch. 2/ reload register ch. 0

R/W 00000000B

0081H 00000000B

0082H (Vacancy)

0083H UTIMC2 U-TIMER control register ch. 2 R/W 00--0000B

0084H to

0093H

(Vacancy)

0094H EIRR External interrupt cause register R/W 00000000B

0095H ENIR Interrupt enable register R/W 00000000B

0096H to

0098H

(Vacancy)

0099H ELVR External interrupt request level setting register

R/W 00000000B

009AH to

00D1H

(Vacancy)

00D2H DDRE Port E data direction register W 00000000B

00D3H DDRF Port F data direction register W 00000000B

00D4H to

00DBH

(Vacancy)

00DCH GCN1 General control register 1 R/W 00110010B

00DDH 00010000B

00DEH (Vacancy)

Table A-1 I/O MAP



386

APPENDIX A I/O Maps

00DFH GCN2 General control register 2 R/W 00000000B

00E0H PTMR0 Ch. 0 timer register R 11111111B

00E1H 11111111B

00E2H PCSR0 Ch. 0 cycle setting register W XXXXXXXXB

00E3H XXXXXXXXB

00E4H PDUT0 Ch. 0 duty setting register W XXXXXXXXB

00E5H XXXXXXXXB

00E6H PCNH0 Ch. 0 control status register H R/W 0000000-B

00E7H PCNL0 Ch. 0 control status register L R/W 00000000B

00E8H PTMR1 Ch. 1 timer register R 11111111B

00E9H 11111111B

00EAH PCSR1 Ch. 1 cycle setting register W XXXXXXXXB

00EBH XXXXXXXXB

00ECH PDUT1 Ch. 1 duty setting register W XXXXXXXXB

00EDH XXXXXXXXB

00EEH PCNH1 Ch. 1 control status register H R/W 0000000-B

00EFH PCNL1 Ch. 1 control status register L R/W 00000000B

00F0H PTMR2 Ch. 2 timer register R 11111111B

00F1H 11111111B

00F2H PCSR2 Ch. 2 cycle setting register W XXXXXXXXB

00F3H XXXXXXXXB

00F4H PDUT2 Ch. 2 duty setting register W XXXXXXXXB

00F5H XXXXXXXXB

00F6H PCNH2 Ch. 2 control status register H R/W 0000000-B

00F7H PCNL2 Ch. 2 control status register L R/W 00000000B

00F8H PTMR3 Ch. 3 timer register R 11111111B

00F9H 11111111B

00FAH PCSR3 Ch. 3 cycle setting register W XXXXXXXXB

00FBH XXXXXXXXB

00FCH PDUT3 Ch. 3 duty setting register W XXXXXXXXB

00FDH XXXXXXXXB

Table A-1 I/O MAP



387

APPENDIX A I/O Maps

00FEH PCNH3 Ch. 3 control status register H R/W 0000000-B

00FFH PCNL3 Ch. 3 control status register L R/W 00000000B

0100H to

01FFH

(Vacancy)

0200H DPDP DMAC parameter descriptor pointer R/W XXXXXXXXB

0201H XXXXXXXXB

0202H XXXXXXXXB

0203H X0000000B

0204H DACSR DMAC control status register R/W 00000000B

0205H 00000000B

0206H 00000000B

0207H 00000000B

0208H DATCR DMAC pin control register R/W XXXXXXXXB

0209H XXXX0000B

020AH XXXX0000B

020BH XXXX0000B

020CH to

03E3H

(Vacancy)

03E4H ICHCR Instruction cache control register R/W --------B

03E5H --------B

03E6H --------B

03E7H --000000B

03E8H to 03EFH

(Vacancy)

03F0H BSD0 Bit reserch module 0-detection data register

W XXXXXXXXB

03F1H XXXXXXXXB

03F2H XXXXXXXXB

03F3H XXXXXXXXB

Table A-1 I/O MAP



388

APPENDIX A I/O Maps

03F4H BSD1 Bit reserch module 1-detection data register

R/W XXXXXXXXB

03F5H XXXXXXXXB

03F6H XXXXXXXXB

03F7H XXXXXXXXB

03F8H BSDC Bit reserch module transition-detection data register

W XXXXXXXXB

03F9H XXXXXXXXB

03FAH XXXXXXXXB

03FBH XXXXXXXXB

03FCH BSRR Bit reserch module detection result register

R XXXXXXXXB

03FDH XXXXXXXXB

03FEH XXXXXXXXB

03FFH XXXXXXXXB

0400H ICR00 Interrupt control register 0 R/W ---11111B










040AH ICR10 Interrupt control register 10 R/W ---11111B

040BH ICR11 Interrupt control register 11 R/W ---11111B

040CH ICR12 Interrupt control register 12 R/W ---11111B

040DH ICR13 Interrupt control register 13 R/W ---11111B

040EH ICR14 Interrupt control register 14 R/W ---11111B

040FH ICR15 Interrupt control register 15 R/W ---11111B




Table A-1 I/O MAP



389

APPENDIX A I/O Maps








041AH ICR26 Interrupt control register 26 R/W ---11111B

041BH ICR27 Interrupt control register 27 R/W ---11111B

041CH ICR28 Interrupt control register 28 R/W ---11111B

041DH ICR29 Interrupt control register 29 R/W ---11111B

041EH ICR30 Interrupt control register 30 R/W ---11111B



0430H DICR Delayed interrupt control register R/W -------0B

0431H HRCL Hold request cancel request level setting register

R/W ---11111B

0432H to

047FH

(Vacancy)

0480H RSRR/WTCR Reset cause register/ watchdog peripheral control register

R/W 1XXXX-00B

0481H STCR Standby control register R/W 000111--B

0482H PDRR DMA controller register R/W ----0000B

0483H CTBR Timebase timer clear register W XXXXXXXXB

0484H GCR Gear control register R/W 110011-1B

0485H WPR Watchdog reset occurrence postpone register

W XXXXXXXXB

0486H (Vacancy)

0487H

0488H PCTR PLL control register R/W 00--0---B

0489Hto

0600H

(Vacancy)

Table A-1 I/O MAP



390

APPENDIX A I/O Maps

0601H DDR2 Port 2 data direction register W 00000000B

0602H to 0604H

(Vacancy)

0605H DDR6 Port 6 data direction register W 00000000B

0606H (Vacancy)

0607H

0608H DDRB Port B data direction register W 00000000B

0609H DDRA Port A data direction register W -000000-B

060AH (Vacancy)

060BH DDR8 Port 8 data direction register W --0--000B

060CH ASR1 Area select register 1 W 00000000B

060DH

060EH AMR1 Area mask register 1 W 00000001B

060FH 00000000B

0610H ASR2 Area select register 2 W 00000000B

0611H 00000000B

0612H AMR2 Area mask register 2 W 00000010B

0613H 00000000B


0615H 00000011B

0616H AMR3 Area mask register 3 W 00000000B

0617H 00000000B


0619H 00000100B

061AH AMR4 Area mask register 4 W 00000000B

061BH 00000000B

061CH ASR5 Area select register 5 W 00000000B

061DH 00000101B

061EH AMR5 Area mask register 5 W 00000000B

061FH 00000000B

0620H AMD0 Area mode register 0 R/W ---00111B

0621H AMD1 Area mode register 1 R/W 0--00000B

Table A-1 I/O MAP



391

APPENDIX A I/O Maps

Note; Do not use (vacancy).

0622H AMD32 Area mode register 32 R/W 00000000B



0625H DSCR DRAM signal control register W 00000000B

0626H RFCR Refresh control register R/W --XXXXXXB

0627H 00---000B

0628H EPCR0 External pin control register 0 W ----1100B

0629H -1111111B

062AH (Vacancy)

062BH EPCR1 External pin control register 1 W 11111111B

062CH DMCR4 DRAM control register 4 R/W 00000000B

062DH 0000000-B

062EH DMCR5 DRAM control register 5 R/W 00000000B

062FH 0000000-B

0630H to

07FDH

(Vacancy)

7FEH LER Little endian register W -----000B

7FFH MODR Mode register W XXXXXXXXB

Table A-1 I/O MAP



392

APPENDIX B Interrupt Vectors


Tables B-1 and B-2 show the interrupt vectors.These interrupt vector tables show the interrupt causes and interrupt vectors of the MB91101 as well as the assignment of interrupt control registers.

Interrupt Vectors

ICR

An ICR, a register provided in the interrupt controller, defines the interrupt level for eachinterrupt request. An ICR is provided for each interrupt request.

TBR

A TBR is a register that indicates the leading address of the EIT vector table.

Add the offset values defined for each TBR and EIT cause to obtain a vector address.

Reference:

A one-kilobyte area starting from an address indicated in a TBR is the EIT vector area.

Each vector is four bytes in length. The correspondence between a vector number and avector address can be represented as follows:

vctadr = TBR + vctofs

= TBR + (3FCH - 4 × vct)

vctadr: Vector address

vctofs: Vector offset

vct: Vector number

393


Table B-1 Interrupt vector table (1/2)

Interrupt cause

Interrupt numberInterrupt level *1

Offset TBR default address *2Decimal Hexa-

decimal

Reset 0 00 – 3FCH 000FFFFCH

Reserved for system 1 01 – 3F8H 000FFFF8H



Reserved for system 4 04 – 3ECH 000FFFECH

Reserved for system 5 05 – 3E8H 000FFFE8H



Reserved for system 8 08 – 3DCH 000FFFDCH

Reserved for system 9 09 – 3D8H 000FFFD8H

Reserved for system 10 0A – 3D4H 000FFFD4H

Reserved for system 11 0B – 3D0H 000FFFD0H

Reserved for system 12 0C – 3CCH 000FFFCCH

Reserved for system 13 0D – 3C8H 000FFFC8H

Undefined instruction exception 14 0E – 3C4H 000FFFC4H

NMI request 15 0F Fixed to FH 3C0H 000FFFC0H

External interrupt 0 16 10 ICR00 3BCH 000FFFBCH




UART 0 receive completed 20 14 ICR04 3ACH 000FFFACH

UART 1 receive completed 21 15 ICR05 3A8H 000FFFA8H

UART 2 receive completed 22 16 ICR06 3A4H 000FFFA4H

UART 0 send completed 23 17 ICR07 3A0H 000FFFA0H

UART 1 send completed 24 18 ICR08 39CH 000FFF9CH

UART 2 send completed 25 19 ICR09 398H 000FFF98H

DMAC 0 (end, error) 26 1A ICR10 394H 000FFF94H

DMAC 1 (end, error) 27 1B ICR11 390H 000FFF90H

DMAC 2 (end, error) 28 1C ICR12 38CH 000FFF8CH

394


DMAC 3 (end, error) 29 1D ICR13 388H 000FFF88H

DMAC 4 (end, error) 30 1E ICR14 384H 000FFF84H

DMAC 5 (end, error) 31 1F ICR15 380H 000FFF80H

DMAC 6 (end, error) 32 20 ICR16 37CH 000FFF7CH

DMAC 7 (end, error) 33 21 ICR17 378H 000FFF78H

A/D (sequential type) 34 22 ICR18 374H 000FFF74H


Reload timer 1 36 24 ICR20 36CH 000FFF6CH



Interrupt cause



decimal


Interrupt cause



decimal

PWM 0 38 26 ICR22 364H 000FFF64H

PWM 1 39 27 ICR23 360H 000FFF60H

PWM 2 40 28 ICR24 35CH 000FFF5CH

PWM 3 41 29 ICR25 358H 000FFF58H

U-TIMER 0 42 2A ICR26 354H 000FFF54H

U-TIMER 1 43 2B ICR27 350H 000FFF50H

U-TIMER 2 44 2C ICR28 34CH 000FFF4CH

Reserved for system 45 2D ICR29 348H 000FFF48H

Reserved for system 46 2E ICR30 344H 000FFF44H

Reserved for system 47 2F ICR31 340H 000FFF40H

Reserved for system 48 30 ICR32 33CH 000FFF3CH

Reserved for system 49 31 ICR33 338H 000FFF38H





395






Reserved for system 58 3A ICR42 314H 000FFF14H

Reserved for system 59 3B ICR43 310H 000FFF10H

Reserved for system 60 3C ICR44 30CH 000FFF0CH

Reserved for system 61 3D ICR45 308H 000FFF08H

Reserved for system 62 3E ICR46 304H 000FFF04H

Delay interrupt cause bit 63 3F ICR47 300H 000FFF00H

Reserved for system (used for REALOS) *3

64 40 – 2FCH 000FFEFCH

Reserved for system (used for REALOS) *3

65 41 – 2F8H 000FFEF8H

Used for INT instruction 66 to 255 42 to FF – 2F4Hto

000H

000FFEF4Hto

000FFC00H


Interrupt cause



decimal

*1 An ICR, a register provided in the interrupt controller, defines the interrupt level for each interrupt request.

*2 An ICR is provided for each interrupt request.A TBR is a register that indicates the leading address of the EIT vector table.Add the offset values defined for each TBR and EIT cause to obtain a vector address.

*3 To use the REALOS/FR, use the 0x40 and 0x41 interrupts for system codes.

396

APPENDIX C Pin Statuses in CPU States

APPENDIX CPin Statuses in CPU States

Table C-1 describes the terminology used in the lists of pin statuses. Tables C-2 through C-7 list the pin statuses in CPU states.

Terminology Used in the Lists of Pin Statuses

The terms for pin status are explained as follows:

Table C-1 Terminology used in the lists of pin statuses

Terminology Description

Input enabled The input function is enabled.

Input fixed to 0 An input gate closest to the pin cuts off the external input and conveys "0" to the inside.

Output Hi-Z The pin-driving transistor is disabled and the pin is set to high impedance.

Output maintained

The status that was output before entering this mode continues to be output. If a built-in peripheral with an output is operating, the output continues according to the built-in peripheral. If a built-in peripheral outputs as a port, the output is maintained.

Previous status maintained

The status that was output before entering this mode continues to be output. Input is enabled.

397


Pin Statuses in CPU States

Table C-2 Pin statuses in the external 16-bit bus and 2CAS1WR mode (1/2)

Pin name

Function During sleepUpon stop

Bus release (BGRNT)

Upon resetDuring

hardware standbyHIZX=0 HIZX=1

P20-P27 D16-23 Output maintained or Hi-Z

The same as left Output Hi-Z / Input fixed to 0

Output Hi-Z

– D24-31

– A00-15 Output maintained (address output)

The same as left FFH output FFH output*

P60-P67 A16-23 P: Previous status

maintained

F: Address output

The same as left

– A24E0P0


The same as left

P80 RDY P: Previous status maintainedF: RDY input

P, F: Previous status maintained

P: Previous status maintainedF: RDY input

P81 BGRNTX P: Previous status maintainedF: H output


L output

P82 BRQ P: Previous status maintainedF: BRQ input

P, F: Previous

status maintainedBRQ input

– RDX Previous status maintained

The same as left H output H output*

– WR0X

P85 WR1X P: Previous status maintainedF: H output


H output*2

– CS0X Previous status maintained

The same as left L output L output*

PA1-PA2 CS1X -CS2X

P: Previous status maintainedF: CS output

P, F: Previous

status

maintained

H output H output*

PA3 CS3XE0P1

P: Previous status maintainedF: CS/E0P output


A4-PA5 CS4X-CS5X


P, F: Previous

status

maintained

PA6 CLK P: Previous status maintainedF: CLK output

P, F: Previous

status

maintained

CLK output CLK output

398


P: When a general-purpose port is specified, F: When a specified function is selected

Pin name: P27-P20

PB0 RAS0 P: Previous status maintainedF: Previous value maintainedOperates when the DRAM pin is set.In refresh mode

P: Previous statusF: Previous valueUpon refresh*1

Output Hi-Z / Input fixed to 0

P: Previous status maintainedF: Previous value maintainedOperates when the DRAM pin is set.In refresh mode

Output Hi-Z/All pin input enabled

Output Hi-Z

/ Input fixed

to 0

PB1 CS0L

PB2 CS0H Previous value maintained

PB3 DW0X

PB4 RAS1E0P2

Previous value maintained

PB5 CS1LDREQ2

PB6 CS1HDACK2


PB7 DW1X


Pin name


Bus release (BGRNT)

Upon resetDuring


*: Input fixed to 0

*1: Enters the self-refreshed status when the self-refresh is activated or maintains the previous status when the self-refresh is canceled.

*2: Becomes Hi-Z for a period immediately after reset.

399



Pin name: P27-P20


Pin name Function During sleepUpon stop

Bus release (BGRNT)

Upon reset

During hardware standbyHIZX=0 HIZX=1

AN0-AN3 AN0-3 Previous status

maintained

Previous

status

maintained

Output Hi-Z

/ All pins

input

enabled

PE0-PE2 INT0-INT2 Input enabled Input

enabled

Input

enabled

PE3 INT3

SC2

PE4-PE5 DREQ0-DREQ1

Previous

status

maintained

Output Hi-Z /

Input fixed to

0

Output

Hi-Z /

Input

fixed to

0

PE6-PE7 DACK0-DACK1

PF0 SI0TRG0

PF1 SO0

TRG1

PF2 SC0OCPA3

PF3 SI1TRG2

PF4 SO1TRG3

PF5 SI2OCPA1

PF6 SO2OCPA2

PF7 OCPA0ATGX

*: Input fixed to 0



400



Pin name


Bus release (BGRNT)

Upon resetDuring


P20-P27 D16-23 Output maintained or Hi-Z


Output Hi-Z

– D24-31




maintained

F: Address output

The same as left

– A24E0P0


The same as left






L output


P, F: Previous

status maintainedBRQ input



– WR0X

P85 WR1X P: Previous status maintainedF: H output


H output*2



PA1-PA2 CS1X -CS2X


P, F: Previous

status

maintained

H output H output*

PA3 CS3XE0P1



PA4-PA5 CS4X-CS5X


P, F: Previous

status

maintained


P, F: Previous

status

maintained


401



Pin name: P27-P20

PB0 RAS0 P: Previous status maintainedF: Previous value maintainedOperates when the DRAM pin is set.In refresh mode

P: Previous statusF: Previous valueUpon refresh*1


P: Previous status maintainedF: Previous value maintainedOperates when the DRAM pin is set.In refresh mode


Output Hi-Z

/ Input fixed

to 0

PB1 CS0L

PB2 CS0H Previous value maintained

PB3 DW0X

PB4 RAS1E0P2


PB5 CS1LDREQ2

PB6 CS1HDACK2


PB7 DW1X


Pin name


Bus release (BGRNT)

Upon resetDuring


*: Input fixed to 0



402



Pin name: P27-P20



Bus release (BGRNT)

Upon reset



maintained

Previous

status

maintained

Output Hi-Z

/ All pins

input

enabled


enabled

Input

enabled

PE3 INT3

SC2

PE4-PE5 DREQ0-DREQ1

Previous

status

maintained

Output Hi-Z /

Input fixed to

0

Output

Hi-Z /

Input

fixed to

0

PE6-PE7 DACK0-DACK1

PF0 SI0TRG0

PF1 SO0

TRG1

PF2 SC0OCPA3

PF3 SI1TRG2

PF4 SO1TRG3

PF5 SI2OCPA1

PF6 SO2OCPA2

PF7 OCPA0ATGX

*: Input fixed to 0



403


Table C-6 External 8-bit bus mode (1/2)

Pin name


Bus release (BGRNT)

Upon resetDuring


P20-P27 Port Previous status maintained



– D24-31 Output maintained or Hi-Z

The same as left Output Hi-Z




maintained

F: Address output

The same as left

– A24E0P0


The same as left






L output



BRQ input



– WR0X

P85 Port Previous status maintained

The same as left Previous value

maintained



PA1-PA2 CS1X -CS2X


P, F: Previous

status

maintained

H output H output*

PA3 CS3XE0P1



PA4-PA5 CS4X-CS5X


P, F: Previous

status

maintained

404



Pin name: P27-P20


P, F: Previous

status

maintained


PB0 RAS0 P: Previous status maintainedF: Previous value maintained*3

The same as leftUpon refresh *1


P: Previous status maintainedF: Previous value maintained*3


Output Hi-Z

/ Input fixed

to 0

PB1 CS0L

PB2 CS0H P: Previous status maintainedF: Previous value maintained

The same as left


PB3 DW0X P: Previous status maintainedF: Previous value maintained*3

The same as leftUpon refresh

*1

PB4 RAS1E0P2


PB5 CS1L

DREQ2 Previous value

maintained

PB6 CS1H P: Previous status maintainedF: Previous value maintained

The same as left Previous status maintained

DACK2 Previous value

maintained

PB7 DW1X P: Previous status maintainedF: Previous value maintained*3

The same as leftUpon refresh

*1


Pin name


Bus release (BGRNT)

Upon resetDuring


*: Input fixed to 0


*3: Operates when the DRAM pin is set.

405



Pin name: P27-P20



Bus release (BGRNT)

Upon reset



maintained

Previous

status

maintained

Output Hi-Z

/ All pins

input

enabled


enabled

Input

enabled

PE3 INT3

SC2

PE4-PE5 DREQ0-DREQ1

Previous

status

maintained

Output Hi-Z /

Input fixed to

0

Output

Hi-Z /

Input

fixed to

0

PE6-PE7 DACK0-DACK1

PF0 SI0TRG0

PF1 SO0

TRG1

PF2 SC0OCPA3

PF3 SI1TRG2

PF4 SO1TRG3

PF5 SI2OCPA1

PF6 SO2OCPA2

PF7 OCPA0ATGX

*: Input fixed to 0


*3: Operates when the DRAM pin is set.

406

APPENDIX D Precautions on Using the Little Endian Area


This appendix describes precautions when using the little endian area in terms of the following items:

D.1 C Compiler (fcc911)

D.2 Assembler (fasm911)

D.3 Linker (flnk911)

D.4 Debuggers (sim911, eml911, and mon911)

407


D.1 C Compiler (fcc911)

In programming in C, the operation is not guaranteed if the little endian area is manipulated as follows:• Placing a variable with an initial value• Substituting a structure• Manipulating a non-character array using a character string manipulation function• Specifying the -K lib option when using a character string manipulation function• Using the double and long double types• Placing a stack in the little endian area

Placing a Variable with an Initial Value

No variable with an initial value must be placed in the little endian area.

The compiler does not have a function of creating an initial value for the little endian area.A variable can be placed in the little endian area but an initial value cannot be set.

Provide the processing of setting an initial value at the beginning of a program.

[Example] Setting an initial value for the variable little_data in the little endian area

extern int little_data;

void little_init(void)

little_data = Initial value;

void main(void)

little_init();

...

408


Substituting a Structure

When substituting a structure for another structure, the compiler selects the most appropriatemethod of transferring data in bytes, half words, or words. Therefore, substituting a structurevariable assigned in the normal area into another structure assigned in the little endian areaprevents a correct result from being obtained.

Substitute members of a structure for those of another structure.

[Example] Substituting a structure in little_st in the little endian area

struct tag char c; int i; normal_st;

extern struct tag little_st;

#define STRMOVE(DEST,SRC) DEST.c=SRC.c;DEST.i=SRC.i;

void main(void)

STRMOVE(little_st,normal_st);

Members of a structure, being placed differently depending on the compiler, may be placeddifferently from those of another structure compiled by another compiler.

If this is the case, a correct result cannot be obtained by proceeding as above.

Do not place a structure variable in the little endian area unless the members of a structurematch.

Manipulating a Non-Character Array Using a Character String Manipulation Function

A character string manipulation function provided as a standard library processes data in bytes.Therefore, using the character string manipulation function to manipulate an area with typesother than char, unsigned char, or signed char placed in the little endian area prevents a correctresult from being obtained.

Do not perform such processing.

[Example of malfunction] Transferring word data using memcpy

int big = 0x01020304; /* Big endian area */

extern int little; /* Little endian area */

memcpy(&little,&big,4); /* Transfer using memcpy */

Executing the above ensures the following result, which is incorrect as a result of transferringword data.

01 02 03 04 01 02 03 04

(Big end ian area) (L i t t le end ian area)

(Correct resu l t )

memcpy

01020304

409


Specifying the -K lib option when using a character string manipulation function

Specifying the -K lib option causes the compiler to perform in-line expansion on some characterstring manipulation functions. At this time, the processing may be changed to manipulating datain half words or words in order to select the optimal processing.

Therefore, the processing on a little endian area is not performed correctly.

To perform processing using a character string manipulation function on the little endian area,do not specify the -K lib option.

Do not specify -04 or -K speed option either because these options include the -K lib option.

Using the double and long double types

Accessing the double and long double types accesses the upper one word and lower one word,respectively. Therefore, accessing double and long double type variables placed in the littleendian area prevents a correct result from being obtained.

Although variables of the same type assigned in the little endian area can be substituted, thesubstitution of these variables may be replaced with the substitution of constants as a result ofoptimization.

Do not place double and long double type variables in the little endian area.

[Example of malfunction] Transferring the double-type data

double big = 1.0; /* Big endian area */

extern int little; /* Little endian area */

little = big; /* Transferring the double type data */

Executing the above ensures the following result, which is incorrect as a result of transferringdouble type data.

Placing a Stack in the Little Endian Area

If all or part of a stack is placed in the little endian area, the operation is not guaranteed.

3f f0 00 00 00 00 00 00

(Big end ian area) (L i t t le end ian area)

(Correct resu l t )

3 ff00000 00 00 00 00

00 00 00 000000 3ff0

410


D.2 Assembler (fasm911)

This section provides precautions for the little endian area when programming in the FR-series assembler language.

Section

The little endian area is provided to exchange data with a little endian CPU. Therefore, definethe little endian area as a data section without an initial value.

If the little endian area is specified as a data section with a code or stack initial value, theaccess operation on the MB91101 cannot be guaranteed.

[Example]

/* Correct little endian area section definition */

.SECTION Little_Area, DATA, ALIGN=4

Little_Word:

.RES.W 1

Little_Half:

.RES.H 1

Little_Byte:

.RES.B 1

Data Access

To access data in the little endian area, the data value can be coded without being aware of theendian. However, access data in the little endian area using the same size as the data size.

[Example]

LDI #0x01020304, r0

LDI #Little_Word, r1

LDI #0x0102, r2

LDI #Little_Half, r3

LDI #0x01, r4

LDI #Little_Byte, r5

411


/* Access 32-bit data using the ST (or LD) instruction. */

ST r0, @r1

/* Access 16-bit data using the STH (or LDH) instruction. */

STH r2, @r3

/* Access 8-bit data using the STB (or LDB) instruction. */

STB r4, @r5

If data is accessed on the MB91101 using a different size than the data size, the value cannotbe guaranteed. For example, if two successive 16-bit data pieces are accessed at once using a32-bit access instruction, the data value cannot be guaranteed.

412


D.3 Linker (flnk911)

This section provides precautions when placing sections for linking when creating a program that uses the little endian area.

Restriction on Section Types

Only a data section without an initial value can be placed in the little endian area.

If a data section, stack section, or code section with an initial value is placed in the little endianarea, the program operation cannot be guaranteed because the linker internally performsoperation processing such as address solution using the big endian.

Not Detecting an Error

The linker, not recognizing the little endian area, does not issue an error message if a section isplaced in violation of the above restriction. Check the contents of a section placed in the littleendian area before using the linker.

413


D.4 Debuggers (sim911, eml911, and mon911)

This section describes precautions when using the simulator debugger and the emulator and monitor debuggers.

Simulator Debugger

The simulator debugger does not provide a memory space specification command that specifiesthe little endian area.

Therefore, a command or an instruction that manipulates memory is used as the big endian.

Emulator and Monitor Debuggers

If the little endian area is accessed using the following commands, the data is not used as acorrect value.

set memory, show memory, enter, examine, and set watch commands

Cannot set or display a specified value if floating-point (single or double) data is used.

search memory command

Cannot search for a specified value if half word or word data is searched.

Line assemble or disassemble (including displaying disassembled data in a source window)

Cannot set or display a normal instruction code (do not place an instruction code in the littleendian area).

call and show call commands

Do not operate if a stack area is placed in the little endian area (do not place a stack area in thelittle endian area).

414

APPENDIX E Instruction (165 Instruction)


The FR Series instructions are listed here. To assist in an understanding of the instruction list, the following items are explained first:• How to Read Instruction Set Summary• Addressing Mode Symbols• Instruction Types

How to Read Instruction Set Summary

Mnemonic Type OP CYCLE NZVC Operation Remarks

ADD*ADD

Rj,#s5,

,,

RiRi

AC,,

A6A4,,

11,,

CCCCCCCC

,,

Ri + Rj --> RiRi + s5 --> Ri

,,

(1) (2) (3) (4) (5) (6) (7)

(1) Name of instructions

Instructions marked with * are not included in CPU specifications. These are extended instruction codes added/extended at assembly language levels.

(2) Addressing modes specified as operands are listed in symbols.

Refer to “2. Addressing mode symbols” for further information.

(3) Instruction types

(4) Hexa-decimal expressions of instructions

(5) The number of machine cycles needed for execution

a: Memory access cycle and it has possibility of delay by Ready function.

b: Memory access cycle and it has possibility of delay by Ready function.If an object register in a LD operation is referenced by an immediately following instruction, the interlock function is activated and number of cycles needed for execution increases.

c: If an immediate following instruction operates to an object of R15, SSP or USP in read/write mode or if the instruction belongs to instruction format A group, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed.

415


d: If an immediate following instruction refers to MDH/MDL, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed.

For a, b, c and d, minimum execution cycle is 1.

(6) Change in flag sign

• Flag changeC: change−: No change0; Clear1: Set

• Flag meaningsN: Negative flagZ: Zero flagV: Over flageC: Carry flag

(7) Operation carried out by instruction

416


Addressing Mode Symbols

Ri : Register direct (R0 to R15,AC,FP,SP)

Rj : Register direct (R0 to R15,AC,FP,SP)

R13 : Register direct (R13,AC)

Ps : Register direct (Program status register)

Rs : Register direct (TBR,RP,SSP,USP,MDH,MDL)

CRi : Register direct (CR0 to CR15)

CRj : Register direct (CR0 to CR15)

#i8 : Unsigned 8-bit immediate (-128 to 255) Note: -128 to -1 are interpreted as 128 to 255.

#i20 : Unsigned 20-bit immediate (-0X80000 to 0XFFFFF) Note: -0X7FFFF to -1 are interpreted as 0X7FFFF to 0XFFFFF.

#i32 : Unsigned 32-bit immediate (-0X80000000 to 0XFFFFFFFF) Note: -0X80000000 to -1 are interpreted as 0X80000000 to 0XFFFFFFFF.

#s5 : Signed 5-bit immediate (-16 to 15)

#s10 : Signed 10-bit immediate (-512 to 508, multiple of 4 only)

#u4 : Unsigned 4-bit immediate (0 to 15)



#u10 : Unsigned 10-bit immediate (0 to 1020, multiple of 4 only)

@dir8 : Unsigned 8-bit direct address (0 to 0XFF)

@dir9 : Unsigned 9-bit direct address (0 to 0X1FE, multiple of 2 only)

@dir10 : Unsigned 10-bit direct address (0 to 0X3FC, multiple of 4 only)

label9 : Signed 9-bit branch address (-0X100 to 0XFC, multiple of 2 only)

label12 : Signed 12-bit branch address (-0X800 to 0X7FC, multiple of 2 only)

label20 : Signed 20-bit branch address (-0X80000 to 0X7FFFF)

label32 : Signed 32-bit branch address (-0X80000000 to 0X7FFFFFFF)

@Ri : Register indirect (R0 to R15, AC, FP, and SP)

@Rj : Register indirect (R0 to R15, AC, FP, and SP)

@(R13, Rj) : Register relative indirect (Rj: R0 to R15, AC, FP, and SP)

@(R14 ,disp10) : Register relative indirect (disp10: -0X200 to 0X1FC, multiple of 4 only)

@(R14, disp9) : Register relative indirect (disp9: -0X100 to 0XFE, multiple of 2 only)

@(R14, disp8) : Register relative indirect (disp8: -0X80 to 0X7F)

417


@(R15, udisp6) : Register relative indirect (udisp6: 0 to 60, multiple of 4 only)

@Ri+ : Register indirect with post-increment (R0 to R15, AC, FP, and SP)

@R13+ : Register indirect with post-increment (R13, AC)

@SP+ : Stack pop

@-SP : Stack push

(reglist) : Register list

418


Instruction Types

Type A

Type B

Type C

Type *C’

Type D

Type E

Type F

MSB LSB16bi t

OP Rj Ri

8 4 4

OP i8/o8 Ri

4 8 4

OP u4/m4 Ri

8 4 4

ADD,ADDN,CMP,LSL,LSR and ASR ins t ruc t ions on ly

7 5 4

OP Ris5/u5

OP u8/re l8 /d i r / reg l is t

8 8

OP SUB-OP Ri

8 4 4

OP re l11

5 11

419


Detailed Description of Instructions

Table E-1 Add/subtract Operation Instructions (10 Instructions)

Mnemonic Type OP Cycle NZVC Operation Remarks

ADD Rj, Ri*ADD #s5, Ri

ADD #i4, RiADD2 #i4, Ri

AC’

CC

A6A4

A4A5

11

11

CCCCCCCC

CCCCCCCC

Ri + Rj --> Ri Ri + s5 --> Ri

Ri + extu(i4) --> RiRi + extu(i4) --> Ri

MSB is interpreted as a sign in assembly language Zero-extensionSign-extension

ADDC Rj, Ri A A7 1 CCCC Ri + Rj + c --> Ri Add operation with sign

ADDN Rj, Ri*ADDN #s5, Ri

ADDN #i4, RiADDN2#i4, Ri

AC'

CC

A2A0

A0A1

11

11

--------

--------

Ri + Rj --> RiRi + s5 --> Ri

Ri + extu(i4) --> RiRi + extu(i4) --> Ri


SUB Rj, Ri A AC 1 CCCC Ri - Rj --> Ri

SUBC Rj, Ri A AD 1 CCCC Ri - Rj - c --> Ri Subtract operation with carry

SUBN Rj, Ri A AE 1 ---- Ri - Rj --> Ri

Table E-2 Compare Operation Instructions (3 Instructions)


CMP Rj, Ri*CMP #s5, Ri

CMP #i4, RiCMP2 #i4, Ri

AC'

CC

AA A8

A8A9

11

11

CCCCCCCC

CCCCCCCC

Ri - RjRi - s5

Ri + extu(i4)Ri + extu(i4)


Table E-3 Logical Operation Instructions (12 Instructions)


AND Rj, RiAND Rj, @RiANDH Rj, @RiANDB Rj, @Ri

AAAA

82848586

11+2a1+2a1+2a

CC--CC--CC--CC--

Ri &= Rj(Ri) &= Rj(Ri) &= Rj(Ri) &= Rj

WordWordHalfwordByte

OR Rj, RiOR Rj, @RiORH Rj, @RiORB Rj, @Ri

AAAA

92949596

11+2a1+2a1+2a

CC--CC--CC--CC--

Ri |= Rj(Ri)|= Rj(Ri)|= Rj(Ri)|= Rj


EOR Rj, RiEOR Rj, @RiEORH Rj, @RiEORB Rj, @Ri

AAAA

9A9C9D9E

11+2a1+2a1+2a

CC--CC--CC--CC--

Ri ^= Rj(Ri)^= Rj(Ri)^= Rj(Ri)^= Rj


420


Table E-4 Bit Manipulation Arithmetic Instructions (8 Instructions)


BANDL #u4, @Ri (u4: 0 to 0FH)BANDH #u4, @Ri (u4: 0 to 0FH)*BAND #u8, @Ri*1

C

C

80

81

1+2a

1+2a

----

----

----

(Ri)&=(0xF0+u4)

(Ri)&=((u4<<4)+0FH)

(Ri)&=u8

Manipulate lower 4 bits

Manipulate upper 4 bits

BORL #u4, @Ri (u4: 0 to 0FH)BORH #u4, @Ri (u4: 0 to 0FH)*BOR #u8, @Ri*2

C

C

90

91

1+2a

1+2a

----

----

----

(Ri)|= u4

(Ri)|= (u4<<4)

(Ri)|= u8



BEORL #u4, @Ri (u4: 0 to 0FH)BEORH#u4, @Ri (u4: 0 to 0FH)*BEOR #u8, @Ri*3

C

C

98

99

1+2a

1+2a

----

----

----

(Ri)^= u4

(Ri)^= (u4<<4)

(Ri)^= u8



BTSTL #u4, @Ri (u4: 0 to 0FH)BTSTH #u4, @Ri (u4: 0 to 0FH)

C

C

88

89

2+a

2+a

0C--

CC--

(Ri) & u4

(Ri) & (u4<<4)

Test lower 4 bits

Test upper 4 bits

*1 Assembler generates BANDL if result of logical operation "u8&0×0F" leaves an active (set) bit and generates BANDH if "u8&0×F0" leaves an active bit. Depending on the value in the "u8" format, both BANDL and BANDH may be generated.

*2 Assembler generates BORL if result of logical operation "u8&0×0F" leaves an active (set) bit and generates BORH if "u8&0×F0" leaves an active bit.

*3 Assembler generates BEORL if result of logical operation "u8&0×0F" leaves an active (set) bit and generates BEORH if "u8&0×F0" leaves an active bit.

421


Table E-5 Add/subtract Operation Instructions (10 instructions)


MUL Rj,RiMULU Rj,RiMULH Rj,RiMULUH Rj,Ri

AAAA

AFABBFBB

5533

CCC-CCC-CC--CC--

Rj × Ri --> MDH,MDLRj × Ri --> MDH,MDLRj × Ri --> MDLRj × Ri --> MDL

32-bit × 32-bit = 64-bitUnsigned16-bit × 16-bit = 32-bitUnsigned

DIVOS RiDIVOU RiDIV1 RiDIV2 RiDIV3DIV4S*DIV Ri*1

*DIVU Ri*2

EEEEEE

97-497-597-697-79F-69F-7

11d111-

-

--------

-C-C-C-C--------

-C-C

-C-C

MDL / Ri --> MDL , MDL % Ri --> MDHMDL / Ri --> MDL , MDL % Ri --> MDH

Step operation32bit/32bit=32bit

Unsigned

*1 DIVOS, DIV 1× 32, DIV2, DIV3, and DIV4S are generated. The instruction code length of 72 bytes.

*2 DIVOU and DIV 1× 32 are generated. A total intstruction code length of 66 bytes.

Table E-6 Shift Arithmetic Instructions (9 Instructions)


LSL Rj, Ri*LSL #u5, Ri LSL #u4, RiLSL2 #u4, Ri

AC'CC

B6B4B4B5

1111

CC-CCC-CCC-CCC-C

Ri << Rj --> RiRi << u5 --> RiRi << u4 --> RiRi <<(u4+16) --> Ri

Logical shift

LSR Rj, Ri*LSR #u5, RiLSR #u4, RiLSR2 #u4, Ri

AC'CC

B2B0B0B1

1111

CC-CCC-CCC-CCC-C

Ri >> Rj --> RiRi >> u5 --> RiRi >> u4 --> RiRi >>(u4+16) --> Ri

Logical shift

ASR Rj, Ri*ASR #u5, Ri ASR #u4, RiASR2 #u4, Ri

AC'CC

BAB8B8B9

1111

CC-CCC-CCC-CCC-C

Ri >> Rj --> RiRi >> u5 --> RiRi >> u4 --> RiRi >>(u4+16) --> Ri

Logical shift

422


Table E-7 Immediate Value Data Transfer Instruction (Immediate Value Set /16-bit/32-bit Immediate Value Transfer Instructions) (3 Instructions)


LDI:32 #i32, RiLDI:20 #i20, Ri

LDI:8 #i8, Ri

*LDI #i8|i20|i32,Ri*1

EC

B

9F-89B

C0

32

1

--------

----

i32 --> Rii20 --> Ri

i8 --> Ri

i8|i20|i32 --> Ri

Upper 12 bits are Zero extendedUpper 24 bits are Zero extended

* If an immediate value is given in absolute, assembler automatically makes i8, i20, or i32 selection.If an immediate value contains relative value or external reference, assembler selects i32.

Table E-8 Memory Load Instructions (13 Instructions)


LD @Rj, RiLD @(R13,Rj), RiLD @(R14,disp10), RiLD @(R15,udisp6), RiLD @R15+, RiLD @R15+, Rs

LD @R15+, PS

AABCEE

E

04002003

07-007-8

07-9

bbbbbb

1+a+b

------------------------

CCCC

(Rj) --> Ri(R13 + Rj) --> Ri(R14 + disp10) --> Ri(R15 + udisp6) --> Ri(R15) --> Ri,R15 + = 4(R15) --> Rs,R15 + = 4

(R15) --> PS,R15 + = 4

Rs: Special-purpose register

LDUH @Rj, RiLDUH @(R13,Rj), RiLDUH @(R14,disp9), Ri

AAB

050140

bbb

------------

(Rj) --> Ri(R13 + Rj) --> Ri(R14 + disp9) --> Ri

Zero extensionZero extensionZero extension

LDUB @Rj, RiLDUB @(R13,Rj), RiLDUB @(R14,disp8), Ri

AAB

060260

bbb

------------

(Rj) --> Ri(R13 + Rj) --> Ri(R14 + disp8) --> Ri

Zero extensionZero extensionZero extension

Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler description from disp8 to disp10 are as follows:

disp8 --> o8 = disp8disp9 --> o8 = disp9>>1disp10 --> o8 = disp10>>2udisp6 --> u4 = udisp6>>2

Each disp is a code extension.

udisp4 is a 0 extension

423


Table E-9 Memory Store Instructions (13 Instructions)


ST Ri, @RjST Ri, @(R13,Rj)ST Ri, @(R14,disp10)ST Ri, @(R15,udisp6)ST Ri, @-R15ST Rs, @-R15

ST PS, @-R15

AABCEE

E

14103013

17-017-8

17-9

aaaaaa

a

------------------------

----

Ri-->(Rj)Ri-->(R13 + Rj)Ri-->(R14 + disp10)Ri-->(R15 + udisp6)R15 - = 4,Ri-->(R15)R15 - = 4,Rs-->(R15) R15- = 4,PS-->(R15)

WordWordWord

Rs: Special-purpose register

STH Ri, @RjSTH Ri, @(R13,Rj)STH Ri, @(R14,disp9)

AAB

151150

aaa

------------

Ri-->(Rj)Ri-->(R13+Rj)Ri-->(R14+disp9)

Half wordHalf wordHalf word

STB Ri, @RjSTB Ri, @(R13,Rj)STB Ri, @(R14,disp8)

AAB

161270

aaa

------------

Ri-->(Rj)Ri-->(R13+Rj)Ri-->(R14+disp8)

ByteByteByte

Note: The relations between o8 field of TYPE-B and u4 field of TYPE-C in the instruction format and assembler description from disp8 to disp10 are as follows:

disp8 --> o8 = disp8disp9 --> o8 = disp9>>1disp10 --> o8 = disp10>>2udisp6 --> u4 = udisp6>>2


udisp4 is a 0 extension

Table E-10 Transfer Instructions Between Registers/Special-purpose Registers Transfer Instructions (5 Instructions)


MOV Rj, Ri

MOV Rs, RiMOV Ri, RsMOV PS, RiMOV Ri, PS

A

AAEE

8B

B7B3

17-107-1

1

111c

----

------------

CCCC

Rj --> Ri

Rs --> RiRi --> RsPS --> RiRi --> PS

Transfer between general-purpose registersRs: Special-purpose registerRs: Special-purpose register

424


Table E-11 Non-delay Normal Branch Instruction (23 Instructions)


JMP @Ri E 97-0 2 ---- Ri --> PC

CALL label12CALL @Ri

FE

D097-1

22

--------

PC + 2 --> RP,PC + 2 + rel11 × 2 --> PCPC + 2 --> RP, Ri --> PC

RET E 97-2 2 ---- RP --> PC Return

INT#u8 D 1F 3+3a ---- SSP - = 4, PS --> (SSP), SSP - = 4, PC + 2 --> (SSP),0 --> I flag,0-->S flag (TBR + 3FC - u8 × 4) -->PC

INTE E 9F-3 3+3a ---- SSP - = 4, PS --> (SSP), SSP - = 4, PC + 2 --> (SSP),0 --> I flag,0 --> S flag (TBR + 3FC - u8 × 4) --> PC

For emulator

RETI E 97-3 2+2a CCCC (R15) --> PC, R15 - = 4,(R15) --> PS, R15 - = 4

BNO label9BRA label9BEQ label9BNE label9BC label9BNC label9BN label9BP label9BV label9BNV label9BLT label9BGE label9BLE label9BGT label9BLS label9BHI label9

DDDDDDDDDDDDDDDD

E1E0E2E3E4E5E6E7E8E9EAEBECEDEEEF

12

2/12/12/12/12/12/12/12/12/12/12/12/12/12/1

----------------------------------------------------------------

Non-branchPC + 2 + rel8 × 2 --> PCPCif Z == 1PCif Z == 0PCif C == 1PCif C == 0PCif N == 1PCif N == 0PCif V == 1PCif V == 0PCif V xor N == 1PCif V xor N == 0PCif (V xor N) or Z == 1PCif (V xor N) or Z == 0PCif C or Z == 1PCif C or Z == 0

Notes: • "2/1" in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch.

• The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and asembler discription label9 and label12 are as follows.label9 --> rel8 = (lable9 - PC - 2) / 2 label12 --> rel11 (label12 - PC - 2) /2

• RETI must be operated while S flag = 0.

425


Table E-12 Branch Instructions with Delays (20 Instructions)


JMP:D @Ri E 9F-0 1 ---- Ri --> PC

CALL:D label12

CALL:D @Ri

F

E

D8

9F-1

1

1

----

----

PC + 4 --> RP ,PC+ 2+ rel11× 2 --> PCPC + 4 --> RP, Ri --> PC

RET:D E 9F-2 1 ---- RP --> PC Return

BNO:D label9BRA:D label9BEQ:D label9BNE:D label9BC:D label9BNC:D label9BN:D label9BP:D label9BV:D label9BNV:D label9BLT:D label9BGE:D label9BLE:D label9BGT:D label9BLS:D label9BHI:D label9

DDDDDDDDDDDDDDDD

F1F0F2F3F4F5F6F7F8F9FAFBFCFDFEFF

1111111111111111

----------------------------------------------------------------

Non-branchPC + 2 + rel8 × 2 -->PCPCif Z == 1PCif Z == 0PCif C == 1PCif C == 0PCif N == 1PCif N == 0PCif V == 1PCif V == 0PCif V xor N == 1PCif V xor N == 0PCif (V xor N) or Z == 1PCif (V xor N) or Z == 0PCif C or Z == 1PCif C or Z == 0

Notes: • The relations between rel8 field of TYPE-D and rel11 field of TYPE-F in the instruction format and asembler discription label9 and label12 are as follows.label9 --> rel8 = (lable9 - PC - 2) / 2 label12 --> rel11 (label12 - PC - 2) /2

• Delayed branch operatation always executes next instruction (delay slot) before making a branch.

• Instructions allowed to be stored in the delay slot must meet one of the following conditions. If the other instruction is stored, this device may operate other operation than defined.The instruction described "1" in the other cycle column than branch instruction.The instruction described "a", "b", "c" or "d" in the cycle column.

426


Table E-13 Direct Addressing Instructions


DMOV @dir10, R13DMOV R13, @dir10DMOV @dir10, @R13+DMOV @R13+, @dir10DMOV @dir10, @-R15DMOV @R15+, @dir10

DDDDDD

08180C1C0B1B

ba

2a2a2a2a

------------------------

(dir10) --> R13R13 -->(dir10)(dir10) -->(R13),R13+=4(R13) -->(dir10),R13+=4R15-=4,(dir10) -->(R15)(R15) -->(dir10),R15+=4

WordWordWordWordWordWord

DMOVH @dir9, R13DMOVH R13, @dir9DMOVH @dir9, @R13+DMOVH @R13+, @dir9

DDDD

09190D1D

ba

2a2a

----------------

(dir9) --> R13R13 -->(dir9)(dir9) -->(R13),R13+=2(R13) -->(dir9),R13+=2

Half wordHalf wordHalf wordHalf word

DMOVB @dir8, R13DMOVB R13, @dir8DMOVB @dir8, @R13+DMOVB @R13+, @dir8

DDDD

0A1A0E1E

ba

2a2a

----------------

(dir8) --> R13R13 -->(dir8)(dir8) -->(R13),R13++(R13) -->(dir8),R13++

ByteByteByteByte

Note: The relations between the dir field of TYPE-D in the instruction format and the assembler description from disp8 to disp10 are as follows:

disp8 --> dir + disp8disp9 --> dir = disp9>>1disp10 --> dir = disp10>>2


Table E-14 Resource Instructions (2 Instructions)


LDRES @Ri+,#u4

STRES #u4, @Ri+

C

C

BC

BD

a

a

----

----

(Ri) -->u4 resourceRi+=4u4 resource -->(Ri)Ri+=4

u4: Channel number

u4: Channel number

Table E-15 Co-processor Instructions (4 Instructions)


COPOP #u4,#CC,CRj,CRiCOPLD #u4,#CC,Rj, CRiCOPST #u4,#CC,CRj,RiCOPSV #u4,#CC,CRj,Ri

EEEE

9F-C9F-D9F-E9F-F

2+a1+2a1+2a1+2a

----------------

CalculationRj --> CRiCRj --> RiCRj --> Ri No error

traps

427

INDEX

INDEX

The index follows on the next page.This is listed in alphabetic order.

428

INDEX

Index

Numerics

0 detection............................................................3771 detection............................................................37716/8-bit data, data transfer section.......................36716/8-bit data, transfer stop timing chart in continuous

transfer mode.............................................36916-bit reload register (TMRLR).............................24016-bit reload timer, block diagram of....................23716-bit reload timer, list of ......................................23616-bit timer register (TMR) ...................................2401-detection data register (BSD1)..........................37532-bit-16-bit bus converter .....................................38

A

A/D converter operation mode .............................309A/D converter, block diagram of...........................302A/D converter, feature of ......................................300A/D converter, other precaution for ......................313A/D converter, register list of ................................301access mode ..........................................................86activating channel of PWM timer with software....267activating using 16-bit reload timer.......................268addressing mode symbol .....................................416area mode register 0 (AMD 0), bit functions of.....136area mode register 0 (AMD 0), configuration of ...136area mode register 1 (AMD 1), bit functions of.....138area mode register 1 (AMD 1), configuration of ...138area mode register 32 (AMD 32), bit functions of.......

...................................................................139area mode register 32 (AMD 32), configuration of .....

...................................................................139area mode register 4 (AMD 4), bit functions of.....140area mode register 4 (AMD 4), configuration of ...140area mode register 5 (AMD 5), bit functions of.....141area mode register 5 (AMD 5), configuration of ...141area select register (ASR) and area mask register

(AMR), configurations of ............................133arithmetic instruction, bit manipulation .................420assembler source, example of .............................123asynchronous (start-stop transmission) mode,

transfer data format in ................................327automatic wait cycle in CBR refresh.....................209automatic wait cycle timing...................................188automatic wait cycle timing for normal DRAM interface

...................................................................198

B

basic programming group ...................................... 52basic read cycle timing......................................... 179basic write cycle timing ........................................ 181baud rate and U-TIMER reload value setting,

example of ................................................. 335baud rate calculation............................................ 233Bit......................................................................... 238bit manipulation arithmetic instruction.................. 420bit search module register, list of ......................... 374bit search module, block diagram of .................... 374block diagram........................................... 10, 90, 107block using peripheral system clock, list of .......... 126branch instruction with delay................................ 425built-in DC-DC regulator, precautions at using ...... 30burst transfer (CLK doubler used, internal descriptor)

................................................................... 356burst transfer mode.............................................. 352bus interface ........................................................ 131bus interface area ................................................ 130bus mode ............................................................... 86bus mode setting bit............................................... 87bus right, obtaining............................................... 210bus right, releasing............................................... 210bus size specification........................................... 131bus width combination ......................................... 144byte access.......................................................... 169

C

cache entry, update of ........................................... 47cache state in each operation mode...................... 46cacheable area ...................................................... 48CAS before RAS (CBR) refresh........................... 208CCR (condition code register)................................ 55channel priority..................................................... 360character string manipulation function, manipulating

non-character array using.......................... 408circuit handling....................................................... 29CLK synchronous mode, transfer data format in .......

................................................................... 328clock doubler function, combination of operating

frequencies by ON/OFF of......................... 119clock doubler function, precaution for ON-OFF of .....

................................................................... 119clock doubler function, starting ............................ 118

429

INDEX

clock doubler function, stopping........................... 118clock for UART, selection of................................. 325clock generator (power-saving mechanism), features of

..................................................................... 89clock selection...................................................... 211clock system reference diagram .......................... 123combination of request sense and transfer modes ....

................................................................... 353continuous transfer .............................................. 361continuous transfer (CLK doubler used, internal descriptor)

................................................................... 355continuous transfer mode .................................... 351continuous transfer mode, transfer stop timing chart

in, 16/8-bit data .......................................... 369control register ..................................................... 295control register configuration.................................. 44control status register (ADCS), bit function of...... 303control status register (ADCS), configuration of... 303control status register (PCNH, PCHL), bit function of

................................................................... 250control status register (PCNH, PCHL), configuration of

................................................................... 250control status register (TMCSR), configuration of 238control status register, bit function of ................... 238conversion data protection function ..................... 311co-processor instruction....................................... 426counter, operation state of ................................... 243CPU ....................................................................... 36CPU state, pin status in ....................................... 397CTBR (time base timer clear register) ................... 95

D

data access.................................................... 65, 410data bus width.............................................. 158, 165data direction register (DDR), configuration of..... 220data format................................................... 157, 163data register (ADCR), configuration of................. 308data register, variation point detection (BSDC).... 376data structure ......................................................... 64data transfer section, 16/8-bit data ...................... 367debugger, emulator and monitor.......................... 413debugger, simulator ............................................. 413delayed interrupt control register (DICR), bit function of

................................................................... 279delayed interrupt control register (DICR),

configuration of .......................................... 279delayed interrupt module, block diagram of ......... 278delayed interrupt module, register list of .............. 278delayed slot............................................................ 74

descriptor access section .....................................365descriptor, first word of .........................................347descriptor, second word of ...................................349descriptor, third word of ........................................349detection data register 0 (BSD0) ..........................375detection data register 1 (BSD1) ..........................375detection result register (BSRR)...........................376detection, 0 ...........................................................377detection, 1 ...........................................................377detection, variation point.......................................378diagram of external dimensions (reference diagram) .

.....................................................................13difference between MB91101 and MB91101A. ........8direct addressing area ............................................66direct addressing instruction.................................426DLYI bit of DICR ...................................................280DMA disabled .......................................................116DMA transfer inhibited if interrupt with high ...............

priority occurs .............................................360DMA transfer request cause.................................362DMA transfer request, using resource interrupt

request as a................................................360DMAC control status register (DACSR), bit function of

...................................................................343DMAC control status register (DACSR), configuration of

...................................................................342DMAC internal register, transfer to .......................361DMAC parameter descripter pointer (DPDP) .......341DMAC pin control register (DATCR), bit function of ...

...................................................................345DMAC pin control register (DATCR), configuration of

...................................................................344DMAC register, list of............................................339DMAC, block diagram of.......................................340DMAC, feature of..................................................338double type and long double type, using ..............409DRAM control pin .................................................172DRAM control register 4 and 5 (DMCRs 4 and 5), bit

functions of .................................................142DRAM control registers 4 and 5 (DMCRs 4 and 5),

configuration of...........................................142DRAM device connection, example of..................174DRAM interface ............................................131, 176DRAM interface timing in fast page mode ............199DRAM refresh.......................................................178DRAM signal control register (DSCR), bit functions of

...................................................................151DRAM signal control register (DSCR), configuration of

...................................................................151DREQ signal, sense mode of ...............................353

430

INDEX

E

EIT (exception/interrupt/trap) .................................72EIT cause ...............................................................72EIT vector table ......................................................77EIT, operation of.....................................................81emulator and monitor debuggers .........................413enable interrupt request register (ENIR) ..............271error not detected.................................................412external bus access .............................................159external bus interface, block diagram of...............129external bus interface, features of ........................128external bus interface, list of registers of..............132external bus operation program example.............212external bus request.............................................178external clock, precaution at using.........................30external interrupt level ..........................................275external interrupt operation ..................................274external interrupt operation, procedure for ...........274external interrupt request register (EIRR) ............272external interrupt/NMI controller, block diagram of.....

...................................................................270external interrupt/NMI controller, register list of....270external level register (ELVR) ..............................273external pin control register 0 (EPCR 0), bit functions of

...................................................................147external pin control register 0 (EPCR 0), configuration

of ................................................................147external pin control register 1 (EPCR 1), bit functions of

...................................................................150external pin control register 1 (EPCR 1), configuration

of ................................................................150external pin function (I/O port or control pin), selection

of ................................................................221external reset input, precaution at using

.....................................................................30external wait cycle timing .....................................189

F

feature ......................................................................2first word of descriptor..........................................347flag and interrupt occurrence ...............................330

G

GCR (gear control register) ....................................96gear function ........................................................112general control register 1 (GCN1), bit function of.258general control register 1 (GCN1), configuration of....

...................................................................257general control register 2 (GCN2) ........................260

general-purpose register........................................ 54

H

half word access .................................................. 168hardware configuration ........................................ 296hardware standby .................................................. 32Harvard-Princeton bus converter ........................... 38hold request cancel request, generation standard for

................................................................... 294hold request cancel request, level to be set for ... 294hold request cancel request, sequence of ........... 296hold request cancel request/level setting register

(HRCL), bit function of ............................... 288hold request cancel request/level setting register

(HRCL), configuration of ............................ 288hyper DRAM interface in read timing................... 205hyper DRAM interface in write timing................... 206hyper DRAM interface timing............................... 207

I

I flag ....................................................................... 73I/O map reading ................................................... 382I/O mapping ......................................................... 383I/O port register .................................................... 218I/O port, basic block diagram of ........................... 218I-chache, setting for use......................................... 49ICR (interrupt control register) ............................... 75ILM................................................................... 57, 74inhibiting DMA transfer if interrupt with high priority

occurs ....................................................... 360initial value, placing variable with......................... 407input/output circuit type.......................................... 23instruction cache.............................................. 38, 41instruction set summary reading .......................... 414instruction set summary, how to read .................. 414instruction type..................................................... 418instruction, bit manipulation arithmetic................. 420instruction, detailed description of........................ 419instruction, memory load...................................... 422instruction, memory store..................................... 423instruction, non-delay normal branch................... 424instruction, outline of .............................................. 39instruction, shift arithmatic ................................... 421INT instruction, operation of................................... 82INTE instruction, operation of ................................ 83internal architecture ............................................... 36internal clock operation........................................ 241interrupt................................................................ 265interrupt control register (ICR), bit function of ...... 286

431

INDEX

interrupt control register (ICR), configuration of... 286interrupt controller, block diagram of.................... 285interrupt controller, hardware configuration of ..... 282interrupt controller, main function of..................... 282interrupt controller, register list of......................... 282interrupt flag timing setting during receive operation in

mode 0....................................................... 330interrupt flag timing setting during receive operation in

mode 1....................................................... 331interrupt flag timing setting during receive operation in

mode 2....................................................... 331interrupt flag timing setting during send operation in

mode 0, mode 1, and mode 2.................... 332interrupt level ......................................................... 72interrupt number................................................... 280interrupt occurrence and flag ............................... 330interrupt source, release of .................................. 292interrupt stack ........................................................ 76interrupt vector ..................................................... 392interrupt with high priority, inhibiting DMA transfer ....

................................................................... 360interrupt/NMI, level mask for .................................. 74

K

-K lib option specifying when using character stringmanipulation function................................. 409

L

latch-up prevention ................................................ 28level mask for interrupt/NMI ................................... 74little endian area, placing stack in ........................ 409little endian bus access, overview of.................... 163little endian register (LER), bit functions of .......... 153little endian register (LER), configuration of......... 153logical operation instruction ................................. 419

M

MB91101 connection to external device, example of................................................................... 166

MB91101 connection with external device, example of................................................................... 162

MB91101, precaution on...................................... 361memory load instruction....................................... 422memory map .......................................................... 66memory space ....................................................... 34memory store instruction...................................... 423mode data ...................................................... 87, 154mode pin ................................................................ 86mode symbol addressing ..................................... 416

multi-EIT processing...............................................79multiply & divide register.........................................63

N

NMI .......................................................................292NMI operation .......................................................276non maskable interrupt (NMI) ...............................292non-character array manipulation using character

string manipulation function........................408non-delay normal branch instruction ....................424normal bus access................................................176normal DRAM interface in read timing..................190normal DRAM interface in write timing .................192normal DRAM read cycle timing ...........................194normal DRAM write cycle timing...........................196

O

o-detection data register (BSD0) ..........................375one-short operation ..............................................263operating frequencies combination by ON/OFF of

clock doubler function.................................119operation instruction, add/subtract .......................419operation instruction, add/subtract (10 instructions)...

...................................................................421operation instruction, compare .............................419operation instruction, logical .................................419operation mode.......................................................86operation of EIT ......................................................81operation of INT instruction ....................................82operation of INTE instruction ..................................83operation of RETI instruction ..................................84operation of step trace trap.....................................83operation of undefined instruction exception ..........83operation of user interrupt/NMI...............................81operation with delayed slot .....................................68operation without delayed slot ................................70operation, list of ....................................................102other bit...................................................................87

P

package and product type support ...........................8PC (program counter).............................................58PCTR (PLL control register) .................................101PDRR (DMA request disable register)..................100peripheral system clock, list of block using...........126pin array diagram....................................................11pin description, list of ..............................................15pin processing handling..........................................28pin state ..................................................................32

432

INDEX

pin status in CPU state.........................................397pin status, terminogogy used in list of ..................396pipeline system of CPU..........................................37PLL clock setting, example of ..............................122port data register (PDR), configuration of.............219power-on reset .................................................32, 85precaution at using built-in DC-DC regulator..........30precaution at using external clock..........................30precaution at using external reset input .................30precaution during input source clock frequency.....32precaution using STOP mode ................................31precaution when using A/D converter ..................313priority determination............................................289product type configuration........................................7program access......................................................65PS (program status) ...............................................55PWM cycle setting register (PCSR) .....................254PWM duty setting register (PDUT).......................255PWM operation ....................................................261PWM output all "L" and all "H"..............................266PWM timer channel activating using software......267PWM timer one channel, block diagram of...........249PWM timer register (PTMR).................................256PWM timer register, list of ....................................247PWM timer, feature of ..........................................246PWM timer, general block diagram of ..................248

R

read cycle timing ..................................................183read/write mixed cycle timing ...............................187refresh control register (RFCR), bit functions of...145refresh control register (RFCR), configuration of .145register in U-TIMER, list of ...................................230register, list of .........................................................89register/special-purpose register transfer instruction .

...................................................................423relationship between data bus widths and control

signals ........................................................155reload register UTIMR..........................................231request sense and transfer modes, combination of ...

...................................................................353reset cause holding ..............................................114reset sequence.......................................................85resource instruction..............................................426resource interrupt request as a DMA transfer ............

request, using ............................................360RETI instruction, operation of.................................84return from EIT .......................................................72return from sleep state .........................................108

row and column address...................................... 172RP (return pointer) ................................................. 60RSRR (reset cause register) and WTCR (watchdog

control register)............................................ 91RSTX pin processing ............................................. 32

S

save and restore processing................................ 379SCR (system condition code register) ................... 57second word of descriptor.................................... 349section.................................................................. 410section type, restriction on ................................... 412self refresh ........................................................... 209sense mode of DREQ signal................................ 353serial control register (SSR), bit function of ......... 320serial control register (SSR), configuration of ...... 320serial input data register (SIDR)/serial output data

register (SODR), configuration of .............. 322serial mode register (SMR), bit function of........... 318serial mode register (SMR), configuration of ....... 318serial status register (SSR), bit function of........... 323serial status register (SSR), configuration of ....... 323series common memory map................................. 66set timing of interrupt flag during receive operation in

mode 0....................................................... 330set timing of interrupt flag during receive operation in

mode 1....................................................... 331set timing of interrupt flag during receive operation in

mode 2....................................................... 331set timing of interrupt flag during send operation in

mode 0, mode 1, and mode 2.................... 332shift arithmetic instruction .................................... 421signal output, transfer acceptance....................... 359signal output, transfer completion........................ 359simulator debugger .............................................. 413single DRAM interface in read timing................... 202single DRAM interface in write timing .................. 203single DRAM interface timing............................... 204single/block transfer mode................................... 350sleep state............................................................ 107sleep state, transition to....................................... 107source clock frequency input, precautions during.. 32SSP (system stack pointer).............................. 61, 76stack placing in little endian area......................... 409standby mode (stop/sleep), returning from .......... 293state transition diagram........................................ 121STCR (standby control register) ............................ 93step trace trap, operation of ................................... 83step transfer (CLK doubler used, internal descriptor,

block size = 1)............................................ 354

433

INDEX

STOP mode, precaution at using........................... 31stop state ............................................................. 103stop state, return from.......................................... 105stop state, returning from ..................................... 274stop state, transition to......................................... 103structure substituting............................................ 408symbol used in timing, description of ................... 364

T

TBR (table base register)................................. 59, 77Term......................................................................... 6terminogogy used in list of pin status................... 396third word of descriptor ........................................ 349time base timer .................................................... 111timing in level, precaution on ............................... 358timing in the edge, precaution on......................... 357TMCSR ................................................................ 238transfer acceptance signal output ........................ 359transfer completion operation (if one of address is fixed)

................................................................... 371transfer completion signal output ......................... 359transfer data format in asynchronous (start-stop

transmission) mode ................................... 327transfer data format in CLK synchronous mode .. 328transfer instruction between register/special-purpose

register transfer instruction ........................ 423transfer mode, burst............................................. 352transfer mode, continuous ................................... 351transfer mode, single/block .................................. 350transfer stop timing chart in continuous transfer

mode, 16/8-bit data.................................... 369transfer to DMAC internal register ....................... 361type of instruction................................................. 418

U

UART operation mode..........................................325UART, application example of ..............................333UART, block diagram of .......................................317UART, feature of...................................................316UART, precaution for using ..................................333UART, register list of ............................................316undefined instruction exception, operation of .........83underflow operation ..............................................241user interrupt/NMI, operation of..............................81using A/D converter, precaution ...........................313USP (user stack pointer) ........................................62U-TIMER and baud rate reload value setting .......335U-Timer control register UTIMIC ..........................231U-TIMER value register UTIM(U-TIMER).............231U-TIMER, block diagram of ..................................230UTIMIC .................................................................231UTIMR ..................................................................231

V

variable placing (with an initial value) ...................407variation point detection........................................378variation point detection data register (BSDC) .....376vector table initial area............................................66

W

wait cycle ..............................................................176watchdog function.................................................110word access..........................................................167WPR (watchdog reset postponement register).......99write cycle timing ..................................................185

434

INDEX

CM71-10102-2E

FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL

FR30

32-Bit Microcontroller

MB91101/MB91101A

Hardware Manual

January 2000 the second edition

Published FUJITSU LIMITED Electronic Devices

Edited Technical Communication Dept.

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32-Bit M

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B991101/M

B91101A

Hardw

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32-bit microcontroller mb91101/mb91101a hardware manual · i-bus 16-bit bus for internal...

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