sn74avc2t245 dual-bit dual-supply bus transceiver with

DIR1

A1

OE

B1

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74AVC2T245SCES692D –JUNE 2008–REVISED FEBRUARY 2016

SN74AVC2T245 Dual-Bit Dual-Supply Bus Transceiver with Configurable Level-Shifting /Voltage Translation and Tri-State Outputs

1

1 Features1• Each Channel Has Independent Direction Control• Control Inputs VIH/VIL Levels Are Referenced to

VCCA Voltage• Fully Configurable Dual-Rail Design Allows Each

Port to Operate Over the Full 1.2 V to3.6 V Power-Supply Range

• I/Os Are 4.6 V Tolerant• Ioff Supports Partial-Power-Down Mode Operation• VCC Isolation Feature - If Either VCC Input is at

GND, Both Ports are in High-Impedance State• Typical Data Rates

– 500 Mbps (1.8 V to 3.3 V Level-Shifting)– 320 Mbps (<1.8 V to 3.3 V Level-Shifting)– 320 Mbps (Translate to 2.5 V or 1.8 V)– 280 Mbps (Translate to 1.5 V)– 240 Mbps (Translate to 1.2 V)

• Latch-Up Performance Exceeds 100 mA PerJESD 78, Class II

• ESD Protection Exceeds JESD 22– 5000 V Human-Body Model (A114-A)– 200 V Machine Model (A115-A)– 1500 V Charged-Device Model (C101)

2 Applications• Personal Electronics• Industrial• Enterprise• Telecom

Logic Diagram (Positive Logic)

(1) Shown for a single channel

3 DescriptionThis dual-bit noninverting bus transceiver uses twoseparate configurable power-supply rails. The A portis designed to track VCCA. VCCA accepts any supplyvoltage from 1.2 V to 3.6 V. The B port is designed totrack VCCB. VCCB accepts any supply voltage from 1.2V to 3.6 V. This allows for universal low-voltagebidirectional translation between any of the 1.2 V, 1.5V, 1.8 V, 2.5 V, and 3.3 V voltage nodes.

The SN74AVC2T245 is designed for asynchronouscommunication between two data buses. The logiclevels of the direction-control (DIR) input and theoutput-enable (OE) activate either the B-port outputsor the A-port outputs or place both output ports intothe high-impedance mode . The device transmits datafrom the A bus to the B bus when the B-port outputsare activated and from the B bus to the A bus whenthe A-port outputs are activated. The input circuitry onboth A and B ports always is active and must have alogic HIGH or LOW level applied to prevent excessICC and ICCZ.

The SN74AVC2T245 control pins (DIR1, DIR2, andOE) are supplied by VCCA.

This device is fully specified for partial-power-downapplications using Ioff. The Ioff circuitry disables theoutputs, preventing damaging current backflowthrough the device when it is powered down.

The VCC isolation feature ensures that if either VCCinput is at GND, both ports are in the high-impedancestate.

To ensure the high-impedance state during power upor power down, OE must be connected to VCCthrough a pull-up resistor; the minimum value of theresistor is determined by the current-sinking capabilityof the driver.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)SN74AVC2T245 UQFN (10) 1.80 mm × 1.40 mm

(1) For all available packages, see the orderable addendum atthe end of the datasheet.

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Table of Contents1 Features .................................................................. 12 Applications ........................................................... 13 Description ............................................................. 14 Revision History..................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ..................................... 46.2 ESD Ratings.............................................................. 46.3 Recommended Operating Conditions ...................... 46.4 Thermal Information .................................................. 56.5 Electrical Characteristics .......................................... 66.6 Switching Characteristics: VCCA = 1.2 V ................... 76.7 Switching Characteristics: VCCA = 1.5 V ± 0.1 V....... 76.8 Switching Characteristics: VCCA = 1.8 V ± 0.15 V..... 86.9 Switching Characteristics: VCCA = 2.5 V ± 0.2 V....... 86.10 Switching Characteristics: VCCA = 3.3 V ± 0.3 V..... 96.11 Operating Characteristics........................................ 96.12 Typical Characteristics .......................................... 10

7 Parameter Measurement Information ................ 11

8 Detailed Description ............................................ 128.1 Overview ................................................................. 128.2 Functional Block Diagram ....................................... 128.3 Feature Description................................................. 128.4 Device Functional Modes........................................ 13

9 Application and Implementation ........................ 149.1 Application Information............................................ 149.2 Typical Application ................................................. 14

10 Power Supply Recommendations ..................... 1611 Layout................................................................... 16

11.1 Layout Guidelines ................................................. 1611.2 Layout Example .................................................... 16

12 Device and Documentation Support ................. 1712.1 Community Resources.......................................... 1712.2 Trademarks ........................................................... 1712.3 Electrostatic Discharge Caution............................ 1712.4 Glossary ................................................................ 17

13 Mechanical, Packaging, and OrderableInformation ........................................................... 17

4 Revision History

Changes from Revision C (July 2015) to Revision D Page

• Made changes to Pin Configuration and Functions .............................................................................................................. 1

Changes from Revision B (June 2015) to Revision C Page

• The Ordering Information table (formally on page 1) contained a Top-Side Marking of TQ_. The table has beenreplaced with the Package Option Addendum in Mechanical, Packaging, and Orderable Information. VC_ wasadded to the device marking . ............................................................................................................................................. 17

Changes from Revision A (May 2012) to Revision B Page

• Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device FunctionalModes, Application and Implementation section, Power Supply Recommendations section, Layout section, Deviceand Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1

• Removed the Ordering Information table. ............................................................................................................................. 1


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VC

CA

VC

CB

OE

DIR

2

B1

B2

GND

A1

A2

DIR1

8 5

9 4

10 3

1 2

67

3

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5 Pin Configuration and Functions

RSW PACKAGE10-PIN UQFN

TOP VIEW

Pin FunctionsPIN

DESCRIPTIONNAME NO.

(UQFN)VCCA 7 Supply Voltage AVCCB 6 Supply Voltage BGND 3 GroundA1 8 Output or input depending on state of DIR. Output level depends on VCCA.A2 9 Output or input depending on state of DIR. Output level depends on VCCA.B1 5 Output or input depending on state of DIR. Output level depends on VCCB.B2 4 Output or input depending on state of DIR. Output level depends on VCCB.DIR1,DIR2 10,1 Direction Pin, Connect to GND or to VCCA

OE 2 Tri-state output-mode enables. Pull OE high to place all outputs in 3-state mode. Referencedto VCCA


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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) The input voltage and output negative-voltage ratings may be exceeded if the input and output current ratings are observed.(3) The output positive-voltage rating may be exceeded up to 4.6 V maximum if the output current rating is observed.

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITVCCAVCCB

Supply voltage –0.5 4.6 V

VI Input voltage (2)

I/O ports (A port) –0.5 4.6VI/O ports (B port) –0.5 4.6

Control inputs –0.5 4.6

VOVoltage applied to any output in the high-impedance or power-offstate (2)

A port –0.5 4.6V

B port –0.5 4.6

VO Voltage applied to any output in the high or low state (2) (3) A port –0.5 VCCA + 0.5V

B port –0.5 VCCB + 0.5IIK Input clamp current VI < 0 –50 mAIOK Output clamp current VO < 0 –50 mAIO Continuous output current ±50 mA

Continuous current through VCCA, VCCB, or GND ±100 mATJ Junction Temperature -40 150 °CTstg Storage temperature range –65 150 °C

(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 5000

VCharged-device model (CDM), per JEDEC specification JESD22-C101 (2)

1500

(1) VCCI is the VCC associated with the input port.(2) VCCO is the VCC associated with the output port.(3) All unused data inputs of the device must be held at VCCI or GND to ensure proper device operation. Refer to the TI application report,

Implications of Slow or Floating CMOS Inputs, literature number SCBA004.

6.3 Recommended Operating Conditions (1) (2) (3)

VCCI VCCO MIN MAX UNITVCCA Supply voltage 1.2 3.6 VVCCB Supply voltage 1.2 3.6 V

VIHHigh-levelinput voltage Data inputs (1)

1.2 V to 1.95 V VCCI × 0.65V1.95 V to 2.7 V 1.6

2.7 V to 3.6 V 2

VILLow-levelinput voltage Data inputs (1)

1.2 V to 1.95 V VCCI × 0.35V1.95 V to 2.7 V 0.7

2.7 V to 3.6 V 0.8

VIHHigh-levelinput voltage

DIR(referenced to VCCA)(2)

1.2 V to 1.95 V VCCA × 0.65V1.95 V to 2.7 V 1.6

2.7 V to 3.6 V 2


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Recommended Operating Conditions(1) (2) (3) (continued)VCCI VCCO MIN MAX UNIT

VILLow-levelinput voltage

DIR(referenced to VCCA)(2)

1.2 V to 1.95 V VCCA × 0.35V1.95 V to 2.7 V 0.7

2.7 V to 3.6 V 0.8VI Input voltage 0 3.6 V

VO Output voltageActive state 0 VCCO V3-state 0 3.6

IOH High-level output current

1.1 V to 1.2 V –3

mA1.4 V to 1.6 V –6

1.65 V to 1.95 V –82.3 V to 2.7 V –93 V to 3.6 V –12

IOL Low-level output current

1.1 V to 1.2 V 3

mA1.4 V to 1.6 V 6

1.65 V to 1.95 V 82.3 V to 2.7 V 93 V to 3.6 V 12

Δt/Δv Input transition rise or fall rate 5 ns/VTA Operating free-air temperature –40 85 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport, SPRA953.

6.4 Thermal Information

THERMAL METRIC (1)SN74AVC2T245

UNITRSW (UQFN)10 PINS

RθJA Junction-to-ambient thermal resistance 109.1 °C/WRθJC(top) Junction-to-case (top) thermal resistance 57.9 °C/WRθJB Junction-to-board thermal resistance 57.0 °C/WψJT Junction-to-top characterization parameter 2.7 °C/WψJB Junction-to-board characterization parameter 57.0 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 18.4 °C/W


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(1) VCCO is the VCC associated with the output port.(2) VCCI is the VCC associated with the input port.

6.5 Electrical Characteristicsover recommended operating free-air temperature range (unless otherwise noted) (1) (2)

PARAMETER TEST CONDITIONS VCCA VCCBTA = 25°C –40°C to 85°C

UNITMIN TYP MAX MIN MAX

VOH

IOH = –100 μA

VI = VIH

1.2 V to 3.6 V 1.2 V to 3.6 V VCCO – 0.2

V

IOH = –3 mA 1.2 V 1.2 V 0.95IOH = –6 mA 1.4 V 1.4 V 1.05IOH = –8 mA 1.65 V 1.65 V 1.2IOH = –9 mA 2.3 V 2.3 V 1.75IOH = –12 mA 3 V 3 V 2.3

VOL

IOL = 100 μA

VI = VIL

1.2 V to 3.6 V 1.2 V to 3.6 V 0.2

V

IOL = 3 mA 1.2 V 1.2 V 0.25IOL = 6 mA 1.4 V 1.4 V 0.35IOL = 8 mA 1.65 V 1.65 V 0.45IOL = 9 mA 2.3 V 2.3 V 0.55IOL = 12 mA 3 V 3 V 0.7

IIControlinputs VI = VCCA or GND 1.2 V to 3.6 V 1.2 V to 3.6 V ±0.025 ±0.25 ±1 μA

Ioff A or B port VI or VO = 0 to 3.6 V0 V 0 V to 3.6 V ±0.1 ±1 ±5

μA0 V to 3.6 V 0 V ±0.1 ±1 ±5

IOZ A or B port VO = VCCO or GND,VI = VCCI or GND, OE = VIH

3.6 V 3.6 V ±0.5 ±2.5 ±5 μA

ICCA VI = VCCI or GND, IO = 01.2 V to 3.6 V 1.2 V to 3.6 V 8

μA0 V 0 V to 3.6 V –20 V to 3.6 V 0 V 8

ICCB VI = VCCI or GND, IO = 01.2 V to 3.6 V 1.2 V to 3.6 V 8

μA0 V 0 V to 3.6 V 80 V to 3.6 V 0 V –2

ICCA + ICCB VI = VCCI or GND, IO = 0 1.2 V to 3.6 V 1.2 V to 3.6 V 16 μA

CiControlinputs VI = 3.3 V or GND 3.3 V 3.3 V 3.5 4.5 pF

Cio A or B port VO = 3.3 V or GND 3.3 V 3.3 V 6 7 pF


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6.6 Switching Characteristics: VCCA = 1.2 Vover recommended operating free-air temperature range, VCCA = 1.2 V (unless otherwise noted) (see Figure 3)

PARAMETER FROM(INPUT)

TO(OUTPUT)

VCCB = 1.2 V VCCB = 1.5 V± 0.1 V

VCCB = 1.8 V± 0.15 V

VCCB = 2.5 V± 0.2 V

VCCB = 3.3 V± 0.3 V UNIT

TYP TYP TYP TYP TYPtPLH A B

2.5 2.1 1.9 1.9 1.9ns

tPHL 2.5 2.1 1.9 1.9 1.9tPLH B A

2.5 2.2 2 1.8 1.7ns

tPHL 2.5 2.2 2 1.8 1.7tPZH OE A

3.8 3.1 2.7 2.6 3ns

tPZL 3.8 3.1 2.7 2.6 3tPZH OE B

3.7 3.7 3.7 3.7 3.7ns

tPZL 3.7 3.7 3.7 3.7 3.7tPHZ OE A

4.4 3.6 3.5 3.3 4.1ns

tPLZ 4.4 3.6 3.5 3.3 4.1tPHZ OE B

4.2 4.2 4.3 4.1 4.2ns

tPLZ 4.2 4.2 4.3 4.1 4.2

6.7 Switching Characteristics: VCCA = 1.5 V ± 0.1 Vover recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (see Figure 3)


TO(OUTPUT)

VCCB = 1.2 V VCCB = 1.5 V± 0.1 V

VCCB = 1.8 V± 0.15 V

VCCB = 2.5 V± 0.2 V


TYP MIN MAX MIN MAX MIN MAX MIN MAXtPLH A B

2.2 0.3 4.4 0.2 3.9 0.1 3.6 0.1 3.9ns

tPHL 2.2 0.3 4.4 0.2 3.9 0.1 3.6 0.1 3.9tPLH B A

2 0.6 5.1 0.4 4.9 0.2 4.6 0.1 4.5ns

tPHL 2 0.6 5.1 0.4 4.9 0.2 4.6 0.1 4.5tPZH OE A

3.4 1.1 7.1 0.9 6.2 0.7 5.5 0.1 6.4ns

tPZL 3.4 1.1 7.1 0.9 6.2 0.7 5.5 0.1 6.4tPZH OE B

2.5 1.1 8.2 1.1 8.2 1.1 8.2 1.1 8.2ns

tPZL 2.5 1.1 8.2 1.1 8.2 1.1 8.2 1.1 8.2tPHZ OE A

4.1 1.2 7.1 0.8 6.7 0.4 5.6 1 74ns

tPLZ 4.1 1.2 7.1 0.8 6.7 0.4 5.6 1 7.4tPHZ OE B

3.3 0.3 7.4 0.2 5.7 0.3 5.6 0.3 5.6ns

tPLZ 3.3 0.3 7.4 0.2 5.7 0.3 5.6 0.3 5.6


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TO(OUTPUT)

VCCB = 1.2 V VCCB = 1.5 V± 0.1 V

VCCB = 1.8 V± 0.15 V

VCCB = 2.5 V± 0.2 V



2 0.1 4.1 0.1 3.6 0.1 3.1 0.1 3.3ns

tPHL 2 0.1 4.1 0.1 3.6 0.1 3.1 0.1 3.3tPLH B A

1.9 0.4 4.3 0.1 4.1 0.1 3.8 0.1 3.7ns

tPHL 1.9 0.4 4.3 0.1 4.1 0.1 3.8 0.1 3.7tPZH OE A

3.2 0.8 6.7 0.4 5.8 0.4 4.8 0.3 4.6ns

tPZL 3.2 0.8 6.7 0.4 5.8 0.4 4.8 0.3 4.6tPZH OE B

1.9 0.2 6.7 0.2 6.6 0.2 6.7 0.2 6.7ns

tPZL 1.9 0.2 6.7 0.2 6.6 0.2 6.7 0.2 6.7tPHZ OE A

3.8 0.7 6.2 0.3 6.5 0.1 5.2 0.8 6.5ns

tPLZ 3.8 0.7 6.2 0.3 6.5 0.1 5.2 0.8 6.5tPHZ OE B

3.4 0.1 6.8 0.1 6.8 0.1 6.7 0.1 6.7ns

tPLZ 3.4 0.1 6.8 0.1 6.8 0.1 6.7 0.1 6.7



TO(OUTPUT)

VCCB = 1.2 V VCCB = 1.5 V± 0.1 V

VCCB = 1.8 V± 0.15 V

VCCB = 2.5 V± 0.2 V



1.9 0.1 3.8 0.1 3.2 0.1 2.7 0.1 2.6ns

tPHL 1.9 0.1 3.8 0.1 3.2 0.1 2.7 0.1 2.6tPLH B A

1.8 0.5 3.4 0.2 3.1 0.1 2.8 0.1 2.6ns

tPHL 1.8 0.5 3.4 0.2 3.1 0.1 2.8 0.1 2.6tPZH OE A

3.1 0.7 6.2 0.5 5.2 0.3 4.1 0.3 3.6ns

tPZL 3.1 0.7 6.2 0.5 5.2 0.3 4.1 0.3 3.6tPZH OE B

1.4 0.4 4.5 0.4 4.5 0.4 4.5 0.4 4.5ns

tPZL 1.4 0.4 4.5 0.4 4.5 0.4 4.5 0.4 4.5tPHZ OE A

3.6 0.2 5.2 0.1 5.4 0.1 4.5 0.7 6ns

tPLZ 3.6 0.2 5.2 0.1 5.4 0.1 4.5 0.7 6tPHZ OE B

2.1 0.1 4.7 0.1 4.6 0.1 4.7 0.1 4.7ns

tPLZ 2.1 0.1 4.7 0.1 4.6 0.1 4.7 0.1 4.7


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TO(OUTPUT)

VCCB = 1.2 V VCCB = 1.5 V± 0.1 V

VCCB = 1.8 V± 0.15 V

VCCB = 2.5 V± 0.2 V



1.8 0.1 3.6 0.1 3 0.1 2.6 0.1 2.4ns

tPHL 1.8 0.1 3.6 0.1 3 0.1 2.6 0.1 2.4tPLH B A

1.9 0.5 3.4 0.2 2.9 0.1 2.5 0.1 2.3ns

tPHL 1.9 0.5 3.4 0.2 2.9 0.1 2.5 0.1 2.3tPZH OE A

3.1 0.9 5.9 0.5 5 0.3 3.8 0.3 3.3ns

tPZL 3.1 0.9 5.9 0.5 5 0.3 3.8 0.3 3.3tPZH OE B

1.2 0.4 3.6 0.4 3.6 0.4 3.6 0.4 3.6ns

tPZL 1.2 0.4 3.6 0.4 3.6 0.4 3.6 0.4 3.6tPHZ OE A

3.4 0.1 4.6 0.1 4.7 0.3 4.8 0.7 4.5ns

tPLZ 3.4 0.1 4.6 0.1 4.7 0.3 4.8 0.7 4.5tPHZ OE B

2.9 0.1 5.4 0.1 5.3 0.1 5.3 0.1 5.3ns

tPLZ 2.9 0.1 5.4 0.1 5.3 0.1 5.3 0.1 5.3

(1) Power dissipation capacitance per transceiver. Refer to the TI application report, CMOS Power Consumption and Cpd Calculation,SCAA035

6.11 Operating CharacteristicsTA = 25°C

PARAMETER TESTCONDITIONS

VCCA =VCCB = 1.2 V

VCCA =VCCB = 1.5 V

VCCA =VCCB = 1.8 V

VCCA =VCCB = 2.5 V

VCCA =VCCB = 3.3 V UNIT

TYP TYP TYP TYP TYP

CpdA(1)

A to B

Outputsenabled

CL = 0,f = 10 MHz,tr = tf = 1 ns

3 3 3 3 4

pF

Outputsdisabled 1 1 1 2 2

B to A

Outputsenabled 12 13 13 15 15


CpdB(1)

A to B

Outputsenabled

CL = 0,f = 10 MHz,tr = tf = 1 ns

12 13 13 14 16

pF


B to A

Outputsenabled 3 3 3 4 4



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0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

0 20 40 60 80 100

VV

olta

ge

(V)

OL

I Current (mA)OL

-40 Co

25 Co

85 Co

4.4

4.6

4.8

5.0

5.2

5.4

5.6

0 -20 -40 -60 -80 -100

VV

olta

ge

(V)

OH

I Current (mA)OH

-40 Co

25 Co

85 Co

4.2

10




6.12 Typical Characteristics

Figure 1. VOL Voltage vs IOL Current Figure 2. VOH Voltage vs IOH Current


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VOH

VOL

From Output

�Under Test

CL

(see Note A)

LOAD CIRCUIT

S1

2 × VCCO

Open

GND

RL

RL

tPLH tPHL

Output

Control

(low-level

enabling)

Output

Waveform 1

S1 at 2 × VCCO

(see Note B)

Output

Waveform 2

S1 at GND

(see Note B)

tPZL

tPZH

tPLZ

tPHZ

VCCA/2VCCA/2

VCCI/2 VCCI/2

VCCI

0 V

VCCO/2 VCCO/2

VOH

VOL

0 V

VCCO/2VOL + VTP

VCCO/2VOH − VTP

0 V

VCCI

0 V

VCCI/2 VCCI/2

tw

Input

VCCA

VCCO

VOLTAGE WAVEFORMS

PROPAGATION DELAY TIMES

VOLTAGE WAVEFORMS

PULSE DURATION

VOLTAGE WAVEFORMS

ENABLE AND DISABLE TIMES

Output

Input

tpd

tPLZ/tPZL

tPHZ/tPZH

Open

2 × VCCO

GND

TEST S1

NOTES: A. CL includes probe and jig capacitance.

B. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.

Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.

C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50 W, dv/dt ≥�1 V/ns.

D. The outputs are measured one at a time, with one transition per measurement.

E.

F.

tPLH and tPHL are the same as tpd.

VCCI is the VCC associated with the input port.

VCCO is the VCC associated with the output port.

1.2 V

1.5 V ± 0.1 V

1.8 V ± 0.15 V

2.5 V ± 0.2 V

3.3 V ± 0.3 V

2 kW

2 kW

2 kW

2 kW

2 kW

VCCO RL

0.1 V

0.1 V

0.15 V

0.15 V

0.3 V

VTPCL

15 pF

15 pF

15 pF

15 pF

15 pF

G.

11




7 Parameter Measurement Information

Figure 3. Load and Circuit and Voltage Waveforms


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DIR1

A1

OE

B1

12




8 Detailed Description

8.1 OverviewThe SN74AVC2T245 is a dual-bit, dual-supply noninverting bidirectional voltage level translation. Pins A andcontrol pins (DIR and OE) are supported by VCCA and pins B are supported by VCCB. The A port can accept I/Ovoltages ranging from 1.2 V to 3.6 V, while the B port can accept I/O voltages from 1.2 V to 3.6 V. A high on DIRallows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set tolow. When OE is set to high, both A and B are in the high-impedance state.

This device is fully specified for partial-power-down applications using off output current (Ioff).

The VCC isolation feature ensures that if either VCC input is at GND, both ports are put in a high-impedance state.

8.2 Functional Block Diagram

Figure 4. Logic Diagram (Positive Logic)

8.3 Feature Description

8.3.1 Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full1.2 V to 3.6 V Power-Supply Range

Both VCCA and VCCB can be supplied at any voltage from 1.2 V to 3.6 V making the device suitable for translatingbetween any of the low voltage nodes (1.2 V, 1.8 V, 2.5 V, and 3.3 V).

8.3.2 Partial-Power-Down Mode OperationThis device is fully specified for partial-power-down applications using off output current (Ioff). The Ioff circuitry willprevent backflow current by disabling I/O output circuits when device is in partial power-down mode.

8.3.3 VCC IsolationThe VCC isolation feature ensures that if either VCCA or VCCB are at GND, both ports will be in a high-impedancestate (IOZ). This prevents false logic levels from being presented to either bus.


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13




8.4 Device Functional Modes

The SN74AVC2T245 is a voltage level translator that can operate from1.2 V to 3.6 V (VCCA) and 1.2 V to 3.6 V(VCCB). The signal translation requires direction control and output enable control. The table below enlists theoperation of the part for the respective states of the control inputs.

(1) Input circuits of the data I/Os are always active.

Table 1. Function Table (1) (Each Transceiver)CONTROL INPUTS OUTPUT CIRCUITS

OPERATIONOE DIR1 A PORT B PORTL L Enabled Hi-Z B data to A dataL H Hi-Z Enabled A data to B dataH X Hi-Z Hi-Z Isolation


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1.8 V

1 kΩ

3.0 V

Processor

UART

Peripheral

OE

DIR1

A1

A2

Tx

Rx

Rx

Tx

VCCA VCCB

B1

B2

GND

DIR2

SN1203086

14




9 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

9.1 Application InformationThe SN74AVC2T45 is used to shift IO voltage levels from one voltage domain to another. Bus A and bus B haveindependent power supplies, and a direction pin is used to control the direction of data flow. Unused data portsmust not be floating; tie the unused port input and output to ground directly.

9.1.1 Enable TimesCalculate the enable times for the SN74AVC16T45 using the following formulas:

tPZH (DIR to A) = tPLZ (DIR to B) + tPLH (B to A) (1)tPZL (DIR to A) = tPHZ (DIR to B) + tPHL (B to A) (2)tPZH (DIR to B) = tPLZ (DIR to A) + tPLH (A to B) (3)tPZL (DIR to B) = tPHZ (DIR to A) + tPHL (A to B) (4)

In a bidirectional application, these enable times provide the maximum delay from the time the DIR bit isswitched until an output is expected. For example, if the SN74AVC2T245 initially is transmitting from A to B, thenthe DIR bit is switched; the B port of the device must be disabled before presenting it with an input. After the Bport has been disabled, an input signal applied to it appears on the corresponding A port after the specifiedpropagation delay.

9.2 Typical Application

Figure 5. Typical Application of the SN74AVC2T245

9.2.1 Design RequirementsThis device uses drivers which are enabled depending on the state of the DIR pin. The designer must know theintended flow of data and take care not to violate any of the high or low logic levels. Unused data inputs must notbe floating, as this can cause excessive internal leakage on the input CMOS structure. Tie any unused input andoutput ports directly to ground.

For this design example, use the parameters listed in Table 2.


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Mag

nitu

de (

V)

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

D001

InputOutput

15




Table 2. Design ParametersDESIGN PARAMETER EXAMPLE VALUE

Input voltage range 1.2 V to 3.6 VOutput voltage range 1.2 V to 3.6 V

9.2.2 Detailed Design ProcedureTo begin the design process, determine the following:

9.2.2.1 Input Voltage RangesUse the supply voltage of the device that is driving the SN74AVC2T245 device to determine the input voltagerange. For a valid logic high the value must exceed the VIH of the input port. For a valid logic low the value mustbe less than the VIL of the input port.

9.2.2.2 Output Voltage RangeUse the supply voltage of the device that the SN74AVC2T245 device is driving to determine the output voltagerange.

9.2.3 Application Curves

Figure 6. 3.3 V to 1.8 V Level-Shifting With 1-MHz Square Wave


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GND

B2

VCCB

LEGEND

VIA to Power Plane

VIA to GND Plane (Inner Layer)

Polygonal Copper Pour

B1

DIR1

A2

VCCA

8

9

10

1

DIR2

A1

Keep OE high until V and

V are powered upCCA

CCB

6

5

4

3

Bypass CapacitorBypass Capacitor

From

Controller

To

Controller

To

System

From

System

OE

VC

CA

SN74AVC2T245

VC

CA

2

7

16




10 Power Supply RecommendationsThe SN74AVC2T245 device uses two separate configurable power-supply rails, VCCA and VCCB. VCCA acceptsany supply voltage from 1.2 V to 3.6 V and VCCB accepts any supply voltage from 1.2 V to 3.6 V. The A port andB port are designed to track VCCA and VCCB respectively allowing for low-voltage bidirectional translation betweenany of the 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V and 5 V voltage nodes.

11 Layout

11.1 Layout GuidelinesTo ensure reliability of the device, following common printed-circuit-board layout guidelines is recommended.• Bypass capacitors should be used on power supplies.• Short trace lengths should be used to avoid excessive loading.• Placing pads on the signal paths for loading capacitors or pullup resistors to help adjust rise and fall times of

signals depending on the system requirements.

11.2 Layout Example

Figure 7. Recommended Layout Example


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17




12 Device and Documentation Support

12.1 Community ResourcesThe following links connect to TI community resources. Linked contents are provided "AS IS" by the respectivecontributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms ofUse.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaborationamong engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and helpsolve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools andcontact information for technical support.

12.2 TrademarksE2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

12.3 Electrostatic Discharge CautionThese devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foamduring storage or handling to prevent electrostatic damage to the MOS gates.

12.4 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.


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PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

SN74AVC2T245RSWR ACTIVE UQFN RSW 10 3000 RoHS & Green NIPDAU | NIPDAUAG Level-1-260C-UNLIM -40 to 85 (TQ7, TQO, TQR, TQ V)(TQH, TQJ, TQY)(VCH, VCO)(VCJ, VCR)

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

SN74AVC2T245RSWR UQFN RSW 10 3000 179.0 8.4 1.7 2.1 0.7 4.0 8.0 Q1




PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

SN74AVC2T245RSWR UQFN RSW 10 3000 200.0 183.0 25.0




PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

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PACKAGE OUTLINE

C

1.451.35

1.851.75

0.550.45

NOTE 3

0.050.00

6X 0.4

2X 0.8

9X 0.450.35

10X 0.250.15

0.550.45

(0.13) TYP

UQFN - 0.55 mm max heightRSW0010APLASTIC QUAD FLATPACK - NO LEAD

4224897/A 03/2019

0.05 C

0.07 C A B0.05

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package complies to JEDEC MO-288 variation UDEE, except minimum package height.

PIN 1 INDEX AREA

SEATING PLANE

PIN 1 ID

SYMM

SYMM

1

2

3 5

6

7

810

SCALE 7.000

AB

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EXAMPLE BOARD LAYOUT

(R0.05) TYP

0.05 MAXALL AROUND

0.05 MINALL AROUND

9X (0.6)

(0.7)10X (0.2)

(1.2)

(1.6)

6X (0.4)


4224897/A 03/2019

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.

SYMM

SYMM

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE: 30X

SEE SOLDER MASKDETAIL

1

2

3 5

6

7

810

METAL EDGE

SOLDER MASKOPENING

EXPOSED METAL

METAL UNDERSOLDER MASK

SOLDER MASKOPENING

EXPOSEDMETAL

NON SOLDER MASKDEFINED

(PREFERRED)SOLDER MASK DEFINED

SOLDER MASK DETAILS

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EXAMPLE STENCIL DESIGN

9X (0.6)

10X (0.2)

6X (0.4)

(1.2)

(1.6)

(R0.05) TYP

(0.7)


4224897/A 03/2019

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

SYMM

SOLDER PASTE EXAMPLEBASED ON 0.125 MM THICK STENCIL

SCALE: 30X

SYMM

1

2

3 5

6

7

810

IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCEDESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANYIMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRDPARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriateTI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicablestandards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants youpermission to use these resources only for development of an application that uses the TI products described in the resource. Otherreproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third partyintellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available eitheron ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’sapplicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2021, Texas Instruments Incorporated

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