TO STUDY THE TRASIENT BEHAVIOR AND RESPONSE OF R-L AND R-C CIRCUIT AND HENCE MEASURE THE TIME CONSTANT FOR DIFFERENT CONDITOINName : Rahatir Rashid Roll : SH-69 ; 2nd year Session : 2001-2002 THEORY:The wave form for the voltage and current of a capacitor or an inductor that result during the charging and discharging phases are called capacitive transient and inductive transient respectively for capacitor and inductor. Whenever a circuit goes from one steady state condition from another steady state condition, it passes through a transient state which is of short duration. The first steady state called initial condition and the second steady state condition is called the final condition. The period during which current and voltage changes take place is called transient condition. We use square wave voltage supply to switch quickly from charging phase to discharging phase. For a capacitive circuit relationship between time and voltage is given by following two equations respectively for charging phase and discharging phase,

Vc = V (1 e

t

RC

)S.G

Rth

Vc = V e

t

RC

C

Here, Vc = Voltage drop across capacitor V0 = Supplied Voltage t = Time R = Thevenin Resistance C = Capacitance of the capacitor

OSC

Fig : Capacitive Circuit

For an inductive circuit relationship between time and voltage is given by following two equations respectively for charging phase and discharging phase,

1

t

VL = V e

L R t

RthL R

VL = V e

S.G

L

OSC

Here, Vc = Voltage drop across capacitor V0 = Supplied Voltage t = Time R = Thevenin Resistance L = Inductance of the capacitor

Fig : Inductive Circuit

Capacitive time constant: The product of resistance and capacitance of a capacitive circuit that establishes the required time for the charging and discharging phases of a capacitive transient, is called capacitive time constant. It is denoted by . = RC Now, let us put t = , at the equation for a capacitive circuit at its discharging phase. Hence we get

Vc = V e

= V e 1 = 0.368 V0

0

So, we can say, the time when voltage drop across capacitor is 36.8% of the supply voltage for the discharging phase, gives us the time constant of the circuit. Inductive time constant: We can get the time constant for an inductive circuit by dividing the inductance of the circuit by resistance of the circuit. It is denoted by .

Now, let us put t = , at the equation for an inductive circuit at its charging phase. Hence we get

= LR

Vc = V e

= V e 1 = 0.368 V0

0

So, we can say, the time when voltage drop across inductor is 36.8% of the supply voltage for the charging phase, gives us the time constant of the circuit.

Equipments:1. 2. 3. 4. 5. 6. Signal Generator Oscilloscope Bread Board Capacitor and Inductor Resistor Wires

FOR CAPACITIVE CIRCUIT:2

Resistance of the main circuit, RC = 9.8 K Capacitance of the circuit, C = 0.1 F = RCC = 0.98 ms

Table for capacitive circuit at discharging phaseN.O. 1 2 3 4 5 6 7 8 Time,t ms 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 Voltage Drop Across Capacitor,Vc 10.4 9.3 8.42 7.5 6.7 6.1 5.5 5.0 N.O. 9 10 11 12 13 14 15 16 Time,t ms 0.8 0.9 1.0 1.5 2.0 2.5 3.4 Voltage Drop Across Capacitor,Vc 4.2 3.9 3.5 1.9 1.1 0.5 0

From graph we see that the maximum voltage supplied by the signal generator is 10.4 V. Therefore, 36.8% of maximum voltage supplied by the signal generator is 0.368 10.4 V = 3.83 V From graph, = 0.95 ms Error:

Percentage of error =

RC 100% (Here is the value taken from the graph. ) RC 0.98 0.95 = 100% = 3.061% 0.98

Result: Capacitive time constant of the circuit is 0.95 ms.

FOR INDUCTIVE CIRCUIT:Internal resistance of the signal generator, r = 600 Resistance of the main circuit, RL = 47.3 Inductance of the circuit, L = 3.76 mH Total resistance of the circuit, R = RL + r = ( 600 + 47.3 ) = 647.3 3 L = 3.76 10 = 5.808744 10 6 s = 5.808744 s = R L 647.3

Table for inductive circuit at charging phase

3

N.O. 1 2 3 4 5 6 7 8

Time,t s 0 2 4 6 8 10 12 14

Voltage Drop Across Inductor,VL 4 3.2 2.1 1.5 1.05 0.75 0.5 0.35

N.O. 9 10 11 12 13 14

Time,t s 16 18 20 22 26 30

Voltage Drop Across Inductor,VL 0.28 0.2 0.15 0.1 0.05 0

From graph we see that the maximum voltage supplied by the signal generator is 10.4 V. Therefore, 36.8% of maximum voltage supplied by the signal generator is 0.368 4 V = 3.83 V From graph, = 5.9 s Error: L = R 100% (Here is the value taken from the graph. ) Percentage of error L R 5.9 5.808744 = 100% = 1.571% 5.808744 Result: Inductive time constant of the circuit is 5.9 s.

Precaution:1. 2. 3. 4. 5. We need to generate square wave form of voltage from the signal generator. We need to discharge the capacitor first. We need to take the value of inductance, capacitance and resistance by using LRC meter. We need to consider the internal value of the signal generator. We need to calibrate the oscilloscope before we take reading from it.

Discussion:1. We set an appropriate value of frequency at signal generator to have a better graph from the oscilloscope. We know, if we increase the frequency, the reactance of the inductor increases and if we decrease the frequency, the reactance of the capacitor increases. If the reactance of a component is larger than another, the most voltage will drop across the component having larger reactance. So we need to apply higher frequency at an inductive circuit and lower frequency at a capacitive frequency. We need to consider the internal resistance of the signal generator to get a small amount of error. If we take much much greater amount of resistance, we can ignore the internal resistance of the whole circuit.4

2.

EXPERIMENT NO: 03

TO STUDY THE RESONANCE OF AN RLC CIRCUIT AND ALSO TO OBSERVE THE TRANSIENT RESPONSENAME : Nishatul Majid ROLL : Sh-018 YEAR : 2nd year (hons.) SESSION : 2002-2003 GROUP : A-8 DEPARTMENT OF APPLIED PHYSICS & ELECTRONICS #Name of the experiment: To Study The resonance of an R-L-C circuit and also to observe the transient response. #Objective: 1. To study the current response of an R-L-C series circuit. 2. To observe the effect of R-L-C at different temperature. 3. To determine the phase difference between voltage and currents by experimental and mathematical means. 4. To study, observe and to be familiar with series resonance. #Theory: When an ac voltage is applied across a series R-L-C circuit for a certain frequency of the applied voltage the capacitive reactance XC becomes equal to the inductive reactance XL in magnitude. This phenomenon is known as resonant frequency. Now VL=IXL and VC=IXC and if the two are equal in magnitude but opposite in phase, they can cancel out each other. The net circuit resistance X= XL-XC =0 And the circuit impedance, Z=(R2+(XL-XC)2)1/2=R In fact, at the resonance the series R-L-C circuit is reduced to purely resistive circuit. Resonant frequency: At resonance the circuit current is maximum as we know,I= E R + (X L X C )22

At resonance, XL=XC, Now,

I = E\R5

XL=XC,

w0 L=1\ w0 C 2 Or, w0 =1\LC Or, ( 2 f 0 )2 = 1\LC Or, f 0 =1\2 LC Where f 0 is the resonant frequency.Or, To observe damping effect: An R-L-C circuit is an oscillatory circuit that produces electrical oscillations of any desired frequency. There are resistive and reactive losses in the coil and dielectric losses in the capacitor. During each cycle a small part of the originally imported energy is used to overcome those losses. #Figure:

VR VL

VC

I IR VR

ILVL

ICVC

Figure: Series R-L-C circuit

6

VL VR

XL

IVC

Z=R

IXC

V

I

OSC

S.G

R

L

C

Figure: R-L-C circuit under experiment The result is that the amplitude of oscillating current decreases gradually and eventually it becomes zero when all the energy is consumed as losses. The R-L-C circuit produces damped oscillation when a square wave is applied. We consider here a capacitor of capacitance C(which is initially fully charged) with a resistor of resistance R and inductor of inductance in a form of closed circuit without any voltage source. Applying KVL for the closed loop after the switch is closed. VR + VL + VC = 0 or, iR + L Rdi 1 + idt = 0 dt C

Differentiating with respect to t,di 1 d 2i +L 2 + i=0 C dt dt

Divided by L yields,R di 1 d 2i + 2 + i = 0 (1) L dt LC dt

A solution of this second order differential equation is of the form, i = A1 + A2 S2t. Substituting this solution in the differential equation (1) obtains,S t 1

7

R d 1 d2 [ (A1S1t + A2 S2t) + 2 [A1S1t + A2 S2t] + [A1S1t + A2 S2t] L dt LC dt

=0

A2S2t) = 0

R 1 (A1S1S1t + A2S2 S2t) + A1S12S1t + A2S22S2t + (A1S1t + L LC R 1 R 1 S1 + ) + A2S2t (S22 + S2 + )=0 L LC L LC 1 =0 LC 2 R 1 - + 2L LC

A1S1t (S12 + R L

that is, if S1 and S2 are the roots of S2 + ( )S + S1 = S2 = R + 2L R 2L 2L

2 R 1 - - 2L LC

R where ,

( ) 2 + ( o ) 2 and

o =

1 LC

is the expressional damping coefficient. Here is measured

of how rapidly the natural response decays or damps out of its steady final values. Describes the relative values of the circuit parameters, the circuit said to be over damped, critically damped or under damped. Over damped case ( o ): In this case, both and are real positive numbers. i = A1 e(- + )t + A2 e(- - )t = e- t(A1e t + A2e- t) From the above equation it is seen that is exponential function, not sine/cosine function, so voltage will not oscillate but it will be take longer time to come to steady state. Critically damped case ( = o ): becomes 2 In this case, = o , so equation (1)

di R R d 2i + 2 + o 2i = 0 [ = = 2 ] 2L L dt dt 1 di 1 d 2i + 2 + i=0[ = o = o 2] 2 LC dt LC dt

whose solution takes the form i = e- t (A1 + A2t) Here, voltage also fails to oscillate and the system comes to steady state in the shortest possible time.8

Under damped case ( o ): When o , is a pure imaginary, S1 and S2 are complex conjugates. The general form of the current is, i = e- t (A1cos t + A2sin t), where = ( ) 2 + ( o ) 2 and A1 and A2 are constants. From the above equation it is seen that it is a sine and cosine function. So, it will oscillate repeatedly before coming to rest.

#Apparatus:1.

2.3.

4.5. 6.

7. 8. #Table:

Oscilloscope Signal generator Inductor Capacitor Resistor Bread board Potential Divider Connecting wires

Data for resonance frequency:No of observa tion Frequenc y f, Hz Volta Volta No. of Freque Volta Volta ge ge Observa ncy ge ge acros gain, tion f, Hz acros gain, s R, Vr/Vi s R, Vr/Vi Vr Vr

1 2 3 4 5 6 7 8 9

1 103 2 103 3 103 4 103 5 103 6 103 7 103 8 103 9 103

0.18 0.37 0.56 0.76 0.97 1.20 1.43 1.70 2.00

0.07 0.14 0.22 0.29 0.37 0.46 0.55 0.65 0.779

21 22 23 24 25 26 27 28 29

23 103 24 103 25 103 26 103 27 103 28 103 29 103 30 103 31 103

3.00 2.80 2.60 2.40 2.21 2.10 2.00 1.90 1.80

1.15 1.08 1.00 0.92 0.85 0.81 0.77 0.73 0.69

10 11 12 13 14 15 16 17 18 19 20 Here, Vi =

10 103 11 103 12 103 13 103 14 103 15 103 17 103 19 103 20 103 21 103 22 103 2.6 volt

2.20 2.60 2.90 3.10 3.30 3.60 3.80 3.60 3.40 3.20 3.10

0.85 1.00 1.12 1.19 1.27 1.38 1.46 1.38 1.31 1.23 1.19

30 31 32 33 34 35 36 37 38 39 40

32 103 33 103 34 103 35 103 36 103 38 103

1.70 1.65 1.55 1.50 1.45 1.40

0.65 0.63 0.59 0.58 0.56 0.54

Data for under damping:No. of observa tion Ti me T, s Voltage across R, Vr(volt) No. of observa tion Ti me T, s Voltage across R, Vr(volt)

1 2 3 4 5 6 7 8 9 10 11 12 13 14

0 10 20 30 40 50 60 70 80 90 10 0 11 0 12 0 13

8.75 6 1.8 -3 -5.1 -3.4 0 2.5 4.2 3 1 -1 -2.2 -1.810

18 19 20 21 22 23 24 25 26 27 28 29 30 31

17 0 18 0 19 0 20 0 21 0 22 0 23 0 24 0 25 0 26 0 27 0 28 0 29 0 30

2 1.1 0 -1.2 -0.8 0 0.5 1 1.2 1 0.5 0 0.5 0

15 16 17

0 14 0 15 0 16 0

-0.5 1 1.8

32 33

0 31 0 32 0

0.2 0

#Calculation: Value of capacitor, C = 0.01 10-6F Value of inductor, L = 8.44 10-3F The theoretical value of fo =1 2 LC

=

1 2 8.44 10 3 0.01 10 6

Hz

= 17332.82 Hz But from the graph we get the value of fo = 17000 Hz Percentage of error = 17332 .82 17000 100% = 1.92% 17332 .82

#Precaution: 1. Circuit elements should be connected carefully. 2. Reading should be taken carefully. #Discussion: 1. Bellow and upper resonant frequency the amplitude of the voltage across resistor is decreased due to the reactive loss in the coil and dielectric loss in the capacitor. 2. To see the damping effect the small value of resistance has been changed by a large value of resistance and square wave was applied instead of sine wave. 3. In spite of taking proper care, personal reading might have some error because of personal equation. Besides, due to the defects of connecting wires and electrical components some error might be introduced.

11

Date: 06-03-06

Name 0f the experiment: To Study The Frequency Response of Passive High Pass and Low Pass Filter NetworkName: FAIZUS SALEHIN Roll: FH 50 Session: 2004-2005 Group: A-2Theory:Any combination of passive (R, L, and C ) and/or active (transistors or operational amplifiers ) elements designed to select or reject a band of frequencies is called a filter. In communication systems, filters are employed to pass those frequencies containing the desired information and to reject the remaining frequencies. In general there are two classifications of filters : Passive Filters : Composed with series or parallel combination of passive elements. Active Filters : Active devices in combination with passive elements. In general, all filters belong to four broad categories of low pass, high pass, pass band and stop band. For each form there are critical frequencies that define the regions of pass bands and stop bands. Any frequency in pass band will pass through to the next stage with at least 70.70% of maximum output voltage. The R-C filter, incredibly simple in design, can be used as low-pass or a highpass filter Low-Pass Filter : While the output is taken off the capacitor ,as shown in fig-1, it will respond as a low-pass filter. R C Vi VO 0.707 Av

fc Fig-1 : R-C Low-Pass Filter Fig-2 : Av versus frequency for lowpass filter

At any intermediate frequency, the output voltage Vo of fig-1 can be determined using the voltage divider rule:

Vo =

Xc 90 V R jXc i

Here, Xc = Reactance of capacitor12

Xc 90 A = o = = v V R jXc i A = v A = v Xc R 2 + Xc 2 Xc R 2 + Xc 2

V

Xc (90 tan 1 ) R 2 + Xc 2 R Xc

The magnitude of the ratio is therefore determined by

For special frequency, Xc=R , at which the magnitude becomes

=

1 1 = = .070 1+1 2

which defines the critical or cut-off frequency of the low-pass filter. The frequency is determined by

Xc = R 1 =R 2Cf c 1 f = c 2CRHigh-Pass Filter : While the output is taken off the resistor ,as shown in fig-3, it will respond as a high-pass filter. Av R VO 0.707

C Vi

fc Fig-3 : R-C High-Pass Filter Fig-4 : Av versus frequency for highpass filter

At any intermediate frequency, the output voltage Vo of fig-3 can be determined using the voltage divider rule:

The magnitude of the ratio is therefore determined by

Xc 90 V R jXc i V Xc 90 A = o = = v V R jXc i Vo = A = v A = v Xc R 2 + Xc 2 Xc R 2 + Xc 2

Here, Xc = Reactance of capacitor

Xc (90 tan 1 ) R 2 + Xc 2 R Xc

For special frequency, Xc=R , at which the magnitude becomes

=

1 1 = = .070 1+1 213

which defines the critical or cut-off frequency of the low-pass filter. The frequency is determined by

Apparatus:

Xc = R 1 =R 2Cf c 1 f = c 2CR

1. Capacitor 2. Resistor 3. Oscillator 4. Signal Generator 5. Bread Board 6. Wires For Low-pass filter: Capacitance, C = 1nF Resistance, R = 27 K Input Voltage, Vo = 8 V Cut off frequency,

1 f = = 5894 .6627522 Hz c 2RC

Data table for R-C low-pass filter: No. of Observation Frequency, f Voltage across Capacitor, Vo 7.8 7.7 7.3 6.8 6.3 5.8 5.5 5.2 5.0 4.8 4.4 4.1 3.8

A = o v V i0.9750 0.9625 0.9125 0.8500 0.7875 0.725 0.6875 0.6500 0.6250 0.6000 0.5500 0.5125 0.4750

V

1 100 2 1000 3 2000 4 3000 5 4000 6 5000 7 5500 8 6000 9 6500 10 7000 11 8000 12 9000 13 10000 For High-pass filter: Capacitance, C = 0.908 nF Resistance, R = 2.5 K Input Voltage, Vo = 8 V Cut off frequency,

1 f = = 6621 .661421 Hz c 2RC

Data table for R-C high-pass filter:

14

No. of Observation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17

Frequency, f 100 200 300 500 1000 2000 3000 4000 5000 5500 6000 6500 7500 8000 15000 20000 25000

Voltage across Resistor, Vo 0.14 0.24 0.38 0.62 1.25 2.40 3.30 4.00 4.60 4.80 5.00 5.20 5.50 5.80 6.30 6.50 6.60

A = o v V i0.01750 0.03500 0.04750 0.07750 0.15625 0.30000 0.41250 0.50000 0.57500 0.60000 0.62500 0.65000 0.68000 0.72500 0.78750 0.81250 0.82500

V

Calculation : FOR LOW-PASS FILTER :Cut off frequency,

1 f = = 5894 .6627522 Hz c 2RC 5894 .6627522 5250 100 = 10.93638057 % 5894 .6627522

From graph we have cut off frequency,fc =5250 Hz Percentage of error =

FOR HIGH-PASS FILTER : Cut off frequency,

1 f = = 6621 .661421 Hz c 2RC 7500 6621.661421 100 = 13.26462534 % 6621 .661421

From graph we have cut off frequency,fc =7500 Hz Percentage of error =

Discussion:Filtering system is used to select certain band of frequencies. The voltage gain versus frequency curve should be started from highest gain (Av = 1 ) and fall to zero when the cut off frequency arrives for a low-pass filter and the opposite for a high-pass filter. But practically we do not get such type of curves. It is more like fig-2 and fig-4. In this practical we have not get a curve falling from highest gain or Av =1 and fall zero after cut off frequency for low-pass filter. We should make some changes at the values of resistor and capacitor. The cure we got will have a greater amount of noise, which is unexpected.

15

Ex No : 05

Date : 19-03-2006

CHARACTERISTIC IMPEDANCE OF A FOUR TERMINAL NETWORKName: Roll: Year: Session:Group:

FAIZUS SALEHIN FH 50 2nd Year 2004-2005A-2

Theory :Most filter sections take the form of a four terminal network, and as such they possess one pair of input terminals and one pair of output terminals. With this arrangement of terminals, a filter section can be inserted directly into a two-wire line. Input ZI1 Output

ZI1

Four terminals Network

ZI2

ZI2

Fig-1 : Four Terminal Network The rectangle shown in Fig-1 is assumed to be any type of four terminal networks, the internal circuit elements of which may or may not be accessible. It is also assumed that the individual circuit elements are linear. The image impedances of a four terminal network are called ZI1 and ZI2 and are defined in the following manner. If the impedance across the input terminals (looking into the network) is ZI1 when the output terminals are closed through ZI2 , and the impedance across the output terminals (looking into the network) is ZI2 when the input terminals are closed through ZI1 , then ZI1 and ZI2 are called the image impedances of the network. The network is correctly matched when the input impedance and the output impedance are and under these conditions the network is said to be terminated on the image basis.16

A special case of image impedance termination is employed in elementary filter theory. The assumption is made that ZI1 = ZI2 and this particular value of impedance is called the characteristic impedance of the filter section. There can be two types of filter sections T-type and type. T-type Network: This type of network is shown below.

Z1Z oT

2

Z1Z 2 Zoc

2

Z oT

Zsc

Fig-2 : T-type Network

From Fig-2 , Zoc = Z1 Zsc = Z1 2 2 + Z2 +2

Z1Z 2 2 Z 2 + Z1 4 + Z1Z 22

ZscZoc = Z1

It can be shown that, + Z1Z 2 4 For our practical we are using following Figure, Rs R R Z 0T = ZocZsc = Z1

SG

OSC

XC

Fig-3 : T-type Network With Elements Here, Zoc = R j 1 ; C Z OC = X 2 + R2 C . . . . (i)

RX 2 R2 X C C j Zsc = R + R jX = R + C 2+X 2 2+X 2 R R C C

(

)

17

2 2 RX 2 R 2 XC C Z = R + + 2 SC R +X 2 R2 + X 2 C C R = R3 + 5R 2 X 2 + 4 X 4 C C 2+X 2 R C ZoT = ZscZoc -type Network : This type of network is shown below

. . . . (ii)

Z1Z o

2Z 2

2Z 2 Zoc

Z o

Zsc

Fig-4 : -type Network

From Fig-4 , 2 Z1Z 2 Z1 + 2 Z 2 2 Z 2 ( Z1 + 2 Z 2 ) Zoc = Z1 + 4Z 2 It can be shown that, Zsc = Z o = ZscZoc = Z 2 Z1 Z 1+ 1 4Z 2

Apparatus required:For T-type Network: 1. Two resistors of same resistance: 100 2. One capacitor: 0.1 10 6 F 3. One resistor of 1K 4. Bread board 5. Wires 6. Signal Generator (Internal resistance): 600 7. Oscilloscope

Table for calculating the characteristic impedance of a type four terminal network:18

RS

Frequency

Voltage Across the network 2.05 V 1.6 V

Voltage Across RS

Current through the circuit, I 8.7185 m.A 9 m. A

Impedance 235.125448 177.7777778

Characteristic impedance, Z (Practical) 204.4506778

Characteristic impedance, Z (Theoretical) 208.3188088

Short Circuit Open Circuit

1600

7500 Hz

13.95 V 14.4 V

Calculation:For T-network: Theoretically: Frequency, f = 7500 Hz; Resistance of two resistors of the T-network, R = 100 Rs = 1000 + internal resistance of signal generator = 1600 Capacitance of the capacitor of the T-network, C = 0.1 10 6 F

Capacitive reactance, XC = From equation (i) we have From equation (ii) we have

1 = 212.2065908 C ZOC = 234.588229 ZSC = 184.991064 ;

ZOT = 208.3188088 Practically:

Input voltage, VO = 16V;Voltage across the T-network when open circuited, VSC = 2.05 V Voltage across VRS = VO-VSC = 13.95 V; Current through the circuit, I= R The impedance of the T-network, ZSC = SC = 235.125448 I V V RS = 8.7185mA S

Voltage across the T-network when short circuited, VSC = 1.6 V Voltage across VRS = VO-VSC = 14.4 V; Current through the circuit, I= R The impedance of the T-network, ZSC = SC = 177.7777778 I V V RS = 9mA S

The characteristic impedance of the T-network, ZOT = ZOC Z SC = 204.4506778 ERROR: 1.856832322% RESULT:For T-type Network, ZoT: 204.4506778

Discussions:The network is very much frequency dependent. We need to take the frequency such that the total network seems to be a resistive network. The higher frequency we take the lowest will be the capacitive reactance. Thus it seems to be there is no presence of a capacitor. Thus the total impedance19

looks much like resistive. Thus the effect of capacitor falls. This will help us to determine the characterize impedance more accurate. To get better reading from oscilloscope, we need to fix the same ground point for both signal generator and oscilloscope.

20

EXP# 6TO STUDY THE I-V CHARACTERISTICS OF RECTIFIER DIODE AND CONSTRUCTION OF HALF WAVE AND FULL WAVE RECTIFIER CIRCUITName Roll Group Session THEORY:The process in which a simple harmonic a.c. voltage is converted into a unidirectional voltage is known as rectification. The term rectifier is applied to a diode when it is frequently used in a rectification process. The property of a junction diode, that it offers a small resistance and hence allows a current to flow through it when it is forward biased, is used for rectification.

: Rahatir Rashid : SH-069 ; 2nd year : A5 : 2001-2002

I-V Characteristic of a rectifier diode:Forward Characteristic: A forward bias or on condition is established by applying the positive potential to the terminal attached to p-type material and negative potential to the terminal attached to n-type material. Following fig-1 shows a circuit with forward biased diode. IF mA +V

- + A Fig-1 : Forward biased condition V + V + + A V o Fig-3 : Reverse biased conditioni

+

R

-Vr 50 V IS IR A Fig-2 : I-V Characteristic of a rectifier diode 0.7 V

VF

R

From the forward characteristic curve we get the following conclusions: The forward characteristic curve is not a straight line. Therefore the diode does not obey Ohms law. For small value of forward voltage, VF less than the internal potential barrier, V (which is approximately 0.3 V and 0.7 V for germanium diodes and silicon diodes respectively at 25o C) IF is zero. When VF becomes greater V than a small current flows. The forward voltage below which isO O

21

zero and just above which IF starts increasing rapidly is called the cut in, threshold, offset, breakpoint voltage. As is further increased IF increases very rapidly. Under the forward bias condition corresponding to the steep part of the curve the P-N junction diode offers low resistance to the flow of the current.

Reverse characteristic:A reverse bias or off condition is established by applying the positive potential to the terminal attached to n-type material and negative potential to the terminal attached to p-type material. Fig-3 shows a circuit with reverse biased diode. From the forward characteristic curve we get the following conclusions: As VR is increased from zero IR increases and reaches its maximum value Io at a small value of VR.When VR is further increased the reverse current is almost independent of magnitude of reverse voltage up to a certain critical value of VR . This reverse current is called reverse saturation current or leakage current. When VR is increased beyond the critical value, Corresponding IR increases rapidly.

Current Voltage Equation:The current voltage equation of a p-n junction diode is represented theoretically by the equation qV nkT 1 I = Ioe Where, I = the diode current in ampere Io = the reverse saturation current at To C V = the potential difference q = the electronic charge n = 1 for germanium, 2 for silicon. k = Boltzman constant.

Half wave rectifier:A simple circuit for half-wave rectification is shown in fig-4 . The voltage to be rectified is connected to the primary coil. Vi Vi Vo RL Vo Fig -4 : Half wave rectifier Fig-5 f

f

Under the action of a sinusoidal a.c. voltage of frequency 2 applied to the primary of the transformer, a.c. voltage across the secondary of the transformer, which is applied to the diode in series with RL is given by, Vi = V m sin t , here Vm is maximum voltage During the half cycle of Vi when p-region of the diode is positive with respect to n-region the diode is forward biased. Hence a current flows through the load. During the half cycle when p-region of the diode is negative with respect to n-region the diode is reverse biased and hence no current flows through load. Consequently, the22

current through load is unidirectional and it flows in the form of half-sine waves separated by period of 180O as shown in fig-5. The unidirectional current pulses are represented by,V sin t i= m = I sin t m R +R f L

, when n t (n+1) ,[here n = 0,2,4,6,.2n ]

i = 0 , when n t (n+1) ,[here n = 1,3,5,. ,(2n-1) ]

Full wave rectifier:A circuit for full-wave rectification is shown in fig-6 . The voltage to be rectified is connected to the primary coil.

D1

D3

RLD2 D4

Vo

Fig-8: Full wave rectifier

Fig-7

During the positive half cycle of input voltage to bridge rectifier, diode D1 and D4 conducts, when diodes D2 and D3 are reversed bias. D2 and D3 are forward bias during the negative half cycle of input voltage when diodes D1 and D4 are reversed bias. The result is that both positive and negative half cycles of input voltage are passed to resistance RL. Also the negative half cycles are inverted, so that the output voltage is a continuous series of positive half cycles of alternating voltage. Apparatus: 1. 2. 3. 4. 5. 6. 7. 8. 9. Precaution: 1. 2. 3. Discussion: 1. 2. 3.

Diodes Resistors Oscilloscope Transformer Bread Board Voltmeter Ammeter Signal Generator Connecting Wares The oscilloscope was calibrated carefully. For correct reading digital meters were used. Before applying voltage circuits were rechecked to avoid any types of wrong connections or loose connections. Our D.C. power supply has a highest range of 25 volts, so we could not examine reverse bias characteristic of the diode. A high value of resistor was used to secure the diodes and to reduce the loading effect. In each case of rectification, pure D.C. was not achieved.23

EXP No. # 07

To Study The I-V Characteristic of Zener Diode And Light Emitting Diode (LED) and Construction Of a Voltage stabilizer Using Zener DiodeName : Rahatir Rashid Roll : SH-069 ; 2nd year Group : A5 Session : 2001-2002

THEORY:Zener Diode: A zener diode is a special type of diode, whose impurity level is much higher than an ordinary diode. It is mainly operated in reverse biased condition. For all diode, except zener diode, at a high reverse voltage, the diode goes under breakdown condition. But in case of zener diode, we get a special breakdown at a comparatively low reverse voltage, which is known as zener breakdown. In this condition we get a highly large current without destroying the diode. Zener breakdown usually occurs in silicon P-N junctions at reverse biases of less than 5V. Under the influence of a high intensity of electric field, large numbers of electrons within the depletion region breaks the covalent bonds with their atoms. The way the electrons become free from their atoms is known as ionization by an electric field. The presence of the free electrons converts the depletion region from an almost insulator to conductor. Again it can be explained, as we knowElectric Field Strenth =

Re verse Voltage Width of Depletion Re gion

As the depletion region is smaller in a zener diode than any other diode, so the electric field strengths in zener diode are high. So at a low level of reverse voltage the electron of depletion region become isolated from their atom making the charge carrier high in depletion region. Thus a large current can be made to flow across the junction. Both external resistance and the power dissipation of the diode control this excess current. IF mA +V

- + A Fig-1 : Forward biased condition

+

R

Vr 5VVZ

Iz + + A Fig-3 : Reverse biased condition +V

IR A

VF

0.7 V

R

Fig-2 : I-V Characteristic of a zener diode

V Z ZZ = I Z24

Light Emitting Diode (LED) : LED is another special type of diode. It emits light in the visible region when it is operated in forward bias condition. Generally, the LED is made up of Gallium-Phosphide (GaP) or Gallium-Arsenic phosphide (Ga-AsP). For any type of diodes, when charged carriers recombined, energy released. For ordinary diode, this energy is released in the form of heat and also in the form of light in the invisible region. And in case of LED it released in the form of light. The color of the emitted light depends on the semiconductor material. For a. GaAs : Infra red radiation (invisible) b. GaP : Red or green c. GaAsP : Red or yellow.

+ -

R +

V

- + A -

Fig-3 : LED Circuit

Zener diode as a voltage stabilizer: One of the commonest applications of a Zener diode is as a simple voltage reference source which supplies little or no current. Fig-4 shows the circuit. Series resistor R limits the device current to V VZ IZ = S R The zener current may be set to just beyond the knee of the reverse characteristic. For low current type Zener diodes, IZT is typically 20 mA. IZ R

IL RL VZ

VS

Fig-5 : Voltage Regulator Circuit Apparatus: 1. 2. 3. 4. 5. 6. 7. 8. A zener diode Two resistor Variable D.C. voltage source Voltmeter D.C. ammeter Light emitting diode Breadboard Connecting Wares

Precaution: o Excessive voltage will cause damage to the diodes. So we should maintain a minimum voltage level which is recommended for the specific diode from the data sheets. o All circuit elements should be connected properly.25

EXP # 08

Date : 06-07-2003

To study the input and output characteristics of Common emitter configurationName : Roll : ; 2nd year Group : A5 Session : 2001-2002

THEORY:A bipolar junction transistor is a solid sate electronic control device. It consists of a silicon or germanium single crystal containing two P-N junctions. The two P-N junctions are formed between the following three layers of the semiconductor: Base: It is a very thin layer of the two types of the semiconductor. It forms the central region of the transistor. It is lightly doped than the emitter layer. Emitter & Collector: These are two layers on the opposite sides of the base layer and they are the same kind of semiconductor and opposite of the base type. Emitter layer is highly doped and shorter than collector layer. Collector layer is more lightly doped than base layer and larger than the emitter layer. There are two types of bipolar junction transistors. PNP types have P-type semiconductors, while NPN types have N-type semiconductors for emitter and collector layers. Fig -1 shows a PNP type, while Fig-2 shows NPN type transistors.

E

P B

N

P

C

E

N B

P

N

C

Fig- 1

Fig- 2

There are three configurations in which a transistor is connected in a circuit. They are: 1. 2. 3. Common-Base configuration Common-Emitter configuration Common-Collector configuration

In this experiment we are using a Common-Emitter configuration, which is also called a grounded-Emitter configuration. In this configuration the base is the input terminal, collector is the output terminal and emitter is common terminal. In this type of configuration the base current IB and collector-emitter voltage VCE are taken as independent variables. A curve representing the variations of dependent variable VBE and IC with one of the independent ones is called a characteristic curve of the transistor.26

Input Characteristics: It is a plot of the input current, IB versus input voltage, VBE for some constant values of output voltage, VCE.

Output Characteristics: It is the plot of the input current, IB versus input voltage, VBE for some constant values of output voltage, VCE.

Apparatus: 1. 2. 3. 4. 5. 6.

A NPN or PNP transistor A breadboard 2 multi meters and two voltmeters Two variable resistors Two DC power supply Connecting wires

A Vi

IB mV

IC mA mV VO

Fig: Common-Emitter connection Precaution: 1. 2. 3. 4.

All the connection should be connected properly. Transistor should be checked to be PNP or NPN before using and all three wires should be marked out. Before applying voltage, transistor breakdown voltage should be maintained. All reading should be taken carefully.

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Experiment no : 09To study the transistor characteristics of Common-Base configurationName Roll Year Session Group: : : : : A. K. M. Asaduzzaman Talukder FH-065 2nd year (hons.) 2002-2003 A-1

DEPARTMENT OF APPLIED PHYSICS & ELECTRONICS

#Name of the experiment: To study the transistor characteristics in Common-Base configuration #Objective: 1. To achieve the basic concepts about common base configuration of a transistor. 2. To study input and output characteristics for different conditions. 3. To observe the advantages and demerits of a common base transistor. #Theory: A bipolar junction transistor is a solid sate electronic control device. It consists of a silicon or germanium single crystal containing two P-N junctions. The two P-N junctions are formed between the following three layers of the semiconductor: Base: It is a very thin layer of the two types of the semiconductor. It forms the central region of the transistor. It is lightly doped than the emitter layer. Emitter & Collector: These are two layers on the opposite sides of the base layer and they are the same kind of semiconductor and opposite of the base type. Emitter layer is highly doped and shorter than collector layer. Collector layer is more lightly doped than base layer and larger than the emitter layer. There are two types of bipolar junction transistors. PNP types have P-type semiconductors, while NPN types have N-type semiconductors for emitter and collector layers. Fig -1 shows a PNP type, while Fig-2 shows NPN type transistors.

Emitter

P

NBase

P

Collecto Emitter N r

PBase

N i

Collector

Figure - 128

Figure - 2

There are three configurations in which a transistor is connected in a circuit. They are: 4. Common-Base configuration 5. Common-Emitter configuration 6. Common-Collector configuration In this experiment we are using a Common-Base configuration, which is also called a grounded-Base configuration. In this configuration the emitter is the input terminal, collector is the output terminal and base is common terminal.It is the most common configuration of transistor. In this type of configuration the input terminal contains clearly emitter current IE and base-emitter voltage and the output terminal with collector current IC and collector-emitter voltage VCE. As base terminal is grounded the emitter-base junction is forward biased and the collector-base junction is reverse biased. The basic diagram of a common base configuration for observing the characteristics curves is like belowIC mV mV VEE VCC

mA

IE

mA

Fig: Common-Base Configuration

Input Characteristics: It is the plot of the input current, IE versus input voltage, VBE for some constant values of output voltage, VCB.It is also called the driving point characteristics curve.

IE (mA)

VCB = 20V

VC = 1V

VBE (V) Input characteristics of a common base transistor

29

Output Characteristics: The output characteristics of a common base configuration is the graph plotting the output voltage VCB with input current IC when input current IE is fixed. It is also known as the collector characteristics curve.

IC (mA)

IE = 7mA IE = 4mA IE = 0mA

Saturation region

Active region

VCB (V) Cutoff region Output characteristics of a common base transistor

#Apparatus: 7. A NPN or PNP transistor 8. A breadboard 9. 2 multi meters and two voltmeters 10. Two variable resistors 11. Two DC power supply 12. Connecting wires #Table: Table for input characteristics in common base configuration No. of Observation1 2 3 4 5 6 7 8 9 10 11

VCE = 1 volt VBE volt0 0.18 0.42 0.53 0.58 0.63 0.66 0.71 0.75 0.76 0.8

VCE = 10 volt VBE Volt0 0.48 0.52 0.56 0.6 0.63 0.69 0.73 0.75 0.77 0.85

IB uA0 0.2 0.3 2.8 12.5 35.7 53.5 88.7 117.8 129.3 167.4

IB uA0 0 1.8 7 20.1 37.4 72.7 96 113.9 130 196.7

30

Table for output characteristic in common base configuration No. of Observation1 2 3 4 5 6 7 8 9 10 11 12 13

IB = 30 uA VCE IC volt mA0 0.04 0.05 0.07 0.11 0.15 0.18 0.2 0.25 0.3 0.36 0.57 0 0.76 1.02 1.73 3.18 4.81 6.33 7.1 8.7 10 10.78 11.9

IB = 66 uA VCE IC volt mA0 0.01 0.04 0.1 0.15 0.17 0.2 0.27 0.34 0.42 0.48 0 0.37 1.1 3.62 6.4 7.52 9 12.5 16 18.5 19.83

IB = 108uA VCE IC volt mA0 0.17 0.3 0.53 1.64 2.69 3.2 3.92 5 5.5 6.15 6.83 7.6 0 1.7 2.2 2.3 2.43 2.56 2.73 2.8 3.06 3.25 3.55 4.09 4.5

#Precaution: 1. All the connections should be connected properly. 2. All the reading should be taken carefully. 3. The voltage across the emitter-base should be less then the breakdown voltage, it should be specified looking the specification sheet. 4. Transistors terminals should be identified before preceding the experiment. 5. The terminals of the meters should be connected properly; otherwise it will deflect in the wrong way. #Discussion: From this experiment some clear view about transistor biasing has been found. In case of input characteristics it was found that less IB current flows for higher level of VCE. This phenomenon is termed as early effect. When VCE become larger it provides high reverse bias in CB junction; which causes in greater depletion region penetration into the base. Thus distance between CB and EB junction is shortened, and most of the charge carriers from the EB junction flow across the CB junction, and fewer flow out via the base terminal. On the other hand, in the output characteristics it has been found that IC reduced to zero when VCE becomes zero. This is because VCE is the sum of the VCB & VBE. So with the reduction in VCE, VCB is also reduced and causes the C-B junction to be less reverse biased. After a certain voltage it causes the C-B junction to be as forward biased which in terms reduced the IC current. And thus, IC become zero at VCE =0. The leakage current can be determined by causing IB = 0. But as it was in the micro ampere level it could not scratch in the out put characteristics graph as the graph was in mille-ampere level. Any electrical device should have a higher input impedence and lower output impedence in order to have the most perfect result.For this reason we have used resistor in kilo-ohm range and ohmic range respectively in cases of input and output terminal.As the total circuit configuration was really a complex one we used different color of wires to avoid complexity and the voltmeters and ammeters were marked also. After all of these, the reading of base current in input characteristics was a bit harder to measure as because it was in micro-ampere range.31

EXP # 10

Date : 06-07-2003 To Study and Constructing Of Clipper and Clamper CircuitName : Roll : ; 2nd year Group : A5 Session : 2001-2002

THEORY:Clippers: The diode networks which have the ability to clip off a portion of the input signal without distorting the remaining part of the alternating wave form. There are two types general categories of clippers: series and parallel. The series configuration is defined as one where the diode is in series with load, while the parallel variety has the diode in a branch parallel to the load. Following Figures of 1 and 2 are

32

series type and figures 3,4,5,6 and 7 are parallel type.

Fig : 1

Fig : 3

Fig : 2

Fig : 4

Fig : 5

Fig : 6

Fig : 7

The clipper which includes one or more the one dc voltage supplies has a great deal of effects on their output signal. If the negative pole of the dc supply connected with p-type of the diode then the dc supply will press the diode to be at off state until the input positive voltage rises to the level of the dc supply. These types of clippers are shown in Figures 2 and 4. While, if the positive pole of the dc supply connected with p-type of the diode then the dc supply will continue to maintain the on state of the diode to until the input negative voltage rises to the level of the dc supply. These types of clippers are shown in Figures 5 and 6. Figure 7 shows the clipper which includes two parallel connections which will make the output signal as both parts of the input signal has been cut off for the dc supplies.

Clampers :The clamping network is one that will clamp a signal to a different dc level without changing the supplied pick to pick voltage. The network must have a capacitor, a diode and a resistive component, but it can also employ an independent dc supply to introduce an additional shift. The magnitude of resistance and capacitance must be chosen such that the time constant = RC is large enough to ensure that the voltage across the capacitor does not discharge significantly during the interval the diode is nonconducting. For a clamping network:33

The total swing of the output is equal to the total swing of the output signal. 2V V -V V -V Fig : 9 2V

Fig : 8

V -V V1 Fig : 10

V1

V -V V1 Fig : 11 V1

V -V V1 Fig : 12 V1

V -V V1 Fig : 13

V1

Apparatus:1. 2. 3. 4. 5. 6. 7. 8. DC power supply Oscilloscope Diode Capacitor Resistor Signal Generator Bread Board Connecting Wires

Precaution: Every element should be connected carefully. DC voltage source should be chosen carefully. Oscilloscope should be calibrated carefully. Signal generators ground must be connected with oscilloscope ground to avoid distortion.

34

EXP # 11 INTRODUCTION TO LOGIC GATES AND CONSTRUCTION OF EQUIVALENT GATESName Roll Session Group Theory :In most cases diodes and transistors are used to construct logic gates. Now a day every logic gates are fabricated as ICs. There are three kinds of basic logic gates. They are AND gate, OR gate and NOT gate. Using semiconductor devices, we describe the construction and workings of these gates below. AND gate: An and gate works like taking more than one inputs and giving only one output which is equal to the multiplication of inputs. We can only give input level high or low. Thus if any of the inputs of a AND gate have input level low, then we have the output low. The construction of a AND gate is given in Fig-1 with its truth table.

: : ; 2nd year : 2001-2002 : A-5

+5 V D1

5 K A

A 0 0

B 0 1 0 1

AB 0 0 0 1

B D2 LED

1 1

Fig-1 When A is connected to ground and B connected to Vcc, current will go to ground through D1. When B is connected to ground and A connected to Vcc, current will go to ground through D2. When both A and B is connected to Vcc, current will go to ground through LED. SO we can say, only when both A and B will be connected with Vcc, then the LED will go on as shown in he truth table, where 1 and 0 represents Vcc and ground respectively. OR gate: An OR gate works like taking more than one inputs and giving only one output which is equal to the addition of the inputs. We can only give input level high or low. Thus if all of the inputs of an OR gate have input level low, then we have the output low and if any of the inputs of an OR gate have input level high, then we have the output high.The construction of an OR gate is given in Fig-2 with its truth table.

35

+5 V D1

A 0 0A

B 0 1 0 1

AB 0 1 1 1

B D2 5 K LED

1 1

Fig-2 When A is connected to ground and B connected to Vcc, current will go to ground through D2 through LED. When B is connected to ground and A connected to Vcc, current will go to ground through D1 through LED. When both A and B is connected to ground, no current will pass through LED. SO we can say, only when both A and B will be connected with ground, then the LED will go off state as shown in he truth table, where 1 and 0 represents Vcc and ground respectively. NOT gate: An OR gate works like taking one input and giving the output which is opposite to the input. We can only give input level high or low. Thus if the input of an NOT gate have input level low, then we have the output high and vice-versa. The construction of a NOT gate is given in Fig-3 with its truth table. +5 V 2.2 K 470 A

A 0

__ A 1 0

5 K

LED Fig-3

1

When A is connected to ground, transistor will be at off state. So current will go to ground through LED. When A connected to Vcc, current will go to ground through the transistor so that the transistor acts at saturation level. Thus no current will flow through LED. Here 1 and 0 represents Vcc and ground respectively. Apparatus: 1. 2. 3. 4. 5. 6. 7. Diodes Transistors LED Resistors Wires Bread Board DC power supply

Precaution:36

1. 2. 3. 4.

Circuit elements should be connected carefully. DC voltage (Vcc) should be in the range 5V - 7V, which will not herm diodes, transistor and LEDs. Resistance of the resistors should be chosen carefully to fulfill the job. LED should checked before using.

Discussions:We need to choose Resistance of the resistor parallel with LED of Fig-2 such that the current through LED be sufficiently high to light on it brightly enough with no herm done to the LED. We also need to bias the NOT gate configuration such that the transistor activates at cutoff region when A connected to Vcc and at saturation region when A connected to ground. We need to set resistance, so that for the cutoff situation LED and transistor are not burned out.

37

EXP # 12 REALIZATION OF LOGIC EXPRESSION USING COMBINATIONAL LOGICTheory :Basic logic circuits are divided into two broad classes: Combinational logic circuit 1. Sequential logic circuit In combinational logic circuits, the output of any instant only depends on the input present at the instants, ie there is no scope for memory in the circuits. In this experiment we are using these types of circuits. Once the expression for a logic circuit has been obtained, We may be able to reduce it to a simpler form containing fewer terms or fewer variable in one or more terms. The new expression then can be used to implement a circuit that is equivalent to the original circuit but that contains fewer gates and connections. We can do this by using boolean algebra theorems. This needs two essential steps: 1. The original expression is put into SOP form by repeated application of DeMorgans theorems and multiplication of terms. 2. Once the original expression is in SOP form, the product terms are checked for common factors and factoring is performed wherever possible. Hopefully, the factoring results in the elimination of one or more terms. Or, we can also reduce the real expression by using Karnaugh map. The steps below are followed in using the K-map method for simplifying a Boolean expression: 1. Construct the K-map and place 1s in those sequences corresponding to the 1s in the truth table and place 0s in the other squares. 2. Examine the map for adjacent 1s and loop those 1s which are not adjacent to any other 1s. 3. Next, look for those 1s are adjacent to only one other 1. Loop any pair containing such 1s. 4. Loop any octet even if it contains some 1s that have already been looped. 5. Loop any quad even if it contains one or more 1s that have not already been looped, making sure to use the minimum number of loops. 6. Loop any pairs necessary to include any 1s that have not yet been looped, making sure to use the minimum number of loops. 7. Form the OR sum of all the terms generated by each loop. The truth table, which we will be working on, is like below: A 0 0 0 0 1 1 1 1 Apparatus: 1. 2. 3. B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 Result 1 0 1 1 1 0 0 1 Expression ___ ABC _ _ ABC _ ABC __ ABC ABC

7408 (two input AND gate), 7404 (NOT gate), 7432 (two input OR gate) ICs Connecting wire Breadboard38

4. 5 volt dc power supply 5. LED Realization: From the truth table we can write: Result, D = A BC + ABC + ABC + A BC + ABC The realization of the given expression using the ICs with the pin connections and LED connection are made. The LED is lighted only for those inputs which satisfied the given expression. There are only five conditions to be satisfied. For For For

For For Proper realization for only these five combinations, the LED should lighted on. Simplification: K-map for this truth table is like below: C AB _ AB __ AB _ AB From the K-map we can reduce it to: D = BC + AB + BC A B C 1 1 0 0 _ C 0 1 1 1

A BC term --- terminate all the input to zero ABC term --- terminal A to zero other to Vcc ABC term --- terminals A & c to zero and B to Vcc A BC term --- terminals B & c to zero and A to Vcc ABC term --- All terminals to Vcc

D=

Precaution: 1. The DC supply should be fixed at 5 volt. 2. All ICs should be checked first. 3. The ICs should be placed in the bread board perfectly and carefully. 4. LED should be checked too. Discussion: We should always check the DC supply whether it is at 5 volt level. If this is not maintained the ICs would be burned off for high voltage or LED will not be lighted for the inputs. We also need to get sure that all the ICs are connected to Vcc and ground with proper pins.

EXP # 1339

TO CONSTRUCT AND STUDY THE HALF ADDER, FULL ADDER, HALF SUBTRCTOR AND FULL SUBTRACTORTheory:Half Adder Circuit: The simplified binary adder is called a half adder which can add two binary digits at a time and produces a two bit data, ie sum and carry. Truth table-1 lists the two columns of output, one of sum and one of carry. The sum and carry outputs have the table of logic pattern like given below:

A B SUM = AB A 0 0 1 1 B 0 1 0 1 SUM 0 1 1 0 CARRY 0 0 0 1

CARRY = AB

Full Adder Circuit: A full adder circuit has three input and two outputs. It can add three bits at a time. The bits to be added come from the two registers and a third input comes from the carry generated by the previous addition. It gives us two outputs, sum and carry. The table of logic pattern is like given below:

ABC SUM = ABC A B 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 C SUM CARRY ( carry from previous) 0 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 0 1 1 1 1

CARRY=C(A+B)+ AB

Half Subtractor: It can only subtract two binary digits at a time and produce a difference (D) and a borrow (B) output. It has two inputs and two outputs. The table of logic pattern is like given below:

40

A B DIFFERENCE = AB

BORRW = AB

A 0 0 1 1

B 0 1 0 1

D 0 1 1 0

B 0 1 0 0

Full subtractor: A full subtractor circuit has three input of one minuend (X) , one subtrahend (Y) and one borrow (Bi-1) and two outputs of one difference (D) and one borrow (Bi). The table of logic pattern is like given below: X Y Bi-1

Difference = XYBi-1 X 0 0 0 0 1 1 1 1 Y 0 0 1 1 0 0 1 1 Bi-1 0 1 0 1 0 1 0 1 Difference 0 1 1 0 1 0 0 1 Borrow 0 1 1 1 0 0 0 1

Bi = Bi 1 ( X Y ) + X YApparatus: 1. 2. 3. 4. 5. Precaution: 1. 2. 3. 4.

DC power supply IC 7404, 7408, 7432, 7486 Bread board LED Connecting wires The DC supply should be fixed at 5 volt. All ICs should be checked first. The ICs should be placed in the bread board perfectly and carefully. LED should be checked too.

Discussion: We should always check the DC supply whether it is at 5 volt level. If this is not maintained the ICs would be burned off for high voltage or LED will not be lighted for the inputs. We also need to get sure that all the ICs are connected to Vcc and ground with proper pins.

41