2 2 lanai uma schematics document -...
TRANSCRIPT
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2007-03-19
Intel Crestline-GM + ICH8M
REV :1.2(DELL: X02)
???
PCB P/N: ???
uFCPGA Mobile Merom
ASUS P/N :
Lanai UMA Schematics Document
???
BOM NO. ???
ElsaMODEL NAME :
ASUS CONFIDENTIAL
PCB NO :
Cover Page1.2 1 68Monday, March 19, 2007PROJECT: SHEET OF
DATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :RELEASE DATE :
Part Number Description
DA800004H0L PCB 00B LA-3071P REV0 M/B
MB PCB
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PG 49PG 59
DMI INTERFACE
PG 47
POWER SEQUENCELOGIC
Crestline
SIO
POWER CONTROLSWITCH
POWER
PG 9,10,11,12,13,14
SIO
USB2.0(P5)
PG 52
+3.3V_SUS/+5V_SUS/+3.3V_RUN+5V/+3.3V/+1.8V/+1.25_RUN
LANAI: UMA
PG 40
CLOCK
FLASH
+1.8V_SUS/+0.9V_DDR_VTT
IO Board
LPC
Merom(478 Micro-FCPGA)XDP
+VCC_GFX_CORE/+1.25V_RUN
USB CONN.
(Symbol Rev.09)
SPI
1299 uFCBGA
PG 21
ECE5011ExpanderUSB 2.0 Hub(4)
REGULATOR
(Symbol Rev.09)
POWER SYSTEM
PG 28
128 Pins VTQFP
CARD READER1394/R5C833
QFN-68
RJ45/Magnetic
POWER VCORE
128 Pins VTQFP
PG 37
Bluetooth
PG 7,8 POWER I/O
MEC5025128KB FlashTMKBC
CAMERA
676 BGA
+1.5V_RUN/+1.05V_VCCP
REGULATOR(Symbol Rev.09)
CK410M+LP
USB2.0(P0,P1)
ICH8-M PCI
DISCHARGE PATH
PG 57
PG 41
PG 49
BC
PG 15,16,17,18
POWER
PG 51
POWERCHARGER
PG 38
POWERCON.
USB2.0(P7)
5V_ALW & 3.3V_ALW
PG 50
D.BCON
IHDA
SATA-HDDSATA
CD-ROMIDE
TouchpadCON.
SPI PS/2
CIR
R5538EXPRESS-CARD
PCIE (Lane4)
USB2.0(P6)
USB Board
CRT CONN. VGA VGA
MINI-CARD
USB CONN.x2USB2.0(P2,3)
USB2.0(P2,3)
MINI-CARD
TO TVCONN.PG 30
S/PDIF
AUDIO/AMP
DIGITALMIC.
JACK Board
MDC
PG 28
AudioJacks*3
RJ11 Board
RJ11
WtoBCON
SpeakerCON
SIMCARD
SIM CARD Board
PG 31
PG 32,33,34
PG 35
PG 36
PG 39
PG 41PG 41
FAN &THERMAL
PG 43EMC4001
USERINTERFACEPG 42 PG 42
SNIFFER
PG 44,45,46
BCM5906KMLG
PG 48
PG 53
PG 54
PG 55
PG 56PG 58
PG 46 PG 46
533/667 MHZ DDR II
533/667 MHZ DDR II
DDR2-SODIMM1
PG 19
PG 19
DDR2-SODIMM2
LVDS
TVOUT
Panel ConnectorPG 28
TV CONN.
WLAN
WWAN
PCIEx1 (Lane2)
USB2.0(P9)USB2.0(P9)
PCIEx1 (Lane2)
PG 31
TVOUT
PCIE (Lane6)
PG 40
CAPBTNCON.
BLOCK DIAGRAM1.2 2 68Monday, March 19, 2007PROJECT: SHEET OF
DATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :RELEASE DATE :
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D
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1 1
2 2
3 3
4 4
5 5
Pg# Description DNI LIST
INDEX
01
02
07-08
03
09-14
15-18
19-20
32-34
22-27
37
38
39
40
41
42
43
44-46
47
50
51
30
35
36
48
49
52
31
28
29
21
04
06
INDEX
Schematic Block Diagram
Bus connection
BLANK PAGE
XDP
LVDS CON & Camera & DMIC
SMBUS BLOCK
Power Sequence Logic
BtoB CON
Clock Generator ( CK410M+LP )
LOM BCM5906
HARDWARE MONITOR ( EMC4001 )
Power Circuit
MEDIA CARD READER / 1394 ( R5C833 )
Magnetics and RJ-45
FLASH & RTC & CAPBTN CONN
TOUCH PAD & BT & CIR & LID
ICH8M
USB PORT x 2
Crestline
EC ( MEC5025 )
DDRII SO-DIMM( 533MHz 667MHz )、
SIO ( ECE5011 )
TV OUT CON
MDC CONN
SWITCH & LED
RGB CON
CPU ( Merom 、 Penryn )
Power Rail
Cover Page
05
53-59
SCREW PAD
SATA(HDD & CD_ROM)
PCI-Express Card
AUDIO CODEC & AMP
Power Control Switch
60
61 Change List 1
Change List 262
68
Pg#
66
64
65
USB board cover page
63
67
DNI LIST
POWER CIRCUIT CHANGE LIST
Modem board change List
Description
USB PORT ( SINGLE * 2 )
Modem board cover page
RJ-11 CONN
INDEX1.2Lanai 3 68Monday, March 19, 2007PROJECT: SHEET OF
DATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :RELEASE DATE :
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
ICH8-0(EHCI#1)
ICH8-1(EHCI#1)
ICH8-2(EHCI#1)
ICH8-3(EHCI#1)
ICH8-4(EHCI#1)
ICH8-7(EHCI#2)
ICH8-5(EHCI#1)
ICH8-6(EHCI#2)
ICH8-9(EHCI#2)
ICH8-8(EHCI#2)
User1(Single port , in USB BD)
User2(Single port , in USB BD)
User3(Dual port-bottom , in I/O BD)
User4(Dual port-top , in I/O BD)
Camera
ExpressCard
BT Module
WWAN / Mini Card
USB TABLE
Note : No USB for WLAN
WWAN / Mini CardLane 1
PCI Express TABLE
Lane 2
Lane 3
Lane 4
Lane 5
Lane 6
WLAN / Mini Card
ExpressCard
PCI TABLE
R5C833PCI_PIRQC#PCI_PIRQD#
PCI_REQ1#PCI_GNT1#
Footprint is 0402 if there is no descriptionResistor
Ferrite Bead
Footprint Definition
Capacitor Footprint is 0402 if there is no description
Footprint is 0603 if there is no description
For all of ESD diode, they should be placed as close aspossible to connectors and the signals from connectorsshould be routed to ESD diodes first. There is no branchor via before diodes
Layout Note
PCI_AD17
PCIDEVICE IDSEL REQ#/GNT# PIRQ
LAN BCM5906KMLG
Bus Connection1.2Lanai <OrgName>4 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
ICH8-M
SIO
DIMM 0
DIMM 1
MEC5025
MEM_SDATA 195MEM_SCLK 197AJ26 ICH_SMBCLK
AD19 ICH_SMBDATA
+3.3V_RUN
7002
7002
2.2K 2.2K+3.3V_RUN
BatteryCONN.
100
+3.3V_ALW10
2.2K
111 PBAT_SMBDAT
9
112 PBAT_SMBCLK
CHARGER2.2K
SMB_DAT 4SMB_CLK 3
+3.3V_ALW
100
100 THRM_SMBCLK
4.7K
+3.3V_ALW
ECE400111+3.3V_ALW
4.7K
1299 THRM_SMBDAT
AC17 AMT_SMBCLKAE19 AMT_SMBDAT
2.2K
12 CKG_SMBDAT
2.2K
CLK GEN.7002
CLK_SDATA 17
2.2K
CLK_SCLK 16
+3.3V_RUN
2.2K
7002
+3.3V_RUN13 CKG_SMBCLK
+3.3V_ALW
2.2K2.2K
+3.3V_SUS
Express Card WWAN3032
78
MEM_SCLK 197MEM_SDATA 195
+3.3V_SUS
10K 10K
VGA LCD_DDCDATLCD_DDCCLK 43
2.2K2.2K
44
+3.3V_RUNLVDSConnector
8 LCD_SMBCLK
47pF
+3.3V_ALW
47pF
8.2K
+3.3V_ALW
7 LCD_SMDDAT
8.2K
3435
+3.3V_RUN
3230
WLAN
I/O Board
5 DOCK_SMBDAT
8.2K8.2K
+5V_MEDIA
6 DOCK_SMBCLKCAPBTN Board
SMBUS BLOCK1.2Lanai <OrgName>5 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
RU
NPW
RO
KIM
VP_V
R_O
N
3.3V
_RU
N_O
NSU
S_O
N
1.25
V_R
UN_
ON
ALW
ON
THER
M_S
TP#
+1.8V_SUS
DDR
_ON
DELL CONFIDENTIAL/PROPRIETARY
TPS51120
+1.05V_VCCP
+0.9V_DDR_VTT
+1.25V_RUN
SN0508073AL
WO
NTH
ERM
_STP
#
PROPRIETARY NOTE: THIS SHEET OF ENGINEERING DRAWING AND SPECIFICATIONS CONTAINS CONFIDENTIAL
TRADE SECRET AND OTHER PROPRIETARY INFORMATION OF DELL INC. ("DELL") THIS DOCUMENT MAY NOT
BE TRANSFERRED OR COPIED WITHOUT THE EXPRESS WRITTEN AUTHORIZATION OF DELL. IN ADDITION,
NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS WAY BE USED BY OR DISCLOSED TO ANY THIRD
PARTY WITHOUT DELL'S EXPRESS WRITTEN CONSENT.
+3.3V_RTC_LDO
1.5V
_RU
N_O
N
3.3V
_SU
S_O
N
FDS6612A SI4800BDY
DDR
_ON
EESIDE
1.05
_RUN
_ON
TPS51100
RUN_
ON
+5V_ALW
FDS6612A
0.9V
_DDR
_VTT
_ON
+2.5V_RUN
+5V_SUS
+1.8V_RUN
SN0508073
BAT54S
ADAPTER
1.8V
_RUN
_ON
SI4800BDY
+5V_RUN +3.3V_RUN+15V_ALW
+VCC_CORE +1.5V_RUN+3.3V_ALW
EMC4001
+3.3V_SUS
ISL6260CISL6208
+PWR_SRC
BATTERY
+5V_ALW2
+RTC_CELL
ALW
ON
THER
M_S
TP#
SI4800BDY
Power Rail1.2Lanai 6 68Monday, March 19, 2007PROJECT: SHEET OF
DATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :RELEASE DATE :
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout note: Place voltagedivider within0.5" of GTLREFpin
Note:H_DPRTSTP need to daisy chainfrom ICH8 to IMVP6 to CPU.
Comp0,2 connect with Zo=27.4ohm, Comp1,3connect with Zo=55 ohm, make those traceslength shorter than 0.5". Trace should beat least 25 mils away from any othertoggling signal.
For the purpose of testability, route these signalsthrough a ground referenced Zo= 55 ohm trace thatends in a via that is near a GND via and isaccessible through an oscilloscope connection.
FSB BCLK BSEL2 BSEL1 BSEL0
533 133 0 0 1
667 166 0 1 1
800 200 0 1 0
Place C close to theCPU_TEST4 pin. Make sureCPU_TEST4 routing isreference to GND and awayfrom other noisy signal.
Voltage Level Shift
MEROM CPU (1)1.2Lanai <OrgName>7 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
H_A#20
H_A#12
H_A#7
H_A#19
H_A#3
H_A#35
H_A#11
H_A#23
H_A#34H_A#33
H_A#5
H_A#30
H_A#22
H_A#18
H_A#21
H_A#13 H_IERR#H_A#14
H_A#25H_A#26
H_A#6
H_A#4
H_A#27
H_A#8
H_A#17
H_A#31H_A#32
H_A#10H_A#9
H_THERMDCH_THERMDA
H_A#28
H_A#15H_A#16
H_A#24
H_A#29
H_A#[3..16]
H_A#[17..35]
CPU_PROCHOT#
H_THERMDCH_THERMDA
COMP0
COMP3COMP2COMP1
CPU_TEST3
CPU_TEST5
CPU_TEST1
CPU_TEST2
CPU_TEST4
CPU_TEST6
XDP_BPM#2
XDP_BPM#0XDP_BPM#1
XDP_TDI
XDP_DBRESET#
XDP_TCK
XDP_TDOXDP_TMS
XDP_BPM#3
XDP_BPM#5XDP_BPM#4
XDP_TRST#
XDP_TMS
XDP_TDI
XDP_TCK
XDP_BPM#5
XDP_TRST#
H_REQ#0H_REQ#1
H_REQ#4
H_REQ#2H_REQ#3
H_REQ#[0..4]
CPU_PROCHOT#
H_D#[0..63]
H_D#40
CPU_TEST4
H_D#28
H_D#9
H_D#3
H_D#61
H_D#35
H_D#20
H_D#41
H_D#39
H_D#21
H_D#12
H_D#8
H_D#59
H_D#53
H_D#38
V_CPU_GTLREF
H_D#29
H_D#6
H_D#55
H_D#33
CPU_TEST3
H_D#24
H_D#18
H_D#15
H_D#48
H_D#32
H_D#34
H_D#23
COMP2
H_D#62
H_D#47
H_D#26H_D#25
H_D#16
H_D#10
H_D#52
H_D#27
H_D#11
H_D#[0..63]
COMP0
H_D#45
CPU_TEST6
H_D#0
H_D#56
H_D#2
H_D#[0..63]
H_D#51
H_D#49
H_D#46
H_D#43
H_D#22
H_D#58
H_D#30
H_D#14
H_D#60
H_D#37
CPU_TEST5
CPU_TEST2
H_D#31
H_D#13
H_D#4
H_D#1
H_D#[0..63]
COMP3
H_D#63
H_D#54
H_D#17
COMP1
H_D#50
H_D#44
H_D#42
CPU_TEST1
H_D#7
H_D#57
H_D#36
H_D#19
H_D#5
H_RESET#
H_DSTBP#09H_DINV#09
H_D#[0..63]9 H_D#[0..63] 9
H_DSTBN#19
H_DPRSTP# 10,15,53
CPU_MCH_BSEL010,21
H_DPSLP# 15
H_PSI# 53
H_DSTBN#09
H_DINV#19H_DSTBP#19
H_DSTBP#2 9
H_DSTBP#3 9
H_CPUSLP# 9
H_DSTBN#3 9
H_DINV#3 9
H_D#[0..63]9
H_PWRGOOD 15
H_DSTBN#2 9
CPU_MCH_BSEL210,21
H_DINV#2 9
CPU_MCH_BSEL110,21
H_D#[0..63] 9
H_DRDY# 9
H_A20M#15
H_BPRI# 9
CLK_CPU_BCLK 21
H_STPCLK#15
H_BNR# 9
H_A#[3..16]9
H_HIT# 9
H_LOCK# 9
H_REQ#[0..4]9
H_INTR15
H_THERMTRIP# 43
H_DEFER# 9
H_A#[17..35]9
CLK_CPU_BCLK# 21
H_ADS# 9
H_ADSTB#09
H_HITM# 9
H_BR0# 9
H_NMI15
H_THERMDC 43
H_RESET# 9,52
H_ADSTB#19
H_FERR#15
H_INIT# 15
H_DBSY# 9
H_SMI#15
H_TRDY# 9
H_IGNNE#15
H_THERMDA 43
H_RS#0 9H_RS#1 9H_RS#2 9
H_DPWR# 9
XDP_TCK 52
XDP_DBRESET# 17,38,52
XDP_BPM#1 52
XDP_TDI 52XDP_TDO 52
XDP_BPM#5 52
XDP_BPM#0 52
XDP_BPM#3 52
XDP_TRST# 52XDP_TMS 52
XDP_BPM#4 52
XDP_BPM#2 52
H_PWRGD_XDP 52
EC_CPU_PROCHOT# 37
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP +3.3V_ALW
C410 2200PF/50V MLCC/+/-10% /*
12
R159 56Ohm 5%1 2
R398
54.9Ohm1%
12
R117 649Ohm 1%12
C409 0.1UF/10V /*MLCC/+/-10%1 2
R112 1KOhm 5%1 2
R397
27.4Ohm1%
12
R118
27.4Ohm1%
12
T271
R114 54.9Ohm 1%12
R368 56Ohm 5%1 2
R396 1KOhm /*1%12
R395 1KOhm /*1%12
DATA GRP 1
DATA GRP 0
DATA
GRP
2DA
TA G
RP 3
MISC
U25B
SOCKET478
MOLEX/47387-4781E22F24E26G22F23G25E25E23K24G24J24J23H22F26K22H23J26H26H25
N22K25P26R23L23
M24L22
M23P25P23P22T24R24L25T25N25L26
M26N24
AD26C23D25C24
AF26AF1A26
B22B23C21
Y22AB24V24V26V23T22U25U23Y25W22Y23W24W25AA23AA24AB25Y26AA26U22
AE24AD24AA21AB22AB21AC26AD20AE22AF23AC25AE21AD21AC22AD23AF22AC23AE25AF24AC20
R26U26AA1Y1
E5B5D24D6D7AE6
D0#D1#D2#D3#D4#D5#D6#D7#D8#D9#D10#D11#D12#D13#D14#D15#DSTBN0#DSTBP0#DINV0#
D16#D17#D18#D19#D20#D21#D22#D23#D24#D25#D26#D27#D28#D29#D30#D31#DSTBN1#DSTBP1#DINV1#
GTLREFTEST1TEST2TEST3TEST4TEST5TEST6
BSEL0BSEL1BSEL2
D32#D33#D34#D35#D36#D37#D38#D39#D40#D41#D42#D43#D44#D45#D46#D47#
DSTBN2#DSTBP2#
DINV2#
D48#D49#D50#D51#D52#D53#D54#D55#D56#D57#D58#D59#D60#D61#D62#D63#
DSTBN3#DSTBP3#
DINV3#
COMP0COMP1COMP2COMP3
DPRSTP#DPSLP#DPWR#
PWRGOODSLP#PSI#
H CLK
ADDR GRO
UP0
RESE
RVED
ICH
ADDR GRO
UP1
XDP/
ITP
SIG
NALS
CONT
ROL
THERMAL
U25A
SOCKET478
MOLEX/47387-4781J4L5L4K5M3N2J1N3P5P2L2P4P1R1M1
K3H2K2J3L1
Y2U5R3
W6U4Y5U1R4T5T3
W2W5Y4U2V4
W3AA4AB2AA3
V1
A6A5C4
D5C6B4A3
M4N5T2V3B2C3D2
D22D3F6
H1E2G5
H5F21E1
F1
D20B3
H4
C1F3F4G3G2
G6E4
AD4AD3AD1AC4AC2AC1AC5AA6AB3AB5AB6C20
D21A24B25
C7
A22A21
A3#A4#A5#A6#A7#A8#A9#A10#A11#A12#A13#A14#A15#A16#ADSTB0#
REQ0#REQ1#REQ2#REQ3#REQ4#
A17#A18#A19#A20#A21#A22#A23#A24#A25#A26#A27#A28#A29#A30#A31#A32#A33#A34#A35#ADSTB1#
A20M#FERR#IGNNE#
STPCLK#LINT0LINT1SMI#
RSVD01RSVD02RSVD03RSVD04RSVD05RSVD06RSVD07RSVD08RSVD09RSVD10
ADS#BNR#BPRI#
DEFER#DRDY#DBSY#
BR0#
IERR#INIT#
LOCK#
RESET#RS0#RS1#RS2#
TRDY#
HIT#HITM#
BPM0#BPM1#BPM2#BPM3#PRDY#PREQ#
TCKTDI
TDOTMS
TRST#DBR#
PROCHOT#THERMDATHERMDC
THERMTRIP#
BCLK0BCLK1
T151
R399 0Ohm /*5%1 2
R1631KOhm1%
12
R1642KOhm1%
12
GS D
32
1
Q54
2N7002Id=280mA/Pd=300mW/*
R122 54.9Ohm 1%12
R121 54.9Ohm 1%12
R119 54.9Ohm 1%12
R120
54.9Ohm1%
12
R1612.2KOhm/*
12
R160 56Ohm 5%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout Note:Place 0.01U/25V near PINB26.
Route VCCSENSE and VSSSENSEtraces at 27.4ohms with 50mils spacing and lengthmatched to within 25 mil.Place PU and PD within1 inch of CPU.
All use 10U 4V (+-20% , X6S , 0805)Pb-Free.
8 inside cavity, north side, secondary layer.
8 inside cavity, south side, secondary layer.
6 inside cavity, north side, primary layer.
6 inside cavity, south side, primary layer.
Layout out:Place these inside socket cavity on North side secondary.
100U/25V *4 Remove to POWER CIRCUIT .
No.43
Merom CPU (2)1.2Lanai <OrgName>8 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
VCCSENSE
VSSSENSE
VSSSENSEVCCSENSE
VCCSENSE 53
VSSSENSE 53
VID0 53VID1 53VID2 53VID3 53VID4 53VID5 53VID6 53
+1.05V_VCCP
+1.5V_RUN
+1.05V_VCCP+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORE
+VCC_CORER128100Ohm1%
12
C39210UF/4VMLCC/+/-20%pt_c0805
12
C38510UF/4VMLCC/+/-20%pt_c0805
12
C18710UF/4VMLCC/+/-20%pt_c0805
12
C39010UF/4VMLCC/+/-20%pt_c0805
12
C17210UF/4VMLCC/+/-20%pt_c0805
12
C13110UF/4VMLCC/+/-20%pt_c0805
12
C13310UF/4VMLCC/+/-20%pt_c0805
12
C40210UF/4VMLCC/+/-20%pt_c0805
12
C39710UF/4VMLCC/+/-20%pt_c0805
12
C40010UF/4VMLCC/+/-20%pt_c0805
12
R127100Ohm1%
12
+CE5
220UF/2Vpt_c7343d_h75SANYO/2TPF220M7
12
C38310UF/4VMLCC/+/-20%pt_c0805
12
C39910UF/4VMLCC/+/-20%pt_c0805
12
C15810UF/4VMLCC/+/-20%pt_c0805
12
C18310UF/4VMLCC/+/-20%pt_c0805
12
U25D
SOCKET478
MOLEX/47387-4781A4A8
A11A14A16A19A23AF2
B6B8
B11B13B16B19B21B24C5C8
C11C14C16C19
C2C22C25
D1D4D8
D11D13D16D19D23D26
E3E6E8
E11E14E16E19E21E24
F5F8
F11F13F16F19
F2F22F25G4G1
G23G26
H3H6
H21H24
J2J5
J22J25K1K4
K23K26
L3L6
L21L24M2M5
M22M25
N1N4
N23N26
P3
P6P21P24R2R5R22R25T1T4T23T26U3U6U21U24V2V5V22V25W1W4W23W26Y3Y6Y21Y24AA2AA5AA8AA11AA14AA16AA19AA22AA25AB1AB4AB8AB11AB13AB16AB19AB23AB26AC3AC6AC8AC11AC14AC16AC19AC21AC24AD2AD5AD8AD11AD13AD16AD19AD22AD25AE1AE4AE8AE11AE14AE16AE19AE23AE26
AF6AF8AF11AF13AF16AF19AF21A25AF25
A2
VSS001VSS002VSS003VSS004VSS005VSS006VSS007VSS008VSS009VSS010VSS011VSS012VSS013VSS014VSS015VSS016VSS017VSS018VSS019VSS020VSS021VSS022VSS023VSS024VSS025VSS026VSS027VSS028VSS029VSS030VSS031VSS032VSS033VSS034VSS035VSS036VSS037VSS038VSS039VSS040VSS041VSS042VSS043VSS044VSS045VSS046VSS047VSS048VSS049VSS050VSS051VSS052VSS053VSS054VSS055VSS056VSS057VSS058VSS059VSS060VSS061VSS062VSS063VSS064VSS065VSS066VSS067VSS068VSS069VSS070VSS071VSS072VSS073VSS074VSS075VSS076VSS077VSS078VSS079VSS080VSS081
VSS082VSS083VSS084VSS085VSS086VSS087VSS088VSS089VSS090VSS091VSS092VSS093VSS094VSS095VSS096VSS097VSS098VSS099VSS100VSS101VSS102VSS103VSS104VSS105VSS106VSS107VSS108VSS109VSS110VSS111VSS112VSS113VSS114VSS115VSS116VSS117VSS118VSS119VSS120VSS121VSS122VSS123VSS124VSS125VSS126VSS127VSS128VSS129VSS130VSS131VSS132VSS133VSS134VSS135VSS136VSS137VSS138VSS139VSS140VSS141VSS142VSS143VSS144VSS145VSS146VSS147VSS148VSS149VSS150VSS151VSS152VSS153
VSS155VSS156VSS157VSS158VSS159VSS160VSS161VSS162VSS163
VSS154
C39110UF/4VMLCC/+/-20%pt_c0805
12
+CE19
220UF/2Vpt_c7343d_h75SANYO/2TPF220M7/*
12
C1240.1UF/10VMLCC/+/-10%
12
C18010UF/4VMLCC/+/-20%pt_c0805
12
C38610UF/4VMLCC/+/-20%pt_c0805
12
C16610UF/4VMLCC/+/-20%pt_c0805
12
C4040.1UF/10VMLCC/+/-10%
12
C3800.1UF/10VMLCC/+/-10%
12
C15710UF/4VMLCC/+/-20%pt_c0805
12
C15910UF/4VMLCC/+/-20%pt_c0805
12
+CE16
220UF/2Vpt_c7343d_h75SANYO/2TPF220M7/*
12
C13210UF/4VMLCC/+/-20%pt_c0805
12
C14010UF/4VMLCC/+/-20%pt_c0805
12
U25C
SOCKET478
MOLEX/47387-4781A7A9
A10A12A13A15A17A18A20
B7B9
B10B12B14B15B17B18B20C9
C10C12C13C15C17C18D9
D10D12D14D15D17D18
E7E9
E10E12E13E15E17E18E20
F7F9
F10F12F14F15F17F18F20AA7AA9
AA10AA12AA13AA15AA17AA18AA20
AB9AC10AB10AB12AB14AB15AB17AB18
AB20AB7AC7AC9AC12AC13AC15AC17AC18AD7AD9AD10AD12AD14AD15AD17AD18AE9AE10AE12AE13AE15AE17AE18AE20AF9AF10AF12AF14AF15AF17AF18AF20
G21V6J6K6M6J21K21M21N21N6R21R6T21T6V21W21
B26C26
AD6AF5AE5AF4AE3AF3AE2
AF7
AE7
VCC001VCC002VCC003VCC004VCC005VCC006VCC007VCC008VCC009VCC010VCC011VCC012VCC013VCC014VCC015VCC016VCC017VCC018VCC019VCC020VCC021VCC022VCC023VCC024VCC025VCC026VCC027VCC028VCC029VCC030VCC031VCC032VCC033VCC034VCC035VCC036VCC037VCC038VCC039VCC040VCC041VCC042VCC043VCC044VCC045VCC046VCC047VCC048VCC049VCC050VCC051VCC052VCC053VCC054VCC055VCC056VCC057VCC058VCC059VCC060VCC061VCC062VCC063VCC064VCC065VCC066VCC067
VCC068VCC069VCC070VCC071VCC072VCC073VCC074VCC075VCC076VCC077VCC078VCC079VCC080VCC081VCC082VCC083VCC084VCC085VCC086VCC087VCC088VCC089VCC090VCC091VCC092VCC093VCC094VCC095VCC096VCC097VCC098VCC099VCC100
VCCP01VCCP02VCCP03VCCP04VCCP05VCCP06VCCP07VCCP08VCCP09VCCP10VCCP11VCCP12VCCP13VCCP14VCCP15VCCP16
VCCA01VCCA02
VID0VID1VID2VID3VID4VID5VID6
VCCSENSE
VSSSENSEC181
10UF/4VMLCC/+/-20%pt_c0805
12
C17910UF/4VMLCC/+/-20%pt_c0805
12
C4140.01UF/25VMLCC/+/-10%pt_c0603
12
C13410UF/4VMLCC/+/-20%pt_c0805
12
C1930.1UF/10VMLCC/+/-10%
12
+CE18
220UF/2Vpt_c7343d_h75SANYO/2TPF220M7
12
C39810UF/4VMLCC/+/-20%pt_c0805
12
C17610UF/4VMLCC/+/-20%pt_c0805
12
C15210UF/4VMLCC/+/-20%pt_c0805
12
C39610UF/4VMLCC/+/-20%pt_c0805
12
C3810.1UF/10VMLCC/+/-10%
12
+CE7
220UF/2Vpt_c7343d_h75SANYO/2TPF220M7
12
+ CE20220UF/4V
TAN/Lf_T=2000hrs_105C/+/-20%pt_c7343d_h79
12
C12610UF/4VMLCC/+/-20%pt_c0805
12
C40310UF/4VMLCC/+/-20%pt_c0805
12
C418
10UF/4Vpt_c0805MLCC/+/-20%
12
C14510UF/4VMLCC/+/-20%pt_c0805
12
+CE6
220UF/2Vpt_c7343d_h75SANYO/2TPF220M7
12
C4050.1UF/10VMLCC/+/-10%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout Note:Place the 0.1uF decoupling capacitorwithin 100 mils from GMCH pins.
Layout Note:H_RCOMP trace should be10-mil wide with 20-milspacing
Crestline(HOST)1.2Lanai <OrgName>9 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
H_A#18
H_A#5
H_A#23
H_A#4
H_A#11H_A#10
H_A#6
H_A#14
H_A#24
H_A#20
H_A#26
H_A#16
H_A#27
H_A#7
H_A#30
H_A#19
H_A#25
H_A#3
H_A#8
H_A#22
H_A#13
H_A#29
H_A#15
H_A#12
H_A#9
H_A#28
H_A#21
H_A#17
H_A#31
H_A#34
H_A#32H_A#33
H_A#35
H_SWING
H_D#2
H_D#0
H_D#37
H_D#7
H_D#26
H_D#19
H_D#56
H_D#51
H_D#60
H_D#43
H_D#53
H_D#57
H_D#33
H_D#22H_D#23
H_D#59
H_D#14
H_D#42
H_D#17
H_D#6
H_D#12
H_D#10
H_D#61
H_D#38
H_D#49
H_D#55
H_D#25
H_D#13
H_D#48
H_D#28
H_D#30
H_D#36
H_D#54
H_D#20
H_D#35
H_D#44
H_D#24
H_D#47
H_D#45
H_D#40
H_D#11
H_D#15
H_D#18
H_D#52
H_D#29
H_D#41
H_D#27
H_D#31
H_D#46
H_D#63
H_D#9
H_D#58
H_D#4
H_SCOMP
H_D#5
H_D#16
H_D#1
H_D#50
H_D#34
H_D#62
H_D#21
H_D#32
H_D#39
H_D#3
H_D#8
H_RCOMP
H_SCOMP#
H_SWING
H_RCOMP
H_SCOMPH_SCOMP#
H_REF
H_A#[3..35]H_D#[0..63]
H_RESET#7,52H_CPUSLP#7
H_DINV#0 7H_DINV#1 7H_DINV#2 7H_DINV#3 7
H_DSTBN#0 7H_DSTBN#1 7H_DSTBN#2 7H_DSTBN#3 7
H_DSTBP#0 7H_DSTBP#1 7H_DSTBP#2 7H_DSTBP#3 7
H_ADS# 7H_ADSTB#0 7H_ADSTB#1 7H_BNR# 7
H_BR0# 7
H_DBSY# 7
H_DPWR# 7H_DRDY# 7H_HIT# 7H_HITM# 7
H_TRDY# 7H_LOCK# 7
CLK_MCH_BCLK# 21CLK_MCH_BCLK 21
H_DEFER# 7
H_BPRI# 7
H_A#[3..35] 7
H_REQ#0 7H_REQ#1 7H_REQ#2 7H_REQ#3 7H_REQ#4 7
H_RS#0 7H_RS#1 7H_RS#2 7
H_D#[0..63]7
+1.05V_VCCP
+1.05V_VCCP
+1.05V_VCCP
R367221Ohm
1%
12
C3710.1UF/10V
MLCC/+/-10%
12
R12954.9Ohm1%
12
R13054.9Ohm1%
12
R3652KOhm1%
12
C3670.1UF/10V
MLCC/+/-10%
12
R366100Ohm1%
12
HOST
U10A
CRESTLINE_965GM
G17C14K16B13L16J17B14K19P15R17B16H20L19D17M17N16J19B18E19B17
J13
B15E17
B11C11M11C15F16L13
G12H17G20C8E8F12
AM7
B6
AM5
E2
A11H13
G2
M10
M3
W3
AB2
AJ14
AE5
N8H2
C10
N12N9H5
P13K9M2
W10Y8V4
G7
J1N5N3
W6W9N2Y7Y9P4
M6
N1AD12
AE3AD9AC9AC7
AC14AD11AC11
H7
AD7AB1
Y3AC6AE2AC5AG3AJ9AH8
H3
AE9AE11AH12
AJ5AH5AJ6AE7AJ7AJ2
G4
AJ3AH2
AH13
F3
D6
K5L2AD13AE13
H8K7
M7K3AD2AH11
L7K2AC2AJ10
W1
B9A9
B7
E4C6G10
M14E13
B12
C18A19B19N19
B3
E5
C2
E12D7D8
W2
H_A#_10H_A#_11H_A#_12H_A#_13H_A#_14H_A#_15H_A#_16H_A#_17H_A#_18H_A#_19H_A#_20H_A#_21H_A#_22H_A#_23H_A#_24H_A#_25H_A#_26H_A#_27H_A#_28H_A#_29
H_A#_3
H_A#_30H_A#_31
H_A#_4H_A#_5H_A#_6H_A#_7H_A#_8H_A#_9
H_ADS#H_ADSTB#_0H_ADSTB#_1
H_BNR#H_BPRI#
H_BREQ#
HPLL_CLK#
H_CPURST#
HPLL_CLK
H_D#_0
H_REQ#_2H_REQ#_3
H_D#_1
H_D#_10
H_D#_20
H_D#_30
H_D#_40
H_D#_50
H_D#_60
H_D#_8H_D#_9
H_DBSY#
H_D#_11H_D#_12H_D#_13H_D#_14H_D#_15H_D#_16H_D#_17H_D#_18H_D#_19
H_D#_2
H_D#_21H_D#_22H_D#_23H_D#_24H_D#_25H_D#_26H_D#_27H_D#_28H_D#_29
H_D#_3
H_D#_31H_D#_32H_D#_33H_D#_34H_D#_35H_D#_36H_D#_37H_D#_38H_D#_39
H_D#_4
H_D#_41H_D#_42H_D#_43H_D#_44H_D#_45H_D#_46H_D#_47H_D#_48H_D#_49
H_D#_5
H_D#_51H_D#_52H_D#_53H_D#_54H_D#_55H_D#_56H_D#_57H_D#_58H_D#_59
H_D#_6
H_D#_61H_D#_62H_D#_63
H_D#_7
H_DEFER#
H_DINV#_0H_DINV#_1H_DINV#_2H_DINV#_3
H_DPWR#H_DRDY#
H_DSTBN#_0H_DSTBN#_1H_DSTBN#_2H_DSTBN#_3
H_DSTBP#_0H_DSTBP#_1H_DSTBP#_2H_DSTBP#_3
H_SCOMP
H_AVREFH_DVREF
H_TRDY#
H_HIT#H_HITM#H_LOCK#
H_REQ#_0H_REQ#_1
H_REQ#_4
H_A#_32H_A#_33H_A#_34H_A#_35
H_SWING
H_CPUSLP#
H_RCOMP
H_RS#_0H_RS#_1H_RS#_2
H_SCOMP#R3641KOhm1%
12
R13224.9Ohm1%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout Note:Location of all MCH_CFG strapresistors needs to be close tominmize stub.
Non-iAMTR0933,R0937Intel 30.1ohm 1%
UMA
Layout Note:Place 150 ohmtermination resistorsclose to GMCH
UMA
DMI LaneReversal
CFG9
DMI X2 SelectLow=DMIx2High=DMIx4 (Default)
Low=No SDVO Device Present(defaults)High=SDVO Device Prsent
SDVO Present.
SDVO/PCIEConcurrentOperation
Low=Normal (default)High=Lane Reversed
PCI ExpressGraphic Lane
Low=Reveise LaneHigh=Normal operation
CFG16FSB DynamicODT
Low=Dynamic ODT DisableHigh=Dynamic ODT Enable (default)
Low=Only SDVO or PCIEx1 is operational (defaults)High=SDVO and PCIEx1 are operating sumultaneously via PEG port
SDVO_CRTL_DATA
CFG19
CFG5
CFG20
UMA
LCTLA_CLK, LCTLB_DATAconnect to XDP CONN.R327,R324 Stuff.
No.2
No.10
Crestline(VGA,DMI)1.2Lanai <OrgName>10 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
VGA_RED
LCD_DDCCLKLCTLB_DATA
VGA_BLU
LCD_DDCDATA
VGA_GRN
LCTLA_CLK
L_IBG
VCC3G_PCIE_R
CFG11
SM_RCOMP_VOH
PLTRST#_R
CFG15
CFG19
CFG8
CFG3
CFG14
CFG20
SMRCOMPP
CFG6
CFG9
SM_RCOMP_VOL
SM_RCOMP_VOH
PM_EXTTS#1
CFG18
SMRCOMPN
CFG4
PM_EXTTS#1
MCH_CLVREF
CFG10
CFG13
THERMTRIP_MCH#
CFG5
CFG7
PM_EXTTS#0
CFG17
SM_RCOMP_VOL
CFG12
THERMTRIP_MCH#
PM_EXTTS#0
CFG16
MCH_CLVREF
L_IBG
VGA_REDVGA_GRNVGA_BLU
SMRCOMPNSMRCOMPP
DDR_A_MA14DDR_B_MA14
PLTRST#_R
LCD_DDCCLK
LCTLA_CLK
LCD_DDCDATA
LCTLB_DATA
TV_Y50
G_CLK_DDC250
LCD_A2-28
LCD_A2+28
LCD_B1+28
VGA_GRN50
TV_C50
LCD_B2+28
LCD_B2-28
TV_CVBS50
BIA_PWM28
LCD_DDCCLK28
LCD_B0+28
PANEL_BKEN38
LCD_A0+28
LCD_A1-28
VGA_RED50
G_DAT_DDC250
LCD_B0-28
LCD_ACLK+28
VGA_BLU50
LCD_A1+28
LCD_ACLK-28
LCD_B1-28
VGAHSYNC50
LCD_DDCDAT28
LCD_A0-28
LCD_BCLK+28LCD_BCLK-28
ENVDD28
VGAVSYNC50
DMI_MRX_ITX_N0 16
DPRSLPVR17,53
DMI_MTX_IRX_N2 16
CLK_MCH_3GPLL# 21
M_CLK_DDR#2 19
H_DPRSTP#7,15,53
M_CLK_DDR#1 19
DMI_MTX_IRX_N0 16
DMI_MRX_ITX_P1 16
DMI_MTX_IRX_P1 16
DMI_MRX_ITX_P2 16
DMI_MRX_ITX_N3 16
DDR_CS2_DIMMB# 19,20
DMI_MTX_IRX_N3 16
DMI_MRX_ITX_N1 16
DDR_CS1_DIMMA# 19,20
DDR_CKE1_DIMMA 19,20
CPU_MCH_BSEL07,21
DDR_CKE0_DIMMA 19,20
DDR_CKE2_DIMMB 19,20
CLK_MCH_3GPLL 21
M_CLK_DDR#3 19
DMI_MTX_IRX_N1 16
M_ODT1 19,20
PM_BMBUSY#17
DMI_MTX_IRX_P2 16
DMI_MRX_ITX_P3 16
DMI_MRX_ITX_P0 16
M_ODT3 19,20
DMI_MTX_IRX_P0 16
DMI_MRX_ITX_N2 16
DDR_CS0_DIMMA# 19,20
DDR_CKE3_DIMMB 19,20
CL_CLK0 17
M_ODT0 19,20
DMI_MTX_IRX_P3 16
M_ODT2 19,20
M_CLK_DDR#0 19
ICH_CL_RST0# 17
CLK_3GPLLREQ# 21
ICH_CL_PWROK 17,37
MCH_ICH_SYNC# 17
CL_DATA0 17
M_CLK_DDR0 19
M_CLK_DDR3 19
M_CLK_DDR1 19
CPU_MCH_BSEL27,21
PM_EXTTS#119
M_CLK_DDR2 19
THERMTRIP_MCH#43
ICH_PWRGD17,51
PM_EXTTS#019
CPU_MCH_BSEL17,21
DDR_CS3_DIMMB# 19,20
MCH_DREFCLK 21MCH_DREFCLK# 21DREF_SSCLK 21DREF_SSCLK# 21
LCTLB_DATA52LCTLA_CLK52
DDR_A_MA1419,20DDR_B_MA1419,20
SB_NB_PCIE_RST#16
PLTRST#16,35,37
+VCC_PEG
V_DDR_MCH_REF
+3.3V_RUN
+3.3V_RUN
+1.05V_VCCP
+1.8V_SUS
+1.25V_RUN
+1.8V_SUS
+3.3V_RUN
R343150Ohm1%
12
T3 1
T98 1
R11020Ohm
1%
12
T109 1
T7 1
C1080.01UF/25VMLCC/+/-10%
12
LVDS
PCI-EXPRESS GRAPHICS
TV
VGA
U10C
CRESTLINE_965GM
N43M43
J51L51N47T45T50U40Y44Y40AB51W49AD44AD40AG46AH49AG45AG41
J50L50M47U44T49T41W45W41AB50Y48AC45AC41AH47AG49AH45AG42
N45
AC46
N51R50T42Y43W46W38AD39
U39
AC49AC42AH39AE49AH44
U47
M45T38T46N50R51U43W42Y47Y39AC38AD47AC50AD43AG39AE50AH43
E39E40C37D35K40
L41L43N41N40D46C45
G51E51F49
E50F48
D44E42
G44B47B45
A47A45
H39
E27G27K27
F27J27L27
H32G32
K33G35
K29J29
F33C32
F29E29
E33
G50
E44
J40
M35P33
PEG_COMPIPEG_COMPO
PEG_RX#_0PEG_RX#_1PEG_RX#_2PEG_RX#_3PEG_RX#_4PEG_RX#_5PEG_RX#_6PEG_RX#_7PEG_RX#_8PEG_RX#_9
PEG_RX#_10PEG_RX#_11PEG_RX#_12PEG_RX#_13PEG_RX#_14PEG_RX#_15
PEG_RX_0PEG_RX_1PEG_RX_2PEG_RX_3PEG_RX_4PEG_RX_5PEG_RX_6PEG_RX_7PEG_RX_8PEG_RX_9
PEG_RX_10PEG_RX_11PEG_RX_12PEG_RX_13PEG_RX_14PEG_RX_15
PEG_TX#_0
PEG_TX#_10
PEG_TX#_3PEG_TX#_4PEG_TX#_5PEG_TX#_6PEG_TX#_7PEG_TX#_8PEG_TX#_9
PEG_TX#_1
PEG_TX#_11PEG_TX#_12PEG_TX#_13PEG_TX#_14PEG_TX#_15
PEG_TX#_2
PEG_TX_0PEG_TX_1PEG_TX_2PEG_TX_3PEG_TX_4PEG_TX_5PEG_TX_6PEG_TX_7PEG_TX_8PEG_TX_9
PEG_TX_10PEG_TX_11PEG_TX_12PEG_TX_13PEG_TX_14PEG_TX_15
L_CTRL_CLKL_CTRL_DATAL_DDC_CLKL_DDC_DATAL_VDD_EN
LVDS_IBGLVDS_VBGLVDS_VREFHLVDS_VREFLLVDSA_CLK#LVDSA_CLK
LVDSA_DATA#_0LVDSA_DATA#_1LVDSA_DATA#_2
LVDSA_DATA_1LVDSA_DATA_2
LVDSB_CLK#LVDSB_CLK
LVDSB_DATA#_0LVDSB_DATA#_1LVDSB_DATA#_2
LVDSB_DATA_1LVDSB_DATA_2
L_BKLT_EN
TVA_DACTVB_DACTVC_DAC
TVA_RTNTVB_RTNTVC_RTN
CRT_BLUECRT_BLUE#
CRT_DDC_CLKCRT_DDC_DATA
CRT_GREENCRT_GREEN#
CRT_HSYNCCRT_TVO_IREF
CRT_REDCRT_RED#
CRT_VSYNC
LVDSA_DATA_0
LVDSB_DATA_0
L_BKLT_CTRL
TV_DCONSEL_0TV_DCONSEL_1
R3521KOhm0.1%
12
T86 1
T16 1
R821KOhm1%
12
T20 1
R3260Ohm
5%
12
R327 10KOhm 5% /*1 2
R330 1.3KOhm 0.5%pt_r06031 2
R345150Ohm1%
12
R340150Ohm1%
12
R336 4.02KOhm /*1%12
R324 10KOhm 5% /*1 2
R350150Ohm1%
12
R329 2.2KOhm 5%1 2
T111
T105 1
T14 1
PM
MISC
NC
DDR MUXING
CLK
DMI
CFG
RSVD
GRAPHICS VID
ME
U10B
CRESTLINE_965GM
AV29BB23
BF23
BA25
AW30BA23
BG23
AW25
BE29AY32BD39BG37
BG20BK16BG16BE13
BH39
BH18BJ15BJ14BE16
BL15BK14
AR49AW4
L32N33
N24
P27N27
L35
C21C23F23N23G23J20C20R24L23J23E23E20K23M20M24
G41
L36J36
AW49AV20
B42C42H48H47
AN47AJ38AN42AN46
AM47AJ39AN41AN45
AJ46AJ41AM40AM44
AJ47AJ42AM39AM43
AR37
AL36AM36
AM37
BJ20BK22BF19BH20BK18
L39
AV23
AW23
BC23BD24
AW20BK20
AR12AR13AM12AN13
P36P37R35N35
E35A39C38B39E36
BJ18
BK31BL31
N20G36
J12
AM49AK50AT43AN49AM50
C48D47B44C44
BJ29BE24
B51
BJ51BK51BK50BL50BL49BL3BL2BK1BJ1E1A5
C51B50A50A49
H35K36G39
D20
G40
H10
A35B37B36B34C34
K45K44
A37BK2 R32
SM_CK_0SM_CK_1
RSVD28
SM_CK_3
SM_CK#_0SM_CK#_1
RSVD29
SM_CK#_3
SM_CKE_0SM_CKE_1SM_CKE_3SM_CKE_4
SM_CS#_0SM_CS#_1SM_CS#_2SM_CS#_3
RSVD34
SM_ODT_0SM_ODT_1SM_ODT_2SM_ODT_3
SM_RCOMPSM_RCOMP#
SM_VREF_0SM_VREF_1
CFG_18CFG_19
CFG_2
CFG_0CFG_1
CFG_20
CFG_3CFG_4CFG_5CFG_6CFG_7CFG_8CFG_9CFG_10CFG_11CFG_12CFG_13CFG_14CFG_15CFG_16CFG_17
PM_BM_BUSY#
PM_EXT_TS#_0PM_EXT_TS#_1PWROKRSTIN#
DPLL_REF_CLKDPLL_REF_CLK#
DPLL_REF_SSCLKDPLL_REF_SSCLK#
DMI_RXN_0DMI_RXN_1DMI_RXN_2DMI_RXN_3
DMI_RXP_0DMI_RXP_1DMI_RXP_2DMI_RXP_3
DMI_TXN_0DMI_TXN_1DMI_TXN_2DMI_TXN_3
DMI_TXP_0DMI_TXP_1DMI_TXP_2DMI_TXP_3
RSVD10
RSVD12RSVD11
RSVD13
RSVD22RSVD23RSVD24RSVD25RSVD26
PM_DPRSTP#
SM_CK_4
SM_CK#_4
RSVD30RSVD31
RSVD35RSVD36
RSVD5RSVD6RSVD7RSVD8
RSVD1RSVD2RSVD3RSVD4
GFX_VID_0GFX_VID_1GFX_VID_2GFX_VID_3
GFX_VR_EN
RSVD27
SM_RCOMP_VOHSM_RCOMP_VOL
THERMTRIP#DPRSLPVR
RSVD9
CL_CLKCL_DATA
CL_PWROKCL_RST#CL_VREF
RSVD37RSVD38RSVD39RSVD40
RSVD32RSVD33
RSVD21
NC_1NC_2NC_3NC_4NC_5NC_6NC_7NC_8NC_9NC_10NC_11NC_12NC_13NC_14NC_15
SDVO_CTRL_CLKSDVO_CTRL_DATA
CLK_REQ#
RSVD14
ICH_SYNC#
RSVD20
RSVD41RSVD42RSVD43RSVD44RSVD45
PEG_CLK#PEG_CLK
TEST_1NC_16 TEST_2
T91 1
R355 4.02KOhm /*1%12
C860.1UF/10VMLCC/+/-10%
12T89
1
R357 0Ohm 5% /*1 2
T5 1
C3510.01UF/25VMLCC/+/-10%
12
R360 0Ohm 5%1 2
R3511KOhm0.1%
12
R84392Ohm1%pt_r0603
12
R5360Ohm
5%
12
R3252.4KOhm1%
12
T131
R335 10KOhm 5%1 2
T8 1
T6 1
C1092.2UF/10VMLCC/+/-10%c0603,pt_c0603
12
T121
R35456Ohm 5%
1 2
T4 1T2 1
R33920KOhm5%
12
R5370Ohm
5%
12
T21 1
T112 1
R341 30Ohm 1%pt_r06031 2
T19 1
R36320Ohm
1%
12
R338 30Ohm 1%pt_r06031 2T100 1
R3483.01KOhm1%
12
T113 1
T99 1
T901
R359 4.02KOhm /*1%12
R342150Ohm1%
12
T18 1
T22 1
R337 10KOhm 5%1 2
R356 4.02KOhm /*1%12
R333 4.02KOhm /*1%12
T9 1
T110 1T93 1
R9024.9Ohm 1%1 2
T111 1
R334 2.2KOhm 5%1 2
T107 1
R344150Ohm1%
12
C3532.2UF/10VMLCC/+/-10%c0603,pt_c0603
12
T17 1
R358 100Ohm 5%12
T10 1
R332 0Ohm 5%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Crestline(DDR2)1.2Lanai <OrgName>11 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
DDR_A_D30
DDR_A_D15
DDR_A_D50
DDR_A_DQS#0
DDR_A_D56
DDR_A_D21
DDR_A_D23
DDR_A_D47
DDR_A_DM1
DDR_A_DQS1
DDR_A_MA3
DDR_A_D44
DDR_A_D5
DDR_A_D36
DDR_A_DM2
DDR_A_DQS#7
DDR_A_D55
DDR_A_CAS#
DDR_A_DQS4
DDR_A_D35DDR_A_D34
DDR_A_D8
DDR_A_MA0
DDR_A_DQS0
DDR_A_MA11
DDR_A_D4
DDR_A_D25
DDR_A_DM5
DDR_A_D27
DDR_A_DQS6
DDR_A_D24
DDR_A_D57
DDR_A_D16
DDR_A_D20
DDR_A_BS1
DDR_A_D59
DDR_A_DQS#2
DDR_A_D17
DDR_A_MA12
DDR_A_D42
DDR_A_D48
DDR_A_BS2DDR_A_D1
DDR_A_D61
DDR_A_D33
DDR_A_D2
DDR_A_D53
DDR_A_DQS#3
DDR_A_MA5
DDR_A_DQS3
DDR_A_D51
DDR_A_BS0
DDR_A_D39DDR_A_D40
DDR_A_DM0
DDR_A_D37DDR_A_D38 DDR_A_MA6
DDR_A_DQS#5
DDR_A_D52
DDR_A_DM6
DDR_A_MA8
DDR_A_D14
DDR_A_D63
DDR_A_DQS5
DDR_A_MA9
DDR_A_DM7
DDR_A_D22
DDR_A_D12
DDR_A_MA10
DDR_A_DQS7
DDR_A_MA13
DDR_A_DM4
DDR_A_DQS#6
DDR_A_D11
DDR_A_D62
DDR_A_MA7
DDR_A_D9
DDR_A_D41
DDR_A_D0
DDR_A_D46
DDR_A_D18
DDR_A_D26
DDR_A_DQS#1
DDR_A_D13
DDR_A_MA2
DDR_A_D43
DDR_A_D31
DDR_A_DQS#4
DDR_A_D10
DDR_A_D28
DDR_A_MA1DDR_A_D32
DDR_A_D19
DDR_A_DM3
DDR_A_D60
DDR_A_D58
DDR_A_DQS2
DDR_A_MA4
DDR_A_D7
DDR_A_D49
DDR_A_D54
DDR_A_D29
DDR_A_D3
DDR_A_D45
DDR_A_D6
DDR_A_WE#
DDR_A_RAS#
DDR_B_MA2
DDR_B_D48
DDR_B_D9
DDR_B_D42
DDR_B_D23
DDR_B_DQS#7
DDR_B_MA11
DDR_B_D58
DDR_B_D3
DDR_B_D8
DDR_B_D34
DDR_B_D32
DDR_B_MA12
DDR_B_MA7
DDR_B_BS1
DDR_B_DQS2
DDR_B_D47
DDR_B_MA3
DDR_B_D18
DDR_B_DM0
DDR_B_D15 DDR_B_DQS0
DDR_B_D46
DDR_B_D63
DDR_B_D39
DDR_B_D37
DDR_B_D7
DDR_B_D43
DDR_B_CAS#
DDR_B_D13
DDR_B_D20 DDR_B_DQS5
DDR_B_DM1
DDR_B_D22
DDR_B_D27
DDR_B_D52
DDR_B_D54
DDR_B_MA0
DDR_B_D17
DDR_B_MA9
DDR_B_D44
DDR_B_D62
DDR_B_D35
DDR_B_D25
DDR_B_D19
DDR_B_D11
DDR_B_BS2
DDR_B_DQS6
DDR_B_D16
DDR_B_MA4
DDR_B_DQS#5
DDR_B_D5
DDR_B_DQS3
DDR_B_D0
DDR_B_D38
DDR_B_D4
DDR_B_D28
DDR_B_BS0
DDR_B_DQS7
DDR_B_D60
DDR_B_D31
DDR_B_D50
DDR_B_MA6
DDR_B_D14
DDR_B_D1
DDR_B_DM2
DDR_B_D29
DDR_B_D2
DDR_B_D49
DDR_B_D41
DDR_B_D61
DDR_B_MA5
DDR_B_D45
DDR_B_MA10
DDR_B_D59
DDR_B_DQS#4
DDR_B_D56
DDR_B_DQS#3
DDR_B_DM3
DDR_B_D24
DDR_B_DQS1
DDR_B_MA13
DDR_B_MA8
DDR_B_D53
DDR_B_DQS#6
DDR_B_D51
DDR_B_DQS#1
DDR_B_D12
DDR_B_D30
DDR_B_MA1
DDR_B_D21
DDR_B_DM7
DDR_B_D55
DDR_B_D40
DDR_B_D57
DDR_B_DQS#0
DDR_B_D6
DDR_B_D26
DDR_B_D36
DDR_B_DM4DDR_B_DM5
DDR_B_D10
DDR_B_DQS#2
DDR_B_DQS4
DDR_B_D33
DDR_B_DM6
DDR_B_WE#
DDR_B_RAS#
DDR_A_CAS# 19,20
DDR_A_BS1 19,20DDR_A_BS2 19,20
DDR_A_RAS# 19,20
DDR_A_WE# 19,20
DDR_B_BS1 19,20DDR_B_BS2 19,20
DDR_B_BS0 19,20
DDR_B_CAS# 19,20
DDR_B_RAS# 19,20
DDR_B_WE# 19,20
DDR_A_BS0 19,20
DDR_A_MA[0..13] 19,20
DDR_A_D[0..63]19
DDR_A_DM[0..7] 19
DDR_B_DQS#[0..7] 19
DDR_B_DM[0..7] 19
DDR_B_MA[0..13] 19,20
DDR_B_DQS[0..7] 19
DDR_B_D[0..63]19
DDR_A_DQS[0..7] 19
DDR_A_DQS#[0..7] 19
DDR SYSTEM MEMORY B
U10E
CRESTLINE_965GM
AP49AR51
BA49BE50BA51AY49BF50BF49BJ50BJ44BJ43BL43
AW50
BK47BK49BK43BK42BJ41BL41BJ37BJ36BK41BJ40
AW51
BL35BK37BK13BE11BK11BC11BC13BE12BC12BG12
AN51
BJ10BL9BK5BL5BK9
BK10BJ8BJ6BF4BH5
AN50
BG1BC2BK3BE4BD3BJ2BA3BB3AR1AT3
AV50
AY2AY3AU2AT2
AV49BA50BB50
AY17BG18BG36
BE17
AR50BD49BK45BL39BH12BJ7BF3AW2
AT50BD50BK46BK39BJ12BL7BE2AV2AU50BC50BL45BK38BK12BK7BF2AV3
BC18BG28
BG17BE37BA39BG13
BG25AW17BF25BE25BA29BC28AY28BD37
AV16AY18
BC17
SB_DQ_0SB_DQ_1
SB_DQ_10SB_DQ_11SB_DQ_12SB_DQ_13SB_DQ_14SB_DQ_15SB_DQ_16SB_DQ_17SB_DQ_18SB_DQ_19
SB_DQ_2
SB_DQ_20SB_DQ_21SB_DQ_22SB_DQ_23SB_DQ_24SB_DQ_25SB_DQ_26SB_DQ_27SB_DQ_28SB_DQ_29
SB_DQ_3
SB_DQ_30SB_DQ_31SB_DQ_32SB_DQ_33SB_DQ_34SB_DQ_35SB_DQ_36SB_DQ_37SB_DQ_38SB_DQ_39
SB_DQ_4
SB_DQ_40SB_DQ_41SB_DQ_42SB_DQ_43SB_DQ_44SB_DQ_45SB_DQ_46SB_DQ_47SB_DQ_48SB_DQ_49
SB_DQ_5
SB_DQ_50SB_DQ_51SB_DQ_52SB_DQ_53SB_DQ_54SB_DQ_55SB_DQ_56SB_DQ_57SB_DQ_58SB_DQ_59
SB_DQ_6
SB_DQ_60SB_DQ_61SB_DQ_62SB_DQ_63
SB_DQ_7SB_DQ_8SB_DQ_9
SB_BS_0SB_BS_1SB_BS_2
SB_CAS#
SB_DM_0SB_DM_1SB_DM_2SB_DM_3SB_DM_4SB_DM_5SB_DM_6SB_DM_7
SB_DQS_0SB_DQS_1SB_DQS_2SB_DQS_3SB_DQS_4SB_DQS_5SB_DQS_6SB_DQS_7
SB_DQS#_0SB_DQS#_1SB_DQS#_2SB_DQS#_3SB_DQS#_4SB_DQS#_5SB_DQS#_6SB_DQS#_7
SB_MA_0SB_MA_1
SB_MA_10SB_MA_11SB_MA_12SB_MA_13
SB_MA_2SB_MA_3SB_MA_4SB_MA_5SB_MA_6SB_MA_7SB_MA_8SB_MA_9
SB_RAS#SB_RCVEN#
SB_WE#
DDR SYSTEM MEMORY A
U10D
CRESTLINE_965GM
AR43AW44
BG47BJ45BB47BG50BH49BE45
AW43BE44BG42BE40
BA45
BF44BH45BG40BF40AR40
AW40AT39
AW36AW41AY41
AY46
AV38AT38AV13AT13
AW11AV11AU15AT11BA13BA11
AR41
BE10BD10BD8AY9
BG10AW9BD7BB9BB5AY7
AR45
AT5AT7AY6BB7AR5AR8AR9AN3AM8
AN10
AT42
AT9AN9AM9
AN11
AW47BB45BF48
BB19BK19BF29
BL17
AT45BD44BD42AW38AW13BG8AY5
AT46BE48BB43BC37BB16BH6BB2AP3
AN6
AT47BD47BC41BA37BA16BH7BC1AP2
BJ19BD20
BC19BE28BG30BJ16
BK27BH28BL24BK28BJ27BJ25BL28BA28
BE18AY20
BA19
SA_DQ_0SA_DQ_1
SA_DQ_10SA_DQ_11SA_DQ_12SA_DQ_13SA_DQ_14SA_DQ_15SA_DQ_16SA_DQ_17SA_DQ_18SA_DQ_19
SA_DQ_2
SA_DQ_20SA_DQ_21SA_DQ_22SA_DQ_23SA_DQ_24SA_DQ_25SA_DQ_26SA_DQ_27SA_DQ_28SA_DQ_29
SA_DQ_3
SA_DQ_30SA_DQ_31SA_DQ_32SA_DQ_33SA_DQ_34SA_DQ_35SA_DQ_36SA_DQ_37SA_DQ_38SA_DQ_39
SA_DQ_4
SA_DQ_40SA_DQ_41SA_DQ_42SA_DQ_43SA_DQ_44SA_DQ_45SA_DQ_46SA_DQ_47SA_DQ_48SA_DQ_49
SA_DQ_5
SA_DQ_50SA_DQ_51SA_DQ_52SA_DQ_53SA_DQ_54SA_DQ_55SA_DQ_56SA_DQ_57SA_DQ_58SA_DQ_59
SA_DQ_6
SA_DQ_60SA_DQ_61SA_DQ_62SA_DQ_63
SA_DQ_7SA_DQ_8SA_DQ_9
SA_BS_0SA_BS_1SA_BS_2
SA_CAS#
SA_DM_0SA_DM_1SA_DM_2SA_DM_3SA_DM_4SA_DM_5SA_DM_6
SA_DQS_0SA_DQS_1SA_DQS_2SA_DQS_3SA_DQS_4SA_DQS_5SA_DQS_6SA_DQS_7
SA_DM_7
SA_DQS#_0SA_DQS#_1SA_DQS#_2SA_DQS#_3SA_DQS#_4SA_DQS#_5SA_DQS#_6SA_DQS#_7
SA_MA_0SA_MA_1
SA_MA_10SA_MA_11SA_MA_12SA_MA_13
SA_MA_2SA_MA_3SA_MA_4SA_MA_5SA_MA_6SA_MA_7SA_MA_8SA_MA_9
SA_RAS#SA_RCVEN#
SA_WE#
T1081T1141
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Layout Note:Place on the edge
Layout Note:370 mils form edge.
Layout Note:Place C1117 where LVDS andDDR2 taps
Layout Note:Inside GMCHcavity
Layout Note:Inside GMCH cavity
Layout Note:Place close to GMCH edge.
Layout Note:370mils form edge.
Layout Note:Inside GMCH cavity for VCC_AXG.
Non-iAMT
Crestline(VCC,NCTF)1.2Lanai <OrgName>12 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
+VCC_AXG
+VCC_GMCH_L
+VCC_AXM
+VCC_AXM
+VCC_GMCH
+VCC_AXG
+VCC_AXG
+VCC_GMCH
VCCSM_LF5
VCCSM_LF1
VCCSM_LF3VCCSM_LF4
VCCSM_LF6VCCSM_LF7
VCCSM_LF2
+1.8V_SUS
+1.05V_VCCP
+1.8V_SUS
+1.05V_VCCP
+3.3V_RUN
+1.05V_VCCP
C3460.1UF/10V
MLCC/+/-10%
12
C3690.1UF/10VMLCC/+/-10%
12
C3480.1UF/10V
MLCC/+/-10%
12
D11
RB751V_40
2 1
C3680.47UF/10V
MLCC/+/-10%pt_c0603
12
C3430.22UF/10V
MLCC/+/-10%pt_c0603
12
+CE8
220UF/2.5V
/*pt_c7343d_h75+/-20%
12
+CE15
220UF/4V
TAN
/Lf_
T=20
00hr
s_10
5C/+
/-20%
pt_c7343d_h79
12
C3490.1UF/10V
MLCC/+/-10%
12
C3401UF/10V
pt_c0603MLCC/+/-10%
12
+CE4
220UF/2.5Vpt_c7343d_h75+/-20%
12
C3700.1UF/10VMLCC/+/-10%
12
C9222UF/4VMLCC/+/-20%pt_c0805_h53
12
+CE11330UF/6.3Vpt_c7343d_h110+/-20%
12
C36622UF/4VMLCC/+/-20%pt_c0805_h53
12
C32122UF/4VMLCC/+/-20%pt_c0805_h53
12
C3281UF/10V
pt_c0603MLCC/+/-10%
12
C9122UF/4VMLCC/+/-20%pt_c0805_h53
12
C3441UF/10V
pt_c0603MLCC/+/-10%
12
C3340.1UF/10V
MLCC/+/-10%
12
C3370.22UF/10VMLCC/+/-10%pt_c0603
12
C3600.22UF/10VMLCC/+/-10%pt_c0603
12
C3760.22UF/10VMLCC/+/-10%pt_c0603
12
C3330.47UF/10VMLCC/+/-10%pt_c0603
12
C3470.1UF/10V
MLCC/+/-10%
12
R143 10Ohm 5%1 2
POWERVCC CORE
VCC SM
VCC GFX
VCC GFX NCTF
VCC SM LF
U10G
CRESTLINE_965GM
AC32
AK32AJ31AJ28AH32AH31AH29AF32
AT34
AC31
BA35
BF33
BJ34
AW35AY35BA32BA33
BB33BC32BC33BC35BD32BD35BE32BE33BE35
AU33
BF34BG32BG33BG35BH32BH34BH35BJ32BJ33
AU35
BK32BK33BK34BK35
U17U19U20U21U23U26V16V17V19V20
T18
V21V23V24Y15Y16Y17Y19Y20Y21Y23
T19
Y24Y26Y28Y29AA16AA17AB16AB19AC16AC17
T21
AC19AD15AD16AD17AF16AF19AH15AH16AH17AH19
T22
AJ16AJ17AJ19AK16AK19AL16AL17AL19AL20AL21
T23
AL23AM15AM16AM19
AM21AM23AP15AP16AP17
T25
AP19AP20AP21
U15U16
BL33
AV33AW33
T17AT35
AU32
R20T14
W13W14Y12
AA20AA23AA26AA28AB21AB24AB29AC20AC21AC23AC24AC26AC28AC29AD20AD23AD24AD28AF21AF26
AH20AH21AH23AH24
AP23AP24AR20AR21AR23AR24AR26
R30
AH26
AJ20AN14
AW45BC39BE39BD17BD4AW8AT6
AA31
AD31
AH28
AM20
AU30
V26V28V29Y31
VCC_5
VCC_6VCC_7VCC_8VCC_9VCC_10VCC_11VCC_12
VCC_2
VCC_4
VCC_SM_10
VCC_SM_20
VCC_SM_30
VCC_SM_6VCC_SM_7VCC_SM_8VCC_SM_9
VCC_SM_11VCC_SM_12VCC_SM_13VCC_SM_14VCC_SM_15VCC_SM_16VCC_SM_17VCC_SM_18VCC_SM_19
VCC_SM_2
VCC_SM_21VCC_SM_22VCC_SM_23VCC_SM_24VCC_SM_25VCC_SM_26VCC_SM_27VCC_SM_28VCC_SM_29
VCC_SM_3
VCC_SM_31VCC_SM_32VCC_SM_33VCC_SM_34
VCC_AXG_NCTF_10VCC_AXG_NCTF_11VCC_AXG_NCTF_12VCC_AXG_NCTF_13VCC_AXG_NCTF_14VCC_AXG_NCTF_15VCC_AXG_NCTF_16VCC_AXG_NCTF_17VCC_AXG_NCTF_18VCC_AXG_NCTF_19
VCC_AXG_NCTF_2
VCC_AXG_NCTF_20VCC_AXG_NCTF_21VCC_AXG_NCTF_22VCC_AXG_NCTF_23VCC_AXG_NCTF_24VCC_AXG_NCTF_25VCC_AXG_NCTF_26VCC_AXG_NCTF_27VCC_AXG_NCTF_28VCC_AXG_NCTF_29
VCC_AXG_NCTF_3
VCC_AXG_NCTF_30VCC_AXG_NCTF_31VCC_AXG_NCTF_32VCC_AXG_NCTF_33VCC_AXG_NCTF_34VCC_AXG_NCTF_35VCC_AXG_NCTF_36VCC_AXG_NCTF_37VCC_AXG_NCTF_38VCC_AXG_NCTF_39
VCC_AXG_NCTF_4
VCC_AXG_NCTF_40VCC_AXG_NCTF_41VCC_AXG_NCTF_42VCC_AXG_NCTF_43VCC_AXG_NCTF_44VCC_AXG_NCTF_45VCC_AXG_NCTF_46VCC_AXG_NCTF_47VCC_AXG_NCTF_48VCC_AXG_NCTF_49
VCC_AXG_NCTF_5
VCC_AXG_NCTF_50VCC_AXG_NCTF_51VCC_AXG_NCTF_52VCC_AXG_NCTF_53VCC_AXG_NCTF_54VCC_AXG_NCTF_55VCC_AXG_NCTF_56VCC_AXG_NCTF_57VCC_AXG_NCTF_58VCC_AXG_NCTF_59
VCC_AXG_NCTF_6
VCC_AXG_NCTF_60VCC_AXG_NCTF_61VCC_AXG_NCTF_62VCC_AXG_NCTF_63
VCC_AXG_NCTF_65VCC_AXG_NCTF_66VCC_AXG_NCTF_67VCC_AXG_NCTF_68VCC_AXG_NCTF_69
VCC_AXG_NCTF_7
VCC_AXG_NCTF_70VCC_AXG_NCTF_71VCC_AXG_NCTF_72
VCC_AXG_NCTF_8VCC_AXG_NCTF_9
VCC_SM_35
VCC_SM_4VCC_SM_5
VCC_AXG_NCTF_1VCC_1
VCC_SM_1
VCC_AXG_1VCC_AXG_2VCC_AXG_3VCC_AXG_4VCC_AXG_5VCC_AXG_6VCC_AXG_7VCC_AXG_8VCC_AXG_9VCC_AXG_10VCC_AXG_11VCC_AXG_12VCC_AXG_13VCC_AXG_14VCC_AXG_15VCC_AXG_16VCC_AXG_17VCC_AXG_18VCC_AXG_19VCC_AXG_20VCC_AXG_21VCC_AXG_22VCC_AXG_23VCC_AXG_24VCC_AXG_25
VCC_AXG_27VCC_AXG_28VCC_AXG_29VCC_AXG_30
VCC_AXG_NCTF_73VCC_AXG_NCTF_74VCC_AXG_NCTF_75VCC_AXG_NCTF_76VCC_AXG_NCTF_77VCC_AXG_NCTF_78VCC_AXG_NCTF_79
VCC_13
VCC_AXG_31
VCC_AXG_33VCC_AXG_34
VCC_SM_LF1VCC_SM_LF2VCC_SM_LF3VCC_SM_LF4VCC_SM_LF5VCC_SM_LF6VCC_SM_LF7
VCC_AXG_26
VCC_AXG_32
VCC_3
VCC_AXG_NCTF_64
VCC_SM_36
VCC_AXG_NCTF_80VCC_AXG_NCTF_81VCC_AXG_NCTF_82VCC_AXG_NCTF_83
C34210UF/6.3V
MLCC/+/-20%pt_c0805_h53
12
+CE10
220UF/2.5V
/*pt_c7343d_h75+/-20%
12
C3320.1UF/10V
MLCC/+/-10%
12
C32622UF/4VMLCC/+/-20%pt_c0805_h53
12
C3500.22UF/10VMLCC/+/-10%pt_c0603
12
C950.1UF/10VMLCC/+/-10%
12
C3410.22UF/10V
MLCC/+/-10%pt_c0603
12
POWER
VCC NCTF
VSS NCTF
VSS SCB
VCC AXM
VCC AXM NCTF
U10F
CRESTLINE_965GM
AB33
AK37
AP35
U31
AF33AF36AH33AH35AH36AH37AJ33
AK33AK35AK36
AB36
AL33AL35
AB37
AP36AR35AR36
T30T34T35U29
AC33
U32U33U35U36
V33V36V37
AC35AC36AD35
T27T37U24U28V31V35
AB17AB35AD19
AD36
AA19
AD37AF17
AK17
AM24AP26
AR15AR19AR28
Y32
AK24AK23AJ26AJ23
AL24AL26AL28AM26AM28AM29AM31
AP29AP31
AR31
Y33Y35Y36Y37 A3
B2C1BL1BL51A51
AA33AA35AA36
AJ35
AD33
AF35
AJ36
AK29
AL29AL31AL32
AM17
AM32AM33
AM35
AP28
AP32AP33
AR32AR33
AT31AT33
V32
VCC_NCTF_1
VCC_NCTF_20
VCC_NCTF_29
VCC_NCTF_42
VCC_NCTF_9VCC_NCTF_10VCC_NCTF_11VCC_NCTF_12VCC_NCTF_13VCC_NCTF_14VCC_NCTF_15
VCC_NCTF_17VCC_NCTF_18VCC_NCTF_19
VCC_NCTF_2
VCC_NCTF_24VCC_NCTF_25
VCC_NCTF_3
VCC_NCTF_30VCC_NCTF_31VCC_NCTF_32
VCC_NCTF_38VCC_NCTF_39VCC_NCTF_40VCC_NCTF_41
VCC_NCTF_4
VCC_NCTF_43VCC_NCTF_44VCC_NCTF_45VCC_NCTF_46
VCC_NCTF_48VCC_NCTF_49VCC_NCTF_50
VCC_NCTF_5VCC_NCTF_6VCC_NCTF_7
VSS_NCTF_1VSS_NCTF_2VSS_NCTF_3VSS_NCTF_4VSS_NCTF_5VSS_NCTF_6
VSS_NCTF_8VSS_NCTF_9
VSS_NCTF_10
VCC_NCTF_8
VSS_NCTF_7
VSS_NCTF_11VSS_NCTF_12
VSS_NCTF_14
VSS_NCTF_16VSS_NCTF_17
VSS_NCTF_19VSS_NCTF_20VSS_NCTF_21
VCC_NCTF_33
VCC_AXM_4VCC_AXM_5VCC_AXM_6VCC_AXM_7
VCC_AXM_NCTF_1VCC_AXM_NCTF_2VCC_AXM_NCTF_3VCC_AXM_NCTF_4VCC_AXM_NCTF_5VCC_AXM_NCTF_6VCC_AXM_NCTF_7
VCC_AXM_NCTF_10VCC_AXM_NCTF_11
VCC_AXM_NCTF_17
VCC_NCTF_34VCC_NCTF_35VCC_NCTF_36VCC_NCTF_37 VSS_SCB1
VSS_SCB2VSS_SCB3VSS_SCB4VSS_SCB5VSS_SCB6
VCC_NCTF_26VCC_NCTF_27VCC_NCTF_28
VCC_NCTF_16
VCC_NCTF_21
VSS_NCTF_13
VCC_NCTF_22
VCC_AXM_3
VCC_AXM_NCTF_14VCC_AXM_NCTF_15VCC_AXM_NCTF_16
VSS_NCTF_15
VCC_AXM_NCTF_8VCC_AXM_NCTF_9
VCC_NCTF_23
VSS_NCTF_18
VCC_AXM_NCTF_12VCC_AXM_NCTF_13
VCC_AXM_NCTF_18VCC_AXM_NCTF_19
VCC_AXM_2VCC_AXM_1
VCC_NCTF_47
+CE9
220UF/2.5Vpt_c7343d_h75+/-20%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1uH+-20%_300mA
Non-iAMT45mA MAX.FB_120ohm+-25%_100mHz_200mA_0.2ohm DC
FB_180ohm+-25_100mHz_1500mA_0.09ohm DC
0.1Caps should beplaced 200 milswith in its pins.
FB_180ohm+-25_100mHz_1500mA_0.09ohm DC
FB_220ohm+-25_100MHz_2A_0.1ohm DC
22nF & 0.1uF forVCC_TVDACA:C_R shouldbe placed with in 250mils from Crestline.
TV DAC Voltage Follower Circuit -700mV.
40mA MAx.10uH+-20%_100mA
FB_180ohm+-25_100mHz_1500mA_0.09ohm DC
91nH+-20%_1.5A
91nH+-20%_1.5A
Reserved L1202 pad forinductor
Non-iAMT
Place on the edge
Place on the edge
1uH+-20%_300mA
Place JP1206 for +1.8V_SUS
JUMP
Non-iAMT
Non-iAMTPlace JP1204 for+1.8V_SUS
Place caps close toVCC_AXF
Place capsclose toVCC_AXD
JUMP
JUMP
JUMP
JUMP
M08 CKT: 91uH+-20%_1.5Aneed to be confirm
No.7
No.7
No.45
Crestline(POWER)1.2Lanai <OrgName>13 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
+VCC_HV_L
+VTTLF1
+VTTLF3+VTTLF2
+VCC_SM_CK_L
+VCC_TVDAC_L
+VCCA_CRTDAC
+VCC_SM_CK
+VCCA_MPLL
+VCCA_DPLLA
+VCCA_DPLLB
+VCC_TVBG
+VCC_TVDACB_R
+VCCA_PEG_PLL
+VCC_TX_LVDS
+VCC_TVDACC_R
+VCCA_DPLLA
+VCCA_PEG_PLL +VCC_RXR_DMI
+VCCA_DPLL
+VCCA_HPLL
+VCCA_PEG_PLL
+VCCA_CRTDAC_R
+VTTLF2
+VCC_TVDACA_R
+VCCQ_TVDAC_R
+VCCA_SM
+VCC_TVDACA_R
+VCC_SM_CK
+VCC_AXD_L
+VCC_TVBG_R
+VCC_TVDACC_R
+VCC_TVBG_R
+VCC_AXF
+VCCA_CRTDAC_R
+VCC_AXF
+VTTLF1
+VCCA_SM_CK
+VCCA_MPLL
+VCC_TX_LVDS
+VCCA_DPLLB
+VCCD_LVDS
+VCC_TX_LVDS_R
+VTTLF3
+VCCD_TVDAC_R
+VCCQ_TVDAC
+VCCD_TVDAC_R
+VCCQ_TVDAC_R
+VCC_AXD_R
+VCC_MPLL_L
+VCC_TVDACB_R+VCC_TVDACB
+VCC_TVDACC
+VCC_TVDACA
+VCCA_HPLL
+1.25V_RUN
+3.3V_RUN
+1.8V_SUS
+1.25V_RUN
+1.05V_VCCP
+3.3V_RUN
+1.5V_RUN +3.3V_RUN
+1.25V_RUN
+1.5V_RUN
+3.3V_RUN
+1.25V_RUN
+3.3V_RUN
+1.05V_VCCP
+3.3V_RUN
+1.25V_RUN
+1.05V_VCCP
+1.25V_RUN
+1.8V_SUS
+3.3V_RUN
+1.05V_VCCP
+1.8V_RUN
+1.25V_RUN
+1.25V_RUN
+1.25V_RUN
+1.8V_RUN
+VCC_PEG
+1.8V_SUS
R111 30mOhm 1%
pt_r06031 2
JP5
0Ohm1 2
JP4
0Ohm1 2
C3450.1UF/10VMLCC/+/-10%
12
C538
1UF/10VMLCC/+/-10%
12
IN OUT
GND
U23
22NF/16V/*
1
2
3
IN OUT
GND
U7
22NF/16V /*
1
2
3
L14 180Ohm
BLM18PG181SN1
21
C3734.7UF/10VMLCC/+/-10%pt_c0805_h37
12
C3720.47UF/10VMLCC/+/-10%pt_c0603
12
C3541UF/10V
pt_c0603MLCC/+/-10%
12
C1210.1UF/10VMLCC/+/-10%
12
IN OUT
GND
U22
22NF/16V /*
1
2
3
C3614.7UF/6.3VMLCC/+/-10%pt_c0603
12
C3240.1UF/10VMLCC/+/-10%
12
R1091Ohm1%pt_r0603
12
L26
10uHpt_l0805
21
C3621UF/10V
pt_c0603MLCC/+/-10%
12
+ CE14100UF/6.3Vpt_c3528_h79+/-20%
12
IN OUT
GND
U18
22NF/16V /*
12
3
C1130.1UF/10VMLCC/+/-10%
12
R328 0Ohm 5% pt_r06031 2
C850.1UF/10VMLCC/+/-10%
12
C3750.1UF/10VMLCC/+/-10%
12
C35722UF/4VMLCC/+/-20%pt_c0805_h53
12
C3250.1UF/10VMLCC/+/-10%
12
JP3
0Ohm /*1 2
C3560.1UF/10VMLCC/+/-10%
12
C3350.1UF/10VMLCC/+/-10%
12
L27
220Ohm/100MhzBLM21PG221SN1D
pt_l0805_h41
21
C1051UF/10V
pt_c0603MLCC/+/-10%
12
L16120Ohm/100Mhz
BLM18AG121SN1D
21
C8310UF/6.3VMLCC/+/-20%pt_c0805_h53
12
L30120Ohm/100Mhz
BLM18AG121SN1D
21
R361 0Ohm 5% pt_r06031 2
+CE3220UF/4V
TAN/Lf_T=2000hrs_105C/+/-20%pt_c7343d_h79
12
D12RB751V_40
/*
21
L24
91NH/1.5A
21
C3200.1UF/10VMLCC/+/-10%
12
IN OUT
GND
U21
22NF/16V /*
1
2
3
C3381UF/10V
pt_c0603MLCC/+/-10%
12
C11122UF/10VMLCC/+80%-20%pt_c1206_h71
12
C3590.1UF/10VMLCC/+/-10%
12
C1161UF/10V
pt_c0603MLCC/+/-10%
12
IN OUT
GND
U19
22NF/16V /*
1
2
3
R538
100Ohm pt_r06031 2
C1000.1UF/10VMLCC/+/-10%
12
R136
0.5Ohm 1%pt_r0603
1 2
C3301000PF/50VMLCC/+/-10%
12
C35822UF/4VMLCC/+/-20%pt_c0805_h53
12
R14210Ohm 5%/*
12
C11510UF/6.3VMLCC/+/-20%pt_c0805_h53
12
C3742.2UF/6.3VMLCC/+/-10%pt_c0603
12
C3390.1UF/10VMLCC/+/-10%
12
JP7
0Ohm1 2
R353 0Ohm 5% pt_r06031 2
C3220.1UF/10VMLCC/+/-10%
12
C32310UF/6.3VMLCC/+/-20%pt_c0805_h53
12
L29
0Ohmpt_r06035%
1 2
L25
91NH/1.5A
21
L23
10uHpt_l0805
21
R3181Ohm 1%pt_r0603
12
+CE17
220UF/4V
TAN/Lf_T=2000hrs_105C/+/-20%pt_c7343d_h79
12
R113 10Ohm
/*5%1 2
L131UH/300mA
pt_l0805_h53
21
JP6
0Ohm /*1 2
C3361000PF/50V
MLCC/+/-10%
12
C3640.1UF/10VMLCC/+/-10%
12
C1061UF/10V
pt_c0603MLCC/+/-10%
12
+ CE12470UF/4Vpt_c7343d_h157+/-20%
12
+CE2
220UF/4V
TAN/Lf_T=2000hrs_105C/+/-20%pt_c7343d_h79
12
D10
RB751V_40 /*
21
C3650.1UF/10VMLCC/+/-10%
12
C1270.47UF/10VMLCC/+/-10%pt_c0603
12
C35522UF/10VMLCC/+80%-20%pt_c1206_h71
12
C1290.47UF/10VMLCC/+/-10%pt_c0603
12
C1040.1UF/10VMLCC/+/-10%
12
+ CE13470UF/4Vpt_c7343d_h157+/-20%
12
C10322UF/4VMLCC/+/-20%pt_c0805_h53
12
C8410UF/6.3VMLCC/+/-20%pt_c0805_h53
12
C11710UF/6.3VMLCC/+/-20%pt_c0805_h53
12
POWER
CRT
PLL
A PEG
A SM
TV
D TV/CRT
LVDS
VTTLF
PEG
SM CK
AXD
AXF
VTT
DMI
HV
A CK
A LVDS
U10H
CRESTLINE_965GM
T2R3R2R1
M32
K50
U51
A33B33
B49
H49
AL2
A41
AM2
C25B25C27B27B28A28
U48
T7T6T5T3
T11T10T9
J32
AN2
U13U12
U9U8U7U5U3U2U1T13
U11
BC29BB29
A30
L29
A7F2AH1
AH50AH51
BK24BK23BJ24BJ23
J41
N28
AU28AU24
AT25
B23B21A21
AW18AV19AU19AU18AU17
AT22AT21AT19
AJ50
A43
B32
B41
K49
C40B40
AD51
AT18AT17AR17AR16
H42
W50W51V49V50
AR29
AT29
AT30
AT23
VTT_19VTT_20VTT_21VTT_22
VCCD_CRT
VCCA_PEG_BG
VCCA_PEG_PLL
VCCA_CRT_DAC_1VCCA_CRT_DAC_2
VCCA_DPLLA
VCCA_DPLLB
VCCA_HPLL
VCCA_LVDS
VCCA_MPLL
VCCA_TVA_DAC_1VCCA_TVA_DAC_2VCCA_TVB_DAC_1VCCA_TVB_DAC_2VCCA_TVC_DAC_1VCCA_TVC_DAC_2
VCCD_PEG_PLL
VTT_15VTT_16VTT_17VTT_18
VTT_12VTT_13VTT_14
VCCSYNC
VCCD_HPLL
VTT_1VTT_2
VTT_4VTT_5VTT_6VTT_7VTT_8VTT_9
VTT_10VTT_11
VTT_3
VCCA_SM_CK_1VCCA_SM_CK_2
VCCA_DAC_BG
VCCD_TVDAC
VTTLF1VTTLF2VTTLF3
VCC_RXR_DMI_1VCC_RXR_DMI_2
VCC_SM_CK_1VCC_SM_CK_2VCC_SM_CK_3VCC_SM_CK_4
VCCD_LVDS_1
VCCD_QDAC
VCC_AXD_2VCC_AXD_3
VCC_AXD_5
VCC_AXF_1VCC_AXF_2VCC_AXF_3
VCCA_SM_1VCCA_SM_2VCCA_SM_3VCCA_SM_4VCCA_SM_5
VCCA_SM_7VCCA_SM_8VCCA_SM_9
VCC_DMI
VCC_TX_LVDS
VSSA_DAC_BG
VSSA_LVDS
VSSA_PEG_BG
VCC_HV_1VCC_HV_2
VCC_PEG_1
VCCA_SM_10VCCA_SM_11VCCA_SM_NCTF_1VCCA_SM_NCTF_2
VCCD_LVDS_2
VCC_PEG_2VCC_PEG_3VCC_PEG_4VCC_PEG_5
VCC_AXD_NCTF
VCC_AXD_4
VCC_AXD_6
VCC_AXD_1
JP8
0Ohm1 2
L8
1UH/300mApt_l0805_h53
2 1
R102 0Ohm 5% pt_r06031 2
C32910UF/6.3V
MLCC/+/-20%pt_c0805_h53
12
C38222UF/10V
MLCC/+80%-20%pt_c1206_h71
12
C37822UF/10V
MLCC/+80%-20%pt_c1206_h71
12
R331 0Ohm 5% pt_r06031 2
C3630.47UF/6.3VMLCC/+/-10%
12
+CE1
220UF/4V
TAN/Lf_T=2000hrs_105C/+/-20%pt_c7343d_h79
12
L11 180Ohm
BLM18PG181SN1
21
JP2
0Ohm1 2
C900.1UF/10VMLCC/+/-10%
12
R362 0Ohm 5% pt_r06031 2
C3774.7UF/10VMLCC/+/-10%pt_c0805_h37
12
C3270.1UF/10VMLCC/+/-10%
12
C1220.1UF/10VMLCC/+/-10%
12
IN OUT
GND
U24
22NF/16V /*
1
2
3
C11010UF/6.3VMLCC/+/-20%pt_c0805_h53
12
R349 0Ohm 5% pt_r06031 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Crestline(VSS)1.2Lanai <OrgName>14 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
VSS
U10J
CRESTLINE_965GM
C46C50C7
D13D24D3
D32D39D45D49E10E16E24E28E32E47F19F36F4
F40F50G1
G13G16G19G24G28G29G33G42G45G48G8
H24H28H4
H45J11J16J2
J24J28J33J35J39
K12K47K8L1
L17L20L24L28L3
L33L49M28M42M46M49M5
M50M9
N11N14N17N29N32N36N39N44N49N7
P19P2
P23P3
P50R49T39T43T47U41U45U50
W11W39W43W47W5W7Y13Y2Y41
V2V3
Y45Y49Y5Y50Y11P29T29T31T33R28
AA32AB32AD32AF28AF29AT27AV25H50
VSS_199VSS_200VSS_201VSS_202VSS_203VSS_204VSS_205VSS_206VSS_207VSS_208VSS_209VSS_210VSS_211VSS_212VSS_213VSS_214VSS_215VSS_216VSS_217VSS_218VSS_219VSS_220VSS_221VSS_222VSS_223VSS_224VSS_225VSS_226VSS_227VSS_228VSS_229VSS_230VSS_231VSS_232VSS_233VSS_234VSS_235VSS_236VSS_237VSS_238VSS_239VSS_240VSS_241VSS_242VSS_243
VSS_245VSS_246VSS_247VSS_248VSS_249VSS_250VSS_251VSS_252VSS_253VSS_254VSS_255VSS_256VSS_257VSS_258VSS_259VSS_260VSS_261VSS_262VSS_263VSS_264VSS_265VSS_266VSS_267VSS_268VSS_269VSS_270VSS_271VSS_272VSS_273VSS_274VSS_275VSS_276VSS_277VSS_278VSS_279VSS_280VSS_281VSS_282VSS_283VSS_284
VSS_287VSS_288VSS_289VSS_290VSS_291VSS_292VSS_293VSS_294VSS_295
VSS_285VSS_286
VSS_296VSS_297VSS_298VSS_299VSS_300VSS_301VSS_302VSS_303VSS_304VSS_305
VSS_306VSS_307VSS_308VSS_309VSS_310VSS_311VSS_312VSS_313
VSS
U10I
CRESTLINE_965GM
A13
C41
A15A17A24
AA21AA24AA29AB20AB23AB26AB28AB31AC10AC13AC3
AC39AC43
AD1AD21AD26AD29AD3
AD41AD45AD49AD5
AD50AD8
AE10AE14AE6
AF20AF23AF24AF31AG2
AG38AG43AG47AG50
AH3AH40AH41AH7AH9
AJ11AJ13AJ21AJ24AJ29AJ32AJ43AJ45AJ49AK20AK21AK26AK28AK31AK51
AL1AM11AM13AM3AM4
AM41AM45
AN1AN38AN39AN43AN5AN7AP4
AP48AP50AR11AR2
AR39AR44AR47AR7
AT10AT14AT41AT49
AW1
AW24AW29AW32AW5AW7AY10AY24AY37AY42AY43AY45AY47AY50B10B20B24B29B30B35B38B43B46B5B8BA1BA17BA18BA2BA24BB12BB25BB40BB44BB49BB8BC16BC24BC25BC36BC40BC51BD13BD2BD28BD45BD48BD5BE1BE19BE23BE30BE42BE51BE8BF12BF16BF36BG19BG2BG24BG29BG39BG48BG5BG51BH17BH30BH44BH46BH8BJ11BJ13BJ38BJ4BJ42BJ46BK15BK17BK25BK29
AU1AU23AU29AU3
AU36AU49AU51AV39AV48
AW16AW12
BK36
BK44
BK8
BL13
BL22
AC47
C12
C19
C29
C36
BK40
BK6
BL11
BL19
BL37BL47
C16
C28
C33
VSS_1
VSS_198
VSS_2VSS_3VSS_4VSS_5VSS_6VSS_7VSS_8VSS_9VSS_10VSS_11VSS_12VSS_13VSS_14VSS_15VSS_16VSS_17
VSS_19VSS_20VSS_21VSS_22VSS_23VSS_24VSS_25VSS_26VSS_27VSS_28VSS_29VSS_30VSS_31VSS_32VSS_33VSS_34VSS_35VSS_36VSS_37VSS_38VSS_39VSS_40VSS_41VSS_42VSS_43VSS_44VSS_45VSS_46VSS_47VSS_48VSS_49VSS_50VSS_51VSS_52VSS_53VSS_54VSS_55VSS_56VSS_57VSS_58VSS_59VSS_60VSS_61VSS_62VSS_63VSS_64VSS_65VSS_66VSS_67VSS_68VSS_69VSS_70VSS_71VSS_72VSS_73VSS_74VSS_75VSS_76VSS_77VSS_78VSS_79VSS_80VSS_81VSS_82VSS_83VSS_84VSS_85VSS_86VSS_87
VSS_97
VSS_100VSS_101VSS_102VSS_103VSS_104VSS_105VSS_106VSS_107VSS_108VSS_109VSS_110VSS_111VSS_112VSS_113VSS_114VSS_115VSS_116VSS_117VSS_118VSS_119VSS_120VSS_121VSS_122VSS_123VSS_124VSS_125VSS_126VSS_127VSS_128VSS_129VSS_130VSS_131VSS_132VSS_133VSS_134VSS_135VSS_136VSS_137VSS_138VSS_139VSS_140VSS_141VSS_142VSS_143VSS_144VSS_145VSS_146VSS_147VSS_148VSS_149VSS_150VSS_151VSS_152VSS_153VSS_154VSS_155VSS_156VSS_157VSS_158VSS_159VSS_160VSS_161VSS_162VSS_163VSS_164VSS_165VSS_166VSS_167VSS_168VSS_169VSS_170VSS_171VSS_172VSS_173VSS_174VSS_175VSS_176VSS_177VSS_178VSS_179
VSS_88VSS_89VSS_90VSS_91VSS_92VSS_93VSS_94VSS_95VSS_96
VSS_99VSS_98
VSS_180
VSS_182
VSS_184
VSS_186
VSS_188
VSS_18
VSS_191
VSS_193
VSS_195
VSS_197
VSS_181
VSS_183
VSS_185
VSS_187
VSS_189VSS_190
VSS_192
VSS_194
VSS_196
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
RSVD
1
Normal operation (Default)
ICH _RSVD
Enter XOR chain
XOR Chain Entrance strap
Set PCIE port config bit 1
1
1
Description
0
1
ACZ_SDOUT
Place within 500 milsof ICH8 ball
Low = Internal VR Disabled
(Internal VR for VccSus1.05, VccSus1.5 and VccCL1.5)
High = Internal VR Enable(Default)ICH_INTVRMEN
ICH8M Internal VR Enable Strap
ICH_LAN100_SLP Low = Internal VR DisabledHigh = Internal VR Enable(Default)
(Internal VR for VccLAN1.05 and VccCL1.05)ICH8M LAN100SLP Strap
The circuit is onlyneeded if theplatform has theSNIFFER.
Place all series terms close to ICH8 except for SDIN input lines, whichshould be close to source. Placement of R208, R201, R205, R213 shouldequal distance to the T split trace point as R219, R202, R199, R220respective. Basically, keep the same distance from T for all seriestermination resistors.
Distance between the ICH-8 M and cap on the "P" signalshould be identical distance between the ICH-8 M and cap onthe "N" signal for same pair.
0
0
0
Pull up for each detect line
No.25
No.57
ICH8: IDE/AC97/LPC/RTC1.2Lanai <OrgName>15 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
THERMTRIP#_ICH
H_DPRSTP#
H_DPSLP#
H_FERR#
SIO_A20GATE
SIO_RCIN#
ACZ_SDOUT
ICH_RTCX1
GLAN_COMP
IDE_DD1
SATA_ACT#
SATA_TX0-_C
IDE_DD5
IDE_DD15
IDE_DD6
IDE_DD3
SIO_A20GATE
ICH_RTCX2
IDE_DD4
H_DPRSTP#
LAN_TXD1
LPC_LDRQ0#
IDE_DD12
IDE_DA0
SATABIAS
IDE_DD10
LAN_RXD1
IDE_DCS1#
ICH_INTVRMEN
H_DPSLP#
SIO_RCIN#
THERMTRIP#_ICH
IDE_DD9
IDE_DD14
IDE_DD11
LPC_LDRQ1#
IDE_DD7
SATA_TX0+_C
LAN_RXD2
LAN_RXD0
IDE_DD[0..15]
IDE_DD13
IDE_DCS3#
IDE_DD8
H_FERR#
LAN_TXD2
LAN_TXD0
ICH_LAN100_SLP
ICH_INTRUDER#
IDE_DD2
ICH_RTCRST#
IDE_DA2
IDE_DD0
IDE_DA1
ICH_INTVRMEN ICH_LAN100_SLP
ICH_RTCX2 ICH_RTCX1
ACZ_BIT_CLKACZ_SYNC
ACZ_RST#
ACZ_SDOUT
ACZ_BIT_CLK
ACZ_SYNC
ICH_RTCRST#
ICH_INTRUDER#
SATA_TX0+_CSATA_TX0-_C
SATA_ACT#
ACZ_RST#
ACZ_SDOUT
GLAN_CLK
RTC_BAT_DET#SPEAKER_DET#
SPEAKER_DET#RTC_BAT_DET#
ICH_RSVD 17
H_INIT# 7
IDE_DDREQ 31
IDE_DA2 31
IDE_DIOW# 31
IDE_DA0 31
IDE_DDACK# 31
IDE_DIORDY 31
IDE_DCS3# 31
IDE_DIOR# 31
H_FERR# 7
IDE_IRQ 31
IDE_DCS1# 31
IDE_DA1 31
H_STPCLK# 7
H_A20M# 7SIO_A20GATE 37
H_IGNNE# 7
H_DPRSTP# 7,10,53
H_SMI# 7
H_DPSLP# 7
H_PWRGOOD 7
H_INTR 7SIO_RCIN# 37
LPC_LFRAME# 37
SATA_RX0+31
IDE_DD[0..15] 31
LPC_LAD1 37
H_NMI 7
CLK_PCIE_SATA21
LPC_LAD0 37
CLK_PCIE_SATA#21
SATA_RX0-31
LPC_LAD2 37LPC_LAD3 37
LED_MASK#38,41
SATA_ACT#_R42
ICH_AZ_MDC_SDIN136ICH_AZ_CODEC_SDIN044
ICH_AZ_MDC_BITCLK36
ICH_AZ_CODEC_BITCLK44
ICH_AZ_CODEC_SYNC44ICH_AZ_MDC_SYNC36
ICH_AZ_CODEC_RST#44ICH_AZ_MDC_RST#36
ICH_AZ_CODEC_SDOUT44ICH_AZ_MDC_SDOUT36
SATA_TX0-31SATA_TX0+31
SPEAKER_DET#46RTC_BAT_DET#40
+1.05V_VCCP
+1.05V_VCCP
+3.3V_RUN
+3.3V_RUN
+RTC_CELL
+3.3V_RUN
+RTC_CELL
+1.5V_PCIE_ICH
+RTC_CELL
+3.3V_RUN+3.3V_RUN
T71 1
R1811KOhm5%/*
12
R201 33Ohm 5%12
R21056Ohm5%
12
R268 24.9Ohm 1%
1 2
T421
X3
32.768KHZ+/-10ppm/6PF
1 4
2 3
C41215PF/50VMLCC/+/-5%/*
12
T122 1
T43 1
R209100KOhm5%
12
T80 1
R219 33Ohm 5%12
C21527PF/50VMLCC/+/-5%
12
R208 33Ohm 5%12
R220 33Ohm 5%12
T131 1
R1900Ohm 5%/*
12
R231332KOhm1%
12
R2291MOhm5%
12
R182 0Ohm 5% /*
12
R202 33Ohm 5%12
C427 3900PF/50VMLCC/+/-10% 12
T133 1
RTC
LAN / GLAN
IHDA
SATAIDE
LPC
CPU
U32A
ICH8-M
AG25AF24
AF25
AD22
B24
D22
C21B21C22
D21E20C20
AJ16AJ15
AE14
AJ17AH17AH15
AE13
AF10
AF6AF5AH5AH6
AG3AG4AJ4AJ3
AB7AC6
AG1AG2
AA4AA1AB3
Y6Y5
V1U2V3T1V4T5AB2T6T3R2T4V6V5U1V2U6
W5Y1Y3Y2W3W4
E5F5G8F6
G9E6
C4
AF13AG26
AF26AE26
AD24
AG29
AF27
AE24AC20AH14
AG28AD23
AA24
AE27
AF23
AH21
C25D25
AD13
AE4
AF2
AE3
AF1
AA23
AE10AG14
AD21
RTCX1RTCX2
INTVRMEN
INTRUDER#
GLAN_CLK
LAN_RSTSYNC
LAN_RXD0LAN_RXD1LAN_RXD2
LAN_TXD0LAN_TXD1LAN_TXD2
HDA_BIT_CLKHDA_SYNC
HDA_RST#
HDA_SDIN0HDA_SDIN1HDA_SDIN2
HDA_SDOUT
SATALED#
SATA0RXNSATA0RXPSATA0TXNSATA0TXP
SATA1RXNSATA1RXPSATA1TXNSATA1TXP
SATA_CLKNSATA_CLKP
SATARBIAS#SATARBIAS
DA0DA1DA2
DCS1#DCS3#
DD0DD1DD2DD3DD4DD5DD6DD7DD8DD9
DD10DD11DD12DD13DD14DD15
DDREQIORDYIDEIRQ
DDACK#DIOW#DIOR#
FWH0/LAD0FWH1/LAD1FWH2/LAD2FWH3/LAD3
LDRQ0#LDRQ1#/GPIO23
FWH4/LFRAME#
A20GATEA20M#
DPRSTP#DPSLP#
FERR#
CPUPWRGD/GPIO49
IGNNE#
INIT#INTR
RCIN#
SMI#NMI
STPCLK#
THRMTRIP#
RTCRST#
GLAN_DOCK#/GPIO13
GLAN_COMPOGLAN_COMPI
HDA_SDIN3
SATA2TXN
SATA2RXN
SATA2TXP
SATA2RXP
TP8
HDA_DOCK_EN#/GPIO33HDA_DOCK_RST#/GPIO34
LAN100_SLP
C42415PF/50VMLCC/+/-5%/*
12
T651
GSD3 2
1
Q37 2N7002Id=180mA/Pd=300mW
R400 10MOhm 5%1 2
R198 24.9Ohm 1%
1 2
R19210KOhm5%
12T81 1
R19456Ohm5%
12
R187332KOhm1%
12
R19710KOhm5%
12
R199 33Ohm 5%12
R196100KOhm5%
12
R2231KOhm5%/*
12
T59 1
R384 0Ohm 5%1 2
T731
C428 3900PF/50VMLCC/+/-10% 12
T75 1
R2300Ohm 5%/*
12
R18656Ohm5%/*
12
T121 1R205 33Ohm 5%12
R183
20KOhm5%
12
R20356Ohm5%/*
12
R213 33Ohm 5%12
R16710KOhm5%
12
C2021UF/10V/X7R
pt_c0603MLCC/+/-10%
12
C22627PF/50VMLCC/+/-5%/*
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Short F2 and F3 at the packageand keep length to less than500mils. Trace Impedanceshould be 60ohms +/- 15%.
Place within 500 mils of ICH8
MiniWWAN
MiniWLAN
ExpressCard
Place TX DC blocking caps close ICH8.
Layout Note:Place 15 ohm within500 mils from ICH.
A16 away override strap.
PCI_GNT3# Low = A16 swap override enabled.High = Default.
Boot BIOS Strap
LPC 11 No stuff No stuff
PCI 10 No stuff Stuff
SPI 01 Stuff No stuff
GNT0# SPI_CS1#
REQ1 GNT1 PIRQCPIRQD
R5C833
Reserved for EMI.Place resister and capclose to ICH.
Non-iAMT
WWAN
USER1 Left side pair top/left
CCD
USER2 Left side pair bottom/right
USER3 Right side pair top/left
USER3 Right side pair bottom/right
Express Card
BlueTooth
BIOS should not enable the internal GPIO pull upresistor
PCI Pullups
Add Buffers as needed forLoading and fanoutconcerns.
Non-iAMT
No.5
No.14
No.14
No.37
No.54
ICH8: PCI/INT/DMI/USB1.2Lanai <OrgName>16 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
PCIE_TXN1_CPCIE_TXP1_C
PCIE_TXP2_CPCIE_TXN2_C
ICH_USBP4-
PCIE_TXN4_C
ICH_EC_SPI_CLK_RICH_SPI_CS#
ICH_SPI_CS1#_R
PCI_GNT0#
PCIE_TXP4_C
ICH_SPI_CS1#_R
ICH_EC_SPI_DO_R
PCI_TRDY#PCI_AD21
PCI_AD15
PCI_SERR#
PCI_GNT3#
PCI_REQ1#
PCI_AD31
PCI_AD24
PCI_AD16
PCI_AD29PCI_AD28
PCI_AD26
PCI_AD8
PCI_PIRQB#
PCI_PLTRST#
PCI_PLOCK#
SB_WWAN_PCIE_RST#
PCI_AD25
PCI_AD14
PCI_AD20
PCI_AD12
PCI_AD2
CLK_PCI_ICH
PCI_RST#_G
PCI_AD19
PCI_AD7
PCI_AD0
PCI_PIRQC#
PCI_GNT1#
PCI_AD30
PCI_AD17
PCI_AD3
PCI_FRAME#
PCI_DEVSEL#
PCI_AD11
PCI_PERR#
PCI_GNT0#
PCI_AD18
PCI_AD5
PCI_AD1
PCI_STOP#
PCI_AD23PCI_AD22
PCI_AD13
PCI_AD9
PCI_AD6PCI_GNT2#
PCI_AD10
PCI_AD4
PCI_PIRQD#
PCI_IRDY#
PCI_REQ0#
PCI_AD27
ICH_GPIO2_PIRQE#
PCIE_TXN1_C
PCIE_TXP1_C
PCIE_TXP2_C
PCIE_TXN2_C
PCIE_TXN4_C
PCIE_TXP4_C
USB_OC0_1#
USB_OC2_3#
OC4#OC5#OC6#OC7#OC8#OC9#
USBRBIAS
CLK_PCI_ICH
OC8#
OC9#
OC6#
OC7#
ICH_SPI_CS#
PCI_PIRQA#
ICH_SPI_CS#_R
ICH_USBP4+
DMI_COMP
PCI_GNT3#
SB_WLAN_PCIE_RST#SB_NB_PCIE_RST#
SB_LOM_PCIE_RST#
GLAN_TXP_C
GLAN_TXN_C
GLAN_TXN_CGLAN_TXP_C
OC4#
USB_OC0_1#
USB_OC2_3#
OC5#
ICH_USBP8-ICH_USBP8+
PCIE_MCARD2_DET#
SB_WLAN_PCIE_RST#SB_NB_PCIE_RST#
SB_NB_PCIE_RST#
SB_LOM_PCIE_RST#SB_WWAN_PCIE_RST#
SB_WLAN_PCIE_RST#
PCI_REQ0#
PCI_PIRQB#
PCIE_MCARD2_DET#
PCI_FRAME#
PCI_PIRQC#
PCI_SERR#
PCI_TRDY#
PCI_DEVSEL#
PCI_PERR#
PCI_IRDY#
PCI_REQ1#
PCI_PIRQD#
PCI_PLOCK#
PCI_PIRQA#
ICH_GPIO2_PIRQE#
PCI_STOP#
PCI_RST#_G
PCI_PLTRST#
PCI_PLTRST#
USB_OC0_1#39
USB_OC2_3#50
ICH_USBP0- 39ICH_USBP0+ 39ICH_USBP1- 39ICH_USBP1+ 39ICH_USBP2- 50ICH_USBP2+ 50ICH_USBP3- 50ICH_USBP3+ 50
ICH_USBP5- 28ICH_USBP5+ 28ICH_USBP6- 35ICH_USBP6+ 35
ICH_USBP9- 50ICH_USBP9+ 50
DMI_MTX_IRX_N0 10DMI_MTX_IRX_P0 10
DMI_MTX_IRX_N1 10DMI_MTX_IRX_P1 10
DMI_MTX_IRX_N2 10DMI_MTX_IRX_P2 10
DMI_MTX_IRX_N3 10DMI_MTX_IRX_P3 10
DMI_MRX_ITX_N0 10DMI_MRX_ITX_P0 10
DMI_MRX_ITX_N1 10DMI_MRX_ITX_P1 10
DMI_MRX_ITX_N2 10DMI_MRX_ITX_P2 10
DMI_MRX_ITX_N3 10DMI_MRX_ITX_P3 10
CLK_PCIE_ICH# 21CLK_PCIE_ICH 21
PCI_AD[0..31]32
PCI_PAR 32PCI_IRDY# 32
PCI_C_BE3# 32PCI_C_BE2# 32PCI_C_BE1# 32PCI_C_BE0# 32
PCI_GNT0#PCI_REQ0#
PCIE_RX1-50PCIE_RX1+50
PCIE_RX2-50PCIE_RX2+50
PCIE_RX4-35PCIE_RX4+35
ICH_EC_SPI_DIN37ICH_EC_SPI_DO37
ICH_EC_SPI_CLK37
PCI_STOP# 32PCI_TRDY# 32PCI_FRAME# 32
PCI_DEVSEL# 32
CLK_PCI_ICH 21ICH_PME# 38
PCI_PERR# 32
PCI_SERR# 32
PCIE_TX1+50
PCIE_TX1-50
PCIE_TX2+50
PCIE_TX2-50
PCIE_TX4+35
PCIE_TX4-35
SIO_SPI_CS# 37SPI_CS0#40
PCI_PIRQC#32PCI_PIRQD#32
PCI_PIRQB#
PCI_REQ1# 32PCI_GNT1# 32SB_WWAN_PCIE_RST# 50
SB_LOM_PCIE_RST# 47
SB_NB_PCIE_RST# 10SB_WLAN_PCIE_RST# 50
PCIE_TX6+/GLAN_TX+47
PCIE_TX6-/GLAN_TX-47
PCIE_RX6+/GLAN_RX+47PCIE_RX6-/GLAN_RX-47
ICH_USBP7+ 41ICH_USBP7- 41
PCIE_MCARD2_DET# 50
PCI_RST# 32
PLTRST# 10,35,37
PLTRST_LAN_MINICARD# 47,50
+1.5V_PCIE_ICH
+3.3V_SUS
+3.3V_ALW
+3.3V_RUN
+3.3V_RUN+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_SUS
+3.3V_SUS
+3.3V_SUS
T721
C496 0.1UF/10V MLCC/+/-10%12
C475 0.1UF/10V MLCC/+/-10%12
U14
SN74AHC1G32DBVR
123 4
5ABGND Y
VCC
T561
R520 100KOhm 5%1 2
C279 0.047UF/10V
MLCC/+/-10%
12
C485 0.1UF/10V MLCC/+/-10%12
R492
22.6Ohm1%pt_r0603
12
RP4H
8.2KOhm 5%9 5
10
RP1C
10KOhm 5%35
10
R518 15Ohm 5%1 2
R519 10KOhm 5%1 2
RP1F
10KOhm 5%7 5
10
C473 0.1UF/10V MLCC/+/-10%12
R28110Ohm5%/*
12
RP3G
8.2KOhm 5%8 5
10
RP3F
8.2KOhm 5%7 5
10 RP3D
8.2KOhm 5%45
10
C2848.2PF/50VMLCC/+/-0.25PF/*
12
T55 1
C55347PF/50VMLCC/+/-5%/*
12
R521 0Ohm 5%
1 2
C483 0.1UF/10V MLCC/+/-10%12
RP1B
10KOhm 5%25
10
R2661KOhm/*
5%
12
R275 15Ohm 5%1 2
RP1G
10KOhm 5%8 5
10
RP3C
8.2KOhm 5%35
10
R221 24.9Ohm 1%12
RP4F
8.2KOhm 5%7 5
10
PCI-Express
Direct Media Interface
USB
SPI
U32D
ICH8-M
P27P26N29N28
M27M26L29L28
K27K26J29J28
H27H26G29G28
F27F26E29E28
D27D26C29C28
V27V26U29U28
Y27Y26W29W28
AB26AB25AA29AA28
AD27AD26AC29AC28
T26T25
Y23Y24
AJ19AG16AG15AE15AF15AG17AD12AJ18
G3G2H5H4H2H1J3J2K5K4K2K1L3L2M5M4
F2F3
C23B23E22
D23F21
AD14AH18
M1M2
N3N2
PERN1PERP1PETN1PETP1
PERN2PERP2PETN2PETP2
PERN3PERP3PETN3PETP3
PERN4PERP4PETN4PETP4
PERN5PERP5PETN5PETP5
PERN6/GLAN_RXNPERP6/GLAN_RXPPETN6/GLAN_TXNPETP6/GLAN_TXP
DMI0RXNDMI0RXPDMI0TXNDMI0TXP
DMI1RXNDMI1RXPDMI1TXNDMI1TXP
DMI2RXNDMI2RXPDMI2TXNDMI2TXP
DMI3RXNDMI3RXPDMI3TXNDMI3TXP
DMI_CLKNDMI_CLKP
DMI_ZCOMPDMI_IRCOMP
OC0#OC1#/GPIO40OC2#/GPIO41OC3#/GPIO42OC4#/GPIO43OC5#/GPIO29OC6#/GPIO30OC7#/GPIO31
USBP0NUSBP0PUSBP1NUSBP1PUSBP2NUSBP2PUSBP3NUSBP3PUSBP4NUSBP4PUSBP5NUSBP5PUSBP6NUSBP6PUSBP7NUSBP7P
USBRBIAS#USBRBIAS
SPI_CLKSPI_CS0#SPI_CS1#
SPI_MOSISPI_MISO
OC8#OC9#
USBP8PUSBP8N
USBP9NUSBP9P
C494 0.1UF/10V MLCC/+/-10%12
R280 20KOhm 5%1 2
RP3A
8.2KOhm 5%15
10
C199 0.047UF/10V
MLCC/+/-10%
12
T601
PCI
Interrupt I/F
U32B
ICH8-M
D20E19D19A20D17A21A19C19A18B16A12E16A14G16A15
B6C11
A9D11B12C12D10
C7F13E11E13E12D8A6E8D6A3
A4D7E18C18B19F18A11C10
C17E15F16E17
C8D9G6D16A7B7F10C16C9A17
AG24B10G7
F9B5C5
A10 B3F12G11F8
AD0AD1AD2AD3AD4AD5AD6AD7AD8AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31
REQ0#GNT0#
REQ1#/GPIO50GNT1#/GPIO51REQ2#/GPIO52GNT2#/GPIO53REQ3#/GPIO54GNT3#/GPIO55
C/BE0#C/BE1#C/BE2#C/BE3#
IRDY#PAR
PCIRST#DEVSEL#
PERR#PLOCK#
SERR#STOP#TRDY#
FRAME#
PLTRST#PCICLK
PME#
PIRQA#PIRQB#PIRQC#PIRQD# PIRQH#/GPIO5
PIRQG#/GPIO4PIRQF#/GPIO3PIRQE#/GPIO2
R548 100KOhm 5%1 2
C542 0.047UF/10V
MLCC/+/-10%
12
R2721KOhm5%
12
T491
RP1D
10KOhm 5%45
10
RP4D
8.2KOhm 5%45
10
R2601KOhm
/*5%
12
A
GND
B
VCC
Y
U36
74AHC1G08GW/*
12
3
4
5
R517 15Ohm5% /*
1 2
U40
SN74AHC1G32DBVR
123 4
5ABGND Y
VCC
RP4G
8.2KOhm 5%8 5
10
RP4B
8.2KOhm 5%25
10
RP4A
8.2KOhm 5%15
10
R274 20KOhm 5%1 2
C465 0.1UF/10V MLCC/+/-10%12
RP1E
10KOhm 5%6 5
10
R267 15Ohm 5%1 2RP4E
8.2KOhm 5%6 5
10
T781
U12
SN74AHC1G32DBVR
123 4
5ABGND Y
VCC
C469 0.1UF/10V MLCC/+/-10%12
RP3E
8.2KOhm 5%6 5
10
RP3H
8.2KOhm 5%9 5
10
R250 100KOhm 5%1 2
RP4C
8.2KOhm 5%35
10
RP1A
10KOhm 5%15
10
R276 8.2KOhm 5%1 2
R253 10KOhm 5%1 2
RP3B
8.2KOhm 5%25
10
T79 1
T481
RP1H
10KOhm 5%9 5
10
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
SMBus address D2
These are forbackdrive issue
Option to "Disable "clkrun. Pulling it downwill keep the clksrunning.
SPKR Low=Default High=No Reboot
No Reboot strap.
Place these close to ICH8
Non-iAMT
Non-iAMT
Non-iAMT
Non-iAMT
Non-iAMTPull up for each detect line
No.26
No.9
No.9
No.14
No.14No.15
ICH8: SMB/PWR/CLK/GPIO1.2Lanai <OrgName>17 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
ICH_PCIE_WAKE#
CLK_ICH_14M
LOM_ICH_SMBALERT#
CLK_ICH_48M
ICH_SMBDATA
CLKRUN#
SPKR
RSV_THRM#IRQ_SERIRQ
SIO_S4_STATE#
RSV_SIO_SLP_M#
ICH_CL_PWROK
RSV_ICH_CL_CLK1
RSV_ICH_CL_DATA1
PLTRST_DELAY#
ICH_RI#
IMVP_PWRGD
RSVD_GPIO6
DPRSLPVR
ICH_BATLOW#
ICH_PWRGD
ICH_LAN_RST#
PCIE_MCARD3_DET#ME_EC_ALERT
EC_ME_ALERT
SIO_EXT_WAKE#
PCIE_MCARD1_DET#
USB_MCARD2_DET#
ICH_SUSCLK
RSV_ICH_CL_RST1#
ICH_SMBCLK
AMT_SMBCLKAMT_SMBDAT
MCH_ICH_SYNC#_R
SIO_SLP_S4#
CL_VREF0 CL_VREF1
CL_VREF0CL_VREF1
WOL_EN
ICH_SMBCLK
CLKRUN#
SIO_EXT_SMI#
RSV_ICH_CL_RST1#AMT_SMBCLKAMT_SMBDATICH_RI#LOM_ICH_SMBALERT#ICH_PCIE_WAKE#
SPKR
CLK_ICH_48M
CLK_ICH_14M
ICH_PWRGD
DPRSLPVR
WOL_EN
SUSPWROK
ICH_LAN_RST#
ICH_CL_PWROK
ICH_SMBDATA
RSVD_GPIO39CCD_VDD_ON
USB_IDE#
SIO_EXT_SMI#SIO_EXT_SCI#
USB_IDE#
SIO_EXT_SCI#
USB_MCARD1_DET#
PCIE_MCARD1_DET#
USB_MCARD2_DET#
USB_MCARD3_DET# PCIE_MCARD3_DET#
EC_ME_ALERT
RSVD_GPIO20
USB_MCARD3_DET#
PLTRST_DELAY#
MCH_ICH_SYNC#_RRSV_THRM#
RSVD_GPIO39RSVD_GPIO6IRQ_SERIRQ
CCD_VDD_ON
RSVD_GPIO20
ICH_SMBCLK35,50ICH_SMBDATA35,50
XDP_DBRESET#7,38,52
PM_BMBUSY#10
H_STP_PCI#21H_STP_CPU#21
CLKRUN#32,37
IRQ_SERIRQ32,37ICH_PCIE_WAKE#38
SATA_CLKREQ#21
SPKR44
MCH_ICH_SYNC#10
CL_CLK0 10
CL_DATA0 10
CLK_ICH_14M 21CLK_ICH_48M 21
SIO_PWRBTN# 37
SUSPWROK 43,51
ICH_CL_PWROK 10,37
ICH_CL_RST0# 10
SIO_SLP_S3# 37
SIO_SLP_S5# 37
DPRSLPVR 10,53
CLK_PWRGD 21
ICH_PWRGD 10,51
IMVP_PWRGD37,51,53
SIO_EXT_WAKE#38
IDE_RST_MOD31
ICH_RSVD15
ICH_SMBDATA35,50
ICH_SMBCLK35,50
MEM_SDATA 19
MEM_SCLK 19
SIO_EXT_SMI#37
ICH_RSMRST# 37
USB_MCARD2_DET#50
USB_MCARD1_DET#50PCIE_MCARD1_DET#50
PLTRST_DELAY#
SIO_EXT_SCI#37
LOM_SMB_ALERT#37
CCD_VDD_ON28
+3.3V_SUS
+3.3V_RUN
+3.3V_SUS
+3.3V_RUN +3.3V_SUS
+3.3V_RUN
+3.3V_SUS
+3.3V_RUN
+3.3V_SUS
+3.3V_RUN
+3.3V_RUN
+3.3V_SUS
+3.3V_RUN
+3.3V_RUN
+3.3V_SUS
+3.3V_RUN
R227 10KOhm 5%1 2
R226 10KOhm 5%1 2
R193 100KOhm 5%1 2
R262 1MOhm 5%1 2
T35 1
R1803.24KOhm1%/*
12
T761
R195 10KOhm 5%1 2
R179453Ohm1%/*
12
C2780.1UF/10VMLCC/+80-20%
12
RP2H
100KOhm 5%9 5
10
T1191
R188 0Ohm 5% /*1 2
R543 4.7KOhm1 2
R544 100KOhm 5%1 2
T311
RP2G
100KOhm 5%8 5
10
T451
RP2A
100KOhm 5%15
10
R237 8.2KOhm 5%1 2
RP2D
100KOhm 5%45
10
R2121KOhm 5%/*
12
R189 0Ohm 5%1 2
R26110Ohm
5%
12
R191 10KOhm 5% /*1 2
R419 8.2KOhm 5%1 2T301
RN36A2.2KOhm5%
12
SATA
SMB
SYS
GPIO
GPIO
GPIO
Clocks
Power MGT
Controller Link
MISC
U32C
ICH8-M
AJ12AJ10AF11AG11
AJ26AD19AG21AC17AE19
F4AD15
AG12
AJ8AJ9AH9
AE16AC19
AG22
AG8AH12
AG10
AG13
AE20AG18
AF9AJ11
AH11
AD10
AE17AF12AC13
AJ20
AG9G5
D3
AG23AF21AD18
AE23
AJ14
AE21
C2
AH20
AG27
AF17
AH27
AH25AD16
AJ22
E1
E3
AJ25
AE11F23AE18
F22AF19
D24AH23
AJ23
AJ24
AG19AF22
AJ27AD9
AJ21
AJ13
SATA0GP/GPIO21SATA1GP/GPIO19SATA2GP/GPIO36SATA3GP/GPIO37
SMBCLKSMBDATALINKALERT#SMLINK0SMLINK1
SUS_STAT#/LPCPD#SYS_RESET#
BMBUSY#/GPIO0
TACH1/GPIO1TACH2/GPIO6TACH3/GPIO7GPIO8GPIO12
SMBALERT#/GPIO11
TACH0/GPIO17GPIO18
SCLOCK/GPIO22
SATACLKREQ#/GPIO35
STP_PCI#/GPIO15STP_CPU#/GPIO25
SLOAD/GPIO38SDATAOUT0/GPIO39
CLKRUN#/GPIO32
SDATAOUT1/GPIO48
WAKE#SERIRQTHRM#
VRMPWRGD
CLK14CLK48
SUSCLK
SLP_S3#SLP_S4#SLP_S5#
PWROK
DPRSLPVR/GPIO16
BATLOW#
PWRBTN#
LAN_RST#
RSMRST#
RI#
S4_STATE#/GPIO26
QRT_STATE0/GPIO27QRT_STATE1/GPIO28
TP7
CK_PWRGD
CLPWROK
SLP_M#
GPIO20CL_CLK0CL_CLK1
CL_DATA0CL_DATA1
CL_VREF0CL_VREF1
CL_RST#
CLGPIO1/GPIO10
WOL_EN/GPIO9CLGPIO2/GPIO14
CLGPIO0/GPIO24SPKR
TP3
MCH_SYNC#
R4228.2KOhm5%
12
R20410Ohm/*5%
12
R173 0Ohm 5% /*1 2
T321
R200 10KOhm 5%1 2
T361
C2704.7PF/50V
MLCC/+/-0.25PF
12
R168 10KOhm 5% /*1 2
C2124.7PF/50V/*MLCC/+/-0.25PF
12
RN37B 2.2KOhm 5%3 4
T120 1
R555 100KOhm 5%1 2
R217 10KOhm 5%1 2
T1231
R206 10KOhm 5%1 2
T33 1
R214 1KOhm 5%1 2
R228 8.2KOhm 5%1 2
RP2F
100KOhm 5%7 5
10
T1241
R2773.24KOhm1%
12
T461
R216 10KOhm 5%1 2
R169 0Ohm 5%1 2
R18410Ohm
/*5%
12
GSD3 2
1
Q36 2N7002Id=180mA/Pd=300mW
R235 10KOhm 5%1 2
R176 10KOhm 5% /*1 2
R224 10KOhm 5%1 2
R420 100KOhm 5%1 2
RN36B2.2KOhm5%
34
R215 10KOhm 5%1 2
C2010.1UF/10VMLCC/+80-20%/*
12
R424 10KOhm 5%1 2
RP2E
100KOhm 5%6 5
10
RP2B
100KOhm 5%25
10
T391T1341
R174 1MOhm 5%1 2
R423 10KOhm 5%1 2
T1171
T381
T69 1
R1858.2KOhm5%
12
GSD3 2
1
Q35 2N7002Id=180mA/Pd=300mW
RN37A 2.2KOhm 5%1 2
R278453Ohm1%
12
RP2C
100KOhm 5%35
10
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Non-iAMT
Non-iAMT
FB_330ohm+-25%_100mHz_1.5A_0.09_ohm DC
Intel 20%
Place CAP
close to A24
Non-iAMT
Non-iAMT
Non-iAMT
Non-iAMT
ICH8-M(POWER,GND)1.2Lanai <OrgName>18 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
+1.5V_DMIPLL_R
+TP_VCCSUS1.05_2
+VCCGLANPLL
TP_VCCSUSLAN2
+ICH_V5REF_RUN
VCCCL1_5
TP_VCCCL1.05
+TP_VCCSUS1.5_2
+TP_VCCSUS1.05_1
+VCCSATPLL
+ICH_V5REF_SUS
+TP_VCCSUS1.5_1
TP_VCCSUSLAN1
+1.5V_DMIPLL
+VCCSUS3_3[0~6]
+VCCSUS3_3[7~19]
+VCCGLANPLL
+VCCSATPLL
+VCCSATPLL_L
+VCC_DMI
+V_CPU_IO
VCCHDA
+1.5V_PCIE_ICH
+3.3V_RUN
+1.5V_RUN
+1.5V_RUN
+3.3V_RUN
+3.3V_RUN
+1.25V_RUN
+1.05V_VCCP
+3.3V_SUS
+3.3V_RUN
+1.5V_RUN
+1.05V_VCCP
+3.3V_SUS
+3.3V_RUN
+RTC_CELL
+5V_RUN
+5V_SUS
+3.3V_SUS
+1.5V_RUN
+1.5V_RUN
+1.5V_RUN
+1.5V_RUN
+1.5V_RUN+1.05V_VCCP
+1.5V_PCIE_ICH
+1.5V_RUN
+3.3V_RUN
C2740.1UF/10VMLCC/+/-10%
12
C2650.1UF/10VMLCC/+/-10%
12
T641
C2250.1UF/10VMLCC/+/-10%
12
C2770.1UF/10VMLCC/+/-10%
12
C2141UF/10V
pt_c0603MLCC/+/-10%
12
L39 0.1Ohm/100Mhzpt_inductor_2p_126x98_tdk
2 1D14
RB751V_40
21
C2360.1UF/10VMLCC/+/-10%
12
C2460.022UF/16VMLCC/+/-10%
12
C2530.1UF/10VMLCC/+/-10%
12
C51722UF/10V
pt_c1206_h75MLCC/+/-20%
12
D15
RB751V_40
21
C2520.1UF/10VMLCC/+/-10%
12
C2190.1UF/10VMLCC/+/-10%
12
C42010UF/6.3VMLCC/+/-20%pt_c0805_h53
12
C2290.1UF/10VMLCC/+/-10%
12
C2831UF/10VMLCC/+/-10%pt_c0603/*
12
L17330Ohm/100MhzMURATA/BLM21PG331SN1Dpt_l0805_h41
21
R284 100Ohm 5%1 2
T371
C2280.1UF/10VMLCC/+/-10%
12
C2850.1UF/10VMLCC/+/-10%
12
C2690.1UF/10VMLCC/+/-10%
12
T61 1
+ CE21220UF/4V
TAN
/Lf_
T=20
00hr
s_10
5C/+
/-20%
pt_c7343d_h79
12
T57 1
C2180.1UF/10VMLCC/+/-10%
12
C2814.7UF/6.3VMLCC/+/-10%pt_c0603
12
C2270.1UF/10VMLCC/+/-10%
12
R2180Ohm5%
12
U32E
ICH8-M
A23A5
AA2AA7A25AB1
AB24AC11AC14AC25AC26AC27AD17AD20AD28AD29
AD3AD4AD6AE1
AE12AE2
AE22AD1
AE25AE5AE6AE9
AF14AF16AF18
AF3AF4AG5AG6
AH10AH13AH16AH19
AH2AF28AH22AH24AH26
AH3AH4AH8AJ5B11B14B17B2
B20B22B8
C24C26C27
C6D12D15D18
D2D4
E21E24E4E9
F15E23F28F29F7G1E2
G10G13G19G23G25G26G27H25H28H29
H3H6J1
J25J26J27J4J5
K23K28K29K3
K7L1L13L15L26L27L4L5M12M13M14M15M16M17M23M28M29M3N1N11N12N13N14N15N16N17N18N26N27N4N5N6P12P13P14P15P16P17P23P28P29R11R12R13R14R15R16R17R18R28R4T12T13T14T15T16T17T2U12U13U14U15U16U17U23U26U27U3U5V13V15V28V29W2W26W27Y28Y29Y4AB4
A1A2A28A29AH1AH29AJ1AJ2AJ28AJ29B1B29
AB23AB5AB6AD5U4
K6
W24
VSS[001]VSS[002]VSS[003]VSS[004]VSS[005]VSS[006]VSS[007]VSS[008]VSS[009]VSS[010]VSS[011]VSS[012]VSS[013]VSS[014]VSS[015]VSS[016]VSS[017]VSS[018]VSS[019]VSS[020]VSS[021]VSS[022]VSS[023]VSS[024]VSS[025]VSS[026]VSS[027]VSS[028]VSS[029]VSS[030]VSS[031]VSS[032]VSS[033]VSS[034]VSS[035]VSS[036]VSS[037]VSS[038]VSS[039]VSS[040]VSS[041]VSS[042]VSS[043]VSS[044]VSS[045]VSS[046]VSS[047]VSS[048]VSS[049]VSS[050]VSS[051]VSS[052]VSS[053]VSS[054]VSS[055]VSS[056]VSS[057]VSS[058]VSS[059]VSS[060]VSS[061]VSS[062]VSS[063]VSS[064]VSS[065]VSS[066]VSS[067]VSS[068]VSS[069]VSS[070]VSS[071]VSS[072]VSS[073]VSS[074]VSS[075]VSS[076]VSS[077]VSS[078]VSS[079]VSS[080]VSS[081]VSS[082]VSS[083]VSS[084]VSS[085]VSS[086]VSS[087]VSS[088]VSS[089]VSS[090]VSS[091]VSS[092]VSS[093]VSS[094]VSS[095]VSS[096]VSS[097]
VSS[099]VSS[100]VSS[101]VSS[102]VSS[103]VSS[104]VSS[105]VSS[106]VSS[107]VSS[108]VSS[109]VSS[110]VSS[111]VSS[112]VSS[113]VSS[114]VSS[115]VSS[116]VSS[117]VSS[118]VSS[119]VSS[120]VSS[121]VSS[122]VSS[123]VSS[124]VSS[125]VSS[126]VSS[127]VSS[128]VSS[129]VSS[130]VSS[131]VSS[132]VSS[133]VSS[134]VSS[135]VSS[136]VSS[137]VSS[138]VSS[139]VSS[140]VSS[141]VSS[142]VSS[143]VSS[144]VSS[145]VSS[146]VSS[147]VSS[148]VSS[149]VSS[150]VSS[151]VSS[152]VSS[153]VSS[154]VSS[155]VSS[156]VSS[157]VSS[158]VSS[159]VSS[160]VSS[161]VSS[162]VSS[163]VSS[164]VSS[165]VSS[166]VSS[167]VSS[168]VSS[169]VSS[170]VSS[171]VSS[172]VSS[173]VSS[174]VSS[175]VSS[176]VSS[177]VSS[178]
VSS_NCTF[01]VSS_NCTF[02]VSS_NCTF[03]VSS_NCTF[04]VSS_NCTF[05]VSS_NCTF[06]VSS_NCTF[07]VSS_NCTF[08]VSS_NCTF[09]VSS_NCTF[10]VSS_NCTF[11]VSS_NCTF[12]
VSS[179]VSS[180]VSS[181]VSS[182]VSS[183]
VSS[098]
VSS[184]
CORE
VCCA3GP
ATX
ARX
IDE
USB CORE
PCI
GLAN POWER
VCCP_CORE
VCCPSUS
VCCPUSB
U32F
ICH8-M
A16T7
G4
AA25AA26AA27AB27AB28AB29
D28D29E25E26E27F24F25G24H23H24J23J24K24K25L23L24L25
M24M25N23N24N25P24P25R24R25R26R27T23T24T27T28T29U24
AF29
R29
AE7AF7AG7AH7AJ7
AJ6
AD2
AC1AC2AC3AC4AC5
D1
F17G18
A13B13C13C14D14E14F14G14L11L12L14L16L17L18M11M18P11P18T11T18
F19G20
AC12
AD11
AC23AC24
AA3U7V7W1W6W7Y7
B15B18B4B9C15D13D5E10E7F11
AD25
AC18AC21AC22AG20AH28
P6P7C1N7P1P2P3P4P5R1R3R5
AC10AC9
AA5AA6
G12G17
J6AF20
F1L6L7M6M7
C3
A8
W23
U18
V17
V14
V11
U11
V18
V16
V12
B27
A27
B28
B26
A26
B25
A24
AF8
AC8
AE8AD8
R6
H7
AC16
AD7AC7
J7
AE29AE28
G22
G21F20
A22
W25
V24
U25
Y25
V25
V23
V5REF[1]V5REF[2]
V5REF_SUS
VCC1_5_B[01]VCC1_5_B[02]VCC1_5_B[03]VCC1_5_B[04]VCC1_5_B[05]VCC1_5_B[06]VCC1_5_B[07]VCC1_5_B[08]VCC1_5_B[09]VCC1_5_B[10]VCC1_5_B[11]VCC1_5_B[12]VCC1_5_B[13]VCC1_5_B[14]VCC1_5_B[15]VCC1_5_B[16]VCC1_5_B[17]VCC1_5_B[18]VCC1_5_B[19]VCC1_5_B[20]VCC1_5_B[21]VCC1_5_B[22]VCC1_5_B[23]VCC1_5_B[24]VCC1_5_B[25]VCC1_5_B[26]VCC1_5_B[27]VCC1_5_B[28]VCC1_5_B[29]VCC1_5_B[30]VCC1_5_B[31]VCC1_5_B[32]VCC1_5_B[33]VCC1_5_B[34]VCC1_5_B[35]VCC1_5_B[36]VCC1_5_B[37]VCC1_5_B[38]VCC1_5_B[39]VCC1_5_B[40]
VCC3_3[01]
VCCDMIPLL
VCC1_5_A[01]VCC1_5_A[02]VCC1_5_A[03]VCC1_5_A[04]VCC1_5_A[05]
VCCSATAPLL
VCC3_3[02]
VCC1_5_A[06]VCC1_5_A[07]VCC1_5_A[08]VCC1_5_A[09]VCC1_5_A[10]
VCCUSBPLL
VCCLAN1_05[1]VCCLAN1_05[2]
VCC1_05[01]VCC1_05[02]VCC1_05[03]VCC1_05[04]VCC1_05[05]VCC1_05[06]VCC1_05[07]VCC1_05[08]VCC1_05[09]VCC1_05[10]VCC1_05[11]VCC1_05[12]VCC1_05[13]VCC1_05[14]VCC1_05[15]VCC1_05[16]VCC1_05[17]VCC1_05[18]VCC1_05[19]VCC1_05[20]
VCCLAN3_3[1]VCCLAN3_3[2]
VCCHDA
VCCSUSHDA
V_CPU_IO[1]V_CPU_IO[2]
VCC3_3[07]VCC3_3[08]VCC3_3[09]VCC3_3[10]VCC3_3[11]VCC3_3[12]VCC3_3[13]
VCC3_3[15]VCC3_3[16]VCC3_3[17]VCC3_3[18]VCC3_3[19]VCC3_3[20]VCC3_3[21]VCC3_3[22]VCC3_3[23]VCC3_3[24]
VCCRTC
VCCSUS3_3[02]VCCSUS3_3[03]VCCSUS3_3[04]VCCSUS3_3[05]VCCSUS3_3[06]
VCCSUS3_3[07]VCCSUS3_3[08]VCCSUS3_3[09]VCCSUS3_3[10]VCCSUS3_3[11]VCCSUS3_3[12]VCCSUS3_3[13]VCCSUS3_3[14]VCCSUS3_3[15]VCCSUS3_3[16]VCCSUS3_3[17]VCCSUS3_3[18]
VCC1_5_A[11]VCC1_5_A[12]
VCC1_5_A[13]VCC1_5_A[14]
VCC1_5_A[15]VCC1_5_A[16]
VCCSUS1_05[1]VCCSUS1_05[2]
VCC1_5_A[20]VCC1_5_A[21]VCC1_5_A[22]VCC1_5_A[23]VCC1_5_A[24]
VCCSUS3_3[01]
VCC3_3[14]
VCC1_5_A[25]
VCC1_05[22]
VCC1_05[27]
VCC1_05[25]
VCC1_05[23]
VCC1_05[21]
VCC1_05[28]
VCC1_05[26]
VCC1_05[24]
VCCGLAN1_5[4]
VCCGLAN1_5[2]
VCCGLAN1_5[5]
VCCGLAN1_5[3]
VCCGLAN1_5[1]
VCCGLAN3_3
VCCGLANPLL
VCC3_3[06]
VCC3_3[03]
VCC3_3[05]VCC3_3[04]
VCCSUS3_3[19]
VCC1_5_A[17]
VCCSUS1_5[1]
VCC1_5_A[19]VCC1_5_A[18]
VCCSUS1_5[2]
VCC_DMI[2]VCC_DMI[1]
VCCCL1_05
VCCCL3_3[2]VCCCL3_3[1]
VCCCL1_5
VCC1_5_B[45]
VCC1_5_B[43]
VCC1_5_B[41]
VCC1_5_B[46]
VCC1_5_B[44]
VCC1_5_B[42]
R4140Ohm 5%
12
C4261UF/10V
pt_c0603MLCC/+/-10%
12
C2090.1UF/10VMLCC/+/-10%
12
C2720.1UF/10VMLCC/+/-10%
12
C2820.1UF/10VMLCC/+/-10%/*
12
L3410uH
pt_l0805Irat=100mA
21
C2610.1UF/10VMLCC/+/-10%
12
T441
T661
C23422UF/10V
pt_c1206_h75MLCC/+/-20%
12
C2642.2UF/10VMLCC/+/-10%pt_c0805_h53
12
C2170.1UF/10VMLCC/+/-10%
12
R252 10Ohmpt_r0805_h24
5%1 2
R497 1Ohm 5%pt_r0603
1 2
C2420.022UF/16VMLCC/+/-10%
12
C22022UF/10V
pt_c1206_h75MLCC/+/-20%
12
C2410.1UF/10VMLCC/+/-10%
12
D13
BAT54C
1
23
C2100.1UF/10VMLCC/+/-10%
12
C5154.7UF/10VMLCC/+/-10%pt_c1206_h71
12
R255 10Ohm5%1 2
C2800.1UF/10VMLCC/+/-10%
12
C2500.01UF/25VMLCC/+/-10%
12
C2130.1UF/10VMLCC/+/-10%
12
C2241UF/10V
pt_c0603MLCC/+/-10%
12
T541
C24910UF/6.3VMLCC/+/-20%pt_c0805_h53
12
C2320.1UF/10VMLCC/+/-10%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TOP
SMbus address A0Non-iAMT
CLOCK 0 , 1CKE 0 , 1
Non-iAMT
SMbus address A4
CLOCK 2 , 3CKE 2 , 3
BOT
Please these Caps near So-Dimm1.
Please these Caps near So-Dimm1.
Please these Caps near So-Dimm2.
Please these Caps near So-Dimm2.
A is required to route to Top
S0DIMM for AMT to function
Ch.A SODIMM needs to be
populated for Intel AMT support.
Non-iAMT
Non-iAMT
Non-iAMT
DDR2 SO-DIMM (0)1.2Lanai <OrgName>19 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
DDR_B_DQS4
DDR_B_D22
DDR_B_D50
DDR_B_D28 DDR_B_D31
DDR_B_DM6
PM_EXTTS#1
DDR_B_DM1
DDR_B_D41
DDR_B_D59
DDR_B_D62
DDR_B_D33
DDR_B_D17
DDR_B_D2
DDR_B_D20
DDR_B_MA3
DDR_B_D3
DDR_B_DQS#1
DDR_B_D42 DDR_B_D43
DDR_B_DQS2
M_ODT3
DDR_B_D26
DDR_B_DQS#7
DDR_B_MA2
DDR_B_D5
DDR_B_DM5
DDR_B_D61DDR_B_D56
DDR_B_D34
DDR_B_D23
DDR_B_D49
DDR_B_D55
DDR_B_D25
DDR_B_D14
DDR_B_D39
DDR_B_MA5
DDR_B_DM0
DDR_B_D58
DDR_B_DQS#3
DDR_B_BS0
DDR_B_DQS1
DDR_B_D54
M_ODT2
DDR_B_DM4
DDR_B_D6
DDR_B_D8
DDR_B_D1
DDR_B_MA11
DDR_B_DQS#0
DDR_B_D44
DDR_B_CAS#
DDR_B_D52
DDR_B_D36
DDR_B_DQS#5
DDR_B_D29
DDR_B_D10
DDR_B_MA8
DDR_B_DQS5
DDR_B_D0
DDR_B_BS2
DDR_B_D35
DDR_B_DQS0
DDR_B_D38
DDR_B_D19
DDR_B_MA0
DDR_B_D51
DDR_B_D15
DDR_B_DQS7
DDR_B_D4
DDR_B_MA7
DDR_B_MA13
DDR_B_D37
DDR_B_D30
DDR_B_D7
DDR_B_D11
MEM_SCLK
DDR_B_DM3
DDR_B_D60
DDR_B_D46
DDR_B_MA9
DDR_B_WE#DDR_B_RAS#
DDR_B_DQS#6
DDR_B_D18
DDR_B_MA10
DDR_B_D48
DDR_B_D57
MEM_SDATA
DDR_B_MA6
DDR_B_D47
DDR_B_DQS6
DDR_B_D40
DDR_B_DQS3
DDR_B_D27
DDR_B_DM7
DDR_B_BS1
DDR_B_D32
DDR_B_D13
DDR_B_DM2
DDR_B_D21
DDR_B_D63
DDR_B_D45
DDR_B_MA12
DDR_B_D12
DDR_B_MA4
DDR_B_DQS#4
DDR_B_D16
DDR_B_MA1
DDR_B_DQS#2
DDR_B_D53
DDR_B_D24
DDR_B_D9
MEM_SCLK
M_ODT0
DDR_A_DQS3
DDR_A_D23
DDR_A_DQS0
DDR_A_D3
DDR_A_D32
DDR_A_D27
DDR_A_D22
DDR_A_DM2DDR_A_DQS2
DDR_A_D21
DDR_A_D41
DDR_A_MA8
DDR_A_D20
DDR_A_DQS#1
DDR_A_DM6
DDR_A_D52
DDR_A_D42
DDR_A_D38
M_ODT1
DDR_A_CAS#
DDR_A_MA10
DDR_A_MA4
DDR_A_MA11
DDR_A_D25
DDR_A_D1
DDR_A_D61
DDR_A_D36
DDR_A_D29
DDR_A_D19
DDR_A_DQS1
DDR_A_D50
DDR_A_D40DDR_A_D45
DDR_A_D37
DDR_A_DM0
DDR_A_D59
DDR_A_D51
DDR_A_MA2
DDR_A_D18
DDR_A_D57
DDR_A_D48
DDR_A_DM5
DDR_A_D47DDR_A_D44
DDR_A_DQS#4
DDR_A_D33
DDR_A_WE#
DDR_A_MA1
DDR_A_MA7
DDR_A_D16
DDR_A_D15
DDR_A_D12
DDR_A_D60DDR_A_D58
DDR_A_DQS#6
DDR_A_MA13
DDR_A_BS1
DDR_A_DQS#7
DDR_A_D55
DDR_A_D49DDR_A_D53
DDR_A_D34
DDR_A_D9
DDR_A_DM1
DDR_A_DQS7
DDR_A_DQS#5
DDR_A_DM3
PM_EXTTS#0
DDR_A_D4
DDR_A_DQS6
DDR_A_DM4
DDR_A_RAS#DDR_A_BS0
DDR_A_MA3
DDR_A_MA6
DDR_A_D31
DDR_A_DQS#2
DDR_A_D6DDR_A_D5
DDR_A_D11
DDR_A_D56
DDR_A_MA9
DDR_A_D30
DDR_A_D28
DDR_A_D7
DDR_A_DQS5
DDR_A_D35DDR_A_D39
DDR_A_D26
DDR_A_D13
MEM_SDATA
DDR_A_DQS4
DDR_A_DQS#3
DDR_A_D2
DDR_A_D10
DDR_A_D8
DDR_A_D46
DDR_A_MA5
DDR_A_BS2
DDR_A_D17
DDR_A_D0
DDR_A_DQS#0
DDR_A_D14
DDR_A_DM7
DDR_A_D54
DDR_A_D43
DDR_A_MA0
DDR_A_MA12
DDR_A_D24
DDR_A_MA14 DDR_B_MA14
DDR_A_D62DDR_A_D63
DDR_A_D[0..63] 11DDR_A_DM[0..7] 11
DDR_A_DQS[0..7] 11DDR_A_DQS#[0..7] 11
DDR_CKE0_DIMMA10,20
DDR_A_BS211,20
DDR_A_BS011,20DDR_A_WE#11,20
DDR_A_CAS#11,20DDR_CS1_DIMMA#10,20
M_ODT110,20
DDR_CKE1_DIMMA 10,20
M_CLK_DDR0 10M_CLK_DDR#0 10
DDR_A_BS1 11,20DDR_A_RAS# 11,20
DDR_CS0_DIMMA# 10,20
M_ODT0 10,20
M_CLK_DDR1 10M_CLK_DDR#1 10
PM_EXTTS#0 10
MEM_SDATA17MEM_SCLK17
DDR_A_MA[0..14] 10,11,20
DDR_CKE3_DIMMB 10,20
M_CLK_DDR#3 10
PM_EXTTS#1 10
DDR_B_MA[0..14] 10,11,20
M_CLK_DDR#2 10M_CLK_DDR2 10
DDR_CS2_DIMMB# 10,20
DDR_B_DQS#[0..7] 11
DDR_B_RAS# 11,20
M_ODT310,20
DDR_B_DQS[0..7] 11DDR_B_D[0..63] 11
DDR_B_WE#11,20
DDR_B_CAS#11,20 M_ODT2 10,20
DDR_B_BS011,20
DDR_CKE2_DIMMB10,20
DDR_CS3_DIMMB#10,20
DDR_B_DM[0..7] 11
DDR_B_BS1 11,20
M_CLK_DDR3 10
DDR_B_BS211,20
+1.8V_SUS
+1.8V_SUS
V_DDR_MCH_REF
+3.3V_RUN
V_DDR_MCH_REF
+3.3V_RUN
+1.8V_SUS +1.8V_SUS
+3.3V_RUN
+3.3V_RUN
V_DDR_MCH_REF
V_DDR_MCH_REF
+1.8V_SUS
+3.3V_RUN
+1.8V_SUS
+1.8V_SUS
+1.8V_SUS
C102
0.1UF/10V
MLC
C/+80-20%
12
C147
2.2UF/6.3VMLCC/+/-10%pt_c0603
12
C395
2.2UF/6.3VMLCC/+/-10%pt_c0603
12
C97
2.2UF/6.3V
MLC
C/+/-10%
pt_c0805_h53
12
R171
10KOhm5%
12
C168
2.2UF/6.3VMLCC/+/-10%pt_c0603
12
C393
0.1UF/10VMLCC/+80-20%
12
R172
10KOhm5%
12
C388
0.1UF/10VMLCC/+80-20%
12
C200
0.1UF/10V
MLC
C/+80-20%
12
C142
2.2UF/6.3VMLCC/+/-10%pt_c0603
12
C163
2.2UF/6.3VMLCC/+/-10%pt_c0603
12
C138
2.2UF/6.3VMLCC/+/-10%pt_c0603
12
C384
0.1UF/10VMLCC/+80-20%
12
C101
0.1UF/10V
MLC
C/+80-20%
12
C99
2.2UF/6.3V
MLC
C/+/-10%
pt_c0805_h53
12
C154
2.2UF/6.3VMLCC/+/-10%pt_c0603
12
C445
2.2UF/6.3V
MLC
C/+/-10%
pt_c0805_h53
12
R178
10KOhm5%
12
C167
0.1UF/10VMLCC/+80-20%
12
C435
2.2UF/6.3V
MLC
C/+/-10%
pt_c0805_h53
12
C153
0.1UF/10VMLCC/+80-20%
12
C128
0.1UF/10VMLCC/+80-20%
12
CON15
STDFOXCONN/AS0A426-NASN-7F
13579
111315171921232527293133353739
414345474951535557596163656769717375777981838587899193959799
101103105107109111113115117119121123125127129131133135137139141143145147149151153155157159161163165167169171173175177179181183185187189191193195197199
246810121416182022242628303234363840
4244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144146148150152154156158160162164166168170172174176178180182184186188190192194196198200
201 202204203
VREFVSS47DQ0DQ1VSS37DQS#0DQS0VSS48DQ2DQ3VSS38DQ8DQ9VSS49DQS#1DQS1VSS39DQ10DQ11VSS50
VSS18DQ16DQ17VSS1DQS#2DQS2VSS19DQ18DQ19VSS22DQ24DQ25VSS23DM3NC4VSS9DQ26DQ27VSS4CKE0VDD7NC1A16_BA2VDD9A12A9A8VDD5A5A3A1VDD10A10/APBA0WE#VDD2CAS#S1#VDD3ODT1VSS11DQ32DQ33VSS26DQS#4DQS4VSS2DQ34DQ35VSS27DQ40DQ41VSS29DM5VSS51DQ42DQ43VSS40DQ48DQ49VSS52NCTESTVSS30DQS#6DQS6VSS31DQ50DQ51VSS33DQ56DQ57VSS3DM7VSS34DQ58DQ59VSS14SDASCLVDDSPD
VSS46DQ4DQ5
VSS15DM0
VSS5DQ6DQ7
VSS16DQ12DQ13
VSS17DM1
VSS53CK0
CK0#VSS41DQ14DQ15
VSS54
VSS20DQ20DQ21VSS6NC3DM2
VSS21DQ22DQ23
VSS24DQ28DQ29
VSS25DQS#3DQS3
VSS10DQ30DQ31VSS8CKE1VDD8
A15A14
VDD11A11A7A6
VDD4A4A2A0
VDD12BA1
RAS#S0#
VDD1ODT0
A13VDD6
NC2VSS12DQ36DQ37
VSS28DM4
VSS42DQ38DQ39
VSS55DQ44DQ45
VSS43DQS#5DQS5
VSS56DQ46DQ47
VSS44DQ52DQ53
VSS57CK1
CK1#VSS45
DM6VSS32DQ54DQ55
VSS35DQ60DQ61VSS7
DQS#7DQS7
VSS36DQ62DQ63
VSS13SA0SA1
GND0 GND1NP_NC2NP_NC1
C125
0.1UF/10VMLCC/+80-20%
12
CON14
STDFOXCONN/AS0A426-N2SN-7F
13579
111315171921232527293133353739
414345474951535557596163656769717375777981838587899193959799
101103105107109111113115117119121123125127129131133135137139141143145147149151153155157159161163165167169171173175177179181183185187189191193195197199
246810121416182022242628303234363840
4244464850525456586062646668707274767880828486889092949698100102104106108110112114116118120122124126128130132134136138140142144146148150152154156158160162164166168170172174176178180182184186188190192194196198200
201 202204203
VREFVSS47DQ0DQ1VSS37DQS#0DQS0VSS48DQ2DQ3VSS38DQ8DQ9VSS49DQS#1DQS1VSS39DQ10DQ11VSS50
VSS18DQ16DQ17VSS1DQS#2DQS2VSS19DQ18DQ19VSS22DQ24DQ25VSS23DM3NC4VSS9DQ26DQ27VSS4CKE0VDD7NC1A16_BA2VDD9A12A9A8VDD5A5A3A1VDD10A10/APBA0WE#VDD2CAS#S1#VDD3ODT1VSS11DQ32DQ33VSS26DQS#4DQS4VSS2DQ34DQ35VSS27DQ40DQ41VSS29DM5VSS51DQ42DQ43VSS40DQ48DQ49VSS52NCTESTVSS30DQS#6DQS6VSS31DQ50DQ51VSS33DQ56DQ57VSS3DM7VSS34DQ58DQ59VSS14SDASCLVDDSPD
VSS46DQ4DQ5
VSS15DM0
VSS5DQ6DQ7
VSS16DQ12DQ13
VSS17DM1
VSS53CK0
CK0#VSS41DQ14DQ15
VSS54
VSS20DQ20DQ21VSS6NC3DM2
VSS21DQ22DQ23
VSS24DQ28DQ29
VSS25DQS#3DQS3
VSS10DQ30DQ31VSS8CKE1VDD8
A15A14
VDD11A11A7A6
VDD4A4A2A0
VDD12BA1
RAS#S0#
VDD1ODT0
A13VDD6
NC2VSS12DQ36DQ37
VSS28DM4
VSS42DQ38DQ39
VSS55DQ44DQ45
VSS43DQS#5DQS5
VSS56DQ46DQ47
VSS44DQ52DQ53
VSS57CK1
CK1#VSS45
DM6VSS32DQ54DQ55
VSS35DQ60DQ61VSS7
DQS#7DQS7
VSS36DQ62DQ63
VSS13SA0SA1
GND0 GND1NP_NC2NP_NC1
C429
0.1UF/10V
MLC
C/+80-20%
12
C136
0.1UF/10VMLCC/+80-20%
12
C119
2.2UF/6.3VMLCC/+/-10%pt_c0603
12
C151
2.2UF/6.3VMLCC/+/-10%pt_c0603
12
R170
10KOhm5%
12
C379
2.2UF/6.3VMLCC/+/-10%pt_c0603
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TOP
BOT
Please these resistorclosely DIMMA, alltrace length<750 mil.
Layout note : Place 1 cap close to every 1 R-pack terminated to SMDDR_VTERM.
Please these resistorclosely DIMMB, alltrace length<750 mil.
DDR2 SO-DIMM (1)1.2Lanai <OrgName>20 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
DDR_A_MA6DDR_A_MA7
DDR_A_MA1
DDR_A_MA10
DDR_A_MA8
DDR_A_MA9DDR_A_MA3
DDR_A_RAS#
DDR_A_BS2
DDR_A_MA5
DDR_A_MA12
DDR_A_BS0
DDR_A_MA13
DDR_B_MA2
DDR_B_MA7
DDR_B_MA8
DDR_B_MA14
DDR_B_MA11DDR_B_MA6
M_ODT0 M_ODT2
DDR_A_BS1DDR_A_MA0
DDR_A_MA14DDR_A_MA11
DDR_B_MA3DDR_B_MA1
DDR_B_MA12DDR_B_MA9
DDR_B_MA10
DDR_B_MA4DDR_B_MA5
DDR_B_CAS#
DDR_A_MA2DDR_A_MA4
DDR_B_WE#DDR_B_BS0
DDR_A_CAS#DDR_A_WE#
DDR_B_BS1DDR_B_MA0
DDR_B_MA13DDR_B_RAS#
DDR_A_MA[0..14]10,11,19 DDR_B_MA[0..14] 10,11,19
DDR_CKE3_DIMMB 10,19
DDR_CS3_DIMMB# 10,19DDR_CS2_DIMMB# 10,19DDR_B_BS2 11,19
DDR_CKE2_DIMMB 10,19
M_ODT3 10,19
DDR_CS1_DIMMA#10,19
DDR_CKE1_DIMMA10,19
M_ODT110,19
DDR_CKE0_DIMMA10,19
DDR_CS0_DIMMA#10,19
DDR_A_RAS#11,19
M_ODT010,19 M_ODT2 10,19
DDR_A_BS111,19
DDR_B_CAS# 11,19
DDR_B_WE# 11,19DDR_B_BS0 11,19
DDR_A_BS011,19
DDR_A_CAS#11,19DDR_A_WE#11,19
DDR_B_BS1 11,19
DDR_B_RAS# 11,19
DDR_A_BS211,19
+0.9V_DDR_VTT
+0.9V_DDR_VTT
+0.9V_DDR_VTT
C1180.1UF/10VMLCC/+80-20%
12
R155 56Ohm5%1 2
R125 56Ohm5%
1 2
RN31B 56Ohm 5%3 4
C1460.1UF/10VMLCC/+80-20%
12
RN21A 56Ohm5%
1 2
RN27A 56Ohm5%
1 2
C1230.1UF/10VMLCC/+80-20%
12
C1560.1UF/10VMLCC/+80-20%
12
RN29B 56Ohm 5%3 4
R158 56Ohm5% 1 2
RN34B 56Ohm 5%3 4
RN16B 56Ohm 5%3 4
RN35A 56Ohm5%
1 2
C1910.1UF/10VMLCC/+80-20%
12
RN30A 56Ohm5%
1 2
RN27B 56Ohm 5%3 4
RN25B 56Ohm 5%3 4
RN24B 56Ohm 5%3 4
R133 56Ohm5%1 2
RN17A 56Ohm5%
1 2
C1300.1UF/10VMLCC/+80-20%
12
RN18B 56Ohm 5%3 4
RN32A 56Ohm5%
1 2
C1430.1UF/10VMLCC/+80-20%
12
RN35B 56Ohm 5%3 4
RN23B 56Ohm 5%3 4
RN17B 56Ohm 5%3 4
RN26A 56Ohm5%
1 2
C1650.1UF/10VMLCC/+80-20%
12
RN18A 56Ohm5%
1 2
RN33A 56Ohm5%
1 2
R149 56Ohm5% 1 2
RN26B 56Ohm 5%3 4
RN34A 56Ohm5%
1 2
R152 56Ohm5% 1 2
RN22B 56Ohm 5%3 4
C1200.1UF/10VMLCC/+80-20%
12
RN28A 56Ohm5%
1 2
R124 56Ohm5% 1 2
C1390.1UF/10VMLCC/+80-20%
12
R126 56Ohm5% 1 2
C1440.1UF/10VMLCC/+80-20%
12
RN19B 56Ohm 5%3 4
R154 56Ohm5%1 2
RN20B 56Ohm 5%3 4
C1750.1UF/10VMLCC/+80-20%
12
C1920.1UF/10VMLCC/+80-20%
12
RN16A 56Ohm5%
1 2
RN21B 56Ohm 5%3 4
RN33B 56Ohm 5%3 4
R157 56Ohm5% 1 2
C1370.1UF/10VMLCC/+80-20%
12
RN25A 56Ohm5%
1 2
R131 56Ohm5%1 2
C1350.1UF/10VMLCC/+80-20%
12
RN19A 56Ohm5%
1 2
C1700.1UF/10VMLCC/+80-20%
12
C1860.1UF/10VMLCC/+80-20%
12
C1850.1UF/10VMLCC/+80-20%
12
R147 56Ohm5% 1 2
RN24A 56Ohm5%
1 2
RN30B 56Ohm 5%3 4
R153 56Ohm5%1 2
C1900.1UF/10VMLCC/+80-20%
12
RN20A 56Ohm5%
1 2
C1890.1UF/10VMLCC/+80-20%
12
C1480.1UF/10VMLCC/+80-20%
12
C1640.1UF/10VMLCC/+80-20%
12
RN32B 56Ohm 5%3 4
RN31A 56Ohm5%
1 2
C1690.1UF/10VMLCC/+80-20%
12
RN22A 56Ohm5%
1 2
C1550.1UF/10VMLCC/+80-20%
12
RN23A 56Ohm5%
1 2
C1490.1UF/10VMLCC/+80-20%
12
RN29A 56Ohm5%
1 2
C1500.1UF/10VMLCC/+80-20%
12
R156 56Ohm5%
1 2
RN28B 56Ohm 5%3 4
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Non-iAMT
Enable ITP
UMA without iAMT
Populate for Napa platforms only
14.318MHz
120 OHM@100MHz
120 OHM@100MHz
Non-iAMT
Non-iAMT
Non-iAMT
0=UMA1=Disc. GRFX down
FSC FSB FSA CPU SRC PCI 1 0 1 100 100 33 0 0 1 133 100 33 0 1 1 166 100 33 0 1 0 200 100 33 0 0 0 266 100 33 1 0 0 333 100 33 1 1 0 400 100 33 1 1 1 RSVD 100 33
Place close to Clock Gen.
SMBus address D2 Non-iAMT
PCI_LOM=FCTSEL1
FCTSEL1(PIN 34) Pin43 Pin44 Pin47 Pin48 0 = UMA DOT96T DOT96C 96/100M_T 96/100M_C 1 = Disc. 27Mout 27M_SSout SRCT0 SRCC0 GRFX down
No.6
No.25
No.28
No.40
No.44
No.57
No.57
CLK GEN. CY285471.2Lanai <OrgName>21 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
CLK_XTAL_OUT
MINI2CLK_REQ#MINI1CLK_REQ#
CLK_3GPLLREQ#SATA_CLKREQ#CARD_CLK_REQ#
PGMODE
PCI_PCCARD
+CK_VDD_MAIN
+CK_VDD_MAIN2
FSA
PCI_ICH
27M_SS
CLK_XTAL_IN
+CK_VDD_REF
27M_NSS
PCI_ICH
+CK_VDD_MAIN2
CLK_PCI_PCCARD
CLK_PCI_5025CLK_ICH_14M
CLK_ICH_48MCLK_PCI_ICH
CLK_SDATA
CLK_SCLK
PCIE_LOM_CLKREQ#
PCIE_MINI2PCIE_MINI2#
FSC
+CK_VDD_48
DOT96_SSC#
PCI_LOM
CPU_XTP
PCIE_MINI1
MCH_BCLK
XDP_3GPLL
DOT96_SSC
FSB
CLK_SDATA
CPU_XTP#
PCI_LOM
PCIE_SATA#
CLK_XTAL_OUT
CLK_SCLK
PCIE_ICH
PCIE_LOM#
FSA
PCIE_EXPCARD#
PCIE_LOM
MCH_3GPLL#
PCI_PCCARD
CPU_BCLKCPU_BCLK#
MCH_3GPLL
XDP_3GPLL#
CLK_XTAL_IN
+CK_VDD_48
MCH_BCLK#
PCIE_ICH#
PCIE_EXPCARD
PCIE_SATA
+CK_VDD_REF
PGMODE
PCI_SIO
CLKREF
+CK_VDD_MAIN
+CK_VDD_A
PCIE_MINI1#
+CK_VDD_A
CLK_XDP 52
CLK_PCIE_MINI1# 50
CLK_PCIE_SATA# 15
CARD_CLK_REQ# 35
CLK_CPU_BCLK# 7CLK_CPU_BCLK 7
CLK_PCIE_ICH 16
MINI1CLK_REQ# 50
CLK_MCH_BCLK# 9
MCH_DREFCLK10
H_STP_PCI# 17
CLK_MCH_3GPLL 10
CLK_PCIE_EXPCARD 35
CLK_PCIE_MINI1 50
CLK_PCIE_MINI2# 50MINI2CLK_REQ# 50
CLK_PCIE_ICH# 16
CLK_PCI_ICH16
CLK_PCIE_EXPCARD# 35MCH_DREFCLK#10
CLK_XDP# 52
CLK_MCH_BCLK 9
CLK_MCH_3GPLL# 10CLK_3GPLLREQ# 10
SATA_CLKREQ# 17
CLK_PCIE_MINI2 50
H_STP_CPU# 17
DREF_SSCLK# 10DREF_SSCLK 10
CLK_ICH_14M17
CLK_PCI_502537CLK_PCI_PCCARD32
CLK_ICH_48M17
CPU_MCH_BSEL17,10CPU_MCH_BSEL07,10
CPU_MCH_BSEL27,10
CLK_PCIE_XDP_3GPLL# 52CLK_PCIE_XDP_3GPLL 52
CLK_PCIE_SATA 15
CLK_PWRGD17
CKG_SMBCLK37
CKG_SMBDAT37
CLK_PCIE_LOM 47CLK_PCIE_LOM# 47PCIE_LOM_CLKREQ# 47
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN
+3.3V_RUN+3.3V_RUN
+3.3V_ALW
+3.3V_RUN
+3.3V_RUN
+3.3V_ALW
U5
ICS9LPR333CKLFT
1
23
4
56
78
9
1011
12
1314
15
1617
18
1920
21
22
23
2425
26
27
28
29
30
31
323334
35
36
37
38
39
40
41
42
4344
45
46
4748
49
5051
5253
54
5556
57
5859
6061
62
6364
65
6667
68
6970
71
72
73
VDDSRC1
SRCC9SRCT9
GNDSRC1
CPUC2_ITP/SRCC10CPUT2_ITP/SRCT10
VDDAGNDA
*PG_MODE
CPUC1_MCHCPUT1_MCH
VDDCPU
CPUC0CPUT0
GNDCPU
SMBCLKSMBDAT
VDDREF
X2X1
GNDREF
REF1
REF0/FSLC/TEST_SEL
CPU_STOP#PCI_SRC_STOP#
CLKREQ2#
PCI1
CLKREQ3#
CLKREQ5#
VDDPCI1
GNDPCI1
*PCI2/TMEPCI3PCI4/FCTSEL1
GNDPCI2
VDDPCI2
PCI_F0/ITP_EN
CLKREQ7#
CK_PWRGD/PD#
VDD48
USB_48MHz/FSLA
GND48
DOTT_96/27MHz_NSDOTC_96/27MHz_SS
FSLB/TEST_MODE
CLKREQ1#
LCD100/SRCT0LCD100/SRCC0
VDDSRC2
SRCT1/SATATSRCC1/SATAC
SRCT2SRCC2
VDDSRC3
SRCT3SRCC3
CLKREQ4#
SRCT4SRCC4
SRCT5SRCC5
CLKREQ6#
SRCT6SRCC6
VDDSRC4
SRCT7SRCC7
GNDSRC2
SRCC8SRCT8
CLKREQ8#
CLKREQ9#
GND
C8010UF/10V
pt_c0805_h53MLCC/+80-20%
12
C7010PF/50V
MLCC/+/-0.5PF
12
RN1A33Ohm5% 1 2
C66
27PF/50VMLCC/+/-5%
12
R89 0Ohm/*
5%1 2
C630.1UF/10VMLCC/+80-20%
12
C710.1UF/10V
MLCC/+80-20%
12
R6110KOhm
5%
1 2
RN13A22Ohm5% 1 2
C624.7UF/6.3VMLCC/+/-10%pt_c0603
12
RN6B2.2KOhm5%
34
RN10B33Ohm5% 3 4
1 2X2
14.31818Mhz
RN5A33Ohm5% 1 2RN5B33Ohm5% 3 4
R55 33Ohm 5%1 2
RN13B22Ohm5% 3 4
C540.1UF/10V
MLCC/+80-20%
12
R77
10KOhm5%/*1
2
R54 2.2Ohm5%pt_r0603
1 2
GSD3 2
1
Q19
2N7002
R67 33Ohm 5%1 2
C6410PF/50V
MLCC/+/-0.5PF
12
RN8A33Ohm5% 1 2RN11A33Ohm5% 1 2
GSD3 2
1
Q18
2N7002
R72
10KOhm5%
12
C730.1UF/10V
MLCC/+80-20%
12
RN3A33Ohm5% 1 2
RN7B33Ohm5% 3 4
R79 10KOhm 5%1 2
R59 33Ohm 5%1 2
C774.7UF/6.3VMLCC/+/-10%pt_c0603
12
R68 2.2KOhm 5%1 2
RN2B33Ohm5% 3 4
R47
1Ohm5%pt_r0603
1 2
R81 2.2Ohm5%pt_r0603
1 2
L10
330Ohm/100Mhzpt_l0805_h41MURATA/BLM21PG331SN1D
21
C69
27PF/50VMLCC/+/-5%
12
RN14B33Ohm5% 3 4
R52
0Ohm5%
1 2
RN3B33Ohm5% 3 4
R86
0Ohm /*
5%
1 2
R70 10KOhm 5%1 2
C740.047UF/10VMLCC/+/-10%
12
R85
10KOhm5%/*1
2
R80 10KOhm 5%1 2
C600.047UF/10VMLCC/+/-10%
12
C560.1UF/10V
MLCC/+80-20%
12
R83
10KOhm5%
12
C550.047UF/10VMLCC/+/-10%
12
RN7A33Ohm5% 1 2
C7610PF/50V
MLCC/+/-0.5PF
12
R88
2.2KOhm5%
12
R57475Ohm1% 1 2
R87
2.2KOhm5%
12
R42 10KOhm 5%1 2R45 10KOhm 5%1 2
RN14A33Ohm5% 1 2
RN4A33Ohm5% 1 2
RN11B33Ohm5% 3 4
L9
330Ohm/100Mhzpt_l0805_h41MURATA/BLM21PG331SN1D
21
C7210PF/50V
MLCC/+/-0.5PF
12
RN9B33Ohm5% 3 4R6233Ohm5% 1 2
RN10A33Ohm5% 1 2
RN9A33Ohm5% 1 2
RN12B33Ohm5% 3 4
R53 33Ohm 5%1 2
R76 10KOhm 5%1 2
RN6A2.2KOhm5%
12
C8110UF/10V
pt_c0805_h53MLCC/+80-20%
12
C750.1UF/10VMLCC/+80-20%
12
C670.1UF/10VMLCC/+80-20%
12
C78
10PF/50VMLCC/+/-0.5PF
12
R78
10KOhm5%/*1
2
R43 10KOhm/*
5%
1 2
R69 2.2KOhm 5%1 2
RN1B33Ohm5% 3 4
R7510KOhm5% /*12
RN4B33Ohm5% 3 4
RN8B33Ohm5% 3 4
RN2A33Ohm5% 1 2
RN12A33Ohm5% 1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.2Lanai <OrgName>23 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.2Lanai <OrgName>24 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
1.2Lanai <OrgName>25 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.2Lanai 26 68Monday, March 19, 2007PROJECT: SHEET OF
DATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :RELEASE DATE :
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
1.2Lanai 27 68Monday, March 19, 2007
Sean KuoPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
40mils 40mils
V_DMIC IS DEPENDENT ON MIC SELECTION (1.8V - 3.3V TYP) Verify to ensure operability with chosen mic supplier.
Note2: If using 2 dig mics, also use AUD_DMIC_IN0.This input supports 2 digimics. AUD_DMIC_IN1 is onlyused to support 4 dig mics.
Note1: If only 1 digital mic, use AUD_DMIC_IN0.
Adress: A9H --Contrast AAH --Backlight
Populate R1 forDPST implementationonly.
Populate R6 forplatform without DPSTsupport. No Stuff forDiscrete DSPT supportdue to back up plan.
No.19
No.27
No.9
No.9
No.9
No.23No.23
No.48
No.52
No.56
LVDS CON1.2Lanai 28 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
+3V_DMIC
USBP5_D-USBP5_D+
LAMP_STAT#
AUX_LCD_CBL_DET#
USBP5_D+
AUD_DMIC_CLK_L
+5V_CCD
LCD_CBL_DET_R
BACKLITEON
USBP5_D-
+3V_DMIC
INVERTER_CBL_DET#
LCDVCC_ON
LCD_ACLK+_C
LCD_B0+
LCD_A0-
LCD_BCLK+_C
LCD_B1+
LCD_ACLK-_C
LCD_B2+
LCD_A2-
LCD_A1-
LCD_A0+
LCD_A2+
LCD_B2-
LCD_B1-
LCD_A1+
LCD_B0-
LCD_BCLK-_C
LCD_B0-
LCD_B2-
LCD_B1+
LCD_A0-
LCD_B2+
LCD_BCLK+_C
LCD_A0+
LCD_A2-
LCD_A2+
LCD_B0+
LCD_ACLK-_C
LCD_ACLK+_C
LCD_A1+
LCD_A1- LCD_B1-
LCD_BCLK-_C
BACKLITEON+5V_CCD
AUD_DMIC_CLK_L
RUN_ON37,49,51,54ICH_USBP5+16
ICH_USBP5-16
LCD_SMBDAT 37LCD_SMBCLK 37
INVERTER_CBL_DET# 37LCD_CBL_DET_R 37
AUD_DMIC_IN0 44
AUX_LCD_CBL_DET# 37
LCD_TST 38
LCDVCC_TST_EN37
ENVDD10
LCD_DDCCLK 10LCD_DDCDAT 10
LCD_A0- 10
LCD_B0+ 10
LCD_A0+ 10
LCD_A2- 10LCD_A2+ 10
LCD_B2- 10LCD_B2+ 10
LCD_B0- 10
LCD_B1+ 10
LCD_A1- 10
LCD_B1- 10
LCD_A1+ 10
LCD_ACLK- 10
LCD_ACLK+ 10 LCD_BCLK+ 10
LCD_BCLK- 10
BIA_PWM10
CCD_VDD_ON17
AUD_DMIC_CLK44
GND
+PWR_SRC
GND
GFX_PWR_SRC
+3.3V_RUN
+5V_ALW
GND
GND
+3.3V_RUN
+5V_ALW
GFX_PWR_SRC
GND
+3.3V_RUN
GND
+15V_ALW +LCDVCC
GND
+3.3V_RUNGND
GND
GND
GND
+3.3V_ALW
+3.3V_RUN
+3.3V_RUN
+5V_RUN
+3.3V_RUN
GND
+LCDVCC
GND
+LCDVCC
GND
CON1
WTOB_CON_56PJAE/FI-M56SB1
1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556
57
58
59
60
61
62
63
64
65
66
67
68
123456789
1011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556
SIDE_1
SIDE_2
SIDE_3
SIDE_4
SIDE_5
SIDE_6
SIDE_7
SIDE_8
SIDE_9
SIDE_10
NP_NC1
NP_NC2
C311
3.3PF/50V
/*12
U1
SN74LVC1G125DBVR/*
123
5
4
OE#AGND
Vcc
YL4480Ohmpt_l0603
21
C10
22UF/10VMLCC/+80%-20%pt_c1206_h71
12
Q1
FDC653N_NL
1256
3
4
C540
1UF/10V/X7Rpt_c0603 MLCC/+/-10%
/*
1 2
C20.1UF/10VMLCC/+80-20%
12
C5
10UF/10VMLCC/+/-20%pt_c0805_h57
12
C305
0.1UF/50VMLCC/+/-10%pt_c0603
12
DS
G1
2 3
Q70
SI2301BDS/*
1
2 3
C4
47PF/50VMLCC/+/-5%/*
12
R23
100KOhm5%
/*
12
R15 0Ohm 5%1 2
R8 0Ohm 5%1 2
C7
0.047UF/10VMLCC/+/-10%
12
C314
3.3PF/50V
/*12
R551 0Ohm 5%1 2
C11
8.2PF/50V/*
12
C315
3.3PF/50V
/*12
C6
0.1UF/16VMLCC/+/-10%
12
R50Ohm5% /*
12
R1 0Ohm 5%1 2
GS
D3
2
1Q4
2N7002
D1
RB751S40T1G
21
GS
D3
2
1Q48
2N7002
C312
0.1UF/10VMLCC/+/-10%
12
C3
47PF/50VMLCC/+/-5%/*
12
R16 0Ohm 5%1 2
R40Ohm5% /*
12
R31410KOhm5%/*
12
T1351
R26 0Ohm 5%/* 1 2
R20
47KOhm5%
/*
12
C307
3.3PF/50V
/*12
R1
R2
ECB
1
2
3
Q71DTC114EKA/*
C1
0.1UF/10VMLCC/+80-20%
12
GS
D3
2
1
Q32N7002
L1
90OHM/100MHz/*MURATA/DLW21SN900SQ2L
14
23
R2 0Ohm 5%1 2
R7 0Ohm 5%1 2
R313
100KOhm5%
12
R540
10KOhm/*
12
C310
2.2UF/25Vpt_c0805_h53
12
R17150Ohmpt_r0603_h225%
12
C54333PF/50VMLCC/+/-5%/*
12
D2
RB751S40T1G
21
R312
100KOhm5%1
2
R24
330KOhm5%1
2
C5391UF/10V/X7R
pt_c0603MLCC/+/-10%/*
12
C16
8.2PF/50V/*
12
R3 0Ohm 5%1 2
R6
10KOhm5%
/*1
2
R1
R2E
CB
1
2
3Q2
DDTC124EUA-7-F
C308
3.3PF/50V
/*12
C309
0.1UF/50VMLCC/+/-10%pt_c0603
12
C15
0.01UF/25VMLCC/+/-10%
12
R55247Ohm5%
1 2
R35
47KOhm5%1
2
L2
600Ohm Irat=200mA
21
R5390Ohmpt_r06031 2
C316
3.3PF/50V
/*12
C30610UF/10V
pt_c0805_h53MLCC/+80-20%
12
Q49
FDC658P_NL
1234 5 6
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
SATA Connector ODD Connector
Place caps close toconnector.
Place caps close toconnector.
PDIAG#
DASP#
SATA(HDD & CD_ROM)1.2Lanai <OrgName>31 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
SATA_RXN0_CSATA_RXP0_C
SATA_RXP0_CSATA_RXN0_C
HDD_EN_5V
IDE_DCS3#
IDE_DIOR#
IDE_DDACK#
IDE_DDREQIDE_DIOW#
IDE_DCS1#
IDE_DA1IDE_DA0
IDE_IRQ
IDE_DIORDY
IDE_DA2
IDE_DD[0:15]
IDE_DDACK#
IDE_DCS3#IDE_DA2
IDE_DDREQ
IDE_DD8
IDE_DD13
IDE_DD9
IDE_DD15
IDE_DIOR#
IDE_DD11IDE_DD10
IDE_DD14
IDE_DD12
IDE_DD0
IDE_DD5
IDE_DD1
IDE_DD6
IDE_DD4
IDE_DD7
IDE_DIORDYIDE_DIOW#
CSEL2
IDE_DD3
IDE_DA1
IDE_DCS1#IDE_DA0
IDE_IRQ
IDE_DD2
SATA_TX0- 15SATA_TX0+ 15
SATA_RX0- 15SATA_RX0+ 15
HDDC_EN38
IDE_DCS1#15
IDE_DDREQ15
IDE_IRQ15
IDE_DCS3#15
IDE_DDACK#15
IDE_DA115
IDE_DIOW#15
IDE_DA215
IDE_DA015
IDE_DD[0:15]15
IDE_DIOR#15IDE_DIORDY15
IDE_RST_MOD17
MODC_EN38
+5V_HDD
+5V_HDD
+3.3V_RUN
+5V_ALW+5V_HDD
+15V_ALW
+5V_RUN
+5V_MOD
+3.3V_RUN+3.3V_RUN
+5V_MOD
+5V_MOD
+5V_MOD
+5V_ALW2
+15V_ALW
+5V_RUN+5V_ALW
+5V_MOD
+5V_ALW2
C26
0
0.1U
F/10
V/Y
5V
MLC
C/+
80-2
0%1
2
GS
D3
2
1Q12
2N7002
R256
0Ohmpt_r0805_h24
/*
1 2
R58100KOhm
5%
12
C26
8
0.1U
F/10
V/Y
5V
MLC
C/+
80-2
0%1
2
R249100KOhm5%
12
R46
100KOhm 5%12
C58
0.1UF/10V/Y5V
MLCC/+80-20%
/* 12
R263
8.2KOhm 5%
12
R51100KOhm
5%
12
C3183900PF/50V/X7RMLCC/+/-10% 12
C46
1000PF/50V
MLCC/+/-10%
/*12
C23
11U
F/16
V/X5
Rpt
_c06
03
MLC
C+/
-10%
12
C24
0
0.1U
F/25
Vpt
_c06
03
MLC
C/+
/-10%
12G
S
D3
2
1Q44
2N7002
R2704.7KOhm 5%
12
C26
6
10U
F/10
V/X5
R
MLC
C/+
/-20%
pt_c
0805
_h57
12
R48100KOhm
5%
12
CON12
SATA_CON_22PFOXCONN/LD2822H-SA3L6
1234567
8910111213141516171819202122
24
23
26
25 1234567
89
10111213141516171819202122
NP_NC2
NP_NC1
NP_NC4
NP_NC3
GS
D3
2
1Q43
2N7002
C57
10U
F/10
V/X5
R
MLC
C/+
/-20%
pt_c
0805
_h57
12
R244
470Ohm 5%
12
C3193900PF/50V/X7RMLCC/+/-10% 12
C25
4
10U
F/10
V/X
5R
MLC
C/+
/-20%
pt_c
0805
_h57
12
R28556Ohm 5%12
R26922Ohm
1 2
R241
100KOhm 5%
12
R248100KOhm
5%1
2
CON19
BtoB_CON_50P
SUYIN/800194MR050S520ZL
5152
5354
13579
1113151719212325272931333537394143454749
2468101214161820222426283032343638404244464850N
P_N
C1
NP_
NC
2
NP_
NC
3N
P_N
C41
35791113151719212325272931333537394143454749
2468
101214161820222426283032343638404244464850
GS
D3
2
1Q11
2N7002
R50
0Ohmpt_r0805_h24
/*1 2
C26
7
0.01
UF/
25V/
X7R
MLC
C/+
/-10%
12
SD
G
Q9
SI3456BDV-T1-E3
123
56
4
SD
G
Q41
SI4800BDY
123
5678
4
C45
0.1U
F/25
Vpt
_c06
03
MLC
C/+
/-10%
12
R254
100KOhm5%/*1
2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
Place these caps as close aspossible to the device pins.
Pull-upresistors to+3.3V_RUN arerequired onthe ICHschematics.
Route to CLK GEN .
Reserve for EMI
The ICH schematics need toinclude a pull-up resistorto implement CLKRUN#, andthe ICH schematics musthave a pull-down, orconstantly drive thesignal low, in order todisable CLKRUN#.
Pull-up to+3.3V_ALWis required onSYS_PME#on SIOschematics.(From SIO).0 ohm of PME#is no-stuffto preventbackdrivefrom thissignalsince thecontrolleris powered oftheRUN rail
Ricoh R5C832 Package Type : TQFP-128-P1 (1414)
Pull-up resistorsto +3.3V_RUN arerequired on the ICHschematics.
Memory Stick Enable
XD Card Enable
Serial ROM disable
SD Card EnableMMC Card Enable
1394 : INTA#
4in1 : INTB#
No.24
R5C833 - PCI INTERFACE1.2Lanai <OrgName>32 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
PCI_AD17
PCI_AD1
PCI_AD14
PCI_AD29
PCI_AD20
PCI_AD22
PCI_AD4
PCI_AD28
PCI_AD5
PCI_AD9
PCI_AD6
PCI_AD10
PCI_AD27
PCI_AD25
PCI_AD11
PCI_AD26
PCI_AD18
PCI_AD23
PCI_AD16
PCI_AD7
PCI_AD24
PCI_AD0
PCI_AD3
PCI_AD15
PCI_AD12
PCI_AD21
PCI_AD19
PCI_AD17
PCI_AD8
PCI_AD13
PCI_AD2
PCI_AD30PCI_AD31
R5C832_IDSEL
PCI_GNT1#16PCI_REQ1#16
PCI_PAR16
PCI_C_BE0#16
PCI_TRDY#16
PCI_SERR#16
CLK_PCI_PCCARD21
PCI_C_BE1#16
PCI_IRDY#16
PCI_PERR#16PCI_PIRQC# 16
PCI_RST#16
CLKRUN#17,37
PCI_C_BE2#16
PCI_STOP#16 PCI_PIRQD# 16
IRQ_SERIRQ 17,37
SYS_PME#38
PCI_C_BE3#16
PCI_FRAME#16
PCI_DEVSEL#16
PCI_AD[0..31]16
PCI_AD1716
+3.3V_R5C832
+3.3V_R5C832
+3.3V_R5C832
+3.3V_R5C832
+3.3V_R5C832
+3.3V_R5C832
+3.3V_R5C832
+3.3V_R5C832+3.3V_RUN
R21110Ohm5%/*
12 R487
100KOhm5%
12
C2040.01UF/16VMLCC/+/-10%
12
R238
100KOhm5%
12
C239
0.47UF/10VMLCC/+/-10%pt_c0603
12
C25510UF/10V
pt_c0805_h53MLCC/+80-20%
12
C2110.01UF/16VMLCC/+/-10%
12
R48810KOhm5%
12
R247 0Ohm 5% pt_r06031 2
C2230.01UF/16VMLCC/+/-10%
12
C2080.01UF/16VMLCC/+/-10%
12
R239 10KOhm 5%1 2
C25810UF/10V
pt_c0805_h53MLCC/+80-20%
12
C2381UF/10V/X7R
pt_c0603MLCC/+/-10%
12
C2070.01UF/16VMLCC/+/-10%
12
C2050.01UF/16VMLCC/+/-10%
12
PCI / OTHER
U31B
R5C833_TQFP128C.S R5C833 TQFP128
57
72
67
115
70
453521
7
535251504948474644
694342403938373619181715141211
965321
127126125
4
1020
16
33
124123
3130292625
8
2423
117
119
121
71
132228
34
86
116
5965
99
103102
61
66
60
56
58
55
273241
128
64114120
54626368118122
107111
UDIO5
UDIO0/SRIRQ#
VCC_3V
INTA#
PME#
C/BE0#C/BE1#C/BE2#C/BE3#
AD0AD1AD2AD3AD4AD5AD6AD7AD8
HWSPND#AD9AD10AD11AD12AD13AD14AD15AD16AD17AD18AD19AD20AD21AD22AD23AD24AD25AD26AD27AD28AD29AD30AD31
GND1
VCC_PCI3V_1VCC_PCI3V_2
VCC_ROUT1
PAR
REQ#GNT#
SERR#PERR#STOP#DEVSEL#TRDY#
IDSEL
IRDY#FRAME#
CLKRUN#
PCIRST#
PCICLK
GBRST#
GND2GND3GND4
VCC_ROUT2
VCC_MD
INTB#
UDIO4UDIO3
AGND1
AGND2AGND3
VCC_RIN
TEST
UDIO1
UDIO2
MSEN
XDEN
VCC_PCI3V_3VCC_PCI3V_4VCC_PCI3V_5VCC_PCI3V_6
VCC_ROUT3VCC_ROUT4VCC_ROUT5
GND5GND6GND7GND8GND9
GND10
AGND4AGND5
C2060.01UF/16VMLCC/+/-10%
12
C222
0.47UF/10VMLCC/+/-10%pt_c0603
12
C20310UF/10V
pt_c0805_h53MLCC/+80-20%
12
R486 0Ohm 5% /*1 2
R225
10KOhm5%/*
12
C2590.01UF/16VMLCC/+/-10%
12
C22110PF/50V
/*MLCC/+/-0.5PF
12
R236 100KOhm 5%12
C2160.01UF/16VMLCC/+/-10%
12
C2450.01UF/16VMLCC/+/-10%
12
R207 100Ohm 5%1 2
R222 0Ohm 5%1 2
T1291
C244
0.1UF/10VMLCC/+80-20%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
Recommended Crystal Specs from Data Sheet:
Normal Frequency : 24.576 MHzFrequency Tolerance : +/- 50ppm @ 25CDriver Level : .1 mWLoad capacitance : 10pFEqu. Resistance : 50 Ohm MaxShunt Capacitance : 7.0pF Max
Place as close toR5C832 as possible.
Place these components close tothe flash memory card connector
For SD/MS Card Power
R5C832 : 0.01uF => stuffR5C833 : 0.01uF => No stuff
No.24
No.24
No.25
No.24
No.47
No.51
R5C833 - FLASH MEMORY PART1.2Lanai <OrgName>33 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
RICHO_FILO
RICHO_REXT
RICHO_VREF
TPBIAS0
TPB0N
TPB0P
TPA0N
TPA0P
SD_CD#
MS_INS#
SD/XD/MS_DATA2
XD_CLE
XD_CE#
SD/XD/MS_DATA0
SD_WP#(XDR/B#)
SD/XD/MS_DATA1
XD_DATA4
SD/XD/MS_DATA3
XD_DATA5
XD_WP#
XD_DATA7
XD_DATA6
SD/XD/MS_CMD
XD_ALE
MC_PWR_CTRL_0
MS_LED#
1394_XI
1394_XO
SD/XD/MS_CLK
XD_CDSW#
MC_PWR_CTRL_0
XD_CLE
XD_DATA6
SD/XD/MS_DATA3
SD/XD/MS_CMD
SD/XD/MS_DATA1
XD_WP#
SD/XD/MS_DATA2
SD/XD/MS_CLK
SD/XD/MS_DATA3
XD_DATA5
SD_CD#
SD/XD/MS_DATA3SD/XD/MS_CMD
SD/XD/MS_CLK
SD/XD/MS_CMD
SD_WP#(XDR/B#)
SD/XD/MS_DATA0
SD/XD/MS_DATA0
XD_ALE
SD/XD/MS_CLK
XD_DATA7
SD/XD/MS_DATA0
SD/XD/MS_DATA1
SD/XD/MS_DATA2
XD_CE#
SD/XD/MS_DATA1
SD/XD/MS_DATA2
XD_DATA4
XD_CDSW#
MS_INS#
SD_WP#
XD_CDSW#
SD_WP#(XDR/B#)
TPB0N 34
TPA0N 34
TPB0P 34
TPA0P 34
TPBIAS0 34
+3.3V_RUN_PHY
+3.3V_RUN_CARD
+3.3V_R5C832 +3.3V_RUN_CARD
+3.3V_RUN_CARD
+3.3V_RUN_CARD
C256 0.01UF/16V MLCC/+/-10% /*
12
C481
0.1UF/10VMLCC/+80-20%
12
R484 0Ohm 5%1 2
R456150KOhm5%
12
R474 10KOhm 1%
1 2
C478
15PF/50VMLCC/+/-5%
12
12
X5
24.576Mhz+/-50ppm/10PF
C472
1UF/10VMLCC/+80%-20%pt_c0603
12
C243 0.01UF/16V MLCC/+/-10%
12
C552
10PF/50VMLCC/+/-0.5PF
12
C4572.2UF/16VMLCC/+/-10%pt_c0603
12
U33
TPS2051BDBVR
1
234
5
OUT
GNDOC#EN
IN
T130TPC26T 1
IEEE1394/SD
U31A
R5C833_TQFP128C.S R5C833 TQFP128
98106110
113
104
105
108
109
94
95
96
101
100
80
90
77
76
75
74
73
88
84
82
81
93
79
78
91
89
92
87
85
83
112
97
AVCC_PHY3V_1AVCC_PHY3V_2AVCC_PHY3V_3
TPBIAS0
TPBN0
TPBP0
TPAN0
TPAP0
XI
XO
FIL0
REXT
VREF
MDIO00
MDIO13
MDIO03
MDIO04
MDIO05
MDIO06
MDIO07
MDIO08
MDIO09
MDIO10
MDIO11
MDIO12
MDIO01
MDIO02
MDIO14
MDIO15
MDIO16
MDIO17
MDIO18
MDIO19
AVCC_PHY3V_4
RSV
D20 1N4148W-7-F1 2
C4610.01UF/16VMLCC/+/-10%
12
C477
15PF/50VMLCC/+/-5%
12
GS D32
1
Q722N7002
D21 1N4148W-7-F1 2
CON20
CARD_READER_41P
TAISOL/144-2420000900
403938
23
37363431
3327
2
35
314
29
16
41 18
25
20
21
22
19
24
17
26
13
28
15
30
12
32
1197654
108
1
44 4542 43
XD_1(CD)XD_2(R/-B)XD_3(-RE)
XD_9(GND)
XD_4(-CE)XD_5(CLE)XD_6(ALE)XD_7(-WE)
SD_1(DAT3)XD_8(-WP)
SD(CD1)
SD_9(DAT2)
SD(WP1)MS_1(VSS)
SD_2(CMD)
MS_2(BS)
XD_0(GND) MS_3(DATA1)
SD_3(VSS)
MS_4(DATA0)
SD_4(VDD)
MS_5(DATA2)
XD_10(D0)
MS_6(INS)
SD_5(CLK)
MS_7(DATA3)
SD_6(VSS)
MS_8(SCLK)
XD_11(D1)
MS_9(VCC)
XD_12(D2)
MS_10(VSS)
XD_13(D3)XD_14(D4)XD_15(D5)XD_16(D6)XD_17(D7)XD_18(VCC)
SD_7(DAT0)SD_8(DAT1)
SD(CD2/WP2/GND)
P_G
ND
1P_
GN
D2
NP_
NC
1N
P_N
C2
R483 0Ohm 5%1 2
C4580.01UF/16VMLCC/+/-10%
12
C4590.01UF/16VMLCC/+/-10%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
Place these caps as close to the R5C832 as possible.
Place as close as possible to 1394 connector.Also, place 0 ohm close to thechokes to minimize stubs
Common mode chokes shouldbe 110- ohms impedance.Theyare reserved for EMI
1394 pairs should berouted as 110-ohmdifferential
Place as close as possible to R5C832
R5C833 - IEEE1394 PART1.2Lanai <OrgName>34 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
LTPA0+
TPA0PTPA0N
TPBIAS0
TPB0NTPB0P
1394_TPB1_R
LTPA0-
LTPB0+
LTPB0-
TPBIAS0 33TPA0P 33TPA0N 33TPB0P 33TPB0N 33
+3.3V_RUN_PHY +3.3V_R5C832
R459 56Ohm 1%12
R45456Ohm1%
12
R371 0Ohm 5%1 2
R377 0Ohm 5%1 2
R378 0Ohm 5%1 2
C2350.01UF/16VMLCC/+/-10%
12
C4530.33UF/25VMLCC/+80%-20%pt_c0603
12
TPXB1-
TPXB1+
TPXA1-
TPXA1+
SIDE_G1
SIDE_G2
CON13
IEEE_1394_CON_4P
FOXCONN/UV31413-WR56P-7F
1
32
4
56
L18
600Ohm/100MHzMURATA/BLM15HD601SN1D
Irat=0.3A
21
R375 0Ohm 5%1 2
L32
120OHM/*MURATA/DLW21HN121SQ2L
14
23 C464
270PF/50V MLCC/+/-10%
12
C25710UF/10V
pt_c0805_h53MLCC/+80-20%
12
C456
0.01UF/16VMLCC/+/-10%
12L31
120OHM/*MURATA/DLW21HN121SQ2L
14
23
R45556Ohm1%
12
R470 56Ohm 1%12
C2301000PF/50VMLCC/+/-10%pt_c0603
12
R458 5.1kOhm 1%1 2
C233
0.1UF/10VMLCC/+80-20%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PCI-Express TX and RX direct to connector .
Express Card
Please the capnear connector.
Please the capnear connector.
Please the capnear pin 12 &14 (1.5VIN).
Please the capnear pin 2 & 4(3.3VIN).
Please the capnear pin 17(AUXIN).
Please the capnear pin 15(AUXOUT).
Please the capnear pin 11 &13 (1.5VOUT).
Please the capnear pin 3 & 5(3.3VOUT).
+1.5V_CARD Max. 650mA, Average 500mA.+3V_CARD Max. 1300mA, Average 1000mA.
PCI-Express Card1.2Lanai <OrgName>35 68
Monday, March 19, 2007
Terry_LinPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
USBP6_D-
CPUSB#
CARD_RESET#
EXPRCRD_PWREN#
USBP6_D+
USBP6_D+
USBP6_D-
EXPRCRD_PWREN#CPUSB#
CARD_RESET#
CLK_PCIE_EXPCARD21CLK_PCIE_EXPCARD#21
CARD_CLK_REQ#21
PCIE_WAKE#38,47,50
PCIE_RX4-16
PCIE_TX4-16
PCIE_RX4+16
PCIE_TX4+16
EXPRCRD_PWREN#38
ICH_USBP6+16
ICH_USBP6-16
ICH_SMBCLK17,50ICH_SMBDATA17,50
EXPRCRD_STDBY#38PLTRST#10,16,37
+3.3V_CARD
+1.5V_CARD
+3.3V_CARDAUX
+1.5V_CARD
+3.3V_CARD
+1.5V_RUN +3.3V_RUN +3.3V_SUS +3.3V_CARDAUX +1.5V_CARD+3.3V_CARD
+3.3V_SUS+3.3V_RUN+1.5V_RUN +3.3V_CARDAUX +1.5V_CARD+3.3V_CARD
+3.3V_SUS
+3.3V_SUS R438 100KOhm 5%1 2
U28
R5538D001_TR_F
14
15
4 5
7
81
2
18
13
3
610
17
16
12
19
20
11
9
21
1.5VIN_1
AUX_OUT
3.3VIN_2 3.3VOUT_2
GND1
PERST#STBY#
3.3VIN_1
RCLKEN
1.5VOUT_2
3.3VOUT_1
SYSRST#CPPE#
AUX_IN
NC
1.5VIN_2
OC#
SHDN#
1.5VOUT_1
CPUSB#
GND2
R417 100KOhm 5%12
C4320.1UF/10VMLCC/+80-20%
12
C4440.1UF/10VMLCC/+80-20%
12
R412 0Ohm 5%1 2
R418 100KOhm 5%12C4460.1UF/10VMLCC/+80-20%
12
C44810UF/10V
pt_c0805_h53MLCC/+80-20%
12
R404 0Ohm 5%1 2 C440
0.1UF/10VMLCC/+80-20%
12
C4410.1UF/10VMLCC/+80-20%
12
R433 0Ohm 5% /*1 2
C4310.1UF/10VMLCC/+80-20%
12
C4370.1UF/10VMLCC/+80-20%
12
C4380.1UF/10VMLCC/+80-20%
12
L33
90OHM/100MHz/*MURATA/DLW21SN900SQ2L
14
23
CON8
EXPRESS_CARD_26P
JAE/PX10ABSB00G-1
27
282625242322212019181716151413121110987654321 29
30
NP_NC1
NP_NC22625242322212019181716151413121110987654321 P_GND1
P_GND2
C4360.1UF/10VMLCC/+80-20%
12
C4490.1UF/10VMLCC/+80-20%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
MDC
Place these caps nearMDC module.
If MDC disable isn't required, connect ICH_A2_MDC_RST# directly to JMDC connector.
If platform requires MDC disable, populate this circuit.
Note: MDC DISABLE.
MDC CONN1.2Lanai <OrgName>36 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
ICH_AZ_MDC_SYNC
ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_BITCLKMDC_SDIN
MDC_SDINICH_AZ_MDC_BITCLK
ICH_AZ_MDC_RST1#
ICH_AZ_MDC_RST1#
ICH_AZ_MDC_SDOUT
ICH_AZ_MDC_SDOUT15
ICH_AZ_MDC_BITCLK 15
ICH_AZ_MDC_SYNC15
ICH_AZ_MDC_SDIN115
MDC_RST_DIS#43
ICH_AZ_MDC_RST#15
+3.3V_SUS
+3.3V_SUS
+5V_SUS
C23
74.
7UF/
10V
MLC
C/+
80-2
0%pt
_c08
05_h
53
12
R246
33Ohm 5%
1 2
R243
10Ohm
5%
/*1
2
CON18
MDC_CONN_12PTYCO/1-1775844-2
1 23 45 67 89 10
11 12
1314
1920
1516
1718
1 23 45 67 89 1011 12
GN
D1
GN
D2
NP_
NC
1N
P_N
C2
GN
D3
GN
D4
GN
D5
GN
D6
C251
10PF/50VMLCC/+/-0.5PF/*
12
GSD
3 2
1
Q42
BSS138/*
R245
0Ohm 5%
1 2
R232
10KOhm5%/*1
2
R240
100KOhm5%/*1
2
R251
10Ohm
5%
/*
12 C
248
0.1U
F/10
V
MLC
C/+
80-2
0%12
C247
10PF/50VMLCC/+/-0.5PF/*
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place close topin 58
Place these caps close to MEC5025
1 = Enabled.0 = Disabled
Flash Recovery
Low=Write Protected.
Flash WriteProtect bottom4K of internalbootblock flash
Place cap close to pin 121.
Populatefor flashcorruptionissue.
NoniAMT
NoniAMT
MLX_53398-0371
Pin 1
Pin 3
32KHz Clock
External Work Around Circuit.
For MEC5025 Rev. C : C4519= 22uF andpopulate workaround circuit.For MEC5025 Rev. D : C4519= 4.7uF anddepopulate workaround circuit.
Pin 5
Debug Serial PortFlash RecoveryPort.
Not Stuff 0 ohm when doingFlash recovery.
Pin 1
MLX_53398-0571
(GPIO4) (GPIO5) CHIPSETCHIPSET_ID1 CHIPSET_ID0 Common Boot block sequence------------------------------------------------------- 0 0 Intel-SR 0 1 ATI-RR 1 0 TBD 1 1 Parker(Intel/ATI)
No.18
No.25
No.33
No.36
MEC50251.2Lanai 37 68
Monday, March 19, 2007
STANLY_HSUPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
SNIFFER_GREEN#
LCD_SMBCLK
PBAT_SMBDAT
PBAT_SMBCLK
LCD_SMBDAT
FWP#
RUN_ONSUS_ON
MEC5025_XTAL2_R
VR_CAPALWON
INVERTER_CBL_DET#
SUS_ON
RUN_ON
DAT_KBDCLK_KBD
DAT_DOCKCLK_DOCK
LCD_CBL_DET8051_RX
DEBUG_ENABLE#
8051_TX
AC_OFF
DOCK_SMBDAT
DOCK_SMBCLK
3.3V_SUS_ON
DAT_DOCK
SIO_SPI_CS#
DOCK_SMBCLK
SNIFFER_GREEN#
CHIPSET_ID0
DEBUG_ENABLE#
SBAT_DH_SMBCLK
LCDVCC_TST_EN
MEC_VCC_PLLMEC5025_XTAL1
SFPI_EN
AUX_LCD_CBL_DET#INVERTER_CBL_DET#
SBAT_DH_SMBDAT
MEC5025_XOSEL
ICH_RSMRST#
SNIFFER_RTC_GPO
PBAT_SMBDAT
CLK_KBD
FWP#
PBAT_SMBCLK
SFPI_EN
INSTANT_ON_SW#
CLK_PCI_5025
LCD_CBL_DET
ALWON
MEC_AGND
MEC5025_XTAL2MEC5025_XTAL1
LOM_SMB_ALERT#
SIO_EXT_SCI#
AUX_ON
DOCK_SMB_ALERT#
MEC5025_VCC0
CLK_PCI_5025
LCD_SMBDAT
DAT_KBD
THRM_SMBCLK
AUX_LCD_CBL_DET#
AUX_EN_WOWL_1
8051_TX
CLK_DOCK
MEC_TEST_PIN
THRM_SMBCLK
LCD_SMBCLK
VR_CAP
SNIFFER_YELLOW#
SNIFFER_YELLOW#
DOCK_SMBDAT
8051_RX
THRM_SMBDAT
MEC5025_XTAL2
THRM_SMBDAT
SBAT_DH_SMBCLK
ICH_RSMRST#CHIPSET_ID0
BC_A_DAT
SBAT_DH_SMBDAT
LOM_SMB_ALERT#
DDR_ON
TP_DET#BC_DAT
SIO_SPI_CS#DOCK_SMB_ALERT#
CHIPSET_ID1
CHIPSET_ID1
PBAT_SMBCLK 57,59PBAT_SMBDAT 57,59
BAT2_LED# 42
RESET_OUT# 51
ALWON 54
MAIN_PWR_SW# 42ACAV_IN 43,57
SIO_SPI_CS# 16
SIO_EXT_SMI# 17
LCD_SMBDAT 28LCD_SMBCLK 28
1.8V_RUN_ON 49
THRM_SMBDAT 43
BREATH_LED# 42
0.9V_DDR_VTT_ON 58
BAT1_LED# 42
3.3V_RUN_ON49
DDR_ON58
SUS_ON49,51
EC_FLASH_SPI_DO40
SIO_SLP_S5#17
TP_DET#41
LPC_LAD115
LPC_LFRAME#15
SNIFFER_GREEN#42
LPC_LAD215
EC_FLASH_SPI_DIN40
SNIFFER_YELLOW#42
EC_FLASH_SPI_CLK40
SIO_SLP_S3#17
CLK_PCI_502521
BC_INT#38
LPC_LAD015
ICH_EC_SPI_CLK16
SIO_PWRBTN#17
BC_A_INT#41
ICH_EC_SPI_DO16
RUN_ON28,49,51,54
LPC_LAD315
PLTRST#10,16,35
ICH_EC_SPI_DIN16
BC_DAT38
SIO_A20GATE15
IMVP_VR_ON 53
THRM_SMBCLK 43
1.25V_RUN_ON 581.5V_RUN_ON 55
HOST_DEBUG_TX 50
FAN1_TACH 43
DAT_TP_SIO41CLK_TP_SIO41
INSTANT_POWER_SW# 41SNIFFER_PWR_SW# 42
8051_RX508051_TX50
SIO_RCIN# 15
HOST_DEBUG_RX 50
BC_CLK38
BC_A_CLK41BC_A_DAT41
CKG_SMBCLK21CKG_SMBDAT21
1.8V_SUS_PWRGD58
ICH_CL_PWROK10,17
CLKRUN#17,32IRQ_SERIRQ17,32
RUNPWROK 51,53
ICH_RSMRST#17
SIO_EXT_SCI# 17
INVERTER_CBL_DET# 28AUX_LCD_CBL_DET# 28
IMVP_PWRGD 17,51,53
AC_OFF59
LCD_CBL_DET_R28
LCDVCC_TST_EN 28
EC_CPU_PROCHOT#7
3.3V_SUS_ON 49
BEEP 44
LOM_SMB_ALERT# 17
PS_ID 59
ALW_PWRGD_3V_5V54
AUX_EN_WOWL 50
EC_32KHZ 38EC_PWM_2 54
+3.3V_ALW
+RTC_CELL
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
+5V_RUN
+3.3V_ALW
+RTC_CELL
+5V_ALW
+3.3V_ALW
R461
100KOhm5%
12
L35120Ohm/100Mhz
2 1
RN38B
4.7KOhm5%
pt_2r4p0402_h18
34
R392 10KOhm 5% /*1 2
R64
1MOhm5%
12
R416
10KOhm/*5%
12
L36120Ohm/100Mhz
21
R393 2.7KOhm5%1 2
R450
10Ohm/*5%
12
R553 100KOhm 5%1 2 R460
200KOhm5%
12
R464 1MOhm5%
12
R4670Ohm5%
12
R435 2.2KOhm
5%12
X4
32.768KHZ+/-10ppm/6PF
14
23
R388 8.2KOhm
5%12
KEYBOARD/MOUSE
PCI POWER/LPC BUS
HOST/8051 SPI
BC
CLOCK
POWER PLANES
MISCELLANEOUS
GPIO
ACCESS BUS
POWER SWITCH
POWER PLANES
U29
MEC5025-NU
121314151617181920232425272829303132
3334353637383940
9250
7576777879808182
575859606162636456
102105107
103106108
109110
878685
122
123124
22
125
104
101
121
21446583116
120119126127128118
5678
93949596111112910979899100
414243
45464748
665554696867
7071
9190894
1235211
1151148473117495372
11388745126
KSO17/GPIOA1/AB1H_DATAKSO16/GPIOA0/AB1H_CLKGPIO5/KSO15GPIO4/KSO14KSO13/GPIO18KSO12/OUT8KSO11/GPIOC7KSO10/GPIOC6KSO9/GPIOC5KSO8/GPIOC4KSO7/GPIO3KSO6/GPIO2KSO5/GPIO1KSO4/GPIO0KSO3/GPIOC3KSO2/GPIOC2KSO1/GPIOC1KSO0/GPIOC0
KSI7/GPIO19KSI6/GPIO17KSI5/GPIO10KSI4/GPIO9KSI3/GPIO8KSI2/GPIO7/BC_A_INT#KSI1/GPIO6/BC_A_DATKSI0/SGPIO30/BC_A_CLK
SGPIO34/A20MOUT5/KBRST
GPIO94/IMCLKGPIO95/IMDATKCLKKDATGPIOA6/EMCLKGPIOA7/EMDATGPIO20/PS2CLK/8051RXGPIO21/PS2DAT/8051TX
LRESET#PCICLKLFRAME#LAD0LAD1LAD2LAD3CLKRUN#SER_IRQ
HSTCLKHSTDATAINHSTDATAOUT
FLCLKFLDATAINFLDATAOUT
GPIO80GPIO81
BC_CLKBC_DATBC_INT#
XTAL1
XOSELXTAL2
VR_CAP
AGND
VCC_PLL
VSS_PLL
VCC0
VCC1_1VCC1_2VCC1_3VCC1_4VCC1_5
ALWONPOWER_SW_IN2#/GPIO23POWER_SW_IN1#/GPIO22
POWER_SW_IN0#ACAV_IN
BGPO0/GPIOA5
AB1A_DATAAB1A_CLK
AB1B_DATA/GPIOA2AB1B_CLK/GPIOA4
GPIO11/AB2_DATAGPIO12/AB2_CLK
GPIO13/AB1G_DATAGPIO14/AB1G_CLK
GPIO87/AB1C_DATAGPIO86/AB1C_CLK
GPIO85/AB1D_DATAGPIO84/AB1D_CLK
GPIO93/AB1F_DATAGPIO92/AB1F_CLK
GPIO91/AB1E_DATAGPIO90/AB1E_CLK
GPIO15/FAN_TACH1GPIO16/FAN_TACH2GPIO82/FAN_TACH3
OUT10/PWM0OUT11/PWM1OUT9/PWM2OUT2/PWM3
nEC_SCI/SPDIN2SGPIO45/MSDATA/SPDOUT2
SGPIO44/MSCLK/SPCLK2SGPIO46/SPDIN1
SGPIO47/SPDOUT1SGPIO31/TIN1/SPCLK1
SYSOPT0/SGPIO32/LPC_TXSYSOPT1/SGPIO33/LPC_RX
SGPIO40SGPIO41SGPIO42SGPIO43
SGPIO35SGPIO36(SFPI_EN)
SGPIO37GPIO96/TOUT1
OUT7/nSMI
nPWR_LEDnBAT_LED
nFWPGPIOA3/WINDMON
GPIO83/32KHZ_OUTPWRGD
nRESET_OUT/OUT6TEST_PIN
VSS1VSS2VSS3VSS4VSS5
RN39A4.7KOhm1 2
R387 8.2KOhm
5%12
R441
100KOhm5%/*
12
R411 0Ohm 5%1 2
RN38A
4.7KOhm5%
pt_2r4p0402_h18
12
R471 100KOhm5%1 2
R439
100KOhm/*5%
12R407 10KOhm 5%1 2
R465
100KOhm5%
12
R440 2.2KOhm
5%12
T127 TPC26T1
C447
4.7PF/50V/*MLCC/+/-0.25PF
12
R427 2.7KOhm5%
/*1 2
RN39C4.7KOhm5 6
R444
100KOhm5%/*
12
C4420.1UF/10VMLCC/+/-10%
12
R394 100KOhm 5%12
C463
10UF/6.3VMLCC/+/-20%pt_c0805_h53
12
R405 100KOhm 5%1 2
R402 8.2KOhm
5%12
R428
100KOhm5%
12
R426
0Ohm5%
12
R453
100KOhm/*5%
12
T40 TPC26T1
T128TPC26T 1
R452
100KOhm5%
12
C4430.1UF/10VMLCC/+/-10%
12
CON4
WTOB_CON_5P/*
12345
6
7
12345
SIDE1
SIDE2
R554 0Ohm 5% /*1 2
R430 0Ohm
5% pt_r06031 2
R434 100KOhm5% /*1 2
R408 100KOhm5%1 2
T125 TPC26T1
BC
E
1
2
3
Q56
PMBS3906/*
C4221UF/10V
pt_c0603MLCC/+/-10%
12
C433
15PF/50VMLCC/+/-5%
12
C434
12PF/50VMLCC/+/-5%
12
R391
1KOhm/*5%
12
T136 TPC26T1
T41 TPC26T1
R43110KOhm 5%
1 2
T116 TPC26T1
R73
10KOhm5%
12
HOLD1
HOLD2
CON2
WTOB_CON_3P/*1
23
45
R429 10KOhm5%
1 2
R409 2.7KOhm5%1 2
C4620.1UF/10VMLCC/+/-10%
12
C439
0.1UF/10VMLCC/+/-10%
12
R549 0Ohm 5%12
R390 0Ohm
/*5%12
R403 10KOhm 5%1 2
R445 0Ohm 5%12
R65
10KOhm5%
12
C4230.1UF/10VMLCC/+/-10%
12
T29 TPC26T1
R386
1KOhm5%
12
D18
RB500V-40/*
2 1
T34 TPC26T1
L37120Ohm/100Mhz
21
GS
D3
2
1
Q55
2N7002
/*
C4254.7UF/6.3V /*
MLCC/+/-10%pt_c060312
R466
100KOhm5%
12
RN39D4.7KOhm7 8
C419 4.7UF/10Vpt_c0805_h37 MLCC/+/-10%
12
R550 0Ohm 5%12
R389 10KOhm 5%1 2
R406 8.2KOhm
5%12
R410
10KOhm/*5%
12
T118TPC26T 1
R4322.2KOhm /*5%
12
C455
0.1UF/10VMLCC/+/-10%
12
T28TPC26T 1
T126TPC26T 1
R66 0Ohm
5%/*1 2
RN39B4.7KOhm3 4
R413
100KOhm/*5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Place these caps near ECE5011
VGA_IDENTIFY1 = Discrete Gfx.0 = UMA
Board ID Straps
UMA
Discrete
BID2 BID1 BID0 M08 M08B 0 0 0 ENG1(X00) ENG1(X00) 0 0 1 ENG2(X01) ENG2(X01) 0 1 0 ENG3(X02) ENG3(X02) 0 1 1 ENG4(X03) ENG4(X03) 1 0 0 QT(X04) QT(X04) 1 0 1 RAMP(A00) RAMP(A00) 1 1 0
24MHz Clock
Crystal and surroundingcomponents not needed unlessSIO USB Hub is utilized
Reserved for BroadcomLOM solution
R514 R479 , ECE5011 is suff ,ECE5021 is not stuff
R498 R493 R506, ECE5011 issuff , ECE5021 is not stuff
R504 R505 R463 , ECE5011 issuff , ECE5021 is not stuff
R462 R489 R480 , ECE5011 issuff , ECE5021 is not stuff
Note : for ECE5011 onlyECE5021 will be non_stuff
No.13
No.16
No.30
No.46
SUPER IO ECE50111.2Lanai 38 68
Monday, March 19, 2007STANLY_HSUPROJECT: SHEET OF
DATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :RELEASE DATE :
EC_VDDA
BID1BID0
BID2VGA_IDENTIFY
ECE5011_XTAL2_R
ECE5011_XTAL2
ECE5011_XTAL1
ECE5011_XTAL1_R
MODPRES#
SBAT_PRES#
SC_DET#DBAY_MODPRES#
PWRUSB_OC#
IMVP6_PROCHOT#
SBAT_PRES#
EC_VDDA
DOCKED
BID2
RSV_TEST_PIN
MODPRES#
DOCK_SMB_PME#
VGA_IDENTIFY
RBIAS
BID0
LOM_CABLE_DETECT
ECE5011_XTAL1
SYS_PME#
HP_NB_SENSE
SC_DET#LOM_LOW_PWR
PCIE_WAKE#
PWRUSB_OC#
BID1
ECE5011_XTAL2
DBAY_MODPRES#
EC_32KHZ
DOCKED
LOM_CABLE_DETECT
HP_NB_SENSELCD_TST
IMVP6_PROCHOT#
SYS_PME#PCIE_WAKE#
DOCK_SMB_PME#
PS_ID_DISABLE# 59
NB_MUTE# 45,46
LCD_TST28
FREE_CIRRX 41
LOM_LOW_PWR47
WIRELESS_ON/OFF# 42
EXPRCRD_PWREN#35
PANEL_BKEN 10
BC_INT# 37
PBAT_PRES#59
SIO_EXT_WAKE#17
ADAPT_OC 57
ICH_PCIE_WAKE#17WLAN_RADIO_DIS#50
EC_32KHZ37
HDDC_EN31
5V_3V_1.8V_1.25V_RUN_PWRGD51
BT_RADIO_DIS# 41WWAN_RADIO_DIS# 50
MODC_EN31
ICH_PME#16
BC_DAT 37
USB_BACK_EN#50
ADAPT_TRIP_SEL 57
LED_MASK#15,41
ATF_INT# 43
USB_SIDE_EN# 39
EXPRCRD_STDBY#35
PCIE_WAKE#35,47,50
BC_CLK 37
SYS_PME#32
IMVP6_PROCHOT#53
M_LED_BK# 42
XDP_DBRESET# 7,17,52
LID_CL_SIO# 421.05V_RUN_ON 55
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_RUN
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+5V_ALW
T53 1
T67 1
R477
10KOhm5%
12
T62 1
R4890Ohm
5%
/*
12
R4620Ohm
5%
/*
12
C509
4.7UF/6.3VMLCC/+/-10%pt_c0603/*
12
C524
0.1UF/10VMLCC/+/-10%
12
RN40A10kOhm 12
R481 10KOhm5%
1 2
T82 1
T74 1
T52 1
C486
0.1UF/10VMLCC/+80-20%/*
12
C5050.1UF/10VMLCC/+80-20%/*
12
R472
10KOhm5%
12
C470
0.1UF/10VMLCC/+80-20%
12
C492
0.1UF/10VMLCC/+/-10%
12
R512 100KOhm 5%1 2
R5060Ohm
5%
/*
12
R5050Ohm
5%
/*
12
T63 1
R4630Ohm
5%
/*
12
T681
R516 0Ohm5%
12
R4930Ohm
5%
/*
12
C487
0.1UF/10VMLCC/+/-10%
12
C497
0.1UF/10VMLCC/+/-10%
12
T51 1
R473
10KOhm/* 5%
12
RN40D10kOhm 78
R485
0Ohm 5%/*
12
R499 10KOhm 5%1 2
R482
1MOhm 5%
/*1 2
C501
0.1UF/10VMLCC/+/-10%
12
RN40C10kOhm 56
C468
0.1UF/10VMLCC/+/-10%
12
C479
0.1UF/10VMLCC/+/-10%
12
1 2X6
24Mhz/*
T771
C482
4.7UF/6.3VMLCC/+/-10%pt_c0603/*
12
R4800Ohm
5%
/*
12C476
30PF/50VMLCC/+/-5%/*
12
R500 100KOhm5%1 2
T47 1
C466
0.1UF/10VMLCC/+/-10%
12
R4980Ohm
5%
/*
12
R469
10KOhm5%
12
T70 1
U34
ECE5021-NU
12345
6
7
8
910
11
1213
14
1516
17
1819
20
2122
23
2425
2627
28293031
3233
34
35
36
37
38
39
40
4142
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
585960
6162
63
64
96
9594939291908988
87
86
85
8483
828180797877
7675
74
73
72
7170696867
6665
128
127126
125
124
123122
121
120
119
118117116115
114113
112111110109
108
107106
105
104103102101100999897
GPIOE[0]GPIOE[1]GPIOE[2]GPIOE[3]GPIOE[4]
GPIOE[7]
PWRGD_PS
VCC1_1
GPIOJ[2]GPIOJ[3]
GPIOJ[4]
GPIOJ[5]GPIOJ[6]
GPIOJ[7]
GPIOK[0]GPIOK[1]
VSS1
GPIOK[2]GPIOK[3]
GPIOK[4]
GPIOK[5]GPIOK[6]
GPIOK[7]
GPIOH[0]GPIOH[1]
GPIOH[4]GPIOH[5]
GPIOD[4]GPIOD[5]GPIOD[6]GPIOD[7]
GPIOH[6]GPIOH[7]
VCC1_2
TEST_PIN
VSS2
VSS7
VSS20
VSS9
VSS22
VSS14VCC1_6
VCC1_7
VSS15
VSS21
NC
VSS13
VSS19
VSS12
VSS18
VSS3
VSS11
VSS17
VSS10
VSS16
VSS8
VCC1_3
BC_INT#BC_DATBC_CLK
GPIOD[1]/CIRTXGPIOD[2]/CIRRX
GPIOD[3]
VSS23
KHz_32
GPIOG[7]GPIOG[6]GPIOG[5]GPIOG[4]GPIOG[3]GPIOG[2]GPIOG[1]GPIOG[0]
VSS5
CAP_LDO
VCC1_4
GPIOE[5]GPIOE[6]
GPIOB[2]GPIOB[3]GPIOB[4]GPIOB[5]GPIOB[6]GPIOB[7]
GPIOC[0]GPIOC[1]
GPIOD[0]
GPIOC[7]
VSS4
GPIOC[6]GPIOC[5]GPIOC[4]GPIOC[3]GPIOC[2]
GPIOB[1]GPIOB[0]
GPIOJ[1]
GPIOJ[0]GPIOI[7]
GPIOI[6]
GPIOI[5]
GPIOI[4]GPIOI[3]
VSS6
GPIOI[2]
GPIOI[1]
GPIOF[0]GPIOF[1]GPIOF[2]GPIOF[3]
CIRRXCIRTX
GPIOF[4]GPIOF[5]GPIOF[6]GPIOF[7]
VCC1_5
GPIOH[3]GPIOH[2]
OUT65
GPIOA[7]GPIOA[6]GPIOA[5]GPIOA[4]GPIOA[3]GPIOA[2]GPIOA[1]GPIOA[0]
C495
30PF/50VMLCC/+/-5%/*
12
R468
10KOhm5%
12
R522 100KOhm5%12
R545 10KOhm 5%1 2
R524 100KOhm 5%1 2
R515 10KOhm 5%1 2
R479 10KOhm 5%
/*
12
C467
0.1UF/10VMLCC/+/-10%
12
R476
10KOhm5%
/*
12
R475
10KOhm5%
12
T50 1
C474
4.7UF/6.3Vpt_c0603MLCC/+/-10%/*
12
R5040Ohm
5%
/*
12
T58 1
R494 100KOhm 5%1 2
R503 100KOhm 5%1 2
R513 10KOhm 5%1 2
R501 10KOhm 5%1 2
C5254.7UF/6.3VMLCC/+/-10%pt_c0603
12
L38180Ohm
BLM18PG181SN1pt_l0603
21
T83 1
RN40B10kOhm 34
C471
4.7UF/6.3Vpt_c0603MLCC/+/-10%
12
R478
10KOhm5%/*
12
C484
0.1UF/10VMLCC/+/-10%
12
R514 10KOhm 5%
/*
12
R523 10KOhm 5% /*1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
Each channel is 1A
Place one 150uF cap by eachUSB connector
USB daughter board connectorNo.55
USB PORT x 21.2Lanai <OrgName>39 68
Monday, March 19, 2007
Terry_LinPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
+USB_SIDE_PWR
+USB_SIDE_PWR
ICH_USBP1-ICH_USBP1+
ICH_USBP0-ICH_USBP0+
+USB_SIDE_PWR
USB_OC0_1# 16USB_SIDE_EN#38
ICH_USBP1-16ICH_USBP1+16
ICH_USBP0-16ICH_USBP0+16
+5V_ALW F1
1.6A/6VPOLYSWITCH SMD1812P160TF
/*
1 2
J1
2MM_OPEN_5mil
1 21 2
CON17
BTOB_CON_10P
SUYIN/127153MA010G521ZR
13579
246810
11
12
13579
2468
10
NP_NC1
NP_NC2
U27
TPS2062DR
12
3
456
87
GNDIN
EN1#
EN2#OC2#OUT2
OC1#OUT1
C41610UF/10VMLCC/+/-10%/*pt_c1206_h75
12
C417
0.1UF/10VMLCC/+/-10%
12
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
Layout Note:Place R449 within 500 mils fromSPI flash. Place R449 & R451within 500 mils of the MEC5025.
RTC BATTERY
Pin 3
MLX_53398-0371
Pin 1
FLASH & RTC1.2Lanai <OrgName>40 68
Monday, March 19, 2007
C.L. HoPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
SPI_SI
SPI_DO
SPI_CLK+RTC_1 +RTC
EC_FLASH_SPI_DIN37
EC_FLASH_SPI_CLK 37
SPI_CS0#16
EC_FLASH_SPI_DO 37
RTC_BAT_DET#15
+3.3V_SUS
+3.3V_RTC_LDO +PWR_SRC+RTC_CELL
R449 15Ohm1 2
C40
82.
2UF/
6.3V
/X5R
MLC
C/+
/-10%
pt_c
0603
12
HOLD1
HOLD2
CON16
WTOB_CON_3PMOLEX/53398-0371(P6497)
123
45
C460
0.1UF/10VMLCC/+80-20%
12
C41
1
1UF/
25V
pt_c
0805
_h57
MLC
C/+
/-10%
/*1
2
D19
RB751V_40
2 1
C42
1
1UF/
25V
pt_c
0805
_h57
MLC
C/+
/-10%1
2
D17
RB751V_40
2 1
U26
MAX1615EUK/*
123 4
5INGNDOUT 5/3#
SHDN#
U30
SST25VF016B
1234 5
678CE#
SOWP#VSS SI
SCKHOLD#
VDD
R451 15Ohm1 2
R457
10KOhm5%
12
R437
10KOhm5%
12
R4211KOhm5%
12R447 15Ohm5%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Lid Switch(Hall) BIO
Touch Pad
Please refer to item 191 of issue_list_0517_TDC ,"Lanai plan to use 3V TP controller. No needTP_VCC " . So we delete this circuit whichsupply TP_VCC power.
Bluetooth
This circuit is only needed ifthe platform has the SNIFFER.
CIR
Vendor suggest :Pin 7 of RC-Rxd isopen collectoroutput.it should beadd external pullupresister
HALL SENSOR
No.17
No.17
No.20
No.22 No.42
TOUCH PAD & BT & CIR & LID1.2Lanai <OrgName>41 68
Monday, March 19, 2007PROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
BT_ACTIVE
+3.3V_CIR
POWER_SW#42,43INSTANT_POWER_SW#37
BC_A_CLK37
BC_A_DAT37
BC_A_INT#37
CLK_TP_SIO37DAT_TP_SIO37
TP_DET#37
LED_MASK# 15,38
BT_RADIO_DIS#38
BT_ACTIVE#_R 42
COEX2_WLAN_ACTIVE 50COEX1_BT_ACTIVE 50
ICH_USBP7+16ICH_USBP7- 16
FREE_CIRRX38
MEDIA_LED_R42
LID_CL#42
+3.3V_ALW +5V_ALW
+3.3V_ALW+5V_ALW
+3.3V_ALW
+3.3V_RUN
+3.3V_RUN +3.3V_ALW
+3.3V_RUN
+3.3V_ALW
R301 100Ohm 5%1 2
C1120.1UF/10V
MLCC/+80-20%
12
BC
E
1
2
3
Q63MMBT3906LT1G
C54
922
PF/5
0VM
LCC
/+/-5
%/*
12
R2960Ohm5%/*
12
L15 600Ohm Irat=200mA pt_l06032 1
C54
822
PF/5
0VM
LCC
/+/-5
%/*
12
C114
0.1UF/10VMLCC/+/-10%
12
C54
522
PF/5
0VM
LCC
/+/-5
%1
2
CON5
WTOB_CON_15PMOLEX/48227-1511
1617
123456789
101112131415
SID
E1SI
DE2
123456789101112131415
C54
722
PF/5
0VM
LCC
/+/-5
%/*
12
R528 10KOhm 5%12
C5360.1UF/16VMLCC/+/-10%
12
C54
622
PF/5
0VM
LCC
/+/-5
%1
2
CON21
WTOB_CON_10PMOLEX/48226-1011
13579
246810
1112
13579
2468
10
SID
E1SI
DE2
GS
D3
2
1Q62
BSS138N
R52610KOhm5%
12
RN
15B
4.7K
Ohm
34
CN
2B10
PF/5
0V3
4
T132 1
C523100PF/50VMLCC/+/-5%
12
R52710KOhm5%
12
C55
122
PF/5
0VM
LCC
/+/-5
%/*
12
L12 600Ohm Irat=200mA pt_l06032 1
C51833PF/50VMLCC/+/-5%
12
CN
2A10
PF/5
0V1
2
R3000Ohm5%
12
R534
10KOhm5%/*1
2
U39
TSOP36136TR
1234
GND1GND2VSOUT
CN
2D10
PF/5
0V
pt_c
_arra
y_8p
_79x
49_h
39
78
C3024.7UF/10VMLCC/+/-10%pt_c1206_h71
12
RN
15A
4.7K
Ohm
12
C54
422
PF/5
0VM
LCC
/+/-5
%1
2
C5120.1UF/10VMLCC/+80-20%
12
CN
2C10
PF/5
0V5
6
C55
022
PF/5
0VM
LCC
/+/-5
%/*
12
CON6
WTOB_CON_3P
MOLEX/48227-03111
2
3
4
5
1
2
3
SIDE1
SIDE2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
HDD activity LED
Power&Suspend
BT activity LED
Battery status
WLAN
Sniffer Switch
Sniffer LED driver circuit
Package 0603
Layout Note: C pad is usedas a Provision For ExternalPower Cycling, Must place Con top to be accessed whenKeyboard is removed.
Hall Switch
Media Bottom Board LED drive circuit
No.13 No.35
No.8
No.39
No.53
No.53
SWITCH & LED1.2Lanai <OrgName>42 68
Monday, March 19, 2007
CPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
BREATH_PWRLED
HDD_LED#
BT_LED#
BAT1_LED_BLUE#
LED_WLAN_OUT_R#
LED_WLAN_OUT_R
BREATH_PWRLED#
SNIFFER1
SNIFFER2
SNIFFER_G_R
SNIFFER_Y_R
SNIFFER_Y_R SNIFFER_G_R
SNIFFER2
HDD_LED
BT_LED
LED_WLAN_OUT_R#
BT_LED#
BREATH_PWRLED#
HDD_LED#
BAT2_LED
BAT1_LED_BLUE#
BAT2_LED
POWER_SW#
BAT1_LED
SNIFFER1
M_LED_BK#
MEDIA_LED_O
BREATH_LED#37
BAT1_LED#37
SATA_ACT#_R15
BT_ACTIVE#_R41
BAT2_LED#37
LED_WLAN_OUT#50
SNIFFER_Y_R
SNIFFER_G_R
SNIFFER_GREEN# 37SNIFFER_YELLOW# 37
SNIFFER_G_RSNIFFER_Y_R
WIRELESS_ON/OFF#38
SNIFFER_PWR_SW#37
MAIN_PWR_SW#37 POWER_SW# 41,43
LID_CL# 41LID_CL_SIO#38
MEDIA_LED_R 41
M_LED_BK#38
+3.3V_ALW
+3.3V_RUN
+3.3V_SUS
+3.3V_RUN
+3.3V_ALW
+3.3V_WLAN
+3.3V_SUS+3.3V_SUS
+RTC_CELL
+5V_SUS
+5V_RUN
+5V_RUN
+5V_RUN
+5V_ALW
+RTC_CELL
+3.3V_ALW
+3.3V_RUN
+3.3V_RUN
+5V_RUN
R304220Ohm
5%
12
R166100KOhm/*
5%
12
NCA
GNDY
VCC
U17
74AHC1G04GW
123 4
5
+
LED4 BLUELITE-ON/LTST-C192TBKT-5A
12
R529 220Ohm
pt_r0603
5%1 2
+
LED2 BLUELITE-ON/LTST-C192TBKT-5A
12
+
LED5 BLUELITE-ON/LTST-C192TBKT-5A
12
R305 750Ohm 5%12
R415 0Ohm 5%12
R541
10KOhm5%
12
R1
R2E
CB
1
2
3Q64
DTC114EKA
R1
R2
IN
GND
OUT
Q47
DDTA114YUA_7_F
1
32
R1
R2E
CB
1
2
3Q39
DTC114EKAR1
R2E
CB
1
2
3Q68
DTC114EKA
R533100KOhm
pt_r06035%
12
C5371UF/10V
pt_c0603MLCC/+/-10%
12
SG
Y
LED6
G&Y
13
2
C4151UF/10V
pt_c0603MLCC/+/-10%
12
R1
R2E
CB
1
2
3Q29
DTC114EKA
R401100KOhm 5%
12
BC
E
1
2
3
Q27
MMBT3906LT1G
+
LED3 BLUELITE-ON/LTST-C192TBKT-5A
12
R425100KOhm 5%
12
C1410.047UF/10VMLCC/+/-10%
12
C4301UF/10V
MLCC/+/-10%pt_c0603/*
12
C4131UF/10V
MLCC/+/-10%/*pt_c0603
12
R1
R2
IN
GND
OUT
Q66
DDTA114YUA_7_F
1
32
R175 0Ohm
pt_r0603
5%12
R385 10KOhm5%1 2
R298
750Ohm5%
12
R134100KOhm5%
12
R302 750Ohm 5%12
R1
R2
IN
GND
OUT
Q67
DDTA114YUA_7_F
1
32
++
Blue
Orange
LED1
BLUE&ORANGE
12
34
R546
0Ohmpt_r0805_h24
5%
12
C5341UF/10V
MLCC/+/-10%pt_c0603/*
12
R1
R2
IN
GND
OUT
Q46
DDTA114YUA_7_F
1
32
R1
R2
IN
GND
OUT
Q57
DDTA114YUA_7_F
1 32
R1
R2
IN
GND
OUT
Q38
DDTA114YUA_7_F
1
32
CON22
SLIDE_SWITCH_4PFOXCONN/1BS008-13130-042-7F
1234
5
6
78
1234
GND1
GND2
NP_NC1NP_NC2
R303 750Ohm 5%12
R297 10KOhm5%1 2
R531 0Ohm 5%12
R299 750Ohm 5%12
R542
10KOhm 5%
12
R532 220Ohm
pt_r0603
5%1 2
R135 10Ohm5%1 2
BC
E
1
2
3Q69
PMBS3904
R1
R2
IN
GND
OUT
Q65
DDTA114YUA_7_F
1
32
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
This Value of R150 canbe 0.27 or 0 ohm and thepackage is 1210
Voltage marginingcircuit for LDO output.For Vmargin stuff R379and R373=30K. R373=1Kfor production.
Note:VSET = (Tp-70)/21, where Tp = 70to 101 degree C. Tp set at 88 degrees C. Guardian temp tolerance = +-3degrees C.
C161 needs to be placed nearGuardian IC.
C160 needs to be placed nearGuardian IC.
Put C196 close toGuardian.
Layout Note:Place those capacitors close toEMC4001.
0603Package.
Guardian Note:150K input impedance on VCP1 (Pin 43)
Put C195 close to Guardian.Put C389 close Diode
Place under CPU.
Layout Note:R177 is put on BOT DIMMsockett
UMA
Put C197 close to Guardian.Put C387 close DiodePlace near the bottomSODIMM.
Put C198 close to Guardian.Put C394 close Diode
Place under Skin.
Pin 3
MLX_53398-0371
Pin 1
No.10
EMC40011.2Lanai 43 68Monday, March 19, 2007
NPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
THERM_B2
THERM_B1
FAN1_VOUT_FB
5V_CAL_SIO2#
FAN1_VOUT
REM_DIODE3_P
THERMATRIP3#
THERM_LDO_IN
THERMATRIP1#
THERMATRIP2#
THERM_LDO_SET
REM_DIODE3_N
VCP2
REM_DIODE4_P
REM_DIODE1_P
REM_DIODE1_P
FAN1_VOUT
H_THERMDAH_THERMDC
THERMATRIP2#THERMATRIP3#
THERM_LDO_IN
REM_DIODE1_N
REM_DIODE1_N
5V_CAL_SIO1#
REM_DIODE4_N
+3V_PWROK#
REM_DIODE3_N
THERM_VEST
REM_DIODE3_P
LDO_SHDN#_ADDR
REM_DIODE4_N
REM_DIODE4_P
5V_CAL_SIO2#
5V_CAL_SIO1#+3VSUS_THRM
THERM_VEST
THERM_PWRGO
THERMATRIP1#
THERM_LDO_SET
VCP2
+3VSUS_THRM
THERMTRIP_MCH#10
H_THERMTRIP#7
MDC_RST_DIS#36
SUSPWROK17,51ICH_PWRGD#51
THERM_STP# 54
H_THERMDA7
FAN1_TACH 37
AUDIO_AVDD_ON45
ATF_INT# 38
2.5V_RUN_PWRGD 51
THRM_SMBCLK37
POWER_SW# 41,42
H_THERMDC7
SIO_GFX_PWR
PWR_MON 53
ACAV_IN 37,57
THRM_SMBDAT37
+2.5V_RUN
+3.3V_SUS
+1.05V_VCCP
+3.3V_RUN
+2.5V_RUN
+3.3V_RUN
+3.3V_SUS
+1.05V_VCCP
+3.3V_SUS
+3.3V_SUS
+3.3V_SUS
+RTC_CELL +3.3V_SUS
+5V_RUN
+RTC_CELL
+3.3V_SUS
+3.3V_RUN
+3.3V_SUS
+3.3V_SUS
+3.3V_SUS+5V_SUS
+5V_RUN
+3.3V_RUN
+RTC_CELL
+2.5V_RUN
C3872200PF/50V/*MLCC/+/-10%
12
BC
E
2
1
3Q32
MMST3904_7_F
C401
0.1UF/10VMLCC/+80-20%
12
C406
0.1UF/10VMLCC/+/-10%
12
C197
2200PF/50VMLCC/+/-10%
12
C194
10UF/10VMLCC/+/-20%pt_c0805_h57
12
T231
G
S
D
1
3
2
Q53
RHU002N06
2
31
R162
49.9Ohm1%
12
R138
8.2KOhm5%
12
R376 7.5KOhm1%
12
U11
EMC4001_HZH
1112
3837
4140
35
21
2316
171819
422634
78
39
101314152236
4346
4544
4847
21
20342524
27
33
28
3231
3029
9
56
49
SMDATASMCLK
DP1DN1
DP2DN2
3V_SUS
RTC_PWR3V
VSUS_PWRGD3V_PWROK#
THERMTRIP1#THERMTRIP2#THERMTRIP3#
VSETXENVSS
FAN_OUT1FAN_OUT2
FAN_DAC1
GPIO1GPIO2GPIO3GPIO4GPIO5GPIO6/FAN_DAC2
VCP1VCP2
DP3DN3
DP4DN4
DP5DN5
ATF_INT#POWER_SW#ACAVAIL_CLR
THERMTRIP_SIOSYS_SHDN#
LDO_SHDN#/ADDR
LDO_POK
LDO_SET
LDO_OUT2LDO_OUT1
LDO_IN2LDO_IN1
VDD_3V
VDD_5V_1VDD_5V_2
GN
D
C178
0.1UF/10VMLCC/+80-20%
/*
12
R146 10KOhm /*1 2
C177
0.1UF/10VMLCC/+80-20%
12
C407
2200PF/50VMLCC/+/-10%
12
R137
8.2KOhm5%
12
R370 1KOhm 5%1 2
BC
E
2
1
3
Q51
MMST3904
R177
10KOHM5%THERMISTOR 10K OHM
12
C160
0.1UF/10VMLCC/+80-20%
12
R140 10KOhm 5% /*1 2
T25 1
C174
0.1UF/10VMLCC/+80-20%
12
C182
10UF/4V
/*
pt_c0805MLCC/+/-20%
12
C196
470PF/50VMLCC/+/-10%
12
C173
0.1UF/10V/*MLCC/+80-20%
12
R139 2.2KOhm 5%1 2
T115 1
C195
2200PF/50VMLCC/+/-10%
12
C18410UF/10V
pt_c0805_h53MLCC/+80-20%
12
R381
118KOhm1%
12
T26 1
R315
0Ohmpt_r0805_h245%1
2
R383
2.2KOhm1%
12
R141 1KOhm 5%1 2
C171
1UF/10VMLCC/+80%-20%
pt_c0603
/*
12
R148 10KOhm /*1 2
R380
10KOhm1%
12
D16
RB751S40T1G/*
21
C3942200PF/50V/*MLCC/+/-10%
12
C162
0.1UF/10Vpt_c0402MLCC/+/-10%
12
C31722UF/10V
pt_c1206_h75MLCC/+/-20%
12
C161
0.1UF/10VMLCC/+80-20%
12
R374 1KOhm 5%1 2
R150
0Ohm /*pt_r1210_h24
12
R144
10KOhm5%/*1
2
BC
E
2
1
3
Q52
MMST3904
R373
1KOhm5%/*pt_r0603
12
R369
8.2KOhm5%
12 R379
31.6KOhm1%
/*
12
BC
E
2
1
3
Q50MMST3904_7_F
BC
E
2
1
3Q31
MMST3904_7_F
C188
0.1UF/10VMLCC/+80-20%
12
T24 1
R316
10KOhm 5%
12
R372
10KOhm5%
12
HOLD1
HOLD2
CON11
WTOB_CON_3PMOLEX/53398-0371(P6497)
123
45
R145 2.2KOhm 5%1 2
C3892200PF/50V/*MLCC/+/-10%
12
C198
2200PF/50VMLCC/+/-10%
12
R382
332KOhm1%
1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
FROM ICH
FROM EC
PLACE CLOSE TO U15 PIN6 PLACE CLOSE TO U15 PIN5
PLACE BETWEEN U15 andU16
If SENSE_B total length >6"change C510 to 0.1uF
PLACE CLOSE TO U15 PIN34
For TV port
If SENSE_A total length >6"change C276 to 0.1uF
PLACE CLOSE TO U15 PIN13
Port F---> HP2
Port A---> HP1
Port E---> ext MicPort D---> Speaker
PORT C : LEAVE NCIF NO INTERNAL MICS.
No.4
No.41
No.41
No.50
STAC92281.2Lanai 44 68Monday, March 19, 2007
Yihao YehPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
AUD_PC_BEEP
DVDD_CORE1
EAPD#_CODEC
AUD_SENSE_A
HDA_SDI
AUD_PC_BEEP
ICH_AZ_CODEC_BITCLK
AUD_SENSE_B
ICH_AZ_CODEC_SDOUT
DVDD_CORE
AVDD_CODEC
AUD_EXT_MIC_R4AUD_EXT_MIC_R3
AUD_EXT_MIC_L4AUD_EXT_MIC_L3
AUD_SENSE_B
AUD_SENSE_A
DVDD_CORE3
AVDD_CODEC
AVDD_CODEC
BEEP37
SPKR17
AUD_HP2_OUT_L 46AUD_HP2_OUT_R 46
AUD_DMIC_CLK28
AUD_EAPD#45
ICH_AZ_CODEC_SDOUT15
AUD_SPDIF_OUT50
ICH_AZ_CODEC_RST#15
ICH_AZ_CODEC_SYNC15
AUD_DMIC_IN028
ICH_AZ_CODEC_SDIN015
ICH_AZ_CODEC_BITCLK15
AUD_EAPD#45
AUD_HP1_OUT_R 45AUD_HP1_OUT_L 45
AUD_VREFOUT_E 46AUD_EXT_MIC_R 46
AUD_EXT_MIC_L 46
AUD_LINE_OUT_R 45AUD_LINE_OUT_L 45
AUD_MIC_SWITCH46
AUD_HP2_NB_SENSE46
AUD_HP1_NB_SENSE45,46
VDDA
VDDA
+3.3V_RUN
+3.3V_RUN
C2630.1UF/16V/X5R
/*
MLCC/+/-10%
12
R271
5.1kOhm1%
12
C276
1000PF/50VMLCC/+/-10%
12
R25733Ohm5% 1 2
C54
1
1000
PF/5
0VM
LCC
/+/-1
0% 12
R5085.1Ohmpt_r0603
1%1 2
R496
20KOhm1%
12
R26410KOhm 5%
1 2
C51
4
1UF/
10V/
X7R
pt_c
0603
MLC
C/+
/-10%
12
C5021UF/10V/X7R
pt_c0603MLCC/+/-10%
1 2
R4900Ohm5% 1 2
GS
D3
2
1Q58
2N7002
R491
39.2KOhm1%
12
C51
6
0.1U
F/16
V/X7
R
MLC
C/+
/-10%
12
C48
8
10U
F/10
V/X5
R
MLC
C/+
/-20%
pt_c
0805
_h57
/* 12
C50
3
1000
PF/
50V
MLC
C/+
/-10%/*1
2
U15
STAC9228
1
23
4
5
6
7
8
9
10
11
1415
1617
181920
2324
3635
34
33
32
31
30
29
28
27
26
25
42
41
4038
37
46
4748
12
4344
45
13
39
2122
DVDD_CORE1
VOLUME_UP/DMIC_0/GPIO1VOLUME_DOWN/DMIC_1/GPIO2
DVSS1
SDO
BITCLK
DVSS2
SDI
DVDD_CORE2
SYNC
RESET#
PORTE_LPORTE_R
PORTF_LPORTF_R
CD_LCD_GND
CD_R
PORTC_LPORTC_R
PORTD_RPORTD_L
SENSE_B
CAP2
VREFOUT_D
VREFOUT_E
VREFOUT_F
VREFOUT_C
VREFOUT_B
VREFFILT
AVSS1
AVDD1
AVSS2
PORTA_R
DVDD_CORE3AVDD2
VREFOUT_A
PORTH_R
SPDIF_IN/GPIO0/EAPD/DMIC_CLKSPDIF_OUT/ADAT_OUT
PCBEEP
PORTG_LPORTG_R
PORTH_L
SENSE_A
PORTA_L
PORTB_LPORTB_R
C273 0.1UF/16V/X7R
pt_c0402MLCC/+/-10%
1 2
R265
2.2KOhm5%
12
L41
600Ohm/100MhzIrat=500mAMURATA/BLM18EG601SN1D
21
C51
3
10U
F/10
V/X5
R
MLC
C/+
/-20%
pt_c
0805
_h57
12
C506
1UF/10V/X7R
pt_c0603
MLCC/+/-10%1 2
R5020Ohm5% /*1 2
JP9
SHORTPIN/*
1 2R2870Ohm5% /*1 2
C50
7
1000
PF/
50V
MLC
C/+
/-10%/*
12
R509100KOhm
5% 1 2
C2620.1UF/16V/X5R
/*
MLCC/+/-10%
12
GS
D3
2
1Q45
2N7002
C49
3
1000
PF/5
0V
MLC
C/+
/-10%
/*12 C
499
1000
PF/5
0V
MLC
C/+
/-10%
/*12
C52
2
10U
F/10
V/X5
R
MLC
C/+
/-20%
pt_c
0805
_h57
12
R5070Ohm5% 1 2
GS
D3
2
1Q59
2N7002
C48
9
1UF/
10V/
X7R
pt_c
0603
MLC
C/+
/-10%
12
R258
47Ohm5%
/*
12
L40
600Ohm/100MhzIrat=500mAMURATA/BLM18EG601SN1D
21
R5100Ohm5% /*1 2
R495
5.1kOhm1%
12
R2730Ohm5% 1 2
C48
0
10U
F/10
V/X5
R
MLC
C/+
/-20%
pt_c
0805
_h57 1
2
C510
1000PF/50VMLCC/+/-10%
12
C275 0.1UF/16V/X7R
pt_c0402MLCC/+/-10%1 2
C49
0
0.1U
F/16
V/X7
R
MLC
C/+
/-10%
12
Y
VCC
GND
A
B
U13
SN74AHCT1G86DCKR
1
2
3 4
5
R279
39.2KOhm1%
12
R259
47Ohm5%
/*
12
R5115.1Ohm
pt_r06031%
1 2
C51
9
10U
F/10
V
MLC
C/+
/-20%
pt_c
0805
_h57
12
R5350Ohm5% /*1 2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
FROM EC
Signal Inveter for Speaker Shutdown
Allow speakers to work while class driver isinstalled
PLACE JUST BEFORE+5V_MAX9789 CROSSESMOAT
GAIN SETTING RESISTORS
dB
0
0
10
1
Gain
21.6
dB
1
0
dB
1
1 15.6
Gain1
0
6
Gain2
dB
ROUTE VIA TRACE BACK TO TIE POINT.
Note: For TPA6040A,pop R291 and no popR294
FROM EC
NOTE:For TPA6040A,pop C291 and no popR292
ROUTE VIA TRACE BACK TO TIE POINT.
TEMPORARY VALUES. FINALVALUES CHOSEN IN PTPHASE.
FROM EC
ROUTE VIA TRACE BACK TO TIE POINT.
Place C295 closeto Pin 30
Recommend a starconnection for PVSSand CPVSS at capacitorC6613 of MAX9789A
NOTE:For TPA6040A, popC292 and C291(0402X5R) and no pop R530and R292. C292 andC291 value shouldmatch C299 and C298
No.49
No.49
No.49
No.49
AMP MAX97891.2Lanai <OrgName>45 68
Monday, March 19, 2007
Yihao YehPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
AUD_SPK_ENABLE#
AUD_AMP_GAIN1AUD_AMP_GAIN2
HP1_INL_AMP1
AUD_AMP_GAIN2
MUTE#_AMP1
HP1_INR_AMP1
AUD_SPK_ENABLE#
SPKR_INL_AMP1
AUD_AMP_GAIN1
+5V_AMP1
SPKR_INR_AMP1
+3.3V_CPVDD_HPVDD
+3.3V_CPVDD_HPVDD
AUD_EAPD#44
NB_MUTE#38,46
AUD_HP1_OUT_L 44
AUD_SPK_R1 46
AUD_HP1_OUT_R 44
AUD_SPK_L146
AUD_HP1_JACK_R 46
AUD_SPK_L246
AUDIO_AVDD_ON 43
AUD_LINE_OUT_R44
AUD_SPK_R2 46
AUD_LINE_OUT_L44
AUDIO_AVDD_ON43
AUD_HP1_JACK_L 46
AUD_HP1_NB_SENSE 44,46NB_MUTE# 38,46
+5V_SPK_AMP
+5V_SPK_AMP
+5V_SPK_AMP+5V_RUN
+5V_SPK_AMP+5V_SPK_AMP
+5V_SPK_AMP
+5V_SPK_AMP
+5V_SPK_AMP
+3.3V_RUN
+5V_SPK_AMP
VDDA
U16
TPA6040A4RHBR
33
34 35 36 37
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8 17
18
19
20
21
22
23
24
2526272829303132
GND1
GN
D2
GN
D3
GN
D4
GN
D5
CPV
DD
1
C1P
CPG
ND
2
C1N
CPV
SS
HPV
SS
HP_
OU
TR
HP_
OU
TL
SPKR_RIN-
SPKR_RIN+
SPKR_LIN+
SPKR_LIN-
SPGND1
LOUT+
LOUT-
SPVDD1 HPVDD
SPVDD2
ROUT-
ROUT+
SPGND2
HP_EN
SPKR_EN#
BYPASSREG
_EN
HP_
INR
HP_
INL
SGN
D
REG
_OU
T
VDD
GAI
N0
GAI
N1
R294100KOhm 5%
/*
12
C29
6
1UF/
10V/
X7R
pt_c
0603
MLC
C/+
/-10% 1
2
R289100KOhm 5%
/*
12
L43
600OhmMURATA/BLM18AG601SN1(J5535)<G>
Irat=200mA
2 1
C29
2
0.03
3UF/
16V/
X7R
MLC
C/+
/-10% 1
2
GS
D3
2
1Q60
2N7002
R525
100KOhm5%
12
C2980.033UF/100V
pt_c1206_h59MLCC/+/-10%
12
R295100KOhm 5%
/*
12
C53
1
47PF
/50V
MLC
C/+
/-5%
/*12
C297
1UF/25V/X7R
pt_c1206_h49
MLCC/+/-10%
12
C52
91U
F/10
V/X7
Rpt
_c06
03
MLC
C/+
/-10%1
2
C30
0
1UF/
10V/
X7R
pt_c
0603
MLC
C/+
/-10% 1
2
C289
1UF/10V/X7R
pt_c0603
MLCC/+/-10%
1 2
C29
3
47PF
/50V
MLC
C/+
/-5% /*1
2
C53
0
10U
F/10
V/X5
RM
LCC
/+/-2
0%
pt_c
0805
_h57
12
C2990.033UF/100V
pt_c1206_h59MLCC/+/-10%
12
C28
6
10U
F/10
V/X5
RM
LCC
/+/-2
0%
pt_c
0805
_h57
12
A
GND
B
VCC
Y
U38
74AHC1G08GW
12
3
4
5
C53
2
47PF
/50V
MLC
C/+
/-5%
/*12
R290100KOhm 5%
12
L20
600O
hm
MU
RAT
A/BL
M18
AG60
1SN
1(J5
535)
<G>
Irat=
200m
A
21
C29
4
47PF
/50V
MLC
C/+
/-5% /*1
2
R288
100KOhm5%
12
C52
7
10U
F/10
V/X5
RM
LCC
/+/-2
0%
pt_c
0805
_h57
12
C29
0
1UF/
10V/
X7R
pt_c
0603
MLC
C/+
/-10% 1
2
C53
3
1UF/
10V/
X7R
pt_c
0603
MLC
C/+
/-10% 1
2
L42
60Ohm Irat=3Apt_l0805_h41
MURATA/BLM21PG600SN1(Y8220)<G>
21
C52
81U
F/10
V/X7
Rpt
_c06
03
MLC
C/+
/-10%1
2
R53
00O
hm5%
/*1
2
C52
0
10U
F/10
V/X5
R
MLC
C/+
/-20%
pt_c
0805
_h57
12
C29
1
0.03
3UF/
16V/
X7R
MLC
C/+
/-10% 1
2
C52
6
0.1U
F/16
VM
LCC
/+/-1
0%
12
R293100KOhm 5%
12
C53
5
1UF/
10V/
X7R
pt_c
0603
MLC
C/+
/-10% 1
2
C301
1UF/25V/X7R
pt_c1206_h49
MLCC/+/-10%
12
C287
1UF/10V/X7R
pt_c0603MLCC/+/-10%
1 2
R2910Ohm
5%1 2
C29
5
0.1U
F/16
V/X7
RM
LCC
/+/-1
0% 12
C28
8
1UF/
10V/
X7R
pt_c
0603
MLC
C/+
/-10%
12
R292
0Ohm5%
/*1 2
GS
D3
2
1Q61
2N7002
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
NOTE: MAKE SURE THERMAL PAD(Pin21)UNDER MAX4411 IS NOTCONNECTED TO GND
TI:1.8V ~ 4.5VMaxim:1.8V ~ 3.6V Speaker CON
Need to adjust EMI cap values as necessary.
No.31
No.50
No.49
AMP MAX4411 & AUDIO JACK1.2Lanai <OrgName>46 68
Monday, March 19, 2007
Yihao YehPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
C1N
C1P
+3.3V_AMP2
PVSS
HP2_INR_AMP2
HP2_INL_AMP2
AUD_MIC_SWITCH
AUD_HP2_NB_SENSE
AUD_HP1_NB_SENSE
AUD_HP2_OUT_L44
AUD_HP2_OUT_R44
AUD_HP2_JACK_L
AUD_HP2_JACK_RNB_MUTE#38,45
AUD_HP2_NB_SENSE44
AUD_VREFOUT_E44
AUD_HP2_JACK_L
AUD_HP1_NB_SENSE44,45
AUD_MIC_SWITCH44
AUD_HP1_JACK_R45AUD_HP1_JACK_L45
AUD_EXT_MIC_L44
AUD_HP2_NB_SENSE44
AUD_HP2_JACK_R
AUD_EXT_MIC_R44
AUD_SPK_R2 45
AUD_SPK_L2 45AUD_SPK_R1 45
AUD_SPK_L1 45
SPEAKER_DET# 15
+3.3V_RUN
+3.3V_RUN
C45
2
100P
F/50
V/N
PO
/*
MLC
C/+
/-5%
12
C521
2.2UF/16Vpt_c1206_h75MLCC/+/-10%
12
C50
0
2.2U
F/10
V/X5
R
pt_c
0603
MLC
C/+
/-10% 1
2
U35
TPA4411MRTJR
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
C1P
PGN
D
C1N
NC1
PVSS
NC2
SVSS
NC3
OUTLSVD
D OUTR
NC4
INL
SHDNR#
INR
NC5
SGN
D
SHDNL# PVD
D
NC6
GN
D
CON7
WTOB_CON_6PMOLEX/48227-0611
6543217
8 654321SIDE1
SIDE2
R282 100KOhm 5%1 2
C27
1
1UF/
10V/
X7R
pt_c
0603
MLC
C/+
/-10% 1
2
C45
0
100P
F/50
V/N
PO
/*
MLC
C/+
/-5%
12
C45
1
100P
F/50
V/N
PO
/*
MLC
C/+
/-5%
12
C50
8
0.1U
F/16
V/X7
RM
LCC
/+/-1
0%1
2C
498
47PF
/50V
MLC
C/+
/-5%
12
C50
4
47PF
/50V
MLC
C/+
/-5%
12
R286 100KOhm 5%1 2
C49
1
2.2U
F/10
V/X5
R
pt_c
0603
MLC
C/+
/-10% 1
2
A
GND
B
VCC
Y
U37
74AHC1G08GW
12
3
4
5
C45
4
100P
F/50
V/N
PO
/*
MLC
C/+
/-5%
12
L19
600OhmMURATA/BLM18AG601SN1(J5535)<G>
Irat=200mA
2 1
CON9
WTOB_CON_15PMOLEX/48227-1511
1617
123456789
101112131415
SID
E1SI
DE2
123456789101112131415
C511
2.2UF/16V
pt_c1206_h75
MLCC/+/-10%12
R283 100KOhm 5%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Core Power DecouplingVDDP Power Decoupling VDDIO Power Decoupling
Layout note:Place Close to LOM
Layout note:Place Close to LOM
No.3
No.12
No.12
No.25
No.27
No.53
LAN BCM5906MKMLG(QFN-68)1.2Lanai <OrgName>47 68
Monday, March 19, 2007
Ivan_ChouPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
EEPROM_WPLAN_SCLK
LAN_UART_MODE
LAN_SO
LINK_LED10#
LAN_XTALVDD
LAN_SCLK
LAN_SO
LINK_LED100#
LAN_AVDDL
LOM_XINLOM_XOUT_R
LOM_XOUT
LOM_LOW_PWR
VAUX_PRSNTVMAIN_PRSNT
LAN_PCIETXDNLAN_PCIETXDP
LAN_PCIE_VDD
ACTLED#
LAN_PCIE_PLLVDD
LAN_BIASVDD
EEPROM_WP
LOM_PERST#
LAN_REGCTL25
LAN_REGCTL12PCIE_LOM_CLKREQ#_R
LAN_RDAC
LINK_LED100# 48
LOM_LOW_PWR38
PCIE_TX6+/GLAN_TX+16PCIE_TX6-/GLAN_TX-16
PCIE_WAKE#35,38,50PLTRST_LAN_MINICARD#16,50
PCIE_RX6+/GLAN_RX+16PCIE_RX6-/GLAN_RX-16
LINK_LED10# 48
ACTLED# 48SB_LOM_PCIE_RST#16
PCIE_LOM_CLKREQ#21
CLK_PCIE_LOM21CLK_PCIE_LOM#21
LOM_RX- 48LOM_RX+ 48
LOM_TX+ 48LOM_TX- 48
+3.3V_LAN
+3.3V_LAN
+1.2V_LOM +2.5V_LOM +3.3V_LAN
+3.3V_LAN
+1.2V_LOM
+2.5V_LOM
+1.2V_LOM
+1.2V_LOM
+3.3V_LAN +2.5V_LOM
+3.3V_LAN
+3.3V_LAN
+3.3V_LAN
+2.5V_LOM
+1.2V_LOM
+3.3V_RUN
C28 0.1UF/10V MLCC/+/-10%1 2
R25 0Ohm 5% /*1 2
R13
49.9
Ohm
1%1
2
R21
4.7KOhm
12
C18
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C79
4.7U
F/10
VM
LCC
/+/-1
0%pt
_c08
05_h
37 12
R9310KOhm5%/*
12
U3
BCM5906MKMLGC.S BCM5906MKMLG A2 QFN68
12
34
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2122
23
24
2526
27
2829
30
3132
33
34
35
36
37
38
39
4041
4243
44
45
46
4748
4950
51
52
5354
55
56
5758
59
60
61
62
63
64
65
66
67
68
69
SPD100_LED#LINK_LED#
LOW_PWRGPIO_0
VDDC1 VDD
IO1
GPIO_1
GPIO_2
UART_MODE
PERST#
CLKREQ#
WAKE
VDDC2
REGCTL12
VDD
IO2
VSS1
VDD
P1
REGCTL25
VDD
IO3
VDDC3
XTALIXTALO
XTALVDD
VSS2
PCIE_TXD_NPCIE_TXD_P
PCIE_VDD1
PCIE_REFCLK_NPCIE_REFCLK_P
PCIE_PLLVDD
PCIE_RXD_PPCIE_RXD_N
PCIE_VDD2
VDDC4
DC1
BIASVDD
RDAC
DC2
AVDDL
RDPRDN
TDNTDP
DC3
DC4
DC5
DC6DC7
DC8DC9
DC10
DC11
VMAIN_PRSNTVAUX_PRSNT
VDDC5
VDD
IO4
NC1NC2
ENERGY_DET
VDDC6
VDD
IO5
SERIAL_DO
NC3
SO
SCLK
TRAFFIC_LED#
SERIAL_DI
VDD
P2
GN
D
R41
0Ohm5% /*
1 2
C20
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C24
4.7U
F/10
VM
LCC
/+/-1
0%pt
_c08
05_h
37 12
R32 47Ohm 5%1 2
L7 600OhmMURATA/BLM18AG601SN1
2 1
C19
4.7U
F/10
VM
LCC
/+/-1
0%pt
_c08
05_h
37 12
R49 1.5Ohm
5%pt_r2512_h261 2
C51
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C21
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C49
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C17
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C32
0.1U
F/10
VM
LCC
/+80
-20% 1
2
R11
49.9
Ohm
1%1
2
R9
1KOhm
1%12
C82
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C52
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C48
0.1U
F/10
VM
LCC
/+80
-20% 1
2
U2
AT24C02BN
1234
8765
A0A1A2
GND
VCCWPSCLSDA
C25 0.1UF/10V MLCC/+/-10%1 2
C3810UF/10V
pt_c0805_h53MLCC/+80-20%
12
C37
27PF
/50V
MLC
C/+
/-5% 1
2
C23
4.7U
F/10
VM
LCC
/+/-1
0%pt
_c08
05_h
37 12
L4 600OhmMURATA/BLM18AG601SN1
21
C12
0.1U
F/10
VM
LCC
/+80
-20% 1
2
R44
0Ohm 5%
1 2
C22
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C8
4.7U
F/10
VM
LCC
/+/-1
0%pt
_c08
05_h
37 12
L5 600OhmMURATA/BLM18AG601SN1
21
R10 1KOhm 1%1 2
C26
0.1U
F/10
VM
LCC
/+80
-20% 1
2
E
BC
1
24
3
Q10
MMJT9435T1G C68
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C61
4.7U
F/10
VM
LCC
/+/-1
0%pt
_c08
05_h
37 12
C30
4.7U
F/10
VM
LCC
/+/-1
0%pt
_c08
05_h
37 12
L3 600OhmMURATA/BLM18AG601SN1
21
C39
0.1U
F/10
VM
LCC
/+80
-20% 1
2
BC
E Q15
MBT35200MT1G3
24
1 5 6
C35
0.1U
F/10
VM
LCC
/+80
-20% 1
2
R19
4.7KOhm
12
12X1
25Mhz+/-30ppm/18PF
C9
0.1U
F/10
VM
LCC
/+/-1
0%1
2
C13
0.1U
F/10
VM
LCC
/+80
-20% 1
2
L6 600Ohm
MURATA/BLM18AG601SN1
21
C33
27PF
/50V
MLC
C/+
/-5% 1
2
C50
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C53
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C14
0.1U
F/10
VM
LCC
/+/-1
0%1
2
C59
0.1U
F/10
VM
LCC
/+80
-20% 1
2
R14
49.9
Ohm
1%1
2
R37 200Ohm 1%1 2
C6510UF/10V
pt_c0805_h53MLCC/+80-20%
12
R18
4.7KOhm
12
C47
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C31
0.1U
F/10
VM
LCC
/+80
-20% 1
2
C43
0.1U
F/10
VM
LCC
/+80
-20% 1
2
R22 1KOhm 1%1 2
R12
49.9
Ohm
1%1
2
C44
0.1U
F/10
VM
LCC
/+80
-20% 1
2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
No Stuff
Reserve Pull-up
JUMP
1. Use +3.3V_SUS if Wake-on-LAN isNOT required out of S4, S52. Use +3.3V_SRC if Wake-on_LAN isrequired out of S4, S5
+3.3V_LAN Source Guideline:
No Stuff
No Stuff
Reserve Pull-up
Layout note:C303 should be close to pin12C304 should be close to pin6
Magnetics and RJ-451.2Lanai <OrgName>48 68
Monday, March 19, 2007
Ivan_ChouPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
ACTLED#_R
LOM_RX-
LOM_TX-
LINK_LED100# LINK_LED100#_RLINK_LED10#_R
ACTLED#
LOM_TX+
LINK_LED10#
LOM_RX+
LOM_CT
LOM_TX-47
LOM_TX+47
LOM_RX+47
LOM_RX-47
LINK_LED100#47LINK_LED10#47
ACTLED#47
+3.3V_LAN+3.3V_SUS
+3.3V_LAN
+2.5V_LOM
+3.3V_LAN
L21 600OhmMURATA/BLM18AG601SN1
21
R307 10KOhm /*5%1 2
C30
40.
1UF/
16V
MLC
C/+
/-10% 1
2
JP1
0Ohmpt_r0603
1 2
CON10
LAN_JACK_17PTYCO/1840427-2,TAB DOWN
14
13
111210
312
879
1517
16
465
18 19
2021
YELLOW+
YELLOW-
TRD1+TRCT1TRD1-
NC_1NC_2NC_3
NC_4NC_5NC_6
ORANGE-GREEN-
COMMON+
TRD2+TRDCTTRD2-
SHIE
LD1
SHIE
LD2
NP_NC1NP_NC2
R310 150Ohm 1%1 2
R306 10KOhm /*5%1 2
R30810KOhm
5% /*
12
R309 150Ohm 1%1 2
C30
30.
1UF/
16V
MLC
C/+
/-10% 1
2
R311 150Ohm 1%1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
For iAMT Support
For iAMT Support
Reserve discharge path
Reserve discharge path
No.11
No.29
No.29
No.34
Power Control Switch1.2Lanai 49 68
Monday, March 19, 2007Eric KoPROJECT: SHEET OF
DATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :RELEASE DATE :
SUS_3.3V_ENABLE
3.3V_SUS_ON
RUN_ON_5V#SUS_ON_3.3V#
RUN_ON
RUN_ENABLE
SUS_ON_5V#
SUS_5V_ENABLE
SUS_ON
RUN_ON_5V#
SUS_ON_5V#
3.3V_SUS_ON37RUN_ON28,37,51,54
1.8V_RUN_ON37
3.3V_RUN_ON37
SUS_ON37,51
+3.3V_SUS+15V_ALW
+3.3V_ALW+5V_RUN
+15V_ALW
+5V_ALW
+1.8V_SUS +1.8V_RUN
+15V_ALW
+3.3V_ALW+3.3V_RUN
+15V_ALW
+5V_SUS+5V_ALW+15V_ALW
+3.3V_RUN +1.8V_RUN +0.9V_DDR_VTT+5V_RUN +1.5V_RUN +1.25V_RUN
+5V_SUS +3.3V_SUS+1.8V_SUS
+5V_ALW2
+5V_ALW2
+5V_ALW2
+5V_ALW2
+5V_ALW2
PC1644700PF/50VMLCC/+/-10%pt_c0603
12
R96
30Ohm1%pt_r0603/*
12
R60
1KOhm/*5%
pt_r0603
12
PR37100KOhm5%
12
PR39100KOhm5%
12
SD
G
PQ39
SI4800BDY
123
5678
4
GS
D3
2
1PQ152N7002pt_sot23_philips
PC924700PF/50V
MLCC/+/-10%/*
pt_c0603
12
R74
1KOhm/*5%
pt_r0603
12
GS
D3
2
1
Q13
2N7002
/*
GS
D3
2
1PQ14
2N7002pt_sot23_philips
PC1674700PF/50VMLCC/+/-10%pt_c0603
12
PR4020KOhm5%
12
GS
D3
2
1
Q34
2N7002
/*
GS
D3
2
1PQ26
2N7002pt_sot23_philips
PR420Ohm
5%
1 2
PR98100KOhm
5%
12
SD
G
PQ41
SI4800BDY
123
5678
4
PR95100KOhm5%
12
PC520.047UF/25VMLCC/+/-10%/*
12
PR157100KOhm5%
12
GS
D3
2
1PQ492N7002pt_sot23_philips
GS
D3
2
1PQ28
2N7002pt_sot23_philips
SD
G
PQ42
SI4800BDY
123
5678
4
PR15120KOhm
5%
12
PD9
RB751V_40
/*pt_sod323_h35
12
PC168
10UF/10VMLCC/+/-20%pt_c0805_h57
12
PR15320KOhm5%
12
R242
1KOhm/*5%
pt_r0603
12
GS
D3
2
1
Q33
2N7002
/*
GS
D3
2
1PQ24
2N7002pt_sot23_philips
GS
D3
2
1
Q22
2N7002
/*
R63
1KOhm/*5%
pt_r0603
12
GS
D3
2
1PQ27
2N7002pt_sot23_philips
PC53
10UF/10VMLCC/+/-20%pt_c0805_h57/*
12
PR96100KOhm
5%
12
PR99100KOhm5%
12
PR97100KOhm5%
12
GS
D3
2
1
Q14
2N7002
/*
R94
1KOhm/*5%
pt_r0603
12
PR101100KOhm5%
12
GS
D3
2
1PQ29
2N7002pt_sot23_philips
SD
G
PQ38
FDS8884
123
5678
4
PR15420KOhm
5%
12
GS
D3
2
1PQ25
2N7002pt_sot23_philips
PC162
10UF/10VMLCC/+/-20%pt_c0805_h57
12
GS
D3
2
1
Q40
2N7002
/*
PC1664700PF/50V
MLCC/+/-10%/*
pt_c0603
12
PD11
RB751V_40
/*pt_sod323_h35
12
PC17010UF/16VMLCC/+/-10%pt_c1206_h71
12
GS
D3
2
1
Q16
2N7002
/*
PR156100KOhm5%
12
PC169
10UF/10VMLCC/+/-20%pt_c0805_h57
12
R165
10Ohm/*5%
pt_r0603
12
PR1020Ohm
5%
1 2
PR15520KOhm5%
12
GS
D3
2
1
Q17
2N7002
/*
GS
D3
2
1PQ402N7002pt_sot23_philips
R71
1KOhm/*5%
pt_r0603
12
PR100100KOhm5%/*
12
R151
1KOhm/*5%
pt_r0603
12
PR152100KOhm5%/*
12
SD
G
PQ16
FDS8884
123
5678
4
GS
D3
2
1
Q21
2N7002/*
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
No.21
BtoB CON1.2Lanai <OrgName>50 68
Monday, March 19, 2007
STANLY_HSUPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
YPRPB_DET#
AUX_EN_WOWL37
ICH_USBP3-16
PCIE_RX2- 16
VGA_BLU10
TV_C10
WWAN_RADIO_DIS#38
G_DAT_DDC210
PCIE_RX1+16
MINI2CLK_REQ# 21
PCIE_TX1-16
COEX1_BT_ACTIVE 41
PCIE_TX2- 16
LED_WLAN_OUT# 42SB_WWAN_PCIE_RST# 16
VGAVSYNC 10
TV_Y10
ICH_USBP2+16
G_CLK_DDC210
PCIE_MCARD1_DET#17
PLTRST_LAN_MINICARD# 16,47
USB_MCARD1_DET# 17
CLK_PCIE_MINI1 21
ICH_USBP9- 16
USB_OC2_3# 16
CLK_PCIE_MINI2#21
ICH_SMBCLK 17,35
VGA_GRN10TV_CVBS10
WLAN_RADIO_DIS# 38
COEX2_WLAN_ACTIVE 41
CLK_PCIE_MINI221
VGAHSYNC 10
MINI1CLK_REQ# 21
USB_BACK_EN# 38
ICH_USBP2-16
VGA_RED10
ICH_USBP3+16
USB_MCARD2_DET#17
PCIE_TX1+16
PCIE_RX1-16
SB_WLAN_PCIE_RST# 16
CLK_PCIE_MINI1# 21
AUD_SPDIF_OUT44
ICH_SMBDATA 17,35PCIE_MCARD2_DET#16
PCIE_TX2+ 16
ICH_USBP9+ 16
PCIE_WAKE# 35,38,47
PCIE_RX2+ 16HOST_DEBUG_RX37HOST_DEBUG_TX37 8051_TX 37
8051_RX 37
+3.3V_RUN
+PWR_SRC
+3.3V_WLAN
+3.3V_ALW
+1.5V_RUN+5V_RUN
+5V_ALW
+3.3V_WLAN
+3.3V_RUN
+3.3V_RUN
C1074700PF/50VMLCC/+/-10%pt_c0603/*
12
R116200KOhm5%/*
12
GS
D3
2
1Q30
2N7002/*
R1040Ohm
pt_r1206_h265%
12
CON3B
PCB_SCK_2X37PSUYIN/127216FA074G500ZR
76
112113
114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146
757778798081828384858687888990919293949596979899100101102103104105106107108109110111
147148149150
NP_NC2
NP_NC38NP_NC39
NP_NC40NP_NC41NP_NC42NP_NC43NP_NC44NP_NC45NP_NC46NP_NC47NP_NC48NP_NC49NP_NC50NP_NC51NP_NC52NP_NC53NP_NC54NP_NC55NP_NC56NP_NC57NP_NC58NP_NC59NP_NC60NP_NC61NP_NC62NP_NC63NP_NC64NP_NC65NP_NC66NP_NC67NP_NC68NP_NC69NP_NC70NP_NC71NP_NC72
NP_NC1NP_NC3NP_NC4NP_NC5NP_NC6NP_NC7NP_NC8NP_NC9
NP_NC10NP_NC11NP_NC12NP_NC13NP_NC14NP_NC15NP_NC16NP_NC17NP_NC18NP_NC19NP_NC20NP_NC21NP_NC22NP_NC23NP_NC24NP_NC25NP_NC26NP_NC27NP_NC28NP_NC29NP_NC30NP_NC31NP_NC32NP_NC33NP_NC34NP_NC35NP_NC36NP_NC37
NP_NC73NP_NC74NP_NC75NP_NC76
GS
D3
2
1Q28
2N7002/*
SD
G
U9
SI4800BDY/*
1235 6 7 8
4
R108100KOhm5%/*
12
T1 1
R107470KOhm5%/*
12
CON3A
PCB_SCK_2X37PSUYIN/127216FA074G500ZR
13579
111315171921232527293133353739414345474951535557596163656769
246810121416182022242628303234363840424446485052545658606264666870
7173
7274
13579111315171921232527293133353739414345474951535557596163656769
2468
10121416182022242628303234363840424446485052545658606264666870
7173
7274
R106100KOhm5%/*
12
R115100KOhm5%/*
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Discrete
Keep Away from high speed buses
Power Sequence Logic1.2Lanai 51 68
Monday, March 19, 2007C.L. HoPROJECT: SHEET OF
DATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :RELEASE DATE :
RESET_OUT#
IMVP_PWRGD
3V_5V_SUS_PWRGD
ICH_PWRGD#
ICH_PWRGD
1.25V_RUN_PWRGD58
RESET_OUT#37
IMVP_PWRGD17,37,53ICH_PWRGD 10,17
2.5V_RUN_PWRGD43
1.5V_RUN_PWRGD551.05V_RUN_PWRGD55
5V_3V_1.8V_1.25V_RUN_PWRGD 38
RUN_ON28,37,49,54
SUSPWROK 17,43
RUNPWROK 37,53
SUS_ON37,49
ICH_PWRGD# 43+5V_ALW+5V_RUN
+1.8V_SUS
+3.3V_ALW+3.3V_RUN
+3.3V_ALW+3.3V_SUS
+5V_ALW+5V_SUS
+3.3V_ALW
+3.3V_SUS
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+3.3V_ALW
+1.8V_RUN
+3.3V_ALW +3.3V_ALW+3.3V_SUS
R27 4.7KOhm
5%1 2
VCC
GND
U8C
74AHC08PW
9
108
147
R105
100KOhm5%
12
R99 0Ohm /*5%1 2
D4
RB751V_40
21
C87
2200PF/50VMLCC/+/-10%
12
C40
0.1UF/10VMLCC/+80-20%
12
R97 10KOhm
5%1 2
R33200KOhm5%
12
R39200KOhm5%
12
C88 0.1UF/10V
MLCC/+80-20%1 2
GS
D3
2
1Q26
2N7002
C36
0.1UF/10VMLCC/+80-20%
12
U4
NC7SZ14P5X_NL
1
2
3
5
4
NC
A
GND
VCC
Y
VCC
GND
U8B
74AHC08PW
4
56
147
C89
0.1UF/10VMLCC/+80-20%
12
D9
RB751V_40
21
BC
E
1
2
3Q24PMBS3904
BC
E
1
2
3
Q8PMBS3906
C34
2200PF/50VMLCC/+/-10%
12
R40 0Ohm 5%1 2
BC
E
1
2
3Q23PMBS3904
R30200KOhm5%
12
C93
2200PF/50VMLCC/+/-10%
12
C98
0.1UF/10VMLCC/+80-20%
12
R38200KOhm5%
12
C96 0.1UF/10V
MLCC/+80-20%1 2
U6A
NC7WZ14P6X_NL
1 6
52
D8
RB751V_40
21
D5
RB751V_40
21
R56 0Ohm 5%1 2
R100
20KOhm5%
12
D7
RB751V_40
21
R36200KOhm5%
12
BC
E
1
2
3
Q7PMBS3906
R98200KOhm5%
12
VCC
GND
U8A
74AHC08PW
1
23
147
R317 0Ohm 5%1 2
R95 4.7KOhm
5%1 2
R31 10KOhm
5%1 2
R92200KOhm5%
12
C27
2200PF/50VMLCC/+/-10%
12
U6B
NC7WZ14P6X_NL
3 4
52
BC
E
1
2
3Q5PMBS3904
R91 10KOhm
5%1 2
C42
0.1UF/10VMLCC/+80-20%
12
R29200KOhm5%
12
C94
0.01UF/25VMLCC/+/-10%
12
R101 0Ohm
5%1 2
R103 4.7KOhm
5%1 2
R34 10KOhm
5%1 2
C41 0.1UF/10V
MLCC/+80-20%1 2
R28 10KOhm
5%1 2
BC
E
1
2
3
Q20PMBS3906
VCC
GND
U8D
74AHC08PW
12
1311
147
BC
E
1
2
3
Q25PMBS3906
BC
E
1
2
3
Q6PMBS3906
C29
2200PF/50VMLCC/+/-10%
12
D3
RB751V_40
21
D6
RB751V_40
21
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
XDP
CAD NOTE:Place the XDP connector on theprimary side of the CRB and placeall components near the connector.
Layout note:R123 shouldconnect to H_RESET# withno stub
XDP1.2Lanai <OrgName>52 68
Monday, March 19, 2007
Terry_LinPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
XDP_OBS6
XDP_BPM#5
XDP_OBS12
XDP_TDI
XDP_OBS11
XDP_OBS0XDP_OBS1
XDP_OBS10
XDP_OBS8XDP_BPM#4
XDP_TRST#
XDP_OBS2
XDP_TMS
XDP_OBS4
XDP_OBS7
XDP_OBS13
RST_SNS1
XDP_OBS9
H_PWRGD_XDP
XDP_OBS5
XDP_OBS20
XDP_OBS14
XDP_OBS16
XDP_OBS15
XDP_TCK
XDP_OBS17
XDP_OBS3_RXDP_BPM#0
XDP_BPM#47
CLK_XDP# 21
XDP_TDI 7
CLK_PCIE_XDP_3GPLL#21H_RESET# 7,9
LCTLA_CLK10
XDP_TCK7
XDP_BPM#57
XDP_DBRESET# 7,17,38
XDP_TDO 7
XDP_BPM#07
XDP_TRST# 7
CLK_PCIE_XDP_3GPLL21
CLK_XDP 21
XDP_TMS 7
LCTLB_DATA10
H_PWRGD_XDP7
XDP_BPM#37XDP_BPM#27
XDP_BPM#17
+1.05V_VCCP
+1.05V_VCCP +3.3V_RUN
C3520.1UF/10VMLCC/+/-10%/*
12
T1031
T1011
R32354.9Ohm1%/*
12
T941
R123 100Ohm 5%
/*
1 2
R320 0Ohm 5%
/*
1 2 T1061
T961
T88 1
R321 0Ohm 5%
/*
1 2
R34754.9Ohm1%/*
12
C3310.1UF/10VMLCC/+/-10%/*
12
T951
R3461KOhm5%
12
R322 0Ohm 5%
/*
1 2
T971R319 0Ohm 5%
/*
1 2
U20
BtoB_CON_60P
SAMTEC/BSH-030-01-L-D-A-TR
/*
13579
11131517192123252729313335373941434547495153555759
24681012141618202224262830323436384042444648505254565860
61 62
GND0OBSFN_A0OBSFN_A1GND2OBSDATA_A0OBSDATA_A1GND4OBSDATA_A2OBSDATA_A3GND6OBSFN_B0OBSFN_B1GND8OBSDATA_B0OBSDATA_B1GND10OBSDATA_B2OBSDATA_B3GND12PWRGOOD/HOOK0HOOK1VCC_OBS_ABHOOK2HOOK3GND14SDASCLTCK1TCK0GND16
GND1OBSFN_C0OBSFN_C1
GND3OBSDATA_C0OBSDATA_C1
GND5OBSDATA_C2OBSDATA_C3
GND7OBSFN_D0OBSFN_D1
GND9OBSDATA_D0OBSDATA_D1
GND11OBSDATA_D2OBSDATA_D3
GND13ITPCLK/HOOK4
ITPCLK#/HOOK5VCC_OBS_CD
RESET#/HOOK6DBR#/HOOK7
GND15TDO
TRSTNTDI
TMSGND17
NP_NC1 NP_NC2
T85 1
T84 1
T1041
T87 1
T921
T1021
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Close to Phase 1Inductor
Design Current:35.2AMaximum current:44AOCP point min.50A
Intersil request tochange.
Close to Phase 1Inductor
POWER_VCORE1.2Lanai <OrgName>53 68
Monday, March 19, 2007
JEFFPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
CORE_LG3
+CPU_PWR_SRC
CLK
_EN
AB
LE#
VSUMCORE_LG2
VSUM
VO_CORE
CORE_HG3
ISEN3
ISE
N2
+VCC_CORE_L3
VDD_CORE
ISE
N1
+CPU_PWR_SRC
PSI#
VO_CORE
ISE
N3
VDD_CORE
VSUM
VIN
CORE_HG1
ISEN1
ISEN2
PWR_MON
VSUM
VO_CORE
PMON
VO_CORE
VO_CORE
PMON
+CPU_PWR_SRC
CORE_HG2
+VCC_CORE_L2
+VCC_CORE_L1
CORE_LG1
IMVP_PWRGD17,37,51
VID
5 8
VCCSENSE8
IMVP_VR_ON37
VID
1 8DPR
SLP
VR
10,1
7
IMVP6_PROCHOT#38
RUNPWROK37,51
VID
3 8
H_D
PR
STP
#
7,10
,15
PWR_MON43
PWR_MON 43
VID
2 8
VID
6 8
H_PSI#7
VSSSENSE8
VID
0 8
VID
4 8
CGND
GND
GND
GND
+5V_ALW
GND
GND
GND
CGND
GND
CGND
+5V_ALW
+CPU_PWR_SRC
GND
GND
GND
CGND
CGND
GND
CGND
GND
+5V_ALW+3.3V_RUN
CGND
GND
GND
GND
CGND
+VCC_CORE
+VCC_CORE
+5V_ALW
CGND
+CPU_PWR_SRC
GND
GND
GND
+PWR_SRC
GND
GND
GND
GND
+VCC_CORE
CGND
CGND
PR8110Ohmpt_r06031%1 2
PR850Ohmpt_r06035%
12
PR56226KOhm
1%/*
12
PR69
4.53
KO
hm1%
12
PR
144
10K
OH
Mpt
_r06
03 5%/*
12
PR7810KOhm1%
1 2
SD
G
PQ19SI4386DY_T1_E3123
5 6 7 8
4
PC
146
10U
F/25
Vpt
_c12
06_h
71M
LCC
/+/-1
0%
12
PC
8822
00PF
/50V
MLC
C/+
/-10%
12
PR7910KOhm1%
1 2
PC
8510
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%
12
PC1531500PF/50Vpt_c0603MLCC/+/-5%
12
PU8
ISL6208CRZ
12
3 4
56
789
BOOTPWM
GN
D1
LGAT
E
VCCFCCM
PH
ASE
UG
ATE
GN
D2
PC1501UF/10Vpt_c0603
MLCC/+/-10%
12
PC
189
1000
PF/5
0VM
LCC
/+/-1
0%
/*
12
+
PCE
210
0uF/
25V
EL/
Lf_T
=300
0hrs
_105
c/+/
-20%
/*
12
PC
8322
00P
F/50
VM
LCC
/+/-1
0%12
PC
5615
00P
F/50
VM
LCC
/+/-1
0% 12
+
PCE
310
0uF/
25V
EL/
Lf_T
=300
0hrs
_105
c/+/
-20%
12
PC
81
1500
PF/
50V
pt_c
0603
MLC
C/+
/-5%1
2
PR872.2Ohmpt_r1206_h265%
12
PR5210KOhm
5%
12
PR7710KOhm1%
1 2
PC
6310
00PF
/50V
MLC
C/+
/-10%
12
PR65
30K
Ohm
5% /*
12
PC570.01UF/16V
MLCC/+/-10%
12 PC58680PF/50V
MLCC/+/-10%
12
PC55220PF/50V
MLCC/+/-10%
12
PC1540.22UF/10Vpt_c0603MLCC/+/-10%
12
PR912.2Ohmpt_r1206_h265%
12
PR
62
499O
hm1%
12
PJP16
4MM_OPEN_5MIL/*
1 21 2
PC
61
1000
PF/
50V
MLC
C/+
/-10%
12
PR671KOhm
1%1 2
PR514.99KOhm 1% /*
12
PC1551UF/10Vpt_c0603
MLCC/+/-10%1
2
PR57147KOhm1%
12
PC781500PF/50Vpt_c0603MLCC/+/-5%
12
PC77
10U
F/25
Vpt
_c12
06_h
71M
LCC
/+/-1
0%
12
PC
8410
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%
12
PR1490Ohmpt_r06035%
12
PR6615KOhm
1%/*
1 2
PR760Ohmpt_r0603
5%1 2
PR4913KOhm
1% /*1 2
PL120.45UH
pt_inductor_4p_453x394_speIrat=25A
21
3 4
PC69
0.03
3UF/
16V
MLC
C/+
/-10%
12
PC1481UF/10Vpt_c0603
MLCC/+/-10%
12
PR591.91KOhmpt_r06031%
12
PC740.22UF/10V
pt_c0603MLCC/+/-10%
12PR902.2Ohmpt_r1206_h265%
12
PR540Ohm 5%1 2
PC
870.
1UF/
50V
pt_c
0603
MLC
C/+
/-10%1
2
PU7
ISL6208CRZ
12
3 4
56
789
BOOTPWM
GN
D1
LGA
TE
VCCFCCM
PHA
SEU
GA
TEG
ND
2
SD
G
PQ17SI4386DY_T1_E3123
5 6 7 8
4
PR737.68KOhmpt_r0805_h241%
12
PR1500Ohmpt_r06035%
12
PR530Ohmpt_r06035%
1 2
PR7015KOhm
1%1 2
PR922.2Ohmpt_r1206_h265%
12
PC
82
0.1U
F/50
Vpt
_c06
03
MLC
C/+
/-10%1
2
PC
91
1500
PF/
50V
pt_c
0603
MLC
C/+
/-5%
12
PC
147
10U
F/25
Vpt
_c12
06_h
71M
LCC
/+/-1
0%
12
+
PCE
410
0uF/
25V
EL/
Lf_T
=300
0hrs
_105
c/+/
-20%
12
PR860Ohmpt_r06035%
12
PC
86
1500
PF/
50V
pt_c
0603
MLC
C/+
/-5%
12
PR501KOhm
1%1 2
G
S
D
PQ22FDS7088SN3
1234
5678
9
PR8210Ohmpt_r06031%
12
PR717.68KOhmpt_r0805_h241%
12
PR7410Ohmpt_r06031%1 2
PR550Ohm 5%
1 2
PR440Ohm5%/*
1 2
PC1490.22UF/10Vpt_c0603MLCC/+/-10%
12
PC79
2200
PF/
50V
MLC
C/+
/-10%1
2
PR
6810
.5K
Ohm
1%
12
PC
6510
00P
F/50
VM
LCC
/+/-1
0%
12
PR8410Ohmpt_r06031%
12
+
PCE
110
0uF/
25V
EL/
Lf_T
=300
0hrs
_105
c/+/
-20%
12
PR
486.
34kO
hm1%
12
PC70
0.01
UF/
25V
MLC
C/+
/-10%
12
PR800Ohmpt_r06035%
12
PC
9010
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%
12
PC
157
10U
F/25
Vpt
_c12
06_h
71M
LCC
/+/-1
0%
12
PR14
547
0KO
HM
pt_r
0603
5%
/*
12
PC64330PF/50V
MLCC/+/-10%12
PR630Ohm5% /*1 2
PL130.45UH
pt_inductor_4p_453x394_speIrat=25A
21
3 4
PR580Ohmpt_r06035%
12
PR882.2Ohmpt_r1206_h265%
12
PR
4733
2Ohm
1%
12
SD
G
PQ21SI4386DY_T1_E3123
5 6 7 8
4
PR600Ohmpt_r06035%
1 2
PC601UF/10Vpt_c0603
MLCC/+/-10%
12
G
S
D
PQ20
FDS7088SN3
1234
5678
9
PC750.22UF/10V
pt_c0603MLCC/+/-10%
12
PC
190
1000
PF/
50V
MLC
C/+
/-10%
/*
12
PC730.22UF/10V
pt_c0603MLCC/+/-10%
12
PC1591500PF/50Vpt_c0603MLCC/+/-5%
12
PJP15
4MM_OPEN_5MIL/*
1 21 2
PR8310Ohmpt_r06031%
12
PC
156
10U
F/25
Vpt
_c12
06_h
71M
LCC
/+/-1
0%
12
PR892.2Ohmpt_r1206_h265%
12
PR757.68KOhmpt_r0805_h241%
12PC72
1UF/10Vpt_c0603MLCC/+/-10%
12
PR1480Ohmpt_r06035%
12
PL140.45UHIrat=25A
pt_inductor_4p_453x394_spe
21
3 4
PR147
6.8KOHM5% pt_r0603
12
PR1460Ohm5%/*
12
PC1580.22UF/10Vpt_c0603MLCC/+/-10%
12
PC590.015UF/16VMLCC/+/-10%
12
PR4382.5KOhm1%
1 2
PC15
210
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%
12
PC
8910
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%
12
PR4611.5KOhm
1%
12
PR640Ohm5%1 2
PU4ISL6260CCRZ_T
123456789
10
11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31
30292827262524232221
41
42
4344
45
PSI#PMONRBIASVR_TT#NTCSOFTOCSETVWCOMPFB
VD
IFF
VS
ENR
TND
RO
OP
DFB
VO
VS
UM
VIN
VS
SV
DD
PG
OO
D3V
3C
LK_E
N#
DP
RS
TP#
DP
RS
LPV
RV
R_O
NVI
D6
VID
5VI
D4
VID
3
VID2VID1VID0
PWM1PWM2PWM3FCCMISEN1ISEN2ISEN3
GN
D
GN
D1
GND2GND3
GN
D4
PU9
ISL6208CRZ
12
3 4
56
789
BOOTPWM
GN
D1
LGA
TE
VCCFCCM
PH
AS
EU
GA
TEG
ND
2
PC622200PF/50VMLCC/+/-10%
/* 12
PR722.43KOhm
1%1 2
PC76
10U
F/25
Vpt
_c12
06_h
71M
LCC
/+/-1
0%
12
PT1
TPC
32T
1
PC66
0.1U
F/10
VM
LCC
/+/-1
0%/*
12
PC
670.
1UF/
16V
MLC
C/+
/-10%1
2
PR610Ohm5% /*1 2
PC
710.
01U
F/50
VM
LCC
/+/-1
0%12
PR
451.
69K
Ohm
1%1
2
PC15
110
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%
12
PC68
0.33
UF/
16V
pt_c
0603
MLC
C/+
/-10%
12
PC80
0.1U
F/50
Vpt
_c06
03M
LCC
/+/-1
0%
12
G
S
D
PQ18FDS7088SN3
1234
5678
9
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
PLACE THESE CAPS CLOSE TO FETS
PLACE THESE CAPS CLOSE TO FETS
OCP point min. 13.14AMaximum current:8.78A
3.3 Volt +/-5%Design Current:6.14A
Maximum current:8.72AOCP point min. : 8.82A
5 Volt +/-5%Design Current:6.11A
For debug
POWER_SYSTEM 5V_ALW&3.3V_ALW1.2Lanai <OrgName>54 68
Monday, March 19, 2007
JEFFPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
+5V_ALWP_L
+5V
_BS
CS1 CS2
+3.3V_BS
+3.3V_ALWP_L
+3.3V_DL
+5V_VBST
+5V_DL
CS
1
CS
2
3V_5V_POK+3.3V_VBST
+5V_VFB
+3.3V_DH
3V_5V_POK
+5V_DH
TONSEL
+10V_ALWP
THERM_STP#
TONSEL
3V_5V_POK +5V_DL
+5V_PMP
+3.3V_VFB
ALWON37
RUN_ON28,37,49,51
THERM_STP#43
ALW_PWRGD_3V_5V 37
EC_PWM_237
+5V_ALW2
+VCC_TPS51120
+PWR_SRC+DC1_PWR_SRC
+3.3V_ALWP
+VCC_TPS51120
+VCC_TPS51120
+15V_ALWP
+5V_ALWP
+3.3V_ALWP
+15V_ALWP +15V_ALW
+5V_ALW+5V_ALWP
+3.3V_ALW
+3.3V_RTC_LDO
+5V_ALWP
+VCC_TPS51120
+VCC_TPS51120
+VCC_TPS51120
+DC1_PWR_SRC
GND
GN
D
GND
GND GND
GND
GND
GND
+3.3V_RTC_LDO +3.3V_ALW
GND
+3.3V_ALWP
GND
GND
GNDGND
GND
GND
GND
GND
GND
GND
GNDGND
+5V_ALWP
GND
+5V_ALW2
GND
GND
GND
GND
+5V_ALWP
PR1741KOhm1%
1 2
PD12
RB
717F
pt_s
ot32
3/*
1 23
DS
G1
2 3
PQ37FDN340P_NL
/*
1
2 3
PR
187
47K
Ohm 5%
12
PC1881UF/25Vpt_c0603MLCC/+/-10%
12
SD
GPQ
48FD
S66
76AS
1235 6 7 8
4
PC
960.
1UF/
25V
pt_c
0603
MLC
C/+
/-10% 1
2
PR1720Ohm5%
12
PC1731000PF/50Vpt_c0603
MLCC/+/-10%1 2
PR16323.2KOhm
1%1 2
PR
173
200K
Ohm
5%1
2
PC
178
0.1U
F/25
Vpt
_c06
03M
LCC
/+/-1
0%1
2
PR17
00O
hm/*
5%1
2
A
B
GND
VCC
Y
PU11
SN74LVC1G00DCKR
1
2
3 4
5
PC
175
2200
PF/5
0VM
LCC
/+/-1
0%12
PR
167
0Ohm 5%
12
SD
GPQ
44S
I439
2DY-
T1-E
3
1235 6 7 8
4
PJP18
2MM_OPEN_5mil/*
1 21 2
PR
182
9.76
KO
hm1%
12
PR944.7KOhm
5%/*
12
PR179
0Ohmpt_r06035% /*
12
PR1610Ohmpt_r06035%/*1
2
PC
9810
UF/
16V
pt_c
1206
_h71
MLC
C/+
/-10%
12
PL3
3.3UHIrat=8.8A
pt_inductor_2p_453x394
21
SD
G
PQ
46S
I480
0BD
Y
1 2 35678
4
PL15
3.3UHIrat=8.8A
pt_inductor_2p_453x394
21
SD
G
PQ
43FD
S66
90AS
1 2 35678
4
DS
G1
2 3
PQ45BSS84LT1G/*
1
2 3
PC
184
1000
PF/
50V
pt_c
0603
MLC
C/+
/-10%1
2
PR
168
0Ohm
/*5%
12
PC
191
0.1U
F/25
Vpt
_c06
03M
LCC
/+/-1
0%
/*
12
PJP8
4MM_OPEN_5MIL/*
1 21 2
PR
169
0Ohm
/*5%
12
PR17
10O
hm 5%1
2
GS
D3
2
1PQ472N7002/*
PC
179
0.1U
F/25
Vpt
_c06
03M
LCC
/+/-1
0%
12
PR
159
0Ohm
pt_r
0603
5%
/*
12
PC
182
0.1U
F/50
Vpt
_c06
03M
LCC
/+/-1
0%1
2
PC
9510
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%1
2
PR1640Ohm
/*5%12
PR1850Ohm5%
12
GS D
32
1PQ232N7002/*
PD20BAT54
321
PC1811UF/25Vpt_c0603MLCC/+/-10%
12
PR188
0Ohm5%
12
PJP17
4MM_OPEN_5MIL/*
1 21 2
PR
160
40.2
KO
hm1%
12
PR18347Ohmpt_r0603
5%12
PR1800Ohm5%/*
12
PR
158
10K
Ohm
pt_r
0603
1%1
2
PR166200KOhm5%/*
12
PC
97
1000
PF/
50V
pt_c
0603
MLC
C/+
/-10%1
2
PC
183
1UF/
10V
pt_c
0603
MLC
C/+
/-10%
12
PU10B TPS51120RHBR
34 35 36 37 38 39 40 41 42
GN
D3
GN
D4
GN
D5
GN
D6
GN
D7
GN
D8
GN
D9
GN
D10
GN
D11
PR1650Ohm
/*5%12
PC1801UF/25Vpt_c0603MLCC/+/-10%
12
+
PC
9433
0UF/
6.3V
pt_c
7343
d_h1
18TA
N/L
f_T=
2000
hrs_
105C
/+/-2
0%1
2
PC161
0.01UF/25Vpt_c0603
MLCC/+/-10%/*
1 2
PR
103
12.4
KO
hm1%
12
PC
176
0.1U
F/50
Vpt
_c06
03M
LCC
/+/-1
0%12
PC
186
1UF/
10V
pt_c
0603
MLC
C/+
/-10%
12
PJP7
4MM_OPEN_5MIL/*
1 21 2
PC
172
2200
PF/5
0VM
LCC
/+/-1
0%12
PR176100KOhm5%
12
GS
D3
2
1
PQ502N7002
PC99
10U
F/16
Vpt
_c12
06_h
71M
LCC
/+/-1
0%1
2
PR932.2MOhm
5%/*
12
PR
178
0Ohm
pt_r
0603
5%
12
PR
175
0Ohm
/*5%
12
PC
9310
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%1
2
PC
174
10U
F/25
Vpt
_c12
06_h
71M
LCC
/+/-1
0%
12
PC16
50.
1UF/
25V
pt_c
0603
MLC
C/+
/-10%1
2
PU10A
TPS51120RHBR
1 2 3 4 5 6 7 8
910111213141516
1718192021222324
252627282930313233
VO
1C
OM
P1V
FB1
VR
EF2
GN
D1
VFB
2C
OM
P2V
O2
EN5EN3
PGOOD2EN2
VBST2DRVH2
LL2DRVL2
PG
ND
2C
S2V
REG
3V5
FILT
VR
EG5
VIN
CS1
PG
ND
1
DRVL1LL1DRVH1VBST1EN1PGOOD1TONSELSKIPSELGND2
PD19BAT54S
pt_sot23_philips
12
3
12
3
PR
162
10KO
hmpt
_r06
031%
12
PD18BAT54S
pt_sot23_philips12
3
12
3
+
PC16
333
0UF/
6.3V
pt_c
7343
d_h1
18TA
N/L
f_T=
2000
hrs_
105C
/+/-2
0%
12
PR
177
0Ohm
pt_r
0603
5%
12
PC1851UF/25Vpt_c0603MLCC/+/-10%
12
PC
192
0.1U
F/25
Vpt
_c06
03M
LCC
/+/-1
0%
/*
12
PR186
120Ohm5%
12
PC16
04.
7UF/
10V
pt_c
1206
_h71
MLC
C/+
/-10%
/*
12PD10
BAT54/*
321
PR1810Ohm5%
12
PC
187
1UF/
25V
pt_c
0603
MLC
C/+
/-10%1
2
PC
177
0.1U
F/50
Vpt
_c06
03M
LCC
/+/-1
0%
12
PC
171
10U
F/25
Vpt
_c12
06_h
71M
LCC
/+/-1
0%12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
OCP point min. 11.91A
1.05 Volt +/-5%
Maximum current:17.75ADesign Current:12.42A
OCP point min. : 9.37A
1.5 Volt +/-5%
Maximum current:4.31ADesign Current: 3.02A
For debug
TI request to change.
(OCP point typ.: 15.71A)
POWER_I/O_1.5VS & 1.05VS1.2Lanai <OrgName>55 68
Monday, March 19, 2007
JEFFPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
+1.5V_LG
+DC2_PWR_SRC
+1.5V_HG
+1.05V_VCCP_P
+1.0
5V_V
5FIL
T
+1.0
5V_V
5FIL
T2_L
+1.5
V_V
BST
+1.5
V_V
5FIL
T2_L
+1.5
V_V
5FIL
T
+1.05V_VCCP_P_L
+1.0
5V_V
BST
+1.5V_PG1
RUN_1.5VO
+1.5V_PG1
RUN_1.05VO
RUN_1.05VO+1.05V_HG
+1.05V_LG
+1.5V_RUN_P_L
+1.5V_RUN_P
+1.05V_VCCP_P
+1.05V_BS+1.5V_BS
+DC2_PWR_SRC
+1.05V_PG2
+1.05V_PG2+1.5V_RUN_P
RUN_1.5VO1.5V_RUN_ON37
1.05V_RUN_ON38
1.5V_RUN_PWRGD51
1.05V_RUN_PWRGD51
+1.5V_RUN_P
+5V_SUS
+5V_SUS
+1.5V_RUN
+1.05V_VCCP_P
+5V_SUS+PWR_SRC
+1.05V_VCCP
GND
GND
GND
GNDGND
GND
GND
GND
GND
GND
PR310Ohm
5%
12
PC
120
1UF/
10V
pt_c
0603
MLC
C/+
/-10%1
2
PR35
15KO
hmpt
_r06
031%
12
PR300Ohm
5%
12
PC39
1UF/
10V
pt_c
0603
MLC
C/+
/-10%1
2
PC12
40.
1UF/
10V
MLC
C/+
/-10%1
2
PC32
10U
F/25
Vpt
_c12
06_h
71M
LCC
/+/-1
0%
12
PC28
0.1U
F/50
Vpt
_c06
03M
LCC
/+/-1
0%12
PC
4110
0PF/
50V
MLC
C/+
/-5%1
2
SD
G
PQ8FDS8880
1235 6 7 8
4
+
PC13
733
0UF/
2.5V
pt_c
7343
d_h7
9TA
N/L
f_T=
2000
hrs_
105C
/+/-2
0%
12
PR
130
10O
hmpt
_r06
035%
12
PR1330Ohm5%
12
PC
2622
00P
F/50
VM
LCC
/+/-1
0%
12
PJP10
4MM_OPEN_5MIL/*
1 21 2
PR1315.6KOhm1%
12
SD
G
PQ7
FDS8
880
1 2 35678
4
PJP9
4MM_OPEN_5MIL/*
1 21 2
PJP11
4MM_OPEN_5MIL/*
1 21 2
PC
126
1UF/
10V
pt_c
0603
MLC
C/+
/-10%1
2
G
S
D
PQ10
FDS7088SN3
1234
5678
9
PC12
210
UF/
25V
MLC
C/+
/-10%
pt_c
1206
_h71
12
PC1290.1UF/25Vpt_c0805_h53MLCC/+/-10%1 2
+
PC13
533
0UF/
2.5V
pt_c
7343
d_h7
9TA
N/L
f_T=
2000
hrs_
105C
/+/-2
0%
12
PC
370.
1UF/
10V
/*M
LCC
/+/-1
0%12
PR
2511
.8KO
hmpt
_r06
031%
12
PC350.1UF/25Vpt_c0805_h53MLCC/+/-10%1 2
PR140210KOhm1%
1 2
PD17BAT54A
pt_sot23_philips/*
12
3
PC12
810
UF/
6.3V
pt_c
1206
_h35
MLC
C/+
/-10%1
2
PR36
15KO
hmpt
_r06
031%
12
PC31
39P
F/50
VM
LCC
/+/-5
%12
PC
360.
1UF/
10V
/*M
LCC
/+/-1
0% 12
PC13
610
UF/
6.3V
pt_c
1206
_h35
MLC
C/+
/-10% 1
2
PC13
30.
1UF/
10V
MLC
C/+
/-10% 1
2
PL9
1UHIrat=14.3A
pt_inductor_2p_453x394
21
PC33
2200
PF/5
0VM
LCC
/+/-1
0%12
PR1410Ohm5%
12
PC
2910
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%1
2
PJP12
4MM_OPEN_5MIL/*
1 21 2
PU2
SN0508073PWR
123456789
1011121314 15
16171819202122232425262728PGND1
DRVL1V5DRV1TRIP1LL1DRVH1VBST1EN_PSV2TON2VOUT2V5FILT2VFB2PGOOD2GND2 PGND2
DRVL2V5DRV2
TRIP2LL2
DRVH2VBST2
EN_PSV1TON1
VOUT1V5FILT1
VFB1PGOOD1
GND1P
C30
0.1U
F/50
Vpt
_c06
03M
LCC
/+/-1
0%
12
+
PC12
533
0UF/
2.5V
pt_c
7343
d_h7
9TA
N/L
f_T=
2000
hrs_
105C
/+/-2
0%
12
PR1429.53KOhm1%
1 2
PC12
710
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%
12
SD
G
PQ9
FDS
6670
AS
1 2 35678
4
PC401UF/10V
pt_c0805_h33MLCC/+/-10%
12
PC11
81U
F/10
Vpt
_c08
05_h
33
MLC
C/+
/-10%
12
PR
34
10O
hmpt
_r06
03 5%
12
PL8
1UHIrat=14.3A
pt_inductor_2p_453x394
21
PR23
29.4
KOhm
pt_r
0603
1%
12
PR134200KOhm1%
1 2
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
VCOMP
VDD
4
14
INTERSIL
Charge Current:4.68ADischarge current:6.6A
Maxim requestto add
V=0.975V,I=3.25A
FOR GPRS IMMUNITY
PLACE AS CLOSE TO THE
IC AS POSSIBLE
FOR GPRS IMMUNITY PLACE
AS CLOSE TO THE IC AS
POSSIBLE
16
3.17
90
PIN NAME DIFFERENCES
TABLE1
NC
TRIP CURRENT (A)
65
17
ADAPTOR (W)
11
PR123
4.43
PR121
57.6K
130
5
VREF
6
ICOMP
MAXIM
NC
GND
8
REF
ICM
CCS
3
20.5K
VDDSMB
13.0K
CCI
17.8K
TABLE3
24.9K
100
105
150
348
PR122PR126
7.43
15
6.43
18
51.1K
32.4K
30.9K
25
24
21
BATSEL
FBSB
FBSA
432
27.4K
N/A
33.2K
20
88.7K
23
DLO
CSIN
LDO
NC
NC
VFB
CSON
LGATE
CSIP CSOP
CCV
LX
VDDP
UGATE
BST
DHI
MAXIM & INTERSIL BOM DIFFERENCES
PC17
PHASE
PR19
DAC
REF DES
PIN
BOOT
PR21
"NC"
TOTAL POWER=65W-->3.34A
PC8
means no-connect
PR108
PC19
PR9
PC18
PC22
PR8
1
PC4
PR22
PC115
TABLE2
PC13
PC21
PR125
PC23
IINP
PC24
0, 0402, 5%
No Stuff
No Stuff
PD16
0.01uF
MAXIM
0.1uF, 0402, 10V
8.45K, 0402, 1%
220pF, 0402, 50V
0.01uF
RB751V-40
0.1uF, 0402, 10V
1.0uF, 0603, 10V
365K, 0402, 1%
0, 0402, 5%
16.0K, 0402, 1%
215K, 0402, 1%
10, 0402, 5%
INTERSIL
0.22uF
No Stuff
No Stuff
No Stuff
3.3nF
1, 0603, 1%
10, 0402, 5%
100, 0402, 5%
4.7K, 0402, 5%
0.01uF
0.01uF
No Stuff
0, 0603, 5%
0, 0402, 5%
7
4.7K, 0402, 5%
0.01uF
0.22uF
0.01uF
No Stuff
No Stuff
No Stuff
No Stuff
NC
9.75 30128K 36.5K200
Note 1: PR122 is populated if ADAPT_TRIP_SET isused to program for the next lower adaptor
19.1K
No stuff
1K, 0603, 5%PR12
PD3 1SS355
No stuff
ADAPT_TRIP_SET is floating for the higheradaptor, grounded for the lower adaptorNote 2: 24.9K at PR122 allows the 65W adaptorsetting to switch down to 45W. (now is N/A)Note 3: PR109 must be 5m ohm instead of 10m ohmfor the 230W adaptor
230 32.4K 1156.49K N/A11.28
POWER_CHARGER1.2Lanai <OrgName>57 68
Monday, March 19, 2007
JEFFPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
BAT_REF
CH
G_B
ST_
L
CHG_DLO_L
INP
LDO
CH
G_L
X_L
BAT_REF
CHG_CSSP_L
CH
G_D
HI_
L
CH
G_C
SSN
_L
ACAV_IN
+VCHGR_L
+DC_IN_SS_X
LDO
CHG_VCC_L
INP
OC TRIP
+VCHGR_LX
CHG_CSIP_L
CH
G_C
SIN
_L
ACAV_IN
PBAT_SMBCLK37,59
PBAT_SMBDAT37,59
ADAPT_TRIP_SEL38
ADAPT_OC 38
ACAV_IN 37,43
+VCHGR
GND
GND_CHA
GND
GND
GND
+5V_ALW
+5V_ALW
GND
GND_CHA
+PBATT
GND_CHA
GND_CHA
+5V_ALW
GND
GND
GND
CHRG_IN
GND_CHA
GND
GND_CHA
+VCHGR
GND_CHA GND_CHA
+PWR_SRC
GND
+DC_IN_SS
GND_CHA
+3.3V_ALW
+VCHGR
GND_CHA
+DC_IN_SS
GND
S D
G
PQ3
SI4835BDY-T1-E3
123
5678
4
PC40.22UF/10Vpt_c0603MLCC/+/-10%
/*1 2
PC
1122
00PF
/50V
MLC
C/+
/-10%
12
PR11910mOhmpt_r2512_4p_h33
1%1 2
34
PR1160Ohmpt_r06035%
12
PC1130.01UF/16VMLCC/+/-10%
12
PR110100KOhm5%
12
PC11
610
0PF/
50V
/*M
LCC
/+/-5
%
12
PR128100KOhm1%
12
PC11UF/10Vpt_c0603
MLCC/+/-10%1 2
PR1110KOhm1%
12
SD
G
PQ
5S
I480
0BD
Y
1235 6 7 8
4
G
S
D
1
3
2
PQ34RHU002N06
2
31
D
SG
PQ4
SI4
810B
DY
-T1-
E3
5 6 7 8
1
4
2 3
PR1181MOhm
1%1 2
PR1258.45KOhm1%
12
PR191Ohmpt_r06031%
12
PR130Ohm5%
12
PC1070.01UF/16VMLCC/+/-10%
12
PC190.22UF/10V
pt_c0603MLCC/+/-10%
/*1 2
PC161UF/10Vpt_c0603
MLCC/+/-10%1 2
PD
16R
B75
1V_4
01
2
PU5
LM393DR
1234 5
678VOUT1
VIN1-VIN1+GND VIN2+
VIN2-VOUT2
VCC
PR124
0Ohm5%
1 2
PC114100PF/50V
MLCC/+/-5%
12
PC11
110
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%1
2
PC108100PF/50V
MLCC/+/-5%
12
PC112100PF/50V
MLCC/+/-5%
12
PR117100KOhm
1%
12
PU1
MAX8731AETI
1234567
8 9 10 11 12 13 14
15161718192021
2223242526272829
GND1ACINREFCCSCCICCVDAC
IINP
SD
AS
CL
VD
DG
ND
2A
CO
KB
ATS
EL FBSAFBSBCSINCSIP
PGNDDLOLDO
DC
INLXDH
IB
STV
CC
CSS
NC
SS
PG
ND
3
GS
D3
2
1PQ35
2N7002
PC11
710
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%1
2
PR10910mOhm
pt_r2512_4p_h331%
1 234
PC220.01UF/25VMLCC/+/-10%
12
PC32200PF/50V
/*MLCC/+/-10%
12
PR12233.2KOhm
1%/*
1 2
PR1015.8KOhm1%
12
PR112470KOhm5%
12
PC
140.
1UF/
25V
pt_c
0603
MLC
C/+
/-10%
12
PC241UF/10Vpt_c0603
MLCC/+/-10%
12
PC
109
10U
F/25
Vpt
_c12
06_h
71M
LCC
/+/-1
0%12
PC210.01UF/25VMLCC/+/-10%
12
SD
G
PQ
6
SI4
800B
DY
1235 6 7 8
4
PC8220PF/50VMLCC/+/-10%
12
PC150.1UF/25Vpt_c0603MLCC/+/-10%
12
PC230.01UF/25VMLCC/+/-10%
12
PR11433Ohmpt_r0603
5%
12
PC11
010
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%1
2
PJP1
4MM_OPEN_5MIL/*
1 21 2
PR121KOhm
5%pt_r0603
/*12
PR12313KOhm
1%
12
PR9100Ohm5%
1 2
PC
1333
00PF
/50V
MLC
C/+
/-10%
12
PC100.1UF/10VMLCC/+/-10%
12
PR12049.9KOhm
1%
12
PR12157.6KOhm1%
12
PC51UF/25Vpt_c0805_h57MLCC/+/-10%1
2
PR126105Ohm
1%
12
PR108365KOhm
1%
12
PC180.1UF/10VMLCC/+/-10%
12
PC1150.01UF/16VMLCC/+/-10%
12
PC7
0.1U
F/50
Vpt
_c06
03M
LCC
/+/-1
0%
12
PR2210KOhm5%
12
SD
G
PQ33
SI4835BDY-T1-E3
123
5678
4
PL7
5.2UHIrat=5.5Apt_inductor_2p_398x394
21
PR
127
1KO
hm1% /*
12
PC20.1UF/50V
pt_c0603
/*MLCC/+/-10%
12
PC200.01UF/25VMLCC/+/-10%
12
PR80Ohm
5%
12
PD31SS355
/*
12
PR210Ohm
5%
12
PR1891.8KOhm5%pt_r1206_h26
/*12
PR11110KOhm5%
1 2
PC6
10U
F/25
Vpt
_c12
06_h
71M
LCC
/+/-1
0%12
PR1130Ohmpt_r06035%
12
G
S
D
1
3
2
PQ51RHU002N06
/*2
31
PC170.1UF/10VMLCC/+/-10%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Change to low profile
FOR LAYOUT ISSUE
Design Current:0.93AMaximum current:1.33AOCP point min. : 6.54A
1.25Volt +/-5%
Maximum current: 9.42AOCP point min. : 16.93A
Design Current: 6.59A1.8Volt +/-5%
0.9Volt +/-5%
Maximum current:1.5ADesign Current:1.05A
For debug
For debug
For debug
For debug
TI request to change.
No.32
No.38
POWER_VGA_1.25V & DDR & VTT1.2Lanai <OrgName>58 68
Monday, March 19, 2007
JeffPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
+DC3_PWR_SRC
+DC3_PWR_SRC
+1.8
V_V
5FIL
T
VG
A_1.
25V
_VB
ST
+1.8
V_V
BST
+1.8V_SUSP
+1.8V_DL
+1.25V_PG1
VGA_1.25V_DH
VGA_1.25V_DL
VGA
_1.2
5V_L
+1.25V_PG1
DDR_ON_P
DDR_ON_P
+1.25V_V5FILT
+1.8V_SUS_L+1.8V_DH
VGA_1.8V_BSVGA_1.25V_BS
+1.8V_SUSP
+1.8V_PG2
+1.8V_PG2
+1.25V_SRC_MP
+1.25V_SRC_MP
+1.8V_SUSP_VLDOIN&VDDQSNS
DDR_ON37
1.25V_RUN_PWRGD51
0.9V_DDR_VTT_ON37
1.25V_RUN_ON 37
1.8V_SUS_PWRGD37
+5V_SUS
+1.8V_SUSP
+PWR_SRC
+1.8V_SUS
+1.25V_SRC_MP
+1.25V_SRC_MP
+5V_ALW+1.8V_SUSP +0.9V_DDR_VTT+0.9V_P
+1.25V_RUN
+3.3V_ALW
V_DDR_MCH_REF
GND
GND
GND
GND
GND
GND
+5V_SUS
GND
+5V_SUS
GND
GNDGND
GND
GND
+3.3V_SUS
PC
440.
1UF/
50V
pt_c
0603
MLC
C/+
/-10%1
2
PC
130
1UF/
10V
pt_c
0603
MLC
C/+
/-10%
12
PC
4622
00PF
/50V
MLC
C/+
/-10%1
2P
R13
214
KO
hmpt
_r06
031%
12
PC
250.
1UF/
10V
/*M
LCC
/+/-1
0% 12
+
PC
144
330U
F/2.
5Vpt
_c73
43d_
h79
TAN
/Lf_
T=20
00hr
s_10
5C/+
/-20%
12
PJP14
4MM_OPEN_5MIL/*
1 21 2
PC11
91U
F/10
Vpt
_c08
05_h
33M
LCC
/+/-1
0%1
2
PR1360Ohm 5%
12
PC
4210
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%1
2
PC
123
1UF/
10V
pt_c
0603
MLC
C/+
/-10%
12
PC
470.
1UF/
50V
pt_c
0603
MLC
C/+
/-10%
12
SD
G
PQ13FDS8880
1235 6 7 8
4
PC1310.1UF/25V
pt_c0805_h53MLCC/+/-10%
1 2
D2S2
D2G2
S1
G1
D1
D1
Q1
Q2
PQ11
FDS6982AS
5
6
7
81
2
3
4
PR28
10O
hm5%
12
PU6
SN0508073PWR
123456789
1011121314 15
16171819202122232425262728PGND1
DRVL1V5DRV1TRIP1LL1DRVH1VBST1EN_PSV2TON2VOUT2V5FILT2VFB2PGOOD2GND2 PGND2
DRVL2V5DRV2
TRIP2LL2
DRVH2VBST2
EN_PSV1TON1
VOUT1V5FILT1
VFB1PGOOD1
GND1
PR13
89.
53KO
hm1%
12
PC
4522
00PF
/50V
MLC
C/+
/-10%
12
PC13
910
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%
12
+
PC
141
330U
F/2.
5Vpt
_c73
43d_
h79
TAN
/Lf_
T=20
00hr
s_10
5C/+
/-20%
12
PR380Ohm 5%
12
PC1341UF/10V
pt_c0805_h33MLCC/+/-10%
12
PR27200KOhm
5%1 2
PC38
0.1U
F/10
V/*
MLC
C/+
/-10%1
2
PC5010UF/6.3Vpt_c0805_h53MLCC/+/-10%
12
PJP4
2MM_OPEN_5mil/*
1 21 2
PJP13
4MM_OPEN_5MIL/*
1 21 2
PJP5
4MM_OPEN_5MIL/*
1 21 2
PR
129
10KO
hmpt
_r06
031%
12
PC4810UF/6.3Vpt_c0805_h53MLCC/+/-10%/*
12
PR32150KOhm1%
1 2
PC511UF/10Vpt_c0603MLCC/+/-10%
12
PR
137
10O
hm5%
12
+
PC
145
220U
F/2.
5Vpt
_c73
43d_
h75
TAN
/Lf_
T=20
00hr
s_10
5C/+
/-20%
12
PJP3
4MM_OPEN_5MIL/*
1 21 2
PR13
922
.6KO
hmpt
_r06
031%
12
PL10
1UHIrat=14.3A
pt_inductor_2p_453x394
21
PR
2410
0KO
hm1%
12
PC
140
10U
F/6.
3Vpt
_c12
06_h
35M
LCC
/+/-1
0% 12
PC5410UF/6.3Vpt_c0805_h53MLCC/+/-10%
12
PU3
TPS51100DGQ
12
3
4
56
78
9
10
11
VDDQSNSVLDOIN
VTT
PGND
VTTSNSVTTREF
S3GND1
S5
VIN
GND2
PC13
810
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%1
2
PJP6
2MM_OPEN_5mil/*
1 21 2
PC490.1UF/10VMLCC/+/-10%
12
PD8BAT54A
pt_sot23_philips
12
3
PC13
210
0PF/
50V
MLC
C/+
/-5%
12
PR410Ohm 5%
12
PC
121
39PF
/50V
MLC
C/+
/-5% 1
2
PC340.1UF/25V
pt_c0805_h53MLCC/+/-10%
1 2
PL11
0.88UHIrat=17A
pt_inductor_2p_453x394
21
PC
142
0.1U
F/10
VM
LCC
/+/-1
0%12
PR14
315
KOhm
pt_r
0603 1%
12
PR
3310
0KO
hm1%
/* 12
SD
G
PQ12FDS6676AS
1235 6 7 8
4
PR26
12.4
KO
hm1%
12
PC
143
0.1U
F/10
VM
LCC
/+/-1
0% 12
PC
271U
F/10
V
pt_c
0603
MLC
C/+
/-10%
12
PC
4310
UF/
25V
pt_c
1206
_h71
MLC
C/+
/-10%
12
PR290Ohm5%
12
PR1350Ohm5%
12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
TDC REQUSET TO CHANGE
CONFIRM JAY EE REQUEST TO
DE-POP
ESD DIODES
POWER_CONNECTOR1.2Lanai <OrgName>59 68
Monday, March 19, 2007
JEFFPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
BATT_VOLTBATT1-
Z4305 SMB_DATZ4306 BATT_PRES#
BATT2-
SYSPRES#
+DCIN_JACK
Z4304 SMB_CLKBATT+_IN
PS_ID 37
PBAT_SMBDAT 37,57
PBAT_ALARM#
PBAT_SMBCLK 37,57
AC_OFF37
PBAT_PRES# 38
PS_ID_DISABLE# 38
GND
GND
+3.3V_ALW
GND
+DC_IN_SS
+3.3V_ALW
GND
GND
+DC_IN
+3.3V_ALW
GND
+3.3V_ALW
+5V_ALW
GND
+5V_ALW
GND
GND
GND
+PBATT
PD2DA204Upt_sot323_rohm
213
PR14100Ohm
5%
1 2
PR18100Ohm
5%1 2
PC
102
0.01
UF/
25V
MLC
C/+
/-10%
12
PD1DA204Upt_sot323_rohm/*
213
PC
104
0.1U
F/50
Vpt
_c06
03M
LCC
/+/-1
0% 12
PR16100Ohm
5%1 2
PR17100Ohm
5%
1 2
PCON1
DC_PWR_JACK_5Ppt_dc_pwr_jack_5p_6hold_lf2
12345
6789
10
11
12345
P_NC1NP_NC1NP_NC2P_NC2
P_NC3
P_NC4
PR333Ohm5%
1 2
PL6
60Ohm/100Mhzpt_l1806
MURATA/BLM41PG600SN1L
2 1
PD5
DA204Upt_sot323_rohm
213
PC
1222
00PF
/50V
MLC
C/+
/-10% 1
2
PR10547KOhm5%
12
PR
106
4.7K
Ohm
pt_r
0805
_h24
5%1
2P
R7
2.2K
Ohm
5%
12PD15
MBRS2040LT3Gpt_smb_h101
/*1
2
S D
G
PQ32FDS6679_NL
123
5678
4
PC
100
10U
F/25
Vpt
_c12
06_h
71M
LCC
/+/-1
0% 12
PR210KOhm
5%/*
1 2PR104100KOhmpt_r0603
5%
12
PL4
1000Ohm/100MHzpt_l0603
FERRITE BEAD(0603)1000OHM/0.1A
21
PC
101
0.47
UF/
25V
pt_c
0805
_h53
MLC
C/+
/-10%
12
PD4
DA204Upt_sot323_rohm/*
213
PD6
DA204Upt_sot323_rohm
213
DS
G1
2 3
PQ2SI2301BDS
/*
1
2 3
BC
E
1
2
3
PQ30PMBS3904
PD14
VZ0603M260APTpt_varistor_0603/*
12
PR60Ohm5%/*
12
PC
90.
1UF/
50V
pt_c
0603
MLC
C/+
/-10% 1
2
PR
107
240K
Ohm
1%1
2
PR
1510
KO
hm5%
12
PR133Ohm5%/*
1 2
G
SD
1
3 2
PQ31
FDV301N_NLpt_sot23
1
3 2
R1
R2E
CB
1
2
3
PQ1DTC115EUApt_umt3_rohm_h39/*
PR4
15K
Ohm
pt_r
0603
5%
12
PR
2010
0KO
hm5%
/*
12
PD7
DA204Upt_sot323_rohm
213
PCON2
BATT_CON_9P
123456789
10
11
123456789
P_GND1
P_GND2
PC1050.1UF/25Vpt_c0603
/*MLCC/+/-10%
12
PR510KOhm5%
12
PC
103
0.1U
F/50
Vpt
_c06
03M
LCC
/+/-1
0% 12
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
GM screw pad
13G021049200DE
13G021052020DE13G021052020DE
13G021049200DE
CPU
13G021049200DE 13G021052010DE
Header2 13G021052030DE
SATA
SCREW PAD1.2Lanai 60 68
Monday, March 19, 2007Sean KuoPROJECT: SHEET OF
DATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :RELEASE DATE :
H27
O43X98DO20X75
1
H25
ESA1-1A_NUT_H0.4
H31
CT295B276I162D142
1
H11
ESA1-1A_NUT_M2_H7_2
H26
CRT394X413B394D138
1
H28
CT315B394I158D138
1
H13
CT315B394I158D138
1
H6
O118X98DO118X98N
1
H30
CT295B276I162D142
1
H37
O43X98DO20X75
1
H36
CT315B394I158D138
1
H34
ESA1-1A_NUT_H0.4
H32
CT295B276DO138X154
1
H35
CRT394X413B394D138
1
H29
crt413x394b394d138
1
H17
ESA1-1A_NUT_M2_H2.5_3
H8
C98D98N
1
H18
ESA1-1A_NUT_M2_H8
H14
CT315B394I158D138
1
H21
CT138B295D118
1
H10
O47X31DO47X31N
1
H1
C256I138D118
1
H3
CRT354X315B394D138
1
H15
CT295B276I158D138
1
H24
CRT335X386B276D138
1
H2
CT315B295I158D118
1
H5
ESA1-1A_NUT_M2_H2.5_1
H7
ESA1-1A_NUT_M2_H2.5_2
H4
CRT337X413B394D138
1
H9
ESA1-1A_NUT_M2_H7
H20
CT236B217D102
1
H12
RT197X413D91
1
SPRING1
EMI_SPRING_PAD/*
11
H33
CT236B217D102
1
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
Lanai:Modem Board
ASUS CONFIDENTIALElsaMODEL NAME :
Jack2P
WtoB2Pcontrol signals
RJ11 BOARD
REV : 1.1(DELL: X01)
BLOCK DIAGRAM1.2Lanai 64 68Monday, March 19, 2007
Stanly_HsuPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
JOHANSON isnot in the QVL
No. 1.
RJ-11 CONN1.2Lanai <OrgName>65 68
Monday, March 19, 2007
Stanly_HsuPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
RJ_RING
RJ_TIP
RJ_RING_R
RJ_RING
RJ_TIPRJ_TIP_R
MGND
MGNDMGND
MGND
ML1 470OhmIrat=0.2A
MURATA/BLM18RK471SN1D
21
MH2
C276D165
1
MH1
CT217BDO91X106
1
MC
133
0PF/
3KV
pt_c
1808
_h65
MLC
C/+
/-10%1
2
ML2 470OhmIrat=0.2A
MURATA/BLM18RK471SN1D
21
MC
233
0PF/
3KV
pt_c
1808
_h65
MLC
C/+
/-10%1
2
MCON2
WTOB_CON_2PMOLEX/53398-0271
1
2
3
4
1
2
SIDE1
SIDE2
MCON1
MODULAR_JACK_2P
1
2
3
4
5
6
1
2
NP_NC1
NP_NC2
P_GND1
P_GND2
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
REV : 1.1(DELL: X01)
???
PCB P/N: ???
ASUS P/N :
Lanai PP2 USB Board
???
BOM NO. ???
ElsaMODEL NAME :
ASUS CONFIDENTIAL
PCB NO :
Cover Page1.2Lanai 67 68Monday, March 19, 2007
Terry_LinPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
Part Number Description
DA800004H0L PCB 00B LA-3071P REV0 M/B
MB PCB
A
A
B
B
C
C
D
D
E
E
1 1
2 2
3 3
4 4
5 5
USB daughter board connector
Platforms should put in PADS for the USB chokes if theyhave the room. Chokes should be NOPOP.
External USB PORT hookup reference. Your design mayneed more or less external ports and may be mappeddifferently .
Place ESD diodes as close as USB connector. SemtechSRV05-4 can also be used but the Philips IP42220CZ6 havea lower input C ( 1pf vs 3pf ).
Consult you ESD Engineer if you think you may need toadd ESD Supression Components to your USB lines.Add PADS ONLY until proven diodes are really needed.
Each channel is 1A
Place one 150uF cap by eachUSB connector
Screw hole
USB PORT ( SINGLE * 2 )1.2Lanai <OrgName>68 68
Monday, March 19, 2007
Terry_LinPROJECT: SHEET OFDATE:REVISION DESCRIPTION: DESIGN ENGINEER :SCHEMATIC FILE NAME :
RELEASE DATE :
USBP0_D-
USBP0_D-
USBP0_D+
U+USB_SIDE_PWR
U+USB_SIDE_PWR
UICH_USBP0+
U+USB_SIDE_PWR
USBP1_D+
USBP1_D-
UICH_USBP0+
USBP1_D-
UICH_USBP0-
UICH_USBP1-
U+USB_SIDE_PWR
UICH_USBP1+ USBP1_D+
USBP1_D+
U+USB_SIDE_PWR
USBP1_D-
UICH_USBP1+
USBP0_D-
UICH_USBP1-
UICH_USBP0-
USBP0_D+
USBP0_D+
UGND
UGND
UGND
UGND
UGND
UGND
UGND
UGND
UGND
UGND
UGND
UR4 0Ohm 5%1 2
UH2 C244DO134X1501
UCON3
USB_CON_1X4P
TYCO/1759528-1
1234
5 6
V1+DATA1_LDATA1_HGND1
P_G
ND
1P_
GN
D2
UU1
SRV05-4/*
1
2
3 4
5
6
UH1 C244D1341
UR1 0Ohm 5%1 2
UL190OHM/100MHz/*
MURATA/DLW21SN900SQ2L
14
23
UCON1
USB_CON_1X4P
TYCO/1759528-1
1234
5 6
V1+DATA1_LDATA1_HGND1
P_G
ND
1P_
GN
D2
UCON2
BTOB_CON_10P
SUYIN/127150FA010G509ZR
1 23 45 67 89 10
11
12
1 23 45 67 89 10
NP_NC1
NP_NC2
UR2 0Ohm 5%1 2
UR3 0Ohm 5%1 2
UC20.1UF/10VMLCC/+/-10%
12
UC10.1UF/10VMLCC/+/-10%
12
UL290OHM/100MHz/*
MURATA/DLW21SN900SQ2L
14
23
+UCE2
150UF/6.3Vpt_c7343d_h79
12
+UCE1
150UF/6.3V
/*pt_c7343d_h79
12