1muhammad amir yousaf o von-neumann architecture o registers o von neumann architecture o von...

1Muhammad Amir Yousaf

oVon-Neumann ArchitectureoRegistersoVon Neumann ArchitectureoVon Neumann SAPoInstruction SetoInstruction executionoVon Neumann Architecture’s limitationoHarvard Architecture

LECTURE 1


The Basic Register

oA register is a storage device that is capable of holding the collection of one or more bits.

0 1 . . n-1 N bit Register

D0 Dn-1

D0 Dn-1

ClkR,/WEn


Data Transfer between registers

0 1 . .n-1

D0 Dn-1Clk

R2,/W2

En2

0 1 . .n-1

D0 Dn-1

Clk

R1, /W1

En1

Control Signal11 10


CPU

Memory

Output Register

Execution unit

ALU

Control unit

IR

Controller

System bus

Both data and instructions at the same system bus

MAR

Register B

Register A

Binary Display

PC

VON NEUMANN ARCHITECTURE


CPU

RAM16 x 8

Output Register

ALU

Controller

MAR

Register B

Register A

Binary Display

PCPC

IR

Clk

clrEp

Cp

Lm

Clk

CE

clrLiEi

Ea

La

Lb

SE

Lo

Clk

clr

EpCpEiLiEaLa S E LbLmCE Lo

VON NEUMANN SAP

Simple As Possible Computer

6

INSTRUCTION SETThe instruction set specifies the basic operations supported by the machine.

It provides an interface to the underlying hardware.

It expresses the machine’s ability to transfer data, store data, operate on data and make decisions.

Components in a microprocessor system

Muhammad Amir Yousaf

o Arithmetic and Logic Instruction.o Looping and decision making.o Transfer of data.o Transfer of control.

7

INSTRUCTION SET



The entities that instructions operate on are denoted operands.

The number of operands that an instruction operate on is called arity of operation.

ADD 9HADD R1,R2z = x+y;x = x+y;x++;


INSTRUCTIONSMore on

Operand 0(Source and/or Destination)

Operation

15 x 0

Operation

15 x 0

Operand 0Source

Operand 1Src / Destination

Operation

15 x 0

Operand 2Src / Dest

Operand 1Src

Operand 0Src

oThe size of operation field is determined by the number of instructions a machine supports.oEach instruction is given a unique code called op-code

9

INSTRUCTION SET FOR SAP



Instruction Operation

000 Load RAM data into Register A

001 Add RAM data to RegisterA

010 Subtract RAM data from RegisterA

011 Load RegisterA into Output register

111 Stop Processing


INSTRUCTION SETThese numbers, called op-codes can be stored in program memory and can be fetched by the computer during execution.

Mnemonic names are given to op-code’s binary pattern to make them easier to work with.


Mnemonics Op-codes Operation

LDA 0000 Load RAM data into Register A

ADD 0001 Add RAM data to RegisterASUB 0010 Subtract RAM data from

RegisterAOUT 0011 Load RegisterA into Output

registerHLT 1111 Stop

Processing

Assembler translate these mnemonics to op-codes


INSTRUCTION SETLDA instruction includes the hex address of the data to be loaded.

LDA 8H

ADD instruction includes the address of the word to be added into RegisterA.

ADD 9H means ‘add the contents of memory location 9H to the RegisterA’; the sum replaces the original contents of RegisterA

SUB instruction includes the address of the word to be subtracted.

RegisterB holds the word to be operated, adder/sub compute instantly and the result is written on RegisterA.



PROGRAMMING SAP


Address Mnemonics

0H LDA 9H

1H ADD AH

2H ADD BH

3H SUB CH

4H OUT

5H HLT

Address Data

6H FFH

7H FFH

8H FFH

9H 01H

AH 04H

BH 02H

CH 03H

DH FFH

EH FFH

FH FFH

How instructions are stored in the memory?

Assembly language: language of mnemonicsMachine language : language of 1,0 strings

0H :0000 1001


CPU

RAM16 x 8

Output Register

ALU

Controller

MAR

Register B

Register A

Binary Display

PCPC

IR

Clk

clrEp

Cp

Lm

Clk

CE

clrLiEi

Ea

La

Lb

SE

Lo

Clk

clr


ADDRESSES

o Each location in memory has an associated address.

o Information is accessed in memory by giving that.

o If a memory has 16 locations, it will have 16 addresses.

o Address word size to access all the locations?

MSBN-1

0

MSBN-10

Big Endian

Little Endian


CPU

Output Register

ALU

Controller

Register B

Register A

Binary Display

PC

IR

Clk

clrEp

Cp

Lm

Clk

CE

clrLiEi

Ea

La

Lb

SE

Lo

Clk

clr


PC0 0 0 0

0 0 0 0

0 0 0 0

0 0 0 00 0 0 0

0 0 0 0

MAR0 0 0 0

PC MAR

INSTRUCTION EXECUTION CYCLE

Fetch instr.

RAM16x8


CPU

Output Register

ALU

Controller

Register B

Register A

Binary Display

PC

IR

Clk

clrEp

Cp

Lm

Clk

CE

clrLiEi

Ea

La

Lb

SE

Lo

Clk

clr


PC0 0 0 0

MAR

0 0 0 0

0 0 0 1

Instruction Execution Cycle

Fetch instr.

PC Inc

RAM16x8


CPU

Output Register

ALU

Controller

Register B

Register A

Binary Display

PC

Clk

clrEp

Cp

Lm

Clk

CE

clrLiEi

Ea

La

Lb

SE

Lo

Clk

clr


PC

MAR

0 0 0 0

0 0 0 1

0000 1001

0000 1001

0000 10010000 1001

IR

0H: xxxxxxx

0000 1001

0H:0000 1001


Fetch instr.

Mem IR

RAM16x8


CPU

Output Register

ALU

Controller

Register B

Register A

Binary Display

PC

Clk

clrEp

Cp

Lm

Clk

CE

clrLiEi

Ea

La

Lb

SE

Lo

Clk

clr


PC

MAR

0 0 0 0

0 0 0 1

IR

1H: xxxxxxx

0000

0H:010 1001


Fetch instr. Decode instr.

10011001

1 0 0 1

RAM16x8

9H: 00000001

1001

1001

1001

1001


CPU

Output Register

ALU

Controller

Register B

Binary Display

PC

Clk

clrEp

Cp

Lm

Clk

CE

clrLiEi

Ea

La

Lb

SE

Lo

Clk

clr


PC

MAR

0 0 0 1

IR

1H: xxxxxxx

0000

0H:010 1001



1001

1 0 0 1

RAM16x8

9H: 00000001

00000001

00000001

Fetch operand

0000000100000001

00

00

00

01

00000001

Register A


CPU

Output Register

ALU

Controller

Register B

Binary Display

PC

Clk

clrEp

Cp

Lm

Clk

CE

clrLiEi

Ea

La

Lb

SE

Lo

Clk

clr


PC

MAR

0 0 0 1

IR

1H: xxxxxxx

0000

0H:010 1001



1001

1 0 0 1

RAM16x8

9H: 00000001

00000001

00000001

Fetch operand

0000000100000001

00

00

00

01

00000001

Register A

Execute Write result


DATA TRANSFER INSTRUCTIONSResponsible for moving data around inside the processor .

Bringing data in from outside and sending data out.

Each data transfer instruction has three pieces of information:

o The datao The sourceo The destination.

The source and destination can be:

o A registero Memoryo IO port

The path to actual selection of operands is controlled by ‘addressing mode’ specified by operand.


DATA TRANSFER INSTRUCTIONSA portion of each operand field is designated as specification to the hardware as how to interprete the information in the remaining bits of operand fields.

A microprocessor design implements four to eight addressing modes.

Common addressing modes are:

o Immediateo Direct and Indirecto Register Direct and Register Indirecto Indexedo Program counter Relative.


o Direct and Indirect

DATA TRANSFER INSTRUCTIONS

o Immediate

o Register Direct and Register Indirect



DATA TRANSFER INSTRUCTIONS

o Indexed

o Program counter Relative



VON NEUMANN LIMITATION

The shared bus between the program memory and data memory leads to the Von Neumann bottleneck.

Because program memory and data memory cannot be accessed at the same time, throughput is much smaller than the rate at which the CPU can work.

The CPU is continuously forced to wait for needed data to be transferred to or from memory.

For example if we try to read an operand at the same time as we try to read an instruction. This is not possible in the von Neumann architecture since we only have one system bus and cannot address two memory positions simultaneously.


HARVARD ARCHITECTURE

Other Architectures

In the Harvard architecture this is solved by having two separate system buses:

o One for instructionso One for datao Data and instructions can be loaded

simultaneously, which improves the efficiency.

Means more I/O signals.

o More expensive processor.o Uses more power.

Is used internally in modern 32-bit microprocessors and RISC processors.

Program Memory

CPU Computer Memory IOs

Program system Bus

Data system Bus

MICROPROCESSOR SYSTEM DESIGN


General Purpose Computer e.g PC

A general-purpose computer, such as a personal computer (PC), is designed to be flexible and to meet a wide range of end-user needs.

Embedded Systems

An embedded system is designed and optimized to perform a specific task very efficiently.

They are different in:

o Resources o Real time.o Robustnesso Outer world interaction (IOs)o Program structure



Embedded Systems

An embedded system is designed and optimized to perform a specific task very efficiently.Microprocessor based systems:

A microprocessor is an integrated implementation of central processing unit portion (CPU).

Use separate integrated circuits for memory and peripherals.



Embedded Systems

An embedded system is designed and optimized to perform a specific task very efficiently.

Microcontroller based systems:

A microcontroller brings together a microprocessor core and a rich collection of peripherals and IO capability into single integrated circuit.

Reduces cost and size.

Timers, ADC, DAC, DIO, serial and parallel communication channels, DMA


INSTRUCTION ADDRESSING MODES

Instruction Architecture

Opcode

0 3 154

Instruction: Add with registerOpcode : 0011 or 3 Operand : address of memory location, register or constant

Operand1 Operand2

RISC vs CISCAddressing modes


PROCESSOR TYPES:

CISC (Complex Instruction Set Computer)

o The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible.

o This is achieved by building processor hardware that is capable of understanding and executing a series of operations.

o "MULT“. When executed, this instruction loads the two values into separate registers, multiplies the operands in the execution unit, and then stores the product in the appropriate register. Thus, the entire task of multiplying two numbers can be completed with one instruction:

o MULT 2:3, 5:2



REDUCED INSTRUCTION SET COMPUTING

RISC (Reduced Instruction Set Computer)

o RISC processors only use simple instructions that can be executed within one clock cycle.

o Thus, the "MULT" command described above could be divided into three separate commands:

o LOAD, which moves data from the memory bank to a register,o PROD, which finds the product of two operands located within the

registers.o STORE, which moves data from a register to the memory banks.o A programmer would need to code four lines of assembly:


LOAD A, 2:3LOAD B, 5:2PROD A, BSTORE 2:3, A


MEMORY:

To store data or instructions the computer system uses a so-called primary memory

The executable program code and data is stored in main memory.

The primary memory is divided in two main parts

o RAM o ROM

The memory can be seen as a number of post boxes



MICROCONTROLLERS

What does a computer system comprise:

o Processor (CPU, Central Processing Unit)

o Memoryo Peripheral units, I/Oo System bus, to communicate with

peripheral units

If we have a chip that comprise all this it is often called a ‘Micro Controller’

The outer world/ The user

I/O unit

RAM

ROM

Primary Memory

CPU

Von Neumann Architecture


PROCESSOR SYSTEM BUS Data buso Communication channel to move data to and from CPU and

peripheral units.

Address buso Used to point out which memory position or IO port that is to be

read or written.


Control signalso Used to signal when a data

transaction starts and stops.o For example signals if a

transaction is a read or write operation.


REFERENCES

Lecture slides: Benny Thörnberg, Mattias O’ NilsVideo Lecture: Prof. Anshul Kumarhttp://www.computersciencelab.com/ComputerHistory/History.htmWebopediahttp://www.world-war-2-planes.com/american-world-war-2-planes.html (slide 12)http://www.anvari.org/cols/Typewritter_ASCII_Art/Steam_Engine_Number_3.html (slide 10)

http://www.old-computers.com/history/detail.asp?n=61 (slide 15)http://www.freewebs.com/computingstudies/S1_UT_Systems/S1UTSystems_07.ht

mhttp://www.computer-museum.org/index.htmlhttp://www.ucdsb.on.ca/school/sla/aboutus/Pages/ExamSchedule.aspxhttp://www.youtube.com/watch?v=AqbyMRs3ocsCamera Pills Use MEMS Micro Reed Sensors to Activate the Batteryhttp://en.wikipedia.org/wikihttp://www-cs-faculty.stanford.edu/~eroberts/courses/soco/projects/risc/risccisc/

http://www.world-war-2-planes.com/american-world-war-2-planes.html

http://www.anvari.org/cols/Typewritter_ASCII_Art/Steam_Engine_Number_3.html

http://www.old-computers.com/history/detail.asp?n=61

http://www.freewebs.com/computingstudies/S1_UT_Systems/S1UTSystems_07.htm

http://www.freewebs.com/computingstudies/S1_UT_Systems/S1UTSystems_07.htm

http://www.computer-museum.org/index.html

http://www.ucdsb.on.ca/school/sla/aboutus/Pages/ExamSchedule.aspx

http://www.youtube.com/watch?v=AqbyMRs3ocs

http://en.wikipedia.org/wiki

1muhammad amir yousaf o von-neumann architecture o registers o von neumann architecture o von...

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