A NEW CONCEPT OF MULTILEVEL STATCOM BASED ON CASCADE TOPOLOGY

Emil KOT, Grzegorz BENYSEK

University of Zielona Góra Zielona Góra (Poland)

Ryszard STRZELECKI Gdynia Maritime University

Gdynia (Poland) Abstract - Paper presents one way for power quality conditioning. This way means parallel connection of the STATCOM circuits with the network, therefore it is possible to “isolate” load from source and vice versa. Described condi-tioner makes possible to get: i) sinusoidal source current; ii) reactive power compensation; iii) load voltage stabilization; iv) balanced source in con-ditions of the unbalanced load. As STATCOM, the four level cascade based VSI has been used. To confirm results of the theoretical analysis some experimental results were presented. Addi-tional, control algorithm, to shape six-step output voltage is proposed.

This work was supoorted by Polish Committee for Scientific Research under Grant Nr 4T10A 037 25 pt.„Energoelektroniczne układy elastycznego ste-rowania przepływem mocy w rozproszonych syste-

mach zasilających prądu przemiennego”

1. INTRODUCTION

In professional literature [1]-[5] there are de-scribed many different ways to “isolate” sources from disturbances introduced by the nonlinear loads and vice versa. For example to compensate reactive and higher harmonics currents, produced by the nonlinear loads, STATCOM (STATic COMpensa-tor) can be used [4]-[9]. In those systems (independ-ent with control algorithm) there is need to extract, from measured load or source currents (it depends if control algorithm is in open or closed loop), com-pensating components, therefore the filtration qual-ity is as good as well it is possible to extract com-pensating components and shape them. Paper presents a one way of power quality im-provement. In presented solution, power quality im-provement is possible to get if parallel connected

STATCOM acts as a sinusoidal, with fundamental frequency, voltage source, therefore described con-ditioner makes possible to get:

i) sinusoidal source current; ii) reactive power compensation; iii) load voltage stabilization; iv) balanced source in conditions of the unbal-

anced load. Because STATCOM has to “produce” sinusoidal voltage, multilevel Voltage Source Inverters (VSI) are the perfect solution in this case [10]-[11]. Onto needs of the STATCOM, four-level cascade based VSI inverter was developed [12]. 2. MULTI-LEVEL VSI

It is possible to notice more and more publications concerning modernization and development, one of the basic directions in building DC/AC converters, which there are multi-level voltage inverters, formu-lating step voltages using few supply sources both iso-lated as sectioned. Absence in such inverters trans-formers takes off limitations in output voltage fre-quency control in range of low frequencies. In result it is possible to distinguish three basic solution direc-tions of multi-level voltage inverters topologies: − multi-level voltage inverters with levelling di-

odes (DC- Diode Clamped); − multi-level voltage inverters with levelling ca-

pacitors (CC- Capacitor Clamped); − multi-level voltage inverters as Isolated Series

H-Bridges (ISHB), also called multi-level cas-cade inverters;

On the base of above been mentioned structures, it is possible to create group of the new inverter topolo-gies as connection of the standard three-phase in-verters with one-phase bridge inverters. All above mentioned structures makes possible ob-tainment quasi-sinusoidal output voltages, in result

a)

b)

Fig.1. Phase-to-phase output voltage and its spec-

trum: a) standard VSI inverter; b) cascade topol-ogy multi-level VSI(without PWM).

of what, it is possible to reduce or even to resign from applying additional filtering arrangements. It is a huge advantage mainly in refer to use of them in drive and telecommunication, etc. Besides those in-verters can be built on higher voltages than conven-tional (with two voltage steps), what in case of de-vices working, e.g. in industrial average voltage sys-tems can lessen whole arrangement about fitting transformer. Multi-level VSI are created among oth-ers to improve output voltage wave shape. Because multi-level voltage (reminds more sinusoidal) it con-tains less higher harmonics, also extorted load cur-rent is more sinusoidal (Fig.1a,b). 2.1. Proposed topology multi-level VSI

Fig.2 presents proposed inverter, which is a se-ries connection of one-phase transistor bridges with three-phase voltage inverter. Proposed inverter can work both in three- as well as four-line nets in last case supply source on inverter input contains divider from two capacitors, creating zero point.

T1

T1 T2

T3 T4

T5

T6N

L2

L1

L3

Udc1

Udc2

Udc2

Udc2

C

C

C

C

VSI 3L1

VSI 2L

VSI 3L2

VSI 3L3

UL1-2

UL1L

R Load

T5'

T6'

T1' T2'

T3' T4'

T5''

T6''

T1'' T2''

T3'' T4''

C/2

C/2

N

L1 L2 L3

STATCOM

Fig.2. Cascade topology based multi-level voltage inverter (experimental circuit)

Basic blocks of this type of inverter there are

conventional three-phase inverter (T5-T6; T5’-T6’; T5’’-T6’’), as well as tree one-phase bridges (T1-T4), (T1’-T4’), (T1’’-T4’’) from which every one is connected in series with half-bridge of the three-phase inverter. Individual modules require isolated supply source. During registration even supply volt-

age values were accepted Udc2 and Udc1. All three one-phase bridges with unipolar modulation are shaping three-step output voltage (VSI 3L), mean-while three-phase bridge with bipolar modulation shapes two-step phase voltage (UVSI 2L). Fig.3 pre-sents formation of the phase-to-phase output voltage UL1-2. It is a sum of voltages on one-phase of the in-

Fig.3. Voltage curves presenting phase-to-phase vol-

tage construction (from above: Ref2 – two step inverter phase-to-phase output voltage VSI 2L, Ch2- three-level inverter output voltage VSI 3L2, Ch4 three-level inverter output voltage VSI 3L1, Ch1 – cascade multi-level inverter phase-to-phase output voltage UL1-2)

verter and phase-to-phase voltage of the three-phase inverter (UL1-2=UVSI 3L2-UVSI 2L-UVSI 3L1). Number of levels in the phase-to-phase output voltage, in three line net, carries out N=2n-1, where: n- number of levels in phase voltage for four line net. In this case 7-step output voltage in cascade topology based in-verter is generated. 2.2. Control algorithm

In system presented in Fig.4. difference signal between current reference value iZ and real value iL is given to proportional-integrating (PI) regulator. Exit signal of this regulator is compared with three triangular signals with frequencies of the commutat-ing switches and with even amplitudes. Triangular signals are shifted in relation to itself with amplitude value as it is in Fig. 5. Result of comparison is given to the comparator, which forms steering impulses with modulated widths. Arrangements possess con-stant switching frequency.

iz

T5

L

komparator

regulator PI

GNP

FN

u L,T6T3T1 T4

T2Q

/Q

Q

/Q

Q

/Q

Udc

+

++

i

Fig.4. Arrangement for load current course forma-

tion with constant switching frequency

Fig.5 presents inverter output voltage for one phase,

which is sum of output voltages first (VSI 2L) and second (VSI 3L1) inverter with bipolar and unipolar modulations and in result of this it is for-even-level quasi-sinusoidal curve (when Udc1=Udc2).

Fig.5. Inverter bridges voltages summation to show formulation of the four-level phase voltage

2.3. Experimental model

Experimental investigations (Fig.6 - Fig.9) were made with the following parameters: Udc1=Udc2= 50V; load resistance R=20Ω and inductance L=2mH. Analog PWM follow-up modulator with 12kHz frequency was applied.

Fig.6. Experimental model view of the multi-level

cascade topology inverter.

Fig.7. Reference signal and load current, RL load.

VSI 3L1 VSI 3L2 VSI 3L3

VSI 2L

PWM follow-up modulator

Triangular signal

Sine waveform

UVSI 3L1

UVSI 2L

UL1

Fig.8. Phase voltages of the cascade four-level VSI. a)

b)

Fig.9. Phase-to-phase voltages of the proposed four-

level VSI a) with PWM, b) without PWM.

2.4. Extension of control algorithm

So far there was considered multi-level cascade topology inverter, in which supply voltage values on individual inverter bridges were even Udc1=Udc2. Then phase output voltage was sum of voltages on one-phase bridge and half-bridge of the three-phase inverter (Fig.5). Founding, that Udc1≠Udc2 as well as applying control algorithm, which both makes pos-sible summation as well as subtraction of voltage values, it is possible on four level inverter topology to shape six-level phase voltage. Proposed diagram of the modified control algorithm presents Fig.10. Modulation in this control algorithm was made on five comparators where there was compared sinusoidal modulating signal with five tri-angular signals with even amplitudes and frequen-

cies. Triangular signals are shifted in relation to it-self with value of amplitude how it shows Fig.11.a). Principle of operation of the control algorithm is similar how in Fig.4, with this that additionally on exit of comparator logical arrangement was applied.

iz

T5

L

komparator

regulator PI

GNP

FN

uL

T6T3T1 T4T2

Q

/Q

Q

/Q

Q

/Q

i

Udc

Q Q

/Q /Q

ukladlogiczny

dc

GNP

-

--

--

++

++

+U

Fig.10. Modified control algorithm of the proposed

multilevel VSI, where it is possible to shape six-level phase output voltage .

Fig. 11. Voltage time base wave shapes presenting phase voltage level formulation for proposed to-pology: a) signal representing PWM; b) control signals (for one branch); c) voltages summation and 4-level voltage UL1(4L) for Udc1=Udc2; d) 5-level voltage UL1(5L) for Udc1=2Udc2 and 6-level voltage UL1(6L) for Udc1=4Udc2.

a)

d)

c)

b)

UVSI 3L1

UVSI

UL1(4L)

UL1(5L)

UL1(6L)

T1 T2

T3 T4 T5 T6

Triangular signal

Sine waveform

Fig.12. shows voltage vectors in one-phase inverter bridge and in one leg of the cascade inverter, which illustrate formation of levels in output voltage. From analysis of voltage vectors it results, that at mainte-nance of condition Udc1=Udc2, proposed topology VSI shapes 4 level phase voltage (Fig.11c; Fig.12b), at maintenance of condition Udc1=2Udc2; five-level (Fig.11d, Fig.12c), meanwhile at Udc1=4Udc2 – six-level (Fig.11d, Fig.12d).

Fig.12. Voltage vectors presenting phase vol-tage

level formulation for cascade topology from Fig.2: a) with 4levels for standard control from Fig. 4 and condition Udc1=Udc2; b) with 4 levels for modified control from Fig.10 and condition Udc1=Udc2; c) with 5 levels for modified control from Fig.10 and condition Udc1=2×Udc2; d) with 6 levels for modified control from Fig.10 and condition Udc1=4×Udc2

In proposed method of voltages formation with 4, 5, 6 levels, in cascade topology inverter with supply condition Udc1≠Udc2 there are voltage "stresses” on switches. Analysing one branch of the cascade in-verter’s, for case from Fig.11b) voltages on transis-tors of the inverter VSI 3L1 are two times larger than on transistors of the three-phase inverter’s VSI 2L; what leads to larger commutation losses. For case from Fig.11c) voltages on transistors are the same, meanwhile for case from Fig.11d) larger volt-age stresses are n transistors of the one-phase in-verter VSI 3L1 o. In this of case losses of the VSI 3L1 inverter, are larger than those of the three-phase bridge inverter’s.

3. RESULTS IMPLEMENTATION PROPOSED VSI FOR STATCOM

To verify results of the theoretical investigations

a down scale multilevel VSI hardware model, with

parameters presented in Tab.1, was developed. Dur-ing investigations DC link voltages were even UDC1=UDC2=UDC3=UDC4 and on output of the cascade based four level VSI a couple choke was imple-mented.

Tabl.1. Investigated system parameters

STATCOM Source voltage 80 [V] DC link voltage 70 [V] Couple choke LS 5.4 [mH] DC link capacitance C 2200 [µF]

switching frequency 10 [kHz]

Fig.(13-17) present experimental waveforms, during steady state operation of the STATCOM VPQC, for two different load types, linear (resistive-inductive load) and non-linear (six pulse rectifier with resis-tive-inductive load). Fig.13 illustrates investigated conditioner’s behav-iour in situation of linear R-L load, R=20 [Ω] , L=72 [mH]. It is seen from this figure that multilevel STATCOM has meaningful influence on the source current, distortions, in which, mostly come as result of the distorted supply voltage ( Fig.14).

a)

b)

Fig.13. Symmetrical RL load: a) load; b) source (Ch-

1: source voltage (phase L1); Ch-2, Ch3, Ch4 – load/source currents in three phases.

Above figure illustrates also the reactive power compensation capability. Fig.15. demonstrates con-ditioner’s possibility for balancing the unbalanced loads in conditions of balanced source. Fig.16. dem-onstrates the filtering capabilities of the multilevel STATCOM. As one can see from those figures, the

Udc1

Udc2

Udc21 level

2 level

3 level

4 level

Udc2

Udc2

Udc2

Udc2

Udc1

1 level

2 level

3 level

4 level

Udc1

Udc1

Udc2

Udc2

Udc2

Udc2

1 level

2 level

3 level

4 level

5 level

Udc1

Udc2

Udc2

Udc2

Udc2

1 level

2 level

3 level

4 level

5 level

6 level

Udc1

a) b)

c) d)

load current contains a large amount of harmonics due to the six pulse rectifier with resistive-inductive load, however the source current is almost sinusoi-dal, see Fig.16. and Tab.2. As it was told earlier, in the paper, STATCOM, with described control algorithm, is “sensitive” on supply voltage variations (sags, dips), one can see from Fig.16. that those variations have impact on nature of the source current, in our case, because of source voltage magnitude is over it’s nominal value, be-comes more inductive. Additionally Tab.2 presents the THD coefficients in characteristic points of the investigated STATCOM and Fig.17 [13] demon-strates, in conditions of the non-linear load, four level cascade based VSC’s DC link voltages.

Fig.14. From above: Ch3 source voltage; Ch4 - mul-tilevel VSI output voltage; Ch2=Ch3-Ch4 .

a)

b)

Fig.15. Linear no symmetrical RL load: a) load side; b) source side (Ch-2, Ch3, Ch4 – load/source currents in three phases)

a)

b)

c)

Fig.16. Non-linear load, source voltage magnitude

over it’s nominal value (3%): a) P2=0.8 [kW]; b), c) P2=1.2 [kW]. Ch-1: multilevel VSI output voltage; Ch-2: source current; Ch3- source volt-age; Ch4- load current.

Fig.17. DC link voltages. From above: R-1: UDC1; R-

2:UDC2; R-3: UDC3; R-4: UDC4.

Tabl.2. THD Coefficients

THD [%] I1 U1 IL Uc 0.8 [kW] 3,3 3,3 25,3 2,9 Non-linear

load 1.2 [kW] 2,6 3,5 24,2 3,7

4. CONCLUSIONS

Paper presents three phase STATCOM based on the four level cascade VSI, which permits to fulfill various tasks. To verify properties of the proposed conditioner’s a down scale hardware model was de-veloped. On the base of experimental investigations one can say that: - conditioner can free from higher harmonics

source current, even in situation of strongly de-formed load current;

- conditioner stabilizes load voltage in situation of source voltage magnitude variations;

- conditioner possess the reactive power compen-sation capability;

- conditioner possess the capability of balancing the unbalanced loads in conditions of balanced source;

- load voltage stabilization in conditions of the source voltage magnitude variations leads to the input reactive power growth;

- to avoid problem of the source voltage shape in-fluence on the filtration quality, control algorithm has to be equipped with low pass filter to check source voltage harmonics.

5. REFERENCES 1. Ghosh A., Ledwich G: Power Quality Enhancement

Using Custom Power Devices. Kluwer Academic Pu-blishers, Boston, 2002.

2. H. Fujita, Y. Watanabe, H. Akagi: Control and analysis of a unified power flow controller, IEEE Trans. Power Electronics, 14, 6, 1999, pp.1021-1027.

3. F. Peng, H. Akagi, H. Nabae: Compensation charac-teristics of the combined system of shunt passive and series active filters, IEEE Trans. on Industry Applica-tions, 1993, Vol.29, No.1, pp.144-15.

4. R. Strzelecki, H. Supronowicz: Power factor in AC supply systems and improvements methods, Publish-ing house of the Technical University of Warszawa, Warszawa 2000.

5. R. Strzelecki, J. Rusiński, G. Benysek: Voltage source power quality conditioner, Electromagnetic phenomena in Nonlinear Circuits - EPNC 2002, XVII Symposium. Leuven, Belgia, 2002, pp. 179-182.

6. N.G. Hingorani, L. Gyugi: Understanding FACTS. Concepts and Technology of Flexible AC Transmis-sion Systems. IEEE Press, New York, 2000

7. C. Schauder: STATCOM for Compensation of Large Electric Arc Furnace Installations: Proceedings of the IEEE PES Summer Power Meeting, Edmonton, Alberta, July 1999, pp. 1109-1112.

8. R. Strzelecki, G. Benysek: Układy STATCOM i ich rola w systemie elektroenergetycznym. Międzynaro-dowa Konf. Nauk-Tech. „Nowoczesne urządzenia

zasilające w energetyce”, Kozienice, marzec 2004, pp.26.1-26.13.

9. R. Strzelecki, G. Benysek, A. Noculak: Wykorzysta-nie urządzeń energoelektronicznych w systemie elek-troenergetycznym. Przegląd Elektrotechniczny, Nr.2, 2003, p.41-49.

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11. J. Song-Manguelle, S. Mariethoz, M. Veenstra and A. Rufer: A Generalized Design Principle of a Uniform Step Asymmetrical Multilevel Converter For High Power Conversion, EPE Conference, Gratz, 2001.

12. G. Benysek, E.Kot, A. Baranowski.: Comparative analysis of the parallel active filters on base of the multilevel inverters. EDPE Conference, Dubrovnik, Croatia, pp.38-43, 2000.

13. R. Strzelecki, G. Benysek, J. Rusiński, E. Kot.: Analysis of DC Link Capacitor Voltage Balance in Multilevel Active Power Filters, EPE’01-Graz.

Prof. Ryszard Strzelecki was born in 1955 in Bydgoszcz, Poland. He received the M.Sc. and Ph.D degree from Technical University in Kiev. He received his D.Sc. degrees from Institute of Electrodynamics Academy Since of Ukraine. Presently, he is Full Professor of the Gdynia Maritime University. His areas of interest include power electronics circuits, electric power quality and power flow controller

Mailing address: Ryszard Strzelecki Gdynia Maritime University, Depart. Of Ship Automation 81 Morska Str, 65-246 Gdynia, POLAND phone:(+48 58) 6901204, fax:(+48 58) 69-01-445 e-mail: rstrzele@am.gdynia.pl Dr. Grzegorz Benysek was born in 1968 in Kramsko (district Zielona Góra), Po-land. He received M.Sc. and Ph.D. degrees from the Technical University of Zielona Góra. At present he is Researcher in the University of Zielona Góra. His fields of interest is in power electronics and distributed genera-tion.

Mailing address: Grzegorz Benysek Univ. of Zielona Góra, Institute of Elec. Engineering 50 Podgórna Str., 65-246 Zielona Góra, POLAND phone:(+48 68) 3282417, fax:(+48 68) 3254615 e-mail: G.Benysek@iee.uz.zgora.pl MSc. Emil Kot was born in 1974 in Bytom Odrzański, Poland. He re-ceived M.Sc. degrees from the Technical University of Zielona Góra. At present he is Researcher in the Univer-sity of Zielona Góra. His fields of interest is in power electronics, in particular multilevel converters.

Mailing address: Emil Kot University of Zielona Góra, Institute of Elec. Engineering 50 Podgórna Str., 65-246 Zielona Góra, POLAND phone:(+48 68) 3282538, fax:(+48 68) 3254615 e-mail: E.Kot@iee.uz.zgora.pl