14 year hrl research

IBM Labs in Haifa © 2008 IBM Corporation

Riding on Maxwell Equations14 years of Analog Fun !

David Goren

IBM Labs in Haifa

© 2008 IBM Corporation2

The starting point (1998)The starting point (1998)Ringing noise example -"Phoenix" projectRinging noise example -"Phoenix" project(SiGe Pin Electronics Driver/Receiver)(SiGe Pin Electronics Driver/Receiver)

Example:

1 [mm] on-chip interconnect = 6.7 [psec] time of flightOutput wire electrical parameters

R=2.5 C=70fF (from cap. extraction, equiv. to 1um HBT)L=0.6 nH (estimated as Linfinity from the capacitance)Swing = I25 Ohm = 0.5 VoltMax. overshoot: L dI/dt = 0.24 Volt !

Interconnect

Driver (Phoenix project)25 500 fF

Driver output: 20mA switching in 50psec into 25 Ohm load

D. Goren et al, IEEE BIPOLAR/BICMOS circuits and technology meeting, Minneapolis, September (1999).

IBM Labs in Haifa


Simulated result Simulated result (model estimated inductance) (model estimated inductance)

25% overshoot ! (spec. requires 5%)

no inductance

inductance included

Just imagine this interconnect line in sensitive comparatorinput ! !

IBM Labs in Haifa


Problem definition:Silicon chip metal interconnect

design & modeling methodologiesfail at high frequencies

Chip level extraction is not the right way at high frequencies: State of the art in interconnect extraction is mostly RC. Even

around 1GHz, inductance starts to impact longer lines behavior Fully automated inductance extraction is impossible without

exact knowledge of the return paths, which is not always practical at post layout extraction

Post layout extraction for high frequency design is often too late Traditional microwave methodology does not apply to VLSI and

A&MS Traditional microwave concepts (Impedance matching, S -

Matrix) are not applicable for most A&MS designs Fully nonlinear, large signal transient SPICE simulations

required Mixed signal simulations required

IBM Labs in Haifa


Our unique solution:Global wires can be designed as

independent, stand-alone devicesInterconnect Design rather than extraction -

Combine design automation with designer’s wisdom

Study and implement the closed environment conditionsenabling stand-alone devices for critical wire structures

Use predefined T-line geometries as design templates Properly designed bends and junctions not requiring separate

models – except few cases in mm-Wave design Develop closed form, wide bandwidth (DC till the transistor Ft)

models for the given geometries (over 200GHz bandwidth today) Support the specific technology details (given metal stack, various

dielectric materials, copper..) Support all simulation kinds (transient, AC, PSS, S-param, mixed-

mode Easy migration between different circuit simulators and design

environments (VerilogA based models)

Vision: From IBM standard upgrade to an industry standard

IBM Labs in Haifa


Optimalgeometry

Semi-analyticalmodeling

EquivalentRLC network

Our approach: We suggest self-contained models for carefully designed T-lines only Focused on careful design of on-chip critical wiring which ensures both

desired performance and modeling accuracy in various/dense VLSI design neighborhoods

Required modification and expanding of the model is enabled by physics-based semi-analytical explicit expressions for the RLC network elements

On-Chip T-line Methodology

Previous solutions: focused on modeling on-chip wiring for circuits which had been considered

as given. They had tried to model any critical wiring in any given design

IBM Labs in Haifa


Microstrip T-lines: up to 110 GHz, for relatively sparse A&MS SiGe design

S

G

S2S1

G

GG S

G

via

via

GG S2S1

G

via

via

On-Chip Interconnect Design Suite:Till 2002

Do not consider the T-line device neighborhood

Consider dielectric as uniform medium

Towards 2002, the microstrip T-lines were already available in almost all SiGe Foundry Design Kits and won numerous customers.

This resulted in an IBM Research Accomplishment Award in 2002.

IBM Labs in Haifa


First T-lines Test Cage (BiCMOS7HP)

Haifa on-chip microstrip straight and bent T-line structures

IBM Labs in Haifa


Measured S-parameters of bent T-line structures versus their straight reference

Dashed: 45o bends, dotted: 90o bends, solid: straight line

S11(magnitude) S11(phase)

S12(phase)S12(magnitude)

Sample Measurement Results

IBM Labs in Haifa


S

G

Dirac BiCMOS8HP Test Cage

Haifa on-chip microstrip T-line structures

IBM Labs in Haifa


Green: model Blue: 110 GHz measurement, Black: EM solvers Red: raw measurement (no pad de-embedding)

Thomas Zwick, Youri Tretiakov and David Goren, IEEE Microwave and Wireless Components Letters (2004)

Sample Dirac Measurement Results: Single Microstrip T-line

IBM Labs in Haifa


Integration Level 359 NPNs 1040 FETs 157 transmission

lines 13 inductors 521 resistors 270 MIMs 60 pads

Size: 4 x 1.5 mm2

Driver

PLL

Mixer & IFVGA

TriplerIF Mix

PA

High integration level is unique for millimeter-wave.

Complexity approaching that seen at 5 GHz.

Die Photo: A 60-GHz Transmitter(taken from the talk at the ’06 IBM BEOL Conf.

made by Brian Gaucher’s team)

IBM Labs in Haifa


60 GHz SiGe Transformer Based Power Amplifier

Combine the power of 4amplifiers (add 6dB!)

Voltage swing well above transistorbreakdown voltage

Efficient impedance matching Compact design Extremely compact design Single-ended or differential operation

possible (balun)

IBM Labs in Haifa


Measured Performance:

23 dBm (200mW) RF power at 60GHz (world record for Silicon)

Up to ±6.5V voltage swing in 100Ω (BVceo = 1.7V)

20 dB gain (two stage) Wilkinson power divider used to

distribute input power Extremely compact design Can be used for input impedance

transformation too

4:1 TransformerSize: 1.8 x 2 mm2

Wilkinson Power Divider

60 GHz SiGe Transformer Based Power Amplifier

Ullrich R. Pfeiffer and David Goren, IEEE Journal of Solid State Circuits, 2007

IBM Labs in Haifa


Variable T-lines

R1 S R1

sC port lines

ws w

ground

R2Rn R2 Rn

crossingcrossing

New concept: maximal flexibility hardware independently controlled by software

IBM Labs in Haifa


Variable T-lines – top view

SR2 R1

IBM Labs in Haifa


3D EM simulation(IBM varsinglewire device)

C port lines

IBM Labs in Haifa


IBM varsinglewire device: user interface

IBM Labs in Haifa


IBM varsinglewire device: S-parameter simulation

We use Cadence vector wire (bus) for elegantly implementing the C ports

Alternating floating and grounded ports case

IBM Labs in Haifa


Simulation Results, 50, 360um Variable T-line

19% extra delay

All C port lines open

All C port lines shorted

At 60GHz, the impedance of the varsinglewire device is:All C ports floating 48.5 OhmAll C ports grounded 40.4 Ohm

IBM Labs in Haifa


Microstrip T-lines: Up to 200 GHz, mostly for SiGe RF & mm wave customers

S

G

optionalcrossunder

optional cossover

S2S1

Goptional crossunder

optional crossover

GG S

G

via

via

optional crossover

optional crossunderGG S2S1

G

via

via

optional crossover

optional crossunder

GG S

Silicon substrate

GG S2S1

Silicon substrateoptional crossunder

optional crossover

optional crossunder

optional crossover

Coplanar T-lines: Up to 100GHz, mostly for Digital CMOS, includes silicon effects

RC Lines: Digital CMOS: short wires/lower frequencies

X2X1 S GG S2S1

crossunder

crossover

crossunder

crossover

IBM On-Chip Interconnect Basic Design Suite:Ever Since 2003

Introduced modeling of:

Crossing lines

Silicon substrate

Non-uniform dielectric structure (low-k)

Metal fill

Copper layers properties (cheezing, OPC etc.)

Towards 2007, the breakthrough to mainstream CMOS technologies. This resulted in an IBM Research Upgrade to Outstanding Accomplishment

Award in 2007.

IBM Labs in Haifa


GG S

Silicon substrate

crossunder

crossover

Y2

X1 X2

Y1

w s wT-line

core structure

The T-line Closed Environment Concept

T-line closed environment – a design fragment

which can be accurately represented by a self-contained, independent model

of the T-line core structure in an actual design environment

T-line closed environment = T-line core structure + ?

ConclusionsSelf-contained models for critical lines in dense

VLSI Manhattan environments are possible in most common cases, provided that

the critical lines are properly designed – proper design guidelines are suggested

the models are modified and expanded to include some environment elements, such as:

silicon substrate, crossing lines, correction of the DC resistance due to the power grid impact

Closed Environment = Proper Design + Proper Modeling

IBM Labs in Haifa


Impact of 3D Crossing Lines

G S G

Impact of crossings on T-line Capacitance:

C = C(hover/under, wover/under, Dover/under)

soverwover

hover

hunder

sunder

wunderT-line

Crossover

Crossunder

tover

tunder

t

D

C

0 100%

C(full plane)

C(no crossings)D = w/(s+w) is crossing metal density

IBM Labs in Haifa


signal

ground

Metal+via fill

signal

Metal fill

Metal fill

ground

Via fill

Metal fillVia fill

Metal fillVia fill

…

3D Metal and Via Fill Study

Conclusions1) Metal fill can be tolerated and estimated by the T-line model, but via fill should better be avoided or excluded from the vicinity of the T-lines2) It is recommended to reduce the process metal fill density in the vicinity of the T-lines to less than 15%

IBM Labs in Haifa


Randall CMOS11S0 Test Cage

Haifa coplanar T-lines test cage - Loki design structures

IBM Labs in Haifa


Single CPW, no crossing lines, w=s=2um (gamma, z0)

Green & Magenta: 60GHz measurement on two different chips Cyan: Haifa T-line model Black: EM solvers Blue: RC model

Sample Randall Measurement Results

IBM Labs in Haifa


Pathfinder CMOS12LP Test Cage

Haifa coplanar T-lines test cage – CPW T-line structures

IBM Labs in Haifa


Sorting wires into 2 groups: critical, small group non-critical, most of the wires

Design of critical wires: Predefined set of parametrized T-line

structures as design components Pcell based: T-line device =

symbol+schematic+layout views DRC and LVS clean layout Monitoring T-line parameters is

enabled

Smart extraction Use T-line models for critical wires Use RC extract for non-critical wiring -

sufficient accuracy Back-annotate final T-lines

parameters

Schematic design including T-line models

Smart Extraction

Physical Design. T-lines as p-cells

Final Simulation

High Level Design

FloorplanArchitecture

Identify critical interconnect

Patented Interconnect-aware Design Flow

D. Goren et al, IEEE DATE conference, Paris (2002). D. Goren et al, IEEE DAC conference, Anaheim (2003).

David Goren et al, Patent Number 10/091,934 filed on March 6 (2002).

IBM Labs in Haifa


RC Extraction Models

Models Verification by Comparison to Other Models

IDENTIFY CRITICAL PATHi.e. High Speed Clock Path

HIGH LEVEL DESIGNFloorplan, Architecture

GEOMETRY OPTIMIZATION USING RC

or CPW MODELS Corners and Monte Carlo

can be run

OPTIMAL GEOMETRYi.e. High Speed Clock

Path

CPW or RC Models From

Haifa TLine Team

CIRCUITS DESIGN AND SIMULATIONS WITH RC AND CPW MODELS

Corners & Monte Carlo

GeometryOptimization

Design RequirementsNot Met

CIRCUITS EXTRACTION AND SIMULATIONS

M2 P M2 N

SUBSTRATE

M4 Crossing (VDD): Width=0.2um, Spacing=0.2um, Thickness=0.25um

0.72um 0.72um 0.72umw=0.96umw=0.96um

w=0.96um

M2w=0.96um

Th=0.74u

Th=0.25um

11G Squall Clock Lines Cross-section, L=400um

High level and high speed clock distribution design flow

Nominal 3-Db bandwidth, 25fF Load C 100 Ohms source imp. 9fF Diffusion

13.7GHz Haifa RC 14.4GHz Haifa CPW 13.8GHz Erie RC

Haifa Coplanar Waveguide and RC models in HSS environment

(from the talk at IBM BEOL’06 Conf. made by H. Camara, HSS team)

IBM Labs in Haifa


Waternoose 2.7 GHz Clock Tree Loki 2.7 GHz Clock Tree

• Loki needed far fewer clock buffers to preserve clock amplitude using Haifa T-Lines.

• Easy to balance skew with a passive tree.

• Some clock paths are a passive multi-drop branch

RC-Lines (Waternoose) vs T-lines (Loki)(taken from the talk at the ’06 IBM Academy Analog Conf.

made by HSS team)

IBM Labs in Haifa


Loki environment: Coplanar T-line vs. RC-line example

GG Scrossunder

1 mm wire

IBM Labs in Haifa


Simulation experiment results: Coplanar T-line vs. RC-line – far end (length=1mm)

trise =10ps

trise = 28psT=370ps

IBM Labs in Haifa


Contribution to IBM Foundry DK’s, 2001-2011

Integration of the Haifa Interconnect Design Suite in IBM Design Kits Till 2002, almost all the SiGe technologiesSince 2002, all the SiGe technologies + the following CMOS technologies:

CMRF8SF, CMOS9SF, CMOS9FLP, CMOS10LP, CMOS10SF, CSG11S0, CMOS11LP, SOI12S0, SOI13S0, 22nm SOI

Since 2007, transition of the coplanar T-line and RC-line models to VerilogA VerilogA based models require significantly less integration effort from the BTV design automation team, enable standard integration in various EDA environments

VerilogA based models are already in the IBM DK’s for the following technologies: CMS9FLP, CMOS10SF, CMOS11LP, SOI13S0, 22nm SOI

Introducing new devices to the Haifa Interconnect Design Suite 2008, R&D of generic compact BUS models and RC-BUS models towards "T-line style" BUS

devices – delivered to BTV – need more internal customer blessing for kit integration

2011, 3DI TSV / mC4 models will be integral part of IBM 22nm design kits.Annual customer satisfaction surveys – feedback from BTV:

“Very satisfied with excellent quality product”

IBM Labs in Haifa


Wires parallel to the T-line have almost no impact on T-line capacitance Impact on T-line inductance

Significant inductive impact may be caused by parallel lines located in layers adjacent to the T-line core structure layer, right above crossover and/or right below crossunder

The inductive impact strongly depends on the horizontal shift of parallel lines relative to the signal line

The inductive impact of parallel lines is pronounced at higher frequencies.

The preliminary study considers parallel wires having periodic structure, i.e. characterized by constant wires width and spacing

Future idea: Impact of Parallel Lines on T-line performance:to be included in future design kits

G S G

Crossover

T-line core structure

Parallel lines above

Crossunder

Parallel lines below

Silicon substrate

IBM Labs in Haifa


BUS device and model templates enable easy high speed BUS design and modeling in the pre-layout stage by the average designer, who is not an electro-magnetic expert

Who needs this? P7 and other processor designs,HSS core designs, RFIC designs (BUS design can bethe bottleneck for multi-GHz speed)

Other usage example: Accurate inductive (and capacitive) crosstalk estimation (Ericsson case, for example)

RC compact multi-line models are included for lower frequencies

Future Impact: Compact Bus Models

IBM Labs in Haifa


Future Impact: Compact Bus Device

G S2S1 Sn

Crossover

Bus core structure

Parallel lines above

Crossunder

Parallel lines below

Silicon substrate

•Distributed bus model, including full inductance matrix for all the signal lines S1-Sn, considering crossing and parallel lines in relevant adjacent levels •Includes skin effect (frequency dependence) modeling

G

Model window

IBM Labs in Haifa


5 Signal Lines: CPW vs. RC vs. EM Solver, 11000 mode, gamma-Z0 format stack: 323102, signal in UB, crossing in UA, parallel in E1, w=s=2um, d=3um

1mm lines, simulation from 10[MHz] up to 50[GHz]

Sample Simulated Results

IBM Labs in Haifa


Simulation Result (1.6mm length)Center signal excited, the rest is off

1 2 3 4 5G G

IBM Labs in Haifa

© 2008 IBM Corporation39 1 2 3 2 1G G

zGryphon Bus Simulated Result (1.6mm length)Signals 1 2 3 have same phase (not design practice)

IBM Labs in Haifa


Interconnect for 3DI:design and modeling motivation/challenges

Target Provide means to design in 3DI technologies considering vertical, as

well as horizontal, interconnect which enable precise prediction of expected circuit behavior – current focus on z360 design in 22nm

Required solution features Should provide high broadband accuracy for both A&MS and digital

design (at least from DC up to 3rd signal harmonic) in actual design environment, including silicon substrate, surrounding vertical and horizontal interconnect, etc.

Designer friendly does not require a deep electromagnetic understanding “protects the designer against himself” supports the given specific technology details (given metal stack,

dielectric structure etc.) simple and very fast in operation

Fully integrated within common design flows (e.g., Cadence, CTE) Supports all simulation kinds: transient, AC, S-Parameters, PSS

IBM Labs in Haifa


The Vertical T-line Concept

metal

Oxide Silicon

S GG

Properly shielded, predefined T-line designs are the key for bothcritical horizontal and vertical wires in any IBM silicon chip technology

The 10 year Haifa T-line design and modeling expertise as the core IP Planned to be fully integrated within future BTV 3DI design kits as T-

line style devices We target standard best design practice vertical structures, thereby

both improving the performance and simplifying the modeling

TSV T S T-line

IBM Labs in Haifa


The silicon dielectric relaxation effectfirst discussed during my 2008 visit to YKT

G

Grounded silicon

SGoxide

IBM Labs in Haifa


TSV + small C4 combinationESCHER& z360

S0

SP

G GS G GS

Face to back and face to face combinations are possible in principle

IBM Labs in Haifa


TSV connection to C4:Vertical model domain

RB

RA

YF

WIWJ

WK

6.86

Array DT Moat

DTp-

n+

50

4

1.0 ?

5.61

2.612.0

3.0

1.0

TSV model domain

TSVV

N+ Epi SOI Target Dopant Profile

1.0E+12

1.0E+13

1.0E+14

1.0E+15

1.0E+16

1.0E+17

1.0E+18

1.0E+19

1.0E+20

0 1 2 3 4 5 6 7 8

Depth (um)

Phos

(at/c

m3)

To package

22SOI 3DI DM,

Sep 2010

z360 (22nm)

IBM Labs in Haifa


“4-on-7” C4 Pattern (typical)

gnd

vdd vcs

S S S S S

S S S S S

185.618

5.6

vdd vdd vddvcs vcs

gndgndgndgndgndgnd

gnd gnd gnd gnd gnd gndgnd

Signal TSV to be modeled

12

TSV connection to C4:Horizontal model domain

TSV corner parameter [-1 ..1] Considers the 1 and 2 neighbor TSVs impactCorner = -1: neighbors bear “hostile” signals Corner = 0: neighbors are ground/VDD Corner = 1: neighbors bear “friendly” signals

371.2

z360 (22nm)

IBM Labs in Haifa


TSV pattern – problem definition

gnd

1

2

gnd

gnd

gnd

gnd

gnd

S

z360 (22nm)

IBM Labs in Haifa


TSV model user interface

Delivered to 3DI team on Nov 30 2010

z360 (22nm)

IBM Labs in Haifa


TSV model results: S-parameters up to 60GHz z360 (22nm)

IBM Labs in Haifa


Mini-C4 connection between 2 strata for z360:horizontal model domain

Signal Mini-C4 to be modeled

gnd1

2

34

5

6

gnd

gnd

1

2

34

5

6

gnd

Mini-C4 corner parameter [-1 ..1] Considers the 1- 6 neighbor mini-C4’s impactCorner = -1: neighbors bear “hostile” signals Corner = 0: neighbors are ground/VDD Corner = 1: neighbors bear “friendly” signals

RB wiring connected to GND mini-C4s

z360 (22nm)

IBM Labs in Haifa


Mini-C4 connection between 2 strata:RB wiring impact in case of grounded neighbors and RB wiring

mini-c4 capacitance to grounded neighbors:impact of the gap between pads and GND wires

55.0

60.0

65.0

70.0

75.0

80.0

85.0

0 10 20 30 40 50 60 70

gap, um

C, f

F

RB power grid removed: C = 24 fFOnly wires close to pads removed: C = 33 fF

gap = 1.2um =min DRC

70

1.2

z360 (22nm)

IBM Labs in Haifa


Mini-C4 model user interface

Corner factor

Delivered to 3DI team on Nov 9 2010

z360 (22nm)

IBM Labs in Haifa


Mini-C4 model results: S-parameters up to 50GHz

Proper shielding in RB level reduces crosstalk between mini-C4s

z360 (22nm)

IBM Labs in Haifa


Target:Design and develop compact models for metal on-chipinterconnect at THz frequencies in existing silicon technologies

Exploratory Research:Explore the boundary between electronics and photonics

• What are the fundamental physical limitations for using metal wires, as opposed to dielectric fiber optics, as on-chip interconnect at ultra high frequencies?

• How to design such ultra high frequency T-lines on-chip?

• How to model these T-lines?

Why do we think it will be successful:We have a proven expertise in the design and compact modeling of broadband on-chip metal interconnect, confirmed by hardware measurements from DC till 110GHz, and used extensively in IBMYKT 60GHz wireless designs.

THz On-Chip: THz level T-line Devices

IBM Labs in Haifa


Surveillancemedical

• 94GHz and 120GHz Radar and imaging applications exist today, which require modeling up to the 3rd harmonic (~360GHz)• THz transistors are becoming reality: Ft =400GHz for SiGe (500GHz nitrogen cooled), 660GHz for InP, etc. • THz frequencies are considered for security surveillance and medical imaging applications:• New idea: THz fiber communication !

THz level on-chip metal interconnects will be needed

THz On-Chip: THz level T-line Applications

IBM Labs in Haifa


Early feasibility study in Haifa shows that: Our electromagnetic analytical T-line modeling approach can be in

principle upgraded to the THz regime – including a complete DC to THz bandwidth modeling.

HFSS verification of the T-line models can be used up to 1THz as first step. Some EM verifications up to 400GHz of our single microstrip T-line have already been performed.

Calculations show that specific copper T-line structures can perform well at 1 [THz]

Fundamental physical effects up to 10THz are being studied in Haifa:- Nonlinear metal scattering effects (Drude model) starts beyond several THz and can be formulated and included in the model- THz effects in semiconductors are under study

Potential collaboration: wuppertal university (Germany): (Ullrich Pfeiffer, a former IBMer) for

performing measurements up to 4 THz (amplitude only).

THz Bandwidth T-line Devices – current progress

IBM Labs in Haifa


When the period of the radiation becomes comparable to the mean time between collisions in the metal (relaxation time), we get that:

The metal conductivity δ starts to decrease, becoming inversely proportional to the frequency

The skin depth δ stops to be frequency dependent, and saturates

The T-line resistance per unit length R starts to grow in proportion to the frequency (no more to the square root of the frequency) till the losses become excessively high

THz Bandwidth T-line DevicesThe Skin Depth Saturation Effect

f

σDC

f

δsat

Fc f

Log(R)

RDC

Log(δ)

Fc FcFtr

√f

f1 / √fConst.

1 / f

Log(σ)

00

2

π21Fc m

nq nm

qsat 021

250)(

6)(

Cusat

THzCuFc

IBM Labs in Haifa


TeraMos Research Background Research Collaboration between IBM and Technion -

Israel Institute of Technology Research Proposal to European Community: FET OPEN

not accepted – now applying for another one IBM FACULTY AWARD 2008 )Y. Nemirovsky, Technion -

Israel Institute of Technology, promoted by David Goren) TMOS (CMOS-SOI-MEMS) transistor for uncooled IR

Imaging, published IEEE Trans. On Electron Devices, Nemirovsky Group, Technion

TMOS Technion patent application (2003) TeraMos Technion provisional patent application

(2008) IBM Antenna Coupled THz sensor patent (2010) HRL No. 1 FRR project.

IBM Labs in Haifa


TeraMOS - THz FPA Imaging silicon chip with MEMS post processing

IBM patent FILEDcapacitively coupled antenna conceptImproves performance dramatically

IBM innovative on-chip antenna design

Suspended diode / transistor by MEMS

Technion Patented Technology

2D FPA testsite in IBM CSOI7RF – back in Haifa

Firm calculations show NEP ~ 1 pW/√Hz – Passive THz Imaging in Silicon!

IBM Labs in Haifa


Operation Principle of Thermal Sensors

Simplified modeling assumes a thermal mass capacitance C connected to a heat sink at T0 through a total thermal conductance G which absorbs the radiation power P with efficiency

d TC G T Pdt

2

/0

1 2

( ) (1 )t

P f GT f

CfG

PT t eG

Steady State:

Thermal Time Constant: CG

0PTG

Heat Balance eq.

Heating Transient:

IBM Labs in Haifa


The patented TMOS / TeraMOS Detector

The sensing element is a MOS transistor operating in sub-threshold The current mechanism is diffusion and is therefore very sensitive to temp. The enabling technology is any standard CMOS-SOI process (IBM is excellent) Sensor matrix is fabricated first, followed by micromachining post-processing

which can be done at the Technion or any advanced MEMS facility Measured sensitivity of TMOS ~ 4% (better than standard Honeywell

bolometers) - achievable NETD < 30mK for IR imaging (8-14um) The TeraMOS detectors are made of large multi-finger transistors on the larger

THz pixel dimensions (200um x 200um)

IBM Labs in Haifa


Transistor

holding arm: electrical wires &thermal isolation

Thermally Isolated Transistor as “active Bolometer”

Taking the THz Bolometer Concept to its feasible limit

IBM Labs in Haifa


MOS transistor operating in the sub-threshold region

VDD

Vg

Id

2 2

*2

2

1 1

1 1 ( )

GS T

DS BB

V Vq

qV k Tnk TBDS ox

TGS T

k TWI C n e eL q

dVdI q qTCC V VI dT T nkT nkT dT

Exponential Current Temperature DependenceLarger TCC at deeper subthreshold Low Power Consumption Low self heating (no need for pulsed operation)

E. Socher, S. M. Beer, Y. Nemirovsky, "Temperature Sensitivity of SOI-CMOSTransistors for Use in Uncooled Thermal Sensing", IEEE Trans. On ElectronDevices, IEEE Trans. On Electron Devices, 52(12), 2784-2790 (2005)

The active bolometer

IBM Labs in Haifa


TeraMOS MEMS Fabrication in the Technion: Built-in Al Masks provided by CMOS

- Active

- Poly

- Met1

- Met2

- Met3

- ILD

- BOX

- Wafer

(a) (c)(b) (d)

CMOS-SOI Wafer Fabrication in any Standard FAB – such as IBM Back Side DRIE Anisotropic Etching of Silicon,

BOX provides etch stop Front Side RIE Etching of ILD using CHF3;

flourine plasma does not etch Al Masks Front Side Metal Mask Etching

IEEE Trans. On Electron Devices (2009)

IBM Labs in Haifa


Measured noise current PSD (Technion)of "virgin" & TMOS transistors at 30Hz

from deep subthreshold to saturation.

10-10

10-8

10-6

10-4

10-28

10-26

10-24

10-22

10-20

Drain Current (A)

Pow

er S

pect

ral D

ensi

ty (

A2 /H

z)

P43 VirginP43 TMOSP68 VirginP68 TMOS

Estimatedoperation

current

Releasing increases a bit the 1/f noise

IBM Labs in Haifa


IR Electro-optical Characterization:Experiment set up in the Technion

• Detector is electrically biased for correct operation point

• Black Body radiates IR radiation (power level depends on temp.)

• Chopper is used to lock the signal in lock-in amplifier

• Output is measured vs. chopper frequency

IBM Labs in Haifa


Signal vs. chopper frequency:Excellent fit of measurement to theory

2)2(1

1)(**)(

GCf

GfPITCCfSignal

IBM Labs in Haifa


The Antenna Coupled TeraMOS (IBM Patented)

Includes high bandwidth back-reflector on a separate chipActual antenna type may differ from this one

IBM Labs in Haifa


300 um

Antenna

AntennaAntenna

Platform

~20um

IBM TeraMOS Pixel Design

Arm length designed for G=1.6x10-8 Watt/°K

Proper mechanical design of holding arm is critical to minimize platform deflections !

Fill Exclude around the antenna (from all metals and poly and RX as well) is crucial to maintain proper antenna performance!

Metal densities

Are far exceeded

in this design (AM

And MT)

It is crucial to design the bending of the holding arm to minimize any horizontal and vertical displacements of the platform !

This is the main bottleneck of this whole design.

IBM Labs in Haifa


Preliminary Layout – Full Matrix

0.2um RIE shielding

0.5um RIE shielding 0.1um RIE shielding

1um RIE shielding

Orange square is DRIE hole. We have 4 X (2 X 2) pixels. Each quarter will contain 2 diodes and 2 NMOS

IBM Labs in Haifa


TeraMos System Design Goals

Topic TeraMOS Design Goals

New System Compact Passive Staring FPA (0.6-1.5THz); for stand-off ranges of ~10-50 meter and real-time passive imaging.High Performance (NETD <1K);Low Cost (<$10000). Image: metallic, ceramic or plastic objects (security - people screening)tissue, tumours, teeth (medical – skin cancer detection, dental)

New TeraMOS Sensor

low NEP- Noise Equivalent Power – 1pWatt/ Hz1/2;Low NETD- Noise Equivalent Temp. Difference-<1K. Oper. Temp.: 77K (a good compromise between noise reduction and added system cost). Stirling cooler ~ $4000, MTTF: 15,000 hours)

New FPA architecture

High bandwidth of operating frequency: 0.6-1.5THz. Low Freq.- 0.6THz: optimized to wavelength penetrating clothing;High Freq.- 1.5THz: optimized for spatial resolution

IBM Labs in Haifa


Backup Slides

IBM Labs in Haifa


Standard CMOS-SOI TechnologyStandard Bulk Micromachining and Built-In MasksActive bolometer – MOS transistor at sub-thresholdLow current eliminates self heatingOn-Chip High resolution THz Focal Plane ArrayOn-chip integrated analog readout in standard CMOSPotential passive THz imaging at room temperaturePotential massive deployment for low cost passive

THzremote imaging at any crowded place

Medical applicationsJust applied to a European fund project (FP7)

Summary – TeraMOS Advantages

IBM Labs in Haifa


Early 2008 beginning –“TSV first” processTSV first

a) ~1.2 um, landing pad

b) ~12-13 um TSV post though Si and m1-c1 BEOL

c) ~10 um TSV though c2-ub+ BEOL

d) ~1-2 um post key

e) ~22-23 um

a

c

b

d

e

IBM Labs in Haifa


2008 – 2009 beginning –TSV / MSV pair connection

MSVTSV

TSV/MSV pair Black Box boundary

TSV / MSV pair

IBM Labs in Haifa


TSV/MSV pair within the dense via farm: modeling approach

TSV/MSV pair to be modeled

TSV / MSV pair

IBM Labs in Haifa


TSV/MSV pair model: Cadence S-parameters simulationTSV / MSV pair

IBM Labs in Haifa


TSV/MSV pair model RLCG simulation up to 40Ghz, nominal (corner factor=0)TSV / MSV pair

IBM Labs in Haifa


TSV Model:Example

Modeled element

Lumped Model

Lumped model: built from s-parameter data; in use for short-reach, long-reach I/O analysis

Parameterized models have been built to support technology definition exploration

Model-hardware correlation structures and test plan in place (Escher technology sites)

Depth: 70

All units: m

large low frequency cap:

key issue for I/O

Example result: EM solver vs. modeled TSV capacitance characteristic

From Status Update for Milestone“Complete Interconnect Compact Model Delivery, I/O

Circuit Design, and Design for Test Plan for 3D Test Vehicle”

by D. Friedman, YKT, Jan 2009

TUNGSTEN TSV

IBM Labs in Haifa


Cadence S-parameters simulation example(Tungsten TSV symbol shown)

TUNGSTEN TSV

IBM Labs in Haifa


4 bar tungsten TSV EM solver and Haifa model resultsexpressed as RLCG(f) up to 50GHz

TUNGSTEN TSV

IBM Labs in Haifa


Investigating 3D I/O Demands TSV, mC4 Modeling Key I/O questions to be addressed by Escher work

Performance of long reach links (where the TSV is an added impairment for a backplane link) Performance/power requirements for short reach links (those connecting layers within a 3D stack)

S1

S0

S2

[Note: modeling work can also be leveraged to predict through-via performance of alternate technology approaches and for Si carrier through-via analysis]

Key elements to be modeled Inter-layer elements

Single signal-carrying C4 in various environments

Single set of signal-carrying W TSV bars in various environments

Stack escape elements Group of signal-carrying W TSV bars

in a C4 unit cell in various environments

From Status Update for Milestone“Complete Interconnect Compact Model Delivery,

I/O Circuit Design, and Design for Test Plan for 3D Test Vehicle”

by D. Friedman, YKT, Jan 2009

TUNGSTEN TSV

IBM Labs in Haifa


30um pitch (32 TSVs)

40um pitch (32 TSVs)

With TSV

Observed TSV capacitance behavior for the first time from measurement

2-bar W-TSV:

1.5 um wide6 um long10 um pad0.5 um thick oxide25 um tall5 um bar-to-bar separation30um/40um pitch (TSV-to-TSV)

Xerxes TV: A 300-mm wafer-level 3DI process using W-TSV and hybrid Cu/adhesive wafer bonding for BEOL; technology reported in IEDM, Dec, 2008 (Liu, F., et al.); TSV L/C/RF test sites measurement/characterization completed in Apr. 2009.

Without TSV

Independent measurements (YKT) confirm the silicon dielectric relaxation strong effectTUNGSTEN TSV

IBM Labs in Haifa


A deeper study: Cu or W TSV?RDC(via diameter) of cylindrical Cu TSV (oxide th =0.5 um)

vs. tungsten TSV structures, for the same TSV length=70um

0.00

0.02

0.04

0.06

0.08

0.10

0.12

0.14

0.16

5 7.5 10 12.5 15 17.5 20

Cu via diameter, um

R, O

hm

cylindrical Cu, R(via diameter)

R(4 bar W)

maxR=2mV/200mA=10 mOhm

Cu TSV with diameter >12.5 um meets the max current requirements

CDC(via diameter) of annular copper TSV (oxide th =0.5 um) vs. tungsten TSV structures, for the same TSV length=70um

75

175

275

375

475

575

675

5 7.5 10 12.5 15 17.5 20

Cu via diameter, um

C, f

F

annular Cu, C(via diameter)

C(1 long bar W)

C(4 bar W)

Cu TSV with diameter <12.5 um, oxide liner th=0.5 um is better than both tungsten TSV structures

CDC(oxide thickness) of annular fat copper TSV (D=21 um) vs. tungsten TSV structures, for the same TSV length=70um

175

275

375

475

575

675

0.5 0.6 0.7 0.8 0.9 1oxide thickness, um

C, f

F

annular fat Cu, C(oxide thickness)

C(1 long bar W)

C(4 bar W)

Fat Cu TSV with oxide liner th>0.9 um is better than both W TSV structures

Electrical considerations: bottom line Currently suggested Cu TSV is better Thicker Cu TSV oxide liner is desirable Smaller Cu TSV diameter is desirable

IBM Labs in Haifa


wq via - 1.0 um thick Cu

oa wiring level – 3.0 um thick Cu

tv stack

0.1 um nblock k=5.3

0.2 um nitride k=7.0

0.65 oxide um k=4.1

td - 1.2 um AL is wide enough (36 um) to shield the bump from upper layers

fv stack


0.45 nm oxide k=4.1

tm stack

0.1 um Ti/W

0.43 um Cu

1.0-2.0 um Ni ( 1.0 um likely )

0.05 um Au

uC4

10-15 um Pb free bump ( closer to 15 um likely) - 15 um in the model Contacts resistance = ?

wk metal stack

0.1 um Ti/W

0.5 um Cu

1.0-2.0 um Ni - 1.0 um in the model 0.05 um Au ( no Au if plating solder )

pbSn ( need Au for lead free )

3DI vertical interconnect based on Cu annular TSV:tech input and models scope

wi metal stack

0.1 um Ti/W

0.5 um Cu

wj opening

1.0 um nitride

oxide cap 1.0 um

uC4model domain

TSVmodel domain

To beextracted

underfill k=3.824

ESCHER

IBM Labs in Haifa


Copper annular TSV model scope – side view

WI backside Cu endplate: 36x36um, th=0.5umDielectric over the silicon: k=4.1, th=1um

TSV part surrounded by silicon: Cu diameter = 21 umsilicon thickness = [30..70] um, thnom = 50umk =11.9, sigma = 0.135 Ohm*moxide liner th = [0.6..1.5] um, thnom = 0.5 um

TSV part surrounded by BEOL: BEOL thickness = 5.05 um BEOL effective keepout square 25.33x25.33umBEOL effective k = 4.1

UA frontside Cu endplate: 24.2x24.2um, thickness = 1.2 um UA keepout width = 25.8 um

TSVmodel domain

Note: Black – constant values Green – model parameters

ESCHER

IBM Labs in Haifa


Copper annular TSV model Top view

TSV XY pitch = 46.4 um

46.4 um

Cu diameter = 21 um

Core diameter = 6 um

oxide coat th = [0.6..1.5] um, thnominal = 0.5 um

TSV corner parameter [-1 ..1] considers the 8 neighbor TSV’s impact Corner = -1: neighbors bear “hostile” signals Corner = 0: neighbors are ground/VDD Corner = 1: neighbors bear “friendly” signals

Modeled TSV

Note: Black – constant values Green – model parameters

ESCHER

IBM Labs in Haifa


Copper Annular TSV Model vs. EM Solver

RLCG for TSV length=50 um, oxide thickness=0.6 um, Corner = 0

ESCHER

IBM Labs in Haifa


wq via - 1.0 um thick Cu

oa wiring level – 3.0 um thick Cu

tv stack

0.1 um nblock k=5.3


0.65 oxide um k=4.1

td - 1.2 um AL is wide enough (36 um) to shield the bump from upper layers

fv stack


0.45 nm oxide k=4.1

tm stack

0.1 um Ti/W

0.43 um Cu

1.0-2.0 um Ni ( 1.0 um likely )

0.05 um Au

uC4

10-15 um Pb free bump ( closer to 15 um likely) - 15 um in the model Contacts resistance = ?

wk metal stack

0.1 um Ti/W

0.5 um Cu

1.0-2.0 um Ni - 1.0 um in the model 0.05 um Au ( no Au if plating solder )

pbSn ( need Au for lead free )

uC4 Model Scope: Side View

wi metal stack

0.1 um Ti/W

0.5 um Cu

wj opening

1.0 um nitride

oxide cap 1.0 um

uC4model domain

TSVmodel domain

To beextracted

underfill k=3.824

ESCHER

IBM Labs in Haifa


uC4 model scope – Top View

uc4 XY pitch = 46.4 um

46.4 um

uC4 diameter = 24 um

uC4 corner parameter [-1 ..1] considers the 8 neighbor uC4’s impact Corner = -1: neighbors bear “hostile” signals Corner = 0: neighbors are ground/VDD Corner = 1: neighbors bear “friendly” signals

Modeled uC4

ESCHER

IBM Labs in Haifa


Extraction scope - parameters

2.4

(OA width > 6 μm) min space ≥ 2.4

Neighbors: wide wires

0.8

UB connection: 1power wire removedNeighbors: w=2.4 um, s = 0.8 um nested

1.2

3.0

0.95

1.2

1.6

1.0

0.9

ub 24.2x2.4

14

uC4model domain

TSVmodel domain

To beextracted

ESCHER

IBM Labs in Haifa


“Extracted” part: worst case close neighbors in OA and UB (min DRC away)

C = 54.2 fF

ESCHER

IBM Labs in Haifa


“Extracted” part: best caseneighbors in OA and UB are far away

C=8.96 fF

ESCHER

IBM Labs in Haifa


Sample Simulated Results5 Signal Lines: CPW vs. RC vs. EM Solver, 11000 mode, S-parameter format stack: 323102, signal in UB, crossing in UA, parallel in E1, w=s=2um, d=3um

1mm lines, simulation from 10[MHz] up to 50[GHz]

IBM Labs in Haifa

© 2008 IBM Corporation94 Significant impact of TSV on I/O performance

Cu-TSV W-TSV

1 Gb/s 10 Gb/s

Cu-TSV W-TSV

TSV Haifa circuit level models enable high-speed I/O analysis for 3D electrical link !

driver

receiver

3 cascaded TSVs connected by uC4

pattern generator

I/O simulation using Escher TSV models for 3D design (YKT)

ESCHER

IBM Labs in Haifa


Haifa broadband TSV test cage on Escher 3DI 45nm test site

ESCHER

IBM Labs in Haifa


TSV capacitance measurements vs. modelResults at 1MHz

4:4C=932 fF

2:2C=497 fF

6:6C=1369 fF

OpenC=71.5 fF

Signal to grounded chuck capacitance measurements

Signal to chuck capacitance de-embeddingFor n=2, 4, 6: Cmeasured (n) = Copen + n*CTSV + (n-2)*Cconnector

For n=2: CTSV = 212.75 fFFor n=4, 6: CTSV = 211.75 fF,

Cconnector = 6.75 fF

(parallel plate estimation Cconnector ~ 7.2fF)

Measured Escher TSV capacitance at zero bias = 212 fFModeled low freq. capacitance (oxide liner th = 0.7um) = 227 fF

ESCHER

IBM Labs in Haifa


Depletion-mode Capacitance Effect on TSV Performance (YKT)

Depletion effect improves TSV signal integrity (estimated ~17% reduction of TSV low freq C for Escher); Capacitance test sites added on EV0/Escher TV for measurement and characterization

Potential new applications: e.g., tune TSV capacitance to change signal timing

r0r1

r2Cu

Oxide liner

Depletion region

( Source: SRC Project IBM-Georgia Tech)

Coxide CdepletionDepletion effect reduces TSV low frequency capacitance

C_TSVC_oxide

Escher TSV diameter

The depletion effect is relatively smallTo estimate it, low frequency measurements are required

IBM Labs in Haifa


TSV measurements vs. model preliminary results: 2:2 CG up to 50GHz

Even mode

S GG GGGG G G

ESCHER

IBM Labs in Haifa


Architecture of TeraMos FPA for Passive Terahertz Imaging (0.6-1.5 THz)

pixels for 1.5THz: 200µm*200µm – higher resolution pixels for 0.6THz: 500µm*500µm – higher clothes penetration Adapting the required pixel dimensions by applying a novel

variable pixel concept based on readout circuitry

IBM Labs in Haifa


We have conceived, designed and modeled a maximal flexibility Variable T-line device in IBM 32nm SOI technology.

Tuning resolution of 4 bit was found practical and sufficient. Optimized design yields high delay tuning range of ~20%. Works well within a dedicated matching network enabling

flexible design styles. Minimal area on silicon and minimal power consumption to

operate. Dedicated existing versions enable multiple background

impedances, fine length tuning resolution, and higher frequency bandwidth exact modeling.

Variable Delay T-lines SUMMARY

IBM Labs in Haifa


TSV model results: RLCG up to 60GHz z360 (22nm)

IBM Labs in Haifa


S-parameters for a simple microstrip structure with parameters: w=4.5um, h=10.45, t=4um, wg=33.4, tg=0.32, length of the microstrip is 150um

Aluminum signal layer (sigma =3.57e7 siemens/meter), Copper ground layer (sigma = 3.48e7 siemens/meter)silicon oxide dielectric (relative epsilon = 4.1)

w

signal

ground

h

t

wg

tg

w

signal

ground

h

t

wg

tg

T-line EM solver results up to 1THz

IBM Labs in Haifa


June 1998 – Research starts at IBM Haifa Research Labs January 2000 – Start of joint work with IBM FAB (Burlington) Design

Automation Department January 2001 – Haifa T-line models inside IBM Design kit January 2002 – Haifa owns T-line model and design R&D for all IBM

leading edge chip technologies December 2002 – IBM Research Accomplishment Award Jan 2005 – T-line models upgraded to include crossing lines and full

closed environment consideration April 2005 – 60GHz on chip 4:1 transformer based on T-line theory August 2005 – T-lines used in a the big IBM Loki project (Xbox 360) Dec 2007 - IBM Outstanding Research Accomplishment Award 2008 – 3DI TSV / mC4 modeling startup 2009 – THz level T-line devices + THz imaging research (MEMS) startup Till 2011 – 18 patents, 22 publications

IBM On-Chip Interconnect Project History

IBM Labs in Haifa


Standard CMOS upper metal layers (Al) provide masking for post-processing

(a) CMOS-SOI Wafer Fabrication in Standard FAB

(b) Back-Side DRIE Anisotropic Etching of SiliconBOX provides etch stop

(c) Front Side RIE Etching of ILD using CHF3flourine plasma does not etch Al Masks

(d) Front Side Metal Mask Wet Etching

The MEMS Post-Processing

Currently performed at the Technion

IBM Labs in Haifa


TargetProvide means to design circuits including on-chip critical wiring enabling precise prediction of the expected circuit behavior

Required solution features Designer friendly

simple and very fast in operation does not require a deep electromagnetic understanding “protects the designer against himself” supports the given specific technology details (given metal stack,

dielectric structure etc.)

Should provide high broadband accuracy for both A&MS and digital design (at least from DC up to 3rd signal harmonic) in actual design environment (including crossing lines, silicon substrate etc.)

Fully integrated within common design flows (e.g., Cadence, CTE)

Supports all simulation kinds: transient, AC, S-Parameter, PSS

On-Chip Interconnect Design and Modeling Challenge

14 year hrl research

Documents