Lecture 4.2 INTERNATIONAL TEST CONFERENCE 1 978-1-4799-0859-2/13/$31.00 ©2013 IEEE

12Gbps SerDes Jitter Tolerance BIST in Production Loopback Testing with Enhanced Spread Spectrum Clock Generation Circuit

Yi Cai, Liming Fang, Ivan Chan, Max Olsen and Kevin Richter

LSI, Inc

1110 American Parkway NE, Allentown, Pennsylvania 18109

Email: yi.cai@lsi.com

Abstract: We designed and tested an on-chip BIST test for high speed SerDes devices. Jitter Tolerance testing is a critical way to stress the SerDes receivers. A jitter free loopback test hardly represents the real application environment. We implemented a jitter injection technique to precisely injecting the amount of in-band and out-of-band jitter to effectively testing receiver clock and data recovery circuits (CDR). Because out-of-band jitter is more effective in stressing the CDR, it is critical to generate jitter frequency that is higher than the receiver CDR loop bandwidth. Both the jitter frequency and amplitude can be programmed digitally in this BIST implementation. And more importantly, it does NOT require any external instrument for calibration. As a result, overall production test coverage is enhanced without additional test cost and tester instrument calibration hardware. 1. Introduction: The evolvement of backplanes from bus-based architectures to fabric/mesh-based architectures has fueled rapid deployment of multi-gigabit serializer and de-serializer (SerDes) devices. The serializer does not transmit a dedicated clock signal. Instead the deserializer needs to have the capability to lock to the received data signal, extract the clock/timing information, retime/resample the received signal with the recovered clock, and make correct detections of the intended transmitted signal. As a result, the two key circuit blocks in the receiver are the clock and data recovery (CDR) and the equalizers (EQ). The CDR extracts the timing information and keeps the data latch staying in the center of the data eye. The EQ reshapes the signal such that logic one is correctly distinguished from logic zero. In addition, because of the leading edge speed of the SerDes devices, the serial data rates under test are generally faster than what the tester can support. So in many cases, looping back the Tx to Rx for a self test is used. However, a jitter free loopback test hardly represents the real application environment. This Built-In-Self-Test (BIST) for the CDR circuit is designed in particular for production test using Automated Test Equipments (ATE). The industry recognized method of

exercising the CDR circuit is through the compliance jitter tolerance (CJT) test. Jitter is defined as deviation of an actual signal edge from the ideal position, which has many contributing components (i.e. DCD, ISI, PJ, RJ and etc…). The periodic jitter (PJ), also referred to as the sinusoidal jitter (SJ), is commonly used in jitter tolerance tests by modulating the signal before it reaches receiver inputs. Two parameters that define the PJ are the jitter amplitude and the jitter frequency. The CDR circuit reacts differently to different PJ frequencies. When the PJ frequency is low and within the bandwidth of the CDR, the CDR could track the jitter and move along with the jittery signal edges. In that case, the recovered clock stays in the center of the data eye. However when the PJ frequency goes higher than the CDR tracking band, the jitter cut into the timing recovery margin for the CDR. That is why the out-of-band jitter is an effective way to test CDR tolerance margins.

Figure 1 USB 3.0 electrical compliance test methodology. Precision PJ generation has been an important component of electrical compliance test methodology on many serial data communication standards. For example, Figure 1 shows USB Super Speed (USB 3.0) compliance test requirements.

Lecture 4.2 INTERNATIONAL TEST CONFERENCE 2

Despite the importance of jitter testing, test methods and equipments targeted for volume production ATE applications are not widely available. This is partially attributed to the fact that the leading edge SerDes development has outpaced the tracking capability for many testing equipments including ATE. Therefore, the need exists for jitter tolerance test on ATE. It is also a prerequisite for any ATE tests to be cost effective and time efficient for high volume production. Conventional ATE testing is typically internal and external loopback tests. Although the printed circuit board (PCB) traces used in loopback create some ISI type of jitter, but it is hardly a rigorous CDR stress test. Although one can tune the PCB trace as cable equivalent filters to stress the Rx properly. [1] It is hard to control or even quantify the amount of ISI generated through these PCB traces. And because the layout constrain, it may not be possible to tune the traces length for large number of SerDes ports on the same PCB. Therefore, loopback functional test alone is inadequate for CDR test coverage. As a result, the devices with marginal performance can escape from production test and cause system failures for the customers. Such problems are very difficult to debug once in a system and the replacement cost is extremely high. The lab characterization can provide a more comprehensive test of the CDR performance with proper jitter injection. [2] An example of jitter tolerance test setup is shown for XFI 10G in Figure 2. This lab setup costs over $300K. Apparently, this setup involves expensive test equipments and requires constant supervision of experienced engineers. It might be feasible for a small sample sized characterization, but not feasible for high volume production test. To achieve an aggressive low defect rate required by some customers, we still rely on DFT innovations. A few BIST or BOST jitter tolerances techniques have been reported. In [3] [4], the amount of jitter tolerance injection is limited by external PCB and voltage offset induced DCD. This technique requires calibration, but the author can use on-chip jitter measurement capability to properly calibrate the jitter injection. In this method the jitter tolerance measurement is deduced from the internal CDR timing margin instead of a direct sweep of jitter injection. In [5], higher amount of jitter tolerance injection has been achieved through directly modulating the PLL. This made a smooth sweep of jitter input possible, but the PLL modulation limited this technique in generating higher frequency jitter to stress the CDR. Other BOST solutions use delay line modulation to add jitter [6] [7], which can achieve much higher frequency but not feasible for a low overhead BIST case. There was other DFT technique to inject jitter using phase interpolator or timing vernier reported in [8] [9]. They use phase select, which was limited by slow software control rate at the time of publication. In this publication, we present a jitter injection solution that can generate much higher

bandwidth jitter, smooth sine wave modulation and no need for offset calibration. [10]

Figure 2 Jitter tolerance test lab characterization setup for XFI 10G. 2. Jitter Tolerance BIST with Enhanced SSC circuit 2.1 Design requirements for using SSC generator for jitter injection In this publication we will present our patent pending DFT implementation for conducting jitter tolerance test in production loopback mode. We utilized an on-chip circuit to generate the jitter needed for jitter tolerance testing. On the production test ATE board, it looks like just a clean external loopback with no add-on circuit at all. Since it can be easily integrated with other functional tests, our method makes jitter tolerance test practical for high volume production test. Our goal is to provide a precise, at speed, and yet low cost solution for jitter tolerance test, so the DFT overhead needs to be very low. All the jitter generation and calibration is on the silicon leveraged from existing circuit, instead of dedicated circuits for testing. In this case, we leveraged the circuit for supporting the SSC (Spread Spectrum Clocking) for this DFT needs. In order to use this DFT as a self contained BIST, it is essential to avoid the needs for external calibration. We achieved that by making the jitter injection function fully synthesized and controlled digitally. This digital approach also simplified the test automation process. In addition, it can be applied on a wide range of ATE platforms because of its tester independent nature. 2.2 Design implementation - a Numerical Control Oscilator (NCO) based SSC design

Lecture 4.2 INTER

Theoretically, we can generate precision peon-chip with precisely controlled frequency controlled duration of time. That will movement as jitter for this test. However,transmitter clock beyond receiver tracking as straight forward. In most applications, thaggressive low jitter design target. Thergeneration PLL’s priority is the loop stabloop bandwidth is controlled much lower counterpart. In other words, if the transmittebandwidth needed to stress the receivetransmitter clock stability is compromiproducing higher jitter from Tx. That is theone would use this bluntly just for DFT. Onmodulation is required on the transmit sspread spectrum clocking (SSC). The SSC for many SerDes industry standards like SHowever, the SSC modulation is mere30~100KHz range, where the CDR will haissue to track. That makes it harmless to thecan NOT rely on this slow modulation to effectively in test. In this application, our SSC circuit is capableclock with more than 100MHz bandwidth. Tgenerate jitter out of the receiver loop bandwSSC design can achieve that. Some of tactively modulates the PLL divider ratios SSC frequency profile, but dynamically chdivider is too slow to generate the required ofrequency. We worked around this issubandwidth modulation NCO design. In frequency adder is separated from the mainloop as illustrated in Figure 3. In this waybandwidth is not compromised by requirement. This new NCO design bacontradicting design requirements (i.e. the hibandwidth needed for adding jitter in test mostability to suppress Tx jitter in mission mod

Figure 3 NCO design for SSC generation In normal SSC mode as shown in Figufrequency modulation is used. The SSC pr

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eriodic jitter (PJ) offset only in an introduce phase , modulating the frequency is not

he Tx design has refore the clock bility factor. The than its receiver

er allows a higher er in test, the ised and hence e reason why no

nly low frequency ide such as the is a requirement

SAS and SATA. ely in the low ave absolutely no e receiver. So we

stress the CDR

e to modulate the That is enough to width. Not every

the SSC designs to generate the

hanging the PLL out-of-band jitter ue with a high this design, the n VCO feedback

y, the modulation stability factor

alanced the two igher modulation ode, and the PLL

de).

ure 4, a triangle rofile is digitally

controlled to ramp up and down ithis.

Figure 4 Normal SSC mode wmodulation profile

Figure 5 Toggle mode for SSC isinjection When we use the SSC generator ijitter injection, as shown in Figfrequency are programmed to tofrequencies (fmax and fmin), the duraalso precisely controlled. This resulphase error accumulation from thduration of such offset, as shown inthe desired PJ frequency from 3amplitude is also programmable fro

Figure 6 Phase error accumulatithe programmed frequency offeach period in a eye diagram forminjected is illustrated.

3

in small steps to achieve

with triangle frequency

s used to generate jitter

in test mode for periodic gure 5, the SSC clock ggle between two fixed

ation of each frequency is lts in a digitally controlled he frequency offset and n Figure 6. We can obtain MHz to 150MHz. Jitter m 0 to a full UI.

ion over the cycles with fsets. When overlaying mat, the amount of jitter

Lecture 4.2 INTER

The mathematical model for this phase errorderived below. If we define the frequencymaximum frequency (fmax) and minimum frpart per million (ppm) as ppmofst , th

transmitter signal is baudF , the frequenc

jittered signal PJoffsetF _ can be defined as:

6_ 10ppm

baudPJoffset

ofstFF ×= ,

From the derivative of phase, we obtafrequency offset (rad/s):

radofst

Fdtd

Fdtd

ppmbaud

PJoffsetPJoffset

.210

2

6

__

π

πω

××=Θ

×==Θ

Integrate the above equations and then we hrad, where PJF is the frequency of PJ inject

radFFofst

Fradofst

F

dradofst

F

PJ

baudppm

PJ

ppmbaud

Tppm

baud

PJ

.2102

2.2

10

.210

6

6

06

π

π

π

××××

=Θ

×××=Θ

××=Θ ∫

Converting the phase to PJ, where ppUI is unit interval:

PJ

baudppmUIin

ppmpp

FFofst

PJ

ofstUI

radPJ

×××

=

×=×Θ=

6_

6

102

102.2π

This is the mathematical model for the perioin this DFT mode with square wave frequenc In standard compliance lab test, the sinusoidcommon used. So we have implememodulation profile to avoid any potential with common lab instruments.

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r accumulation is y offset between requency (fmin) in he frequency of

cy offset of the

ain the angular

rad.π

have the phase in ted:

dt

the peak-to-peak

ppPJ

baud UIFF

×××

6

dic jitter injected cy modulation.

dal jitter profile is ented sinusoidal correlation issue

Figure 7 Sinusoidal Jitter injectioa sine DAC for frequency modula For sinusoidal frequency modulatithe maximum frequency offset betwper million as ppmofst , the frequen

baudF , the frequency offset of thecan be defined as:

10

10

_

max__

max_

ofstFF

FF

ofsFF

pbaudSJoffset

offsetSJoffset

baudoffset

×=

×=

×=

Where SJf is the frequency of modfrequency of resulted SJ. From theobtain the angular frequency offset

ofstF

dtd

Fdtd

ppmbaud

SoffsetPJoffset

si106

__ω

××=Θ

==Θ

Integrate the above equations and thrad:

2102

210

6

6

fofstF

ofstF

JS

ppmbaud

ppmbaud

×××

×=Θ

××

=Θ

ππ

π

Converting the phase to SJ, with resunit interval ppUI :

4

on is implemented using

ation.

ion, again we can define ween fmax and fmin in part

ncy of transmitter signal is

e jittered signal PJoffsetF _

)2sin(

)2sin(0

6

6

tf

tf

t

SJppm

SJ

ppm

×××

××

π

π

dulation, which is also the e derivative of phase, we (rad/s):

radtf

rad

SJ

SJ

.2)2in(

.2

ππ

π

×××

×

hen we have the phase in

)2cos(.

)2sin(.

tfrad

dttfrad

SJ

SJ

×××

××∫

ππ

π

spect to the peak-to-peak

Lecture 4.2 INTER

SJ

baudppm

pp

fFofst

SJ

UIrad

SJ

××××

×=

×Θ=

2cos(102

.2

6 ππ

π

Consider the fact cosine wave is a phase shwe can derive the amplitude of the sinusoida

SJ

baudppmSJ

SJSJ

fFofst

UIA

tfASJ

×××

=

×××=

610)(

)2sin(2

π

π

The following plots illustrate SJ injectionmeasurements from real silicon. Figure generated with a fixed 25MHz square wwhen we programmed the SSC frequency oto 17000ppm using digital control logic. Tresults aligned in a very linear curve for theinjected. The silicon data highly corremathematical model, but at high modulatiodiverge from model is observed. This conresulted from the band-limited distortimodulation waveform. As shown in Figure is about 4ps as 1UI of jitter injected at 6Gbps

Figure 8 At a fixed jitter frequency, a sweoffset generates a linearly increasing jitterjitter amplitude above 120ps, slight error to the waveform distortion at high frequerate. The mathematical model above showed thdigitally control the jitter injection amount –and its duration. The NCO based design inhthe frequency offset accuracy to the

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ppSJ UItf ××× )

hifted sine wave, al jitter:

n obtained from 8 shows the SJ

wave modulation, offset from 0ppm The measurement e amount of jitter elates with the on PPM a slight nversion error is ion of squared 8, the jitter error s.

eep of frequency r amplitude. For will happen due

ency modulation

he two variables – frequency offset herently bounded

digital control

oscillator’s resolution. The durationoffset is also controlled digitallyallowed phase movement accumulaof clock cycles. The end resultaccumulative phase movement, whia very repeatable jitter inject amdevice. This important design featuexternal calibration of the actual jitt

Figure 9 Illustration of Injectamplitude capability with SSC tog Next, we demonstrate a sinusoidal achieve with the same precision. Infrequency changed from a square wmodulation waveform. The jitterintegral or accumulation of the phain Figure 9, we can generate 1.4Uand 0.8UI worth of SJ at 50MHz. Tfor test 12Gbps SAS CDR with higfrequency, and large enough jitter a 3. Accuracy Verification Data forthe SSC Design In this section, we will discuss tinjection frequency and amplitudetheoretically we do NOT need to cinjection, it is still necessary to profile, to make sure that we have target. We used a flexible setup where the device under test (DUThave the option to be connected texternal real-time sampling scope (Tvalidating jitter performance, as sho

5

n in time of this frequency , in terms of maximum

ations over precise number t is a very predictable ich is directly translated to mplitude from device to ure eliminated the need for ter amplitude.

ted SJ frequency and ggle approach.

modulation profile can be n this case, the ppm offset wave to a sine wave as a r amplitude is still the ase movement. As shown

UI worth of SJ at 30MHz, This is more than enough gh enough out-of-band SJ mplitude.

r the Jitter Injection with

test setup to verify jitter e accuracy. Even though calibrate the on-chip jitter verify the resulted jitter accomplished our design in test hardware design, ) transmitter and receiver o a loopback path, or an Tektronix DSA72004) for

own in Figure 10.

Lecture 4.2 INTER

Figure 10 Flexible test hardware provideto verify injected jitter in different wayproduction test. We used an external realtime sampling scopreal silicon results to confirm the frequencyand duration control resolution is adequat12Gbps signals with SJ frequency of 15MHat different jitter magnitude are displafrequency and amplitude measurements matcthe theoretical calculation, the result was vemultiple loop-run with power on reset. In thused double transition clock pattern to minicomponents in this SJ verification.

Figure 11 Realtime scope view of SJ correlates very well with expected jitter frequency.

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es the capability s while support

pe to illustrate the y offset accuracy e. In Figure 11,

Hz and 31.25MHz ayed. The jitter ch very well with ery repeatable in he test setup, we imize other jitter

injected signal, magnitude and

Realtime oscilloscope is capable accurately, but time consuming if wnumber of settings. By using ATE hwe can also systematically verify thwithout using an external oscillosjittered clock pattern from DUT, widependent jitter (DDJ) and inter-swe assume ATE measured total jit

combination of random jitter (RJDCD ) jitter and device intrinsic

this as total intrinsic jitter ( IntrinsiTJ

Intrinsic DCDRJTJ ++=

With the same device, same data pplane, we then add controlled amo

IntrinsicTJ stay the same, with jitter

will grow linearly as injected InjPJ

IntrinsicTotal

Total

PJTJTJ

DCDRJTJ

+=

++=

Therefore, we can depend on theATE high speed equipment, and amplitude by subtracting the calibtest setup displayed in Figure 10 pcorrelating injected jitter with autoat different jitter frequency and process corner. Figure 12 shows normalized SJ amplitude and thesmall variation is a result of ATE The oscilloscope capture showBenefiting from single-tone Sinewhich contains less high frequencyin square wave modulations, the jamplitude shows an improvement in

6

of measuring jitter very we have to measure a large high speed test equipment, he jitter amplitude profile scope. By driving an un-ithout the presence of data symbol interference (ISI), tter ( TotalTJ ) equal to the

J ), duty cycle distortion (PJ ( DUTPJ ), we define

ic ).

DUTPJ+

pattern and same test back ount of PJ. If we assume injected, the TJ measured

.

Inj

InjDUT

J

PJPJ ++

e TJ measurements from normalize to injected SJ

brated intrinsic jitter. The provides the feasibility of mated ATE measurement

devices from different the correlation between

eoretical calculation. The measurement noise floor.

ws better repeatability. e modulation waveform

y harmonic components as itter error at higher jitter n Figure 8.

Lecture 4.2 INTER

Figure 12 ATE measured jitter cortheoretical values 4. Jitter tolerance test in production andfor CDR setting optimization The next step of verification of this techniquBIST in loopback mode. We took advantagesweep the PJ frequencies, and plot out thelevel v.s. PJ frequency. Figure 13 shows a swPJ frequency points to illustrate that our Ndesign actually reach beyond the out-of-baneffective receiver CDR stressing. The resuexpected curve with a clear transition aroutracking band of a few MHz. Below thebandwidth, a large amount low frequency jiis still not enough to stress the receiver. frequency reaches beyond the receiver trajitter tolerance curve became flat, indicatingtracking the fast phase movement.

Figure 13 Jitter tolerance test results at vPJ frequencies at 12Gbps. As expected, ouproduced a relative flat jitter toleranceCDR loses the ability to keep track of thejitter. Taking advantage of the relatively fastapproach, we can achieve faster CDR settand reduce the validation workload traditiondone with bench instruments. Fig. 14 illutolerance spectrums with different CDR lodata series in green is a result from the besachieved best jitter tolerance performanbalanced CDR tracking capability to low frefrequency noise. The other 3 non-optimyielded in lower jitter tolerance performance The internal Rx “eye scope” is built in Rx eWe captured Rx internal eye diagrams u

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related to the

d its application

ue is to apply the e of the ability to e jitter tolerance weep of different NCO based SSC nd jitter range for ult illustrated an und the receiver e CDR tracking itter (i.e. >=1UI) When the jitter

acking band, the g CDR no longer

various injected ut of band jitter e profiles when e high frequency

t loopback test ting optimization nally can only be ustrate the jitter oop settings, the st settings, which nce, and more

equency and high mal loop settings

.

eye monitor tool. under 4 different

settings to help visualize the actuaIn Figure 14, with the same amountscopes indicate significant differenthese 4 CDR settings. The differeindicate the difference of CDR tracsame injected jitter condition (i.e. aclearly shown the bottom setting wiwithout margin, while the top ontolerate even more jitter coming in.jitter injection capability like that, will show all 3 settings above as allcapability, we can provide construwith quantifiable margin analysis.

Figure 14 Loopback based jitter trelative fast approach to optimizeand more balanced tracking effici 4. Conclusions: We demonstrated the effectivenesbased jitter tolerance test in loopbato produce robust jitter toleranceeffective fashion. The important dfor this technique is that we do instruments or elaborate calibratiothese unique attributes, this techniqtester platform choice. The limitation of this technique isjitter (PJ) to stress the CDR. Even in stressing the receiver, but the reawith a combination of different jdirectly emulated. For example, thfrom bandwidth limited transmissiof jitter can stress the receiver CDR References:

7

l Rx jitter timing margin. t of jitter injected, the eye nce in eye opening under ent levels of eye opening cking capability under the a 0.3UI 25MHz SJ). This ill make the device failing

ne with a lot of room to Without the built in SSC ATE test with loopback

l “passing”. Now with this uctive setting optimization

tolerance sweep provides e CDR settings for better iency

ss of our enhanced SSC ack mode. This enables us e test in the most cost

distinguishable advantages NOT need any external

on schemes. Because of que is independent to the

s using only one type of though it is very efficient

al application environment jitter types can NOT be he ISI type of jitter result on media is another type

R differently.

Lecture 4.2 INTERNATIONAL TEST CONFERENCE 8

[1] B. Laquai, Y. Cai, “Test Gigabit Multilane SerDes Interfaces with Passive Jitter Injection Filters”, ITC, 2001

[2] Y. Cai, S. Werner, G. Zhang, M. Olsen, R. Brink, “ Jitter Testing for Multi-Gigabit Backplane SerDes –Techniques to Decompose and Combine Various Types of Jitter”, ITC, 2002

[3] S. Sunter, A. Roy, “Structural Tests for Jitter Tolerance in SerDes Receivers”, ITC, 2005

[4] S. Sunter, A. Roy, “A Self-Testing BOST for High-Frequency PLLs, DLLs and SerDes”, ITC, 2007

[5] M. Hafed, D. Watkins, C. Tam, B. Pishdad, “Massively Parallel Validation of High-speed Serial Interface Using Compact Instrument Modules”, ITC, 2006

[6] D. Keezer, D. Minier, P. Ducharme, A. Majid, ‘‘An Electronic Module for 12.8 Gbps Multiplexing and Loopback Test”, ITC, 2008

[7] T. Lyons, “Complete Testing of Receiver Jitter Tolerance”, ITC, 2010

[8] A. Meixner, A. Kakizawa, B. Provost, S Bedwani, “ External Loopback Testing Experiences with High Spedd Serial Interfaces”, ITC, 2008

[9] T. Fujibe, M. Suda, K, Yamamoto, Y. Nagata, K. Fujita, D. Watanabe, T. Okayasu, “Dynamic Arbitrary Jitter Injection Method”, ITC, 2009

[10] Yi Cai, Ivan Chan, Liming Fang, Max Olsen, and Stanley Ma, Patent application “SerDes Jitter Tolerance BIST in Production Loopback Testing with Enhanced Spread Spectrum Clock Generation Circuit”, filed on Jan, 2011