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D. Garg and M. K. Rai / IJECCT 2012, Vol. 2 (4) 18

CMOS Based 1-Bit Full Adder Cell for Low-Power Delay

Product

Deepak Garg1, Mayank Kumar Rai

2

1ECE Department, IIMT Engineering College, Meerut, U.P., India

2ECE Department, Thapar University, Patiala, Punjab, India

[email protected]

[email protected]

Abstract: The 1-bit full adder circuit is one of the most

important components of any digital system applications.

The power-delay product is a measurement of the energy

expanded per operational cycle of an arithmetic circuit.

This paper presents a new low power full adder based on

a new logic approach, which reduces power consumption

by implementing full adder using 3T XOR module and

2-to-1 multiplexer, with 8 transistor in total, named

CBFA-8T. An eight transistor full adder has been

designed using the proposed three-transistor XOR gate

and its performance has been investigated using 0.18µm

technologies. Compared to the earlier designed 10, 12,

16, 28 transistors full adder, the proposed adder shows a

significant improvement in silicon area and power delay

product. Here Simulation results are performed by

TANNER-EDA with 2.3 supply voltage based on 0.18

µm CMOS technology. The results show that the

proposed circuit has the lowest power-delay product with

a significant improvement in silicon area and delay than

recently proposed full adders in the literature.

Keywords — Full- adder; MUX; XOR; Low-power;

PDP; High performance; Very Large Scale

Integrated Circuit

I. INTRODUCTION

With the explosive growth in laptops, portable personal

communication systems, and the evolution of the

shrinking technology, the research effort in low-power

electronics has been intensified. Today, there are an

increasing number of portable applications requiring

small-area low-power high throughput circuitry.

Therefore, circuits with low-power consumption become

the major candidates [1]–[3] for design of systems.

Technology trends show that circuit delay is scaling down

by 30%, performance and transistor density are doubled

approximately every two years, and the transistor’s

threshold voltage is reduced by almost 15% every

generation. All of these technology trends lead to higher

and higher power consumption in circuits. Higher power

consumptions raise chips’ temperature and directly affect

battery life. A higher temperature directly affects circuit

operation and reliability; complicated cooling and

packaging techniques are required. In addition, higher

current density either shortens battery packs [4].

Addition is the most commonly used arithmetic operation

in microprocessors and DSPs, and it is often one of the

speed-limiting elements [5-6]. Hence optimization of the

adder both in terms of speed and power consumption

should be pursued. During the design of an adder we have

to make two choices in regard to different design

abstraction levels. One is responsible for the adder’s

architecture implemented with the one-bit full adder as a

building block. The other defines the specific design style

at transistor level to implement the one-bit full adder.

There are several issues related to the full adders. Some of

them are power consumption, performance, area, noise

immunity and regularity and good driving ability [1].

Several works have been done in order to decrease

transistor count and consequently decrease power

consumption and area [1, 7, 8, 10].

In some designs, reducing transistor count has been

resulted in threshold loss problem that causes non-full

swing outputs [7, 9, 12], low speed and low noise

immunity especially when they are used in cascaded

fashion. Some of them has threshold loss problem that

cause non-full swing outputs, the sentelow speed and low

noise immunity. However, usually they have less power

consumption in comparison to full adders with full swing

outputs. Not full swing full adders are useful in building

up larger circuits as multiple bit input adders and

multipliers.

In Integrated Circuits mainly two types of full adders

(Static & dynamic) are used. Static full adders commonly

are more reliable, simpler and lower power than

dynamic ones. However, dynamic full adders are faster

and some times more compact than static full adders.

Dynamic full adders suffer from charge sharing, high

power due to high switching activity, clock load and

complexity.

In this paper, we propose a new hybrid low-power based

1-bit static full-adder, named CBFA-8T.

II. POWER CONSIDERATIONS

The aim to design the system for low power is not a

straight forward task, as it is involved in all the IC-

design stages.

There are several sources of power consumption in

CMOS circuits:

1) Switching Power: Due to output switching during


output transitions.

2) Short Circuit Power: Due to the current between

VDD and GND during a transistor switching.

3) Static Power: Caused by leakage current and

static current.

Researchers have been found many ways to reduce

power consumption in CMOS full adder circuits. The

summery are some considerations to design of full

adders [4].

1) Output and input capacitances should be low

to reduce dynamic power. Therefore, fewer nodes

should be connected to SUM and COUT signals.

2) Avoid using inverters will reduce switching activity and static power.

3) Avoid using both VDD and GND simultaneously

in circuit components. It can reduce short circuit and

static power.

4) Using Pass transistors usually lead to low

transistor count full adders with low power

consumption. However, sometimes pass transistor full

adders have not full swing outputs due to threshold loss

problem. PMOS cannot pass logic 0 and NMOS cannot

pass logic1 completely. Uncompleted swing reduces

dynamic power but some times increases leakage power,

because transistors do not turn off completely by poor

signals.

5) Most important components of the power

consumption in full adders are the XOR and XNOR gates.

Therefore, more work should be done to reduce

transistor count and power of these components or

completely omit them [8].

6) Reducing number of transistors usually lead to

reduce the power in full adders. However, sometimes it

does not improve PDP. Therefore, reducing transistor

counts does not always lead to reduce in PDP or power

consumption.

III. PREVIOUS WORKS REVIEW

The full-adder function can be described as follows:

Given the three 1-bit inputs A, B, and C, it is desired to

calculate the two 1-bit outputs SUM and COUT, where

SUM = A ⊕ B ⊕ Cin

Cout= Cin (A ⊕ B) +AB

These outputs can be expressed in many different logic

expressions. Therefore, many full adder circuits can be

designed using the different expressions. There are three

main components to design a full adder cell [12]. Those

are XOR or XNOR, Carry generator and SUM Generator.

In [7] different components have been combined to make

41 new 10- transistor full adders. Each full adder that uses

more than one logic style is called hybrid full adder [12].

There is a variety of full adders in the literature for

example there are 41 full adders only in [7]. Many of

them use XOR and XNOR as intermediate signals [13].

There are full adders based on only multiplexers or

inverters.

The conventional CMOS [14] adder cell using 28

transistors based on standard CMOS topology is shown in

fig.1. Due to high number of transistors, its power

consumption is high. Large PMOS transistor in pull up

network result in high input capacitances, which cause

high delay and dynamic power. However, using inverters

on the output nodes decreases the rise-time and fall-time

and increases the driving ability. It functions well at low

power supply voltages because it does not have threshold

loss problem.

Fig. 1: CCMOS full adder circuit [14].

SERF full adder is implemented by 10 transistors, as

shown in Fig. 2, uses energy recovery technique to reduce

power consumption [1]. SERF use energy recovery

technique to decrease the power consumption. Energy

recovery logics reuse charge. Therefore, it consumes less

energy than the other full adders. There are some

problems in this circuit. First SUM is generated from two

cascaded XNOR gates (group1) which lead to long delay.

Second, it cannot work correctly in low voltage. As

shown in Fig. 3 in the worst case, when A=B=’1’ there is

2Vtn threshold loss in output voltage. Therefore, logic 1 is

becomes equal to VDD-2Vtn in this case. The suitable

operating supply voltage is limited to VDD> 2Vtn+|Vtp|.

Second, there are five gate capacitances on node X. It

causes to long delay in generating of intermediate A⊕ B

signal and finally delay in generating SUM and COUT.

This problem also increases the power.

Fig. 2. Energy recovery full adder -SERF full adder circuit [1].


Fig. 3. Worst case of threshold loss problem in SERF full adder[1].

MB12T [15] has been implemented using six multiplexers

and 12 transistors. Each multiplexer is implemented by

pass-transistor logic with two transistors. As shown in

Fig. 4, there is no VDD or GND connection in this circuit

and there are some paths containing three serried

transistors. It causes to increase delay of producing SUM

signal. The size of each transistor in mentioned path

should be three times larger to balance the output and

optimize the circuit for PDP. Therefore, the area of the

circuit is increased.

Fig.4. Multiplexer based full adder (MB12T) [15].

An improvement from 14T [16] is shown in Fig.5. It has

simultaneous XOR and XNOR signals. Feedback

transistors provide rail-to-rail outputs in XOR-XNOR

module. However, they prompt high delay.

Fig.5. New version of 14T [16].

Fig. 6 shows another improved version from 14T, which

is called 16T [17]. It is the same as New-14T in terms of

the output modules. However, the XOR-XNOR module

has been modified to reduce delay and power

consumption. The XOR-XNOR modules does not have

full-swing outputs thus, the transistors which have been

connected to this module are turned on or off slowly.

Fig.6. 16T full adder [17].

A full adder in form of centralized structure is made by

ten-transistor-10T [10] is shown in Fig. 7. As shown in

Fig.7 SUM and COUT are generated using two double

transistors multiplexers. 3T XOR and XNOR consume

high energy due to short circuit current in ratio logic.

Maximum serried transistors here are two transistors

while in MB12T are three transistors.

Fig.7. 10T full adder use two three-transistor XOR-XNOR.

Outputs have threshold loss problem due to non-full

swing output of XNOR and XOR circuit and pass gate

multiplexer output stage. By adjusting proper sizes for

transistors, acceptable swing can be achieved. In term of

intermediate nodes and capacitances, each XOR and

XNOR circuits drives two gates. Input C drives two

transistor gates.

IV. CIRCUITS USED IN THE PROPOSED FULL ADDERS

A. 3T XOR Module

The design of the full adder is based on the design of the

XOR gate. The proposed design of full adder uses three

transistor XOR gates [18]. The design of a three transistor

XOR gate is shown in figure 8.


Fig.8. Design of 3T XOR gate.

The design is based on a modified version of a CMOS

inverter and a PMOS pass transistor. When the input B is

at logic high, the inverter on the left functions like a

normal CMOS inverter. Therefore the output Y is the

complement of input A. When the input B is at logic low,

the CMOS inverter output is at high impedance. However,

the pass transistor M3 is enabled and the output Y gets the

same logic value as input A. The operation of the whole

circuit is thus like a 2 input XOR gate. However, when

A=1 and B=0, voltage degradation due to threshold drop

occurs across transistor M3 and consequently the output Y

is degraded with respect to the input. The voltage

degradation due to threshold drop can be considerably

minimized by increasing the W/L ratio of transistor M3.

B. 2-to-1 Multiplexer Circuits

For our proposed full adder circuit, the possible circuit

design for the 2-to-1 multiplexer [11] illustrated in Fig. 2.

In this, pass transistors are used in lieu of the transmission

gate to reduce the circuit complexity. The price to pay is

the degraded output voltage swing.

Fig.9. 2-to-1 multiplexer circuits.

V. PROPOSED LOGIC APPROACHES AND FULL

ADDERS

In this paper, the design of proposed full adder is based on

three transistor XOR gate and 2-to-1 multiplexer with 8

transistors in total. It acquires least silicon area. The

design of 3T XOR gate is shown in Fig.8. The heart of the

design is based on a modified version of a CMOS inverter

and a PMOS pass transistor. With this design a significant

improvement in delay. The Boolean equation for the

design of the 8T full adder as follows:

SUM = A ⊕ B ⊕ Cin (1)

CARRY= Cin (A ⊕ B) +AB (2)

The logic circuit of the full adder is shown in figure 10.

The OR gate can be realized using a wired OR logic.

Fig.10. Logic Circuit of the full adder

The circuit diagram of the eight transistor full adder is

shown in fig.11. The sum output is basically obtained by a

cascaded exclusive ORing of the three inputs in

accordance with equation (1).The carry output is obtained

in accordance with equation (2). The final sum of the

products is obtained using a wired OR logic.

The W/L ratios of transistors M1 -M6 are same as the

corresponding ones in figure 8. The W/L ratios of

transistors M7 and M8 are taken as 5/1 [18]. It is quite

evident from fig.10 that two stage delays are required to

obtain the sum output and at most two stage delays are

required to obtain the carry. The voltage drop due to the

threshold drop in transistors M3 and M6 in fig.11can be

minimized by suitably increasing the aspect ratios of the

two transistors. However, the threshold voltage drop of |

VT,p| provided by the pMOS pass transistor M3 when

a=0 and b=0 is used to turn on the nMOS pass transistor

M8 and therefore we get an output voltage equal to

|VT,p|-VT,n , where VT,p is the threshold voltage of the

pMOS transistor and VT,n is the value is very close to

0V. Similarly, the threshold drop of the transistors M7

and M8 can be minimized by suitably increasing the

aspect ratios of transistors M7 and M8.

Fig.11. Schematic Model of 1-bit Full-adder cell using 8-Transistor (CBFA-8T).

VI. LAYOUT DESIGN & SIMULATION OF THE 8T FULL

ADDER

The layout of the proposed 8T full adder has been

designed and simulated. The designed layout using 0.18

μm technology using Tanner EDA is shown in fig 12.


Fig.12.Layout design of the proposed 8T full adder (CBFA-8T).

The post layout simulation of proposed eight transistor

full adder has been carried out with all combinations of

inputs. The output waveforms show small voltage

degradation for some input combinations as shown in

fig.13. However these degradations can be minimized by

use of CMOS inverters as level restorers at appropriate

places in the circuit [11]. All the net lists have been

simulated using HSPICE in 0.18μm bulk technology.

Such type of level restoring logic is required in a long

cascading chain of adders so that the penalty paid in

silicon area for introducing two transistors of the CMOS

inverter is minimal. The proposed full adder has been

found to operate faithfully at an input voltage as low as

0.17V when using the 0.18 μm technology.

Fig.13. Simulation results of 8-T transistor full adder (CBFA-8T).

Comparative studies on the different adders found in

literature have been done using the 0.18 μm technologies.

Studies have been done with 28T, 12T, 10T and the

proposed 8T full adders. The results have been shown in

Table 1.

The results of the comparative study show that the

performance of the 8T full adder is somewhat poorer than

the 10T full adder proposed in [11], in regard to its

average power dissipation. However, the delay of the

proposed adder is much less compared to any other adder

shown in the table 1. The net effect is that our proposed

8T full adder shows a much better power-delay product

(PDP) compared to any other adders mentioned in

literature.

Table 1. Comparative Studies of Power-Delay Product of Different

Adders

Types of

adder

Technology

(µm)

Average

Power

(µW)

Delay

(ps)

PDP

(10-18J)

28T[14] 0.18 4.82 48.472 233.16

16T[1] 0.18 2.378 42.412 100.855

12T[11] 0.18 5.353 29.372 157.142

10T[7] 0.18 1.000 39.481 39.481

DG-8T 0.18 1.129 12.512 14.123

A comparative study of the silicon area of the proposed

adder with the earlier designed adders10 transistor full

adder [14] is shown in Table 2.

Table 2. Comparative Studies of Power-Delay Product of Different

Adders

Types of

adder

Technology

(µm)

Area

(µm2)

28T[14] 0.18 7.3

16T[1] 0.18 4.3

12T[11] 0.18 3.9

10T[7] 0.18 3.5

DG-8T 0.18 2.9

From table 2, it is evident that the proposed 8T full adder

occupies the minimum silicon area on chip amongst all

the full adders reported so far. The small silicon area of

the proposed full adder makes it potentially useful for

building compact VLSI circuits on a small area of chip.

VII. CONCLUSION

In conclusion, in this paper, we have presented a 1- bit

full adder design using as few as eight transistors per bit.

The design adopts 3T-XOR designs to alleviate the

threshold voltage loss problem and to enhance the driving

capability foe cascaded operations. The proposed 8T full

adder has been designed and studied using 0.18 µm

technologies. Using XOR gate an eight transistor adder

has been realized using the conventional the equations of

the full adder circuit. The designed adder is found to give

better performance that most of the adders mentioned in

literature so far as the power delay product is concerned.

It successfully embeds the buffering circuit in the full

adder design, so the transistor count is minimized.

Enhanced driving capability also facilitates lower voltage

or faster operations, which lead to less energy

consumption. If a specific input pattern is applied, the

standby power dissipation can be further minimized to

leakage components only.

The layout of the proposed full adder has also been

designed and simulated. The proposed full adder can

operate at low voltages, yet giving quite a good speed.

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