IntroductionThe STEVAL-VP12201F is a 12 V - 5 W power supply in isolated flyback topology featuring the VIPer122 offline high voltageconverter by STMicroelectronics.

The evaluation board has the following characteristics:• Wide input range from 85 VAC to 265 VAC

Stand-by mains consumption: < 30mW at 230 VAC

Average efficiency > 77%Meets IEC55022 Class B conducted EMI even with reduced EMI filter, thanks to the frequency jittering feature

• RoHS compliant

Some of the key features of the VIPer122 include:• 730 V avalanche rugged Power MOSFET

Embedded HV start-up60kHz fixed switching frequency with jitteringEmbedded error amplifier internally referenced to 3.3VCurrent mode PWM controller with drain current limit protection for easy compensation

• Several protection mechanisms:– delayed overload protection (OLP)– VCC clamp protection– thermal shutdown with hysteresis

All protections are in auto restart mode

Figure 1. STEVAL-VP12201F evaluation board top and bottom

12 V, 5 W isolated flyback converter based on VIPer122

AN5441

Application note

AN5441 - Rev 1 - October 2020For further information contact your local STMicroelectronics sales office.

www.st.com

1 Characteristics and specifications

Table 1. STEVAL-VP12201F electrical specifications

Parameter Min. Typ. Max. Unit

AC main input voltage 85 - 265 VAC

Main frequency (fL) 50 - 60 Hz

Output Voltage 11.4 12 12.6 V

Output Current - - 0.416 A

Rated output power - 5 - W

Output ripple voltage - - 100 mV

Standby input power at 230 VAC - - 30 mW

Ambient operating temperature - - 60 ºC

The power supply is set in isolated flyback topology. The input section includes resistor R1 for inrush currentlimiting, diode bridge (BR) and LC filter (L1, C1) for rectification and EMC suppression.A clamp network (R7, C8) provides leakage inductance demagnetization.The C4 capacitor provides the compensation of the board and it is connected between the EA-OUT (erroramplifier output) pin and the GND pin

1.1 Output voltage characteristics

The output voltage of the board is measured at different line and load conditions. As output voltage is low affectedby line variations, only the load regulation at 115 VAC is shown in the figure below.

Figure 2. Output voltage load regulation at 115 VAC

AN5441Characteristics and specifications

AN5441 - Rev 1 page 2/28

1.2 Schematic diagrams

Figure 3. STEVAL-VP12201F circuit schematic

SFH6106

AC IN

22uF

R8

22

620

C8

15uF - 400V

D3

3

C6

5

1mH

R3

1.2K

SFH6106

33nF

220k

2

OPTO

D2

4

1.5nF

STPS1H100A

REF

BR220uF

R4

100pF

R1

22

10K

2 - +

2.2nF

R2

C2 GND

130K1

OPTO

T1

EA-OUT

R6

BAT41ZFILM

6

15K

12V - 5W

GND

AC IN

L1

R5

C1

C9

C5

220pF

18V

EA-IN

D1

R7

TS432

4

3

VIPer122

DRAIN

220pF

CONTROL

C7

C4

C3

VCC

1

AN

5441 - Rev 1

page 3/28

AN

5441Schem

atic diagrams

1.3 Bill of materials

Table 2. STEVAL-VP12201F bill of materials

Item Q.ty Ref. Part / Value Description Manufacturer Order code

1 1 BR RMB6S Full Wave DiodeBridge, MBS

TaiwanSemiconductor RMB6S RCG

2 1 C1 15uF, 400V,±20%

ELCAP, Dia 10mm xH 18mm Pitch 5mm Rubycon 400AX15MEFC10X16

3 1 C2 100pF, 50V,±10%

Ceramic CapacitorX7R, 0603 Wurth Elektronik 885012206077

4 1 C3 22uF, 50V, ±20% ELCAP, Dia 5mm x H11mm Pitch 2mm Rubycon 50YXM22MEFC5X11

5 1 C4 1.5nF, 50V, ±5% Ceramic CapacitorC0G, 0603 Murata GRM1885C1H152JA01D

6 1 C5 220uF, 25V,±20%

ELCAP, Dia 8mm x H11.5mm Pitch 3.5mm Rubycon 25ZL220MEFC8X11.5

7 1 C6 33nF, 50V, ±10% Ceramic CapacitorX7R, 0603 KEMET C0603C333K5RACTU

8 1 C7 220pF, 50V,±10%

Ceramic CapacitorX7R, 0603 Wurth Elektronik 885012206079

9 1 C8 220pF, 1000V,±10%

Ceramic CapacitorX7R, 0805 Knowles Syfer 0805J1K00221KJT

10 1 C9 2.2nF, 250Vrms,±20%

Ceramic CapacitorX1/Y2 Class, ThroughHole

Murata DE2E3KY222MA2BM01F

11 1 D1 BAT41ZFILM,100V

Schottky Diode,SOD-123 ST BAT41ZFILM

12 1 D2 STPS1H100A,100V

Ultrafast RectifierDiode, SMA ST STPS1H100A

13 1 D3 18V, 0.5W, ±5% Diodo zener,SOD-123 ON Semiconductor MMSZ5248BT1G

14 1 IC1 Integrato, SSO10 ST VIPer122LSTR

15 1 L1 1mH, ±5% Axial Inductor,Through Hole EPCOS B82144A2105J000

16 2 M1, M2 Connector,250Vca, 13.5A

Input Connector,Output Connector,Through Hole5.08mm pitch

TE Connectivity 282837-2

17 1 OPTO SFH6106 Optocoupler, SMD Vishay SFH6106-2T

18 1 R1 22Ω, 1W, ±5%

Power Metal OxideFilm Resistor300ppm/°C, ThroughHole

TE Connectivity ROX1SJ22R

19 1 R2 1.2kΩ, 0.1W, ±5% Stand. Film Resistor200ppm/°C, 0603 Panasonic ERJ3GEYJ122V

20 1 R3 10kΩ, 0.1W, ±5% Stand. Film Resistor200ppm/°C, 0603 Panasonic ERJ3GEYJ103V

21 1 R4 130kΩ, 0.1W,±1%

Stand. Film Resistor100ppm/°C, 0603 Panasonic ERJ3EKF1303V

22 1 R5 15kΩ, 0.1W, ±1% Stand. Film Resistor100ppm/°C, 0603 Panasonic ERJU03F1502V

AN5441Bill of materials

AN5441 - Rev 1 page 4/28

Item Q.ty Ref. Part / Value Description Manufacturer Order code

23 1 R6 620Ω, 0.66W,±1%

Stand. Film Resistor200ppm/°C, 1206 Panasonic ERJP08F6200V

24 1 R7 220kΩ, 0.33W,±5%

Stand. Film Resistor200ppm/°C, 0805 TE Connectivity CRGH0805J220K

25 1 R8 22Ω, 0.1W, ±5% Stand. Film Resistor200ppm/°C, 0603 Panasonic ERJ3GEYJ220V

26 1 REF TS432ILT Voltage reference,SOT-23-3 ST TS432ILT

27 1 T1 Transformer Wurth Elektronik 7508110351

1.4 Transformer

Table 3. Transformer characteristics

Manufacturer Wurth Elektonik

Part number 7508110351

Primary Inductance 2.5 mH ±10%

Leakage inductance 125 µH max.

Primary (3-4) to auxiliary (2-1) turns ratio 4.51

Primary (3-4) to auxiliary (2-1) turns ratio 5.57

Figure 4. Dimensional drawing, pin placement (distances, bottom view) and electrical diagrams

AN5441Transformer

AN5441 - Rev 1 page 5/28

Figure 5. Dimensional drawing and pin placement diagram (bottom, side and top view)

AN5441Transformer

AN5441 - Rev 1 page 6/28

2 Efficiency and consumption

2.1 Efficiency characteristics

The average efficiency, measured as average of the efficiencies at 25%, 50%, 75% and 100% of the rated outputpower, has been calculated at nominal input voltages (VIN = 115 VAC and VIN = 230 VAC).

Table 4. Average efficiency at 115 VAC

%Load IOUT (A) VOUT (V) PIN (W) POUT (W) Efficiency (%)

25% 0.104 12.164 1.617 1.265 78.23

50% 0.208 12.166 3.193 2.531 79.27

75% 0.312 12.169 4.835 3.797 78.53

100% 0.416 12.170 6.558 5.063 77.20

Average Efficiency 78.31

Table 5. Average efficiency at 230 VAC

%Load IOUT (A) VOUT (V) PIN (W) POUT (W) Efficiency (%)

25% 0.104 12.162 1.730 1.265 73.12

50% 0.208 12.167 3.265 2.531 77.52

75% 0.312 12.170 4.819 3.797 78.79

100% 0.416 12.176 6.379 5.065 79.40

Average Efficiency 77.21

The following table shows the efficiency measured at 10% of the rated output power.

Table 6. Average efficiency at 10% of the max output load

VIN [VAC] IOUT (A) VOUT (V) PIN (W) POUT (W) Efficiency (%)

115 0.0416 12.163 0.661 0.506 76.55

230 0.0416 12.159 0.786 0.506 64.38

AN5441Efficiency and consumption

AN5441 - Rev 1 page 7/28

Figure 6. Efficiency vs. Output current load

Note: As this evaluation board is designed to represent a low-cost power supply, the transformer is also a low-costsolution requiring no construction optimization. Overall efficiency performance can therefore be improved byimplementing transformer construction optimization to reduce leakage inductance and parasitic elements.

2.2 Consumption characteristics

No load consumption

The input power of the converter was measured in the no load condition, which the VIPer112 manages in burstmode to lower the average switching frequency and thereby minimize any frequency-related losses.

AN5441Consumption characteristics

AN5441 - Rev 1 page 8/28

Figure 7. No load consumption vs. input voltage

Light load consumption

The input power of the evaluation board in light load conditions was also measured in order to verify itscompliance with EuP Lot 6, in which the EPS requires an efficiency above 50% when the output load is 250mW.The evaluation board satisfies this requirement.

Figure 8. Light load consumption at different output power

AN5441Consumption characteristics

AN5441 - Rev 1 page 9/28

3 Typical waveforms

The drain voltage and current waveforms in full load condition are shown in the following images for minimum andmaximum AC input voltage.

Figure 9. Drain current and voltage at full load at85 VAC

Figure 10. Drain current and voltage at full load at265 VAC

The drain voltage and current waveforms in full load condition are shown in the following images for the twonominal input voltages.

Figure 11. Drain current and voltage at full load at115 VAC

Figure 12. Drain current and voltage at full load at230 VAC

The output voltage ripple at the switching frequency is shown in the following images for full load at nominal inputvoltages.

AN5441Typical waveforms

AN5441 - Rev 1 page 10/28

Figure 13. Output voltage ripple at full load at115 VAC

Figure 14. Output voltage ripple at full load at230 VAC

The output voltage ripple at the switching frequency is shown in the following images for no load at nominal inputvoltages.

Figure 15. Output voltage ripple at no load at115 VAC

Figure 16. Output voltage ripple at no load at230 VAC

3.1 Dynamic step load regulation

In any power supply, it is important to measure the output voltage when the converter is subjected to dynamicload variations, in order to ensure appropriate stability free of overvoltage and undervoltage events.The test is performed by varying the output load from 0 to 0.416 A (100% of nominal value) for both nominal inputvoltages.In the tested conditions, no abnormal oscillations were observed on the output, and over/under shoot were wellwithin acceptable levels.

AN5441Dynamic step load regulation

AN5441 - Rev 1 page 11/28

Figure 17. Dynamic step load (IOUT from 0 to0.416 A) at 115 VAC

Figure 18. Dynamic step load (IOUT from 0 to0.416 A) at 230 VAC

AN5441Dynamic step load regulation

AN5441 - Rev 1 page 12/28

4 Startup

When the converter starts, the output capacitor is discharged and needs time to reach the steady state condition.During this time, the power demand from the control loop is at its maximum, leading to a deep continuousoperating mode of the converter.Another consideration is that when the MOSFET is switched on, it cannot be switched off before the minimum ontime (TON_MIN) has elapsed. Because of the deep continuous working mode of the converter, an excessive draincurrent during TON_MIN can stress the component of the converter, the device itself, the output diode and thetransformer. Transformer saturation may also occur under these conditions.To avoid these negative effects, the VIPer122 implements an internal soft-start feature. As the device starts tooperate, the drain current is allowed to gradually increase from zero to the maximum value, regardless of thecontrol loop request.The soft-start time tSS is internally set at 8.5 ms (typical value).The following figure shows the soft-start phase of the converter when it is operating at minimum line voltage andmaximum load..

Figure 19. Soft start feature

AN5441Startup

AN5441 - Rev 1 page 13/28

5 Protection features

5.1 Overload and short circuit protection

When the load power demand increases, the feedback loop reacts by increasing the voltage on the EA-OUT pin.In this way, the PWM current set point increases and the power delivered to the output rises. This process endswhen the delivered power equals the load power request.In case of overload or output short circuit, the drain current value rises to IDLIM. For every cycle that this conditionis met, an internal OCP counter is incremented and the protection is tripped if the overload condition persists for50 ms. The power section is turned off and the converter is disabled for 1 s. After this time has elapsed, the ICresumes switching and the protection continues to be triggered as long as the fault condition remains. Thisensures a low converter restart attempt rate, providing safe operation with extremely low power throughput andavoiding IC overheating in case of repeated overload events.The internal soft start function is also invoked at startup after the protection is tripped. After the fault is removed,the IC resumes working normally. If the fault is removed before the protection is triggered, the counter isdecremented on a cycle-by-cycle basis down to zero and the protection is not tripped. If the short circuit isremoved during the 1 s time interval, the IC still waits until has elapsed before resuming switching.

Figure 20. Overload event and OLP triggering Figure 21. Overload event, continuous overload

Figure 22. Overload event, steady-state zoom Figure 23. Overload event, fault removed and autorestart

AN5441Protection features

AN5441 - Rev 1 page 14/28

5.2 VCC clamp protection

As the loop fails (R4 open or R5 shorted), the output voltage increases and the VIPER122 runs at its maximumcurrent limitation. The voltage on VCC pin also increases as it is linked to the VOUT voltage through the auxiliary tosecondary turn ratio.If the VCC voltage increases up to the internal VCC clamp threshold (23.5 V minimum), with a clamp currentinjected on the pin greater than the latch threshold ICC_FAIL (4 mA minimum), and the VIPER122 operates at itsdrain current limitation, a fault signal is internally generated and the device stops switching.The failure of the loop is simulated by opening R4 resistor. The same behavior can be induced by shorting R5resistor.

Figure 24. VCC clamp protection

AN5441VCC clamp protection

AN5441 - Rev 1 page 15/28

6 Noise measurements

The VIPer122 frequency jittering feature allows the spectrum to be spread over frequency bands rather thanbeing concentrated on single frequency value. Especially when measuring conducted emission with the averagedetection method, the level reduction can be several dBµV.A pre-compliance test for the EN55022 (Class B) European normative was performed and the averagemeasurements of the conducted noise emissions at full load and nominal mains voltages are shown in thefollowing figures.

Figure 25. CE average measurement at 115 VAC fullload

Figure 26. CE average measurement at 230 VAC fullload

AN5441Noise measurements

AN5441 - Rev 1 page 16/28

7 Thermal measurements

A thermal analysis of the board has been performed using an IR camera for the two nominal input voltages(115VAC and 230VAC) in full load condition. The results are shown below.

Figure 27. Thermal map at 115 VAC full load.Bottom layer

Figure 28. Thermal map at 115 VAC full load. Toplayer

Figure 29. Thermal map at 230 VAC full load.Bottom layer

Figure 30. Thermal map at 230 VAC full load. Toplayer

Table 7. Temperature of key components (TAMB = 25 °C, emissivity = 0.95 for all points)

PointTemp (°C)

Reference115 VAC 230 VAC

A 60.6 58.5 VIPer122

B 59 58 Zener diode (D3)

C 53 53.3 Output diode (D2)

D 54.5 57.5 Transformer

AN5441Thermal measurements

AN5441 - Rev 1 page 17/28

8 Conclusions

An flyback converter has been described and characterized, with the bench results showing good performance interms of line and load regulation.The STEVAL-VP12201F reference design meets the EN55022 – Class B EMI regulation standard using a simpleand low-cost LC input filter.

AN5441Conclusions

AN5441 - Rev 1 page 18/28

Appendix A Feedback loop calculation guidelines

A.1 CCM flyback converter transfer functionThe control-to-output transfer function of the flyback converter in CCM, Gvc s , is given by the approximation:

Gvc s ≈ HO ∙ 1 + sωZ1 ∙ 1− sωZ21 + sωP1 (1)

Gain, poles and zero are defined below: HO = n ∙ ROHCOMP ∙ 1− D1 + D (2)

ωZ1 = 1RC ∙ CO (3)

ωZ2 = n2 ∙ 1− D 2 ∙ ROD ∙ L (4)ωP1 = 1 + DRO ∙ CO (5)

Where:• n = primary to secondary turns ratio• R0 = VOUT/IOUT = nominal output resistance• C0 = capacitance of the output capacitor• RC = ESR of the output capacitor• D = converter duty cycle• L = primary inductance• HCOMP = ΔVCOMP/ΔIDRAIN (from device datasheet)

A.2 CCM flyback type-2 compensator designTo compensate the CCM flyback, we use a type-2 compensator featuring the integrator effect that provides highDC gain to minimize static error, as well as a pole-zero pair to boost the phase according to the phase margintarget.

The compensator is determined using a manual pole-zero placement technique in which the zero is placed in thevicinity of the power stage dominant pole to cancel its effect and the pole position is adjusted to achieve therequired phase margin.Follow the procedure below to design compensation with a type 2 compensator:

Step 1. Select the crossover frequency fC and the phase margin Φm :

For CCM flyback, the crossover frequency must be selected as low as possible with respect to theRHP zero ωZ2 in order to limit the phase degradation that it introduces.

As a general rule, you should set fC to below 20% of the RHP zero.

Step 2. Evaluate the gain and phase of the plant at crossover frequency:Gvc fC = Gvc 2 ∙ π ∙ fC (6)Φvc fC = arg Gvc 2 ∙ π ∙ fC (7)

Step 3. Design the compensator to have following gain and phase (at fC ):

The compensated open-loop gain must attain unit gain at fC , with the required phase margin.Gc fC = Gc 2 ∙ π ∙ fC = 1Gvc fC (8)Φc fC = arg Gc 2 ∙ π ∙ fC = 90− 180 + Φm−Φvc fC (9)

AN5441Feedback loop calculation guidelines

AN5441 - Rev 1 page 19/28

Step 4. Cancel the pole of the plant fP p by placing the zero of the compensator fZ c in the neighborhood( α = 1 to 5): fZ c = ωZ c2 ∙ π = α ∙ fP p (10)

Step 5. Place the pole of the compensator to boost the phase and to obtain the desired phase margin:fP c = fCtan tan−1 fCfZ c − Φc fC (11)

Step 6. Calculate the gain Gco :Gco = Gc fC ∙ ωC ∙ 1 + fCfP c 2

1 + fCfZ c 2 (12)

GC s is thus determined.

A.3 Deriving actual compensator parametersThe following figure shows the schematic of the Type 2 amplifier used in secondary side regulation (SSR).

Figure 31. Secondary feedback implementation using secondary reference voltage and optocoupler

Ref

TS432

RDYN

C4

Vdd

R2

EA-OUT pin

GND

D2

R4

Cout1

R3

C6

OPTO

Vout

R5

OPTO

The transfer function of this compensator can be expressed as the following:

GC s = CTR ⋅ RDYNR2 ⋅ 1 + 1s ⋅ R4 ⋅ C61 + s ⋅ RDYN ⋅ C4 + COPTO (13)

In the equation, the capacitor COPTO is the intrinsic capacitor across the collector which introduces a pole in thetransfer function and limits the frequency response. Because this pole enters the controller transfer function, thecorrect value must be determined for the selected optocoupler through specific bench testing as close to realoperating conditions as possible.The first component to be chosen is resistor R3. The purpose of this resistor is to provide the minimum requiredbias current to the reference IC to ensure correct operation.

AN5441Deriving actual compensator parameters

AN5441 - Rev 1 page 20/28

Step 1. Calculate R3

Considering that the forward voltage of the opto-diode is almost constant (typically ≈ 1 V), the value ofR3 is simply given by: R3 ≤ VFIBIAS ≈ 15.4kΩ (14)

The selected value for R3 is: R3 = 10 kΩ (15)

Step 2. Select R4

The value must be high enough to minimize the residual losses across the output, but low enough toensure that the input current of the REF pin of the reference IC is negligible with respect to the currentacross R4 itself.A general rule is to set the current across R4 30 to 50 higher than the REF input current.The selected value for R4 is: R4 = 130 kΩ (16)

Step 3. Calculate R5

The resistor R5 is selected to define the output voltage set-point:R5 = R4 ⋅ VREFVOUT− VREF ≈ 14.98 kΩ (17)

The selected value for R5 is: R5 = 15 kΩ (18)

Step 4. Calculate the value of the capacitor C6 to set the zero fZ(C):C6 = 12 ⋅ π ⋅ R4 ⋅ fZC ≈ 38.9 nF (19)

The selected value for C6 is: C6 = 33 nF (20)

Step 5. Calculate the value of R2 to set the mid-band gain GCO:R2 = CTR ⋅ RDYNGCO ≈ 1.3 kΩ (21)

The value of R2 must also ensure minimum current through the opto-diode in order to drive the EA-OUT pin ensuring its full dynamic.ROPTO_MAX ≤ VOUT− VF− VREFIEA− OUTCTR + VFR3 ≈ 12.4 kΩ (22)

The selected value for R2 is: R2 = 1.2 kΩ (23)

Step 6. Calculate the value of C4 to set the proper phase boost of the compensator:C4 = 12 ⋅ π ⋅ RDYN ⋅ fPC ≈ 1.4 nF (24)

The selected value for C4 is: C4 = 1.5 nF (25)

The resulting crossover frequency fC and the phase margin Φm are:fC ≈ 1.8 kHz (26)Φm ≈ 76 (27)

AN5441Deriving actual compensator parameters

AN5441 - Rev 1 page 21/28

Appendix B Layout guidelines and design recommendationsA proper PCB layout is essential for correct operation of any switch-mode converter, including the VIPER122. Agood PCB layout ensures clean signals to the IC and good immunity against external noises and switchingnoises, and also helps reduce radiated and conducted electromagnetic interference so a solution can satisfy EMCrequirements more easily.Consider the concepts below when designing an SMPS using the VIPER122.Separate signal and power tracks:• Traces carrying signal currents should generally be run at a distance from other tracks carrying pulsed

currents or with rapidly changing voltages.• Signal ground traces should be connected to the IC signal ground, GND, using a single "star point", placed

close to the IC.• Power ground traces should be connected to the IC power ground, GND.• The compensation network should be connected to EA-OUT, maintaining the trace to GND as short as

possible.• In two-layer PCBs, it is a good practice to route signal traces on one PCB side and power traces on the

other side.

Filter sensitive pins and crucial points on the circuit:• A small high-frequency bypass capacitor to GND might be useful to get a clean bias voltage for the signal

part of the IC and protect the IC itself during EFT/ESD tests.• A low ESL ceramic capacitor (a few hundred pF up to 0.1 µF) should be connected across VCC and GND,

placed as close as possible to the IC.• With flyback topologies, when the auxiliary winding is used, it is suggested to connect the VCC capacitor on

the auxiliary return and then to the main GND using a single track.

Keep power loops as confined as possible:• Minimize the area circumscribed by current loops where highly pulsed currents flow in order to reduce its

parasitic self-inductance and the radiated electromagnetic field; this will greatly reduce the electromagneticinterferences produced by the power supply during the switching.

• In a flyback converter the most critical loops are:– The one with the input bulk capacitor, the power switch and the power transformer– the one with the snubber.– the one with the secondary winding, the output rectifier and the output capacitor.

• In a buck converter the most critical loop is:– The one with the input bulk capacitor, the power switch, the power inductor, the output capacitor and

the free-wheeling diode.

Reduce line lengths as any wire will act as an antenna:• With the very short rise times exhibited by EFT pulses, any antenna has the capability of receiving high

voltage spikes. Shorter lines reduce the level of radiated energy received and lower the spikes resulting fromelectrostatic discharges. This will also keep both resistive and inductive effects to a minimum.

• All traces carrying high currents, especially if pulsed (tracks of the power loops), should be as short and wideas possible.

Optimize track routing:• As levels of pickup from static discharges are likely to be greater closer to the extremities of the board, it is

wise to keep any sensitive lines away from these areas.• Input and output lines will often need to reach the PCB edge at some stage, but they can be routed away

from the edge as soon as possible where applicable.• Since vias are considered inductive elements, they should be kept to a minimum in signal paths and avoided

in power paths.

Improve thermal dissipation:• An adequate copper area must be provided under the DRAIN pins to dissipate heat• It is not recommended to place large copper areas on the GND.

AN5441Layout guidelines and design recommendations

AN5441 - Rev 1 page 22/28

Figure 32. Recommended routing of flyback converter~ AC

Vout

GND~ AC

C5

R4OPTO

R7

C4

C6

DRAIN

GND

VCC

EA-OUT

CONTROLEA-IN

VIPer122

OPTO

D1

D2

R2

R1

- +

BR

T

C3

R5

C1

R3

C8

AN5441Layout guidelines and design recommendations

AN5441 - Rev 1 page 23/28

Revision history

Table 8. Document revision history

Date Version Changes

15-Oct-2020 1 Initial release.

AN5441

AN5441 - Rev 1 page 24/28

Contents

1 Characteristics and specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2

1.1 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Schematic diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.3 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.4 Transformer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Efficiency and consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

2.1 Efficiency characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2 Consumption characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3 Typical waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

3.1 Dynamic step load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4 Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

5 Protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14

5.1 Overload and short circuit protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.2 VCC clamp protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

6 Noise measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

7 Thermal measurements. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

8 Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Appendix A Feedback loop calculation guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

A.1 CCM flyback converter transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

A.2 CCM flyback type-2 compensator design. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

A.3 Deriving actual compensator parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Appendix B Layout guidelines and design recommendations . . . . . . . . . . . . . . . . . . . . . . . . .22

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24

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List of figuresFigure 1. STEVAL-VP12201F evaluation board top and bottom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1Figure 2. Output voltage load regulation at 115 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Figure 3. STEVAL-VP12201F circuit schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3Figure 4. Dimensional drawing, pin placement (distances, bottom view) and electrical diagrams. . . . . . . . . . . . . . . . . . . 5Figure 5. Dimensional drawing and pin placement diagram (bottom, side and top view) . . . . . . . . . . . . . . . . . . . . . . . . . 6Figure 6. Efficiency vs. Output current load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Figure 7. No load consumption vs. input voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 8. Light load consumption at different output power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9Figure 9. Drain current and voltage at full load at 85 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 10. Drain current and voltage at full load at 265 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 11. Drain current and voltage at full load at 115 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 12. Drain current and voltage at full load at 230 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10Figure 13. Output voltage ripple at full load at 115 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 14. Output voltage ripple at full load at 230 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 15. Output voltage ripple at no load at 115 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 16. Output voltage ripple at no load at 230 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11Figure 17. Dynamic step load (IOUT from 0 to 0.416 A) at 115 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 18. Dynamic step load (IOUT from 0 to 0.416 A) at 230 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12Figure 19. Soft start feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 20. Overload event and OLP triggering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 21. Overload event, continuous overload. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 22. Overload event, steady-state zoom . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 23. Overload event, fault removed and autorestart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14Figure 24. VCC clamp protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15Figure 25. CE average measurement at 115 VAC full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 26. CE average measurement at 230 VAC full load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Figure 27. Thermal map at 115 VAC full load. Bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 28. Thermal map at 115 VAC full load. Top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 29. Thermal map at 230 VAC full load. Bottom layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 30. Thermal map at 230 VAC full load. Top layer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17Figure 31. Secondary feedback implementation using secondary reference voltage and optocoupler . . . . . . . . . . . . . . . 20Figure 32. Recommended routing of flyback converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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List of tablesTable 1. STEVAL-VP12201F electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Table 2. STEVAL-VP12201F bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4Table 3. Transformer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5Table 4. Average efficiency at 115 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 5. Average efficiency at 230 VAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 6. Average efficiency at 10% of the max output load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7Table 7. Temperature of key components (TAMB = 25 °C, emissivity = 0.95 for all points). . . . . . . . . . . . . . . . . . . . . . . . 17Table 8. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

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