12-bit, 8-channel sampling analog-to-digital converter … · · 2016-10-2712-bit, 8-channel...

12-Bit, 8-Channel SamplingANALOG-TO-DIGITAL CONVERTER

with I2C™ Interface

FEATURES 8-CHANNEL MULTIPLEXER

50kHz SAMPLING RATE

NO MISSING CODES

2.7V TO 5V OPERATION

INTERNAL 2.5V REFERENCE

I2C INTERFACE SUPPORTS:Standard, Fast, and High-Speed Modes

TSSOP-16 PACKAGE

APPLICATIONS VOLTAGE-SUPPLY MONITORING

ISOLATED DATA ACQUISITION

TRANSDUCER INTERFACES

BATTERY-OPERATED SYSTEMS

REMOTE DATA ACQUISITION

DESCRIPTIONThe ADS7828 is a single-supply, low-power, 12-bit dataacquisition device that features a serial I2C interface and an8-channel multiplexer. The Analog-to-Digital (A/D) converterfeatures a sample-and-hold amplifier and internal,asynchronous clock. The combination of an I2C serial,2-wire interface and micropower consumption makes theADS7828 ideal for applications requiring the A/D converter tobe close to the input source in remote locations and forapplications requiring isolation. The ADS7828 is available ina TSSOP-16 package.

ADS7828

SBAS181C – NOVEMBER 2001 - REVISED MARCH 2005

www.ti.com

PRODUCTION DATA information is current as of publication date.Products conform to specifications per the terms of Texas Instrumentsstandard warranty. Production processing does not necessarily includetesting of all parameters.

Copyright © 2001-2005, Texas Instruments Incorporated

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

SAR

2.5V VREF

SerialInterface

SDA

ComparatorS/H Amp

REFIN/REFOUT

SCL

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COMA0

A1

CDAC

8-ChannelMUX

Buffer

®ADS7828

I2C is a trademark of Koninklijke Philps Electronics N.V. All other trademarks are the property of their respective owners.

ADS78282SBAS181Cwww.ti.com

MAXIMUMINTEGRAL SPECIFIEDLINEARITY PACKAGE TEMPERATURE ORDERING TRANSPORT

PRODUCT ERROR (LSB) PACKAGE-LEAD DESIGNATOR RANGE NUMBER MEDIA, QUANTITY

ADS7828E ±2 TSSOP-16 PW –40°C to +85°C ADS7828E/250 Tape and Reel, 250

" " " " " ADS7828E/2K5 Tape and Reel, 2500

ADS7828EB ±1 TSSOP-16 PW –40°C to +85°C ADS7828EB/250 Tape and Reel, 250

" " " " " ADS7828EB/2K5 Tape and Reel, 2500

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this data sheet, or see the TI web site at www.ti.com.

PACKAGE/ORDERING INFORMATION(1)

ABSOLUTE MAXIMUM RATINGS(1)

+VDD to GND ........................................................................ –0.3V to +6VDigital Input Voltage to GND ................................. –0.3V to +VDD + 0.3VOperating Temperature Range ...................................... –40°C to +105°CStorage Temperature Range ......................................... –65°C to +150°CJunction Temperature (TJ max) .................................................... +150°CTSSOP Package

Power Dissipation .................................................... (TJ max – TA)/θJA

θJA Thermal Impedance ........................................................ 240°C/WLead Temperature, Soldering

Vapor Phase (60s) ............................................................ +215°CInfrared (15s) ..................................................................... +220°C

NOTE: (1) Stresses above those listed under Absolute Maximum Ratings maycause permanent damage to the device. Exposure to absolute maximumconditions for extended periods may affect device reliability.

ELECTROSTATICDISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. TexasInstruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper han-dling and installation procedures can cause damage.

ESD damage can range from subtle performance degradationto complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametricchanges could cause the device not to meet its publishedspecifications.

PIN CONFIGURATION

Top View TSSOP

PIN DESCRIPTIONS

PIN NAME DESCRIPTION

1 CH0 Analog Input Channel 02 CH1 Analog Input Channel 13 CH2 Analog Input Channel 24 CH3 Analog Input Channel 35 CH4 Analog Input Channel 46 CH5 Analog Input Channel 57 CH6 Analog Input Channel 68 CH7 Analog Input Channel 79 GND Analog Ground10 REFIN / REFOUT Internal +2.5V Reference, External Reference Input11 COM Common to Analog Input Channel12 A0 Slave Address Bit 013 A1 Slave Address Bit 114 SCL Serial Clock15 SDA Serial Data16 +VDD Power Supply, 3.3V Nominal

1

2

3

4

5

6

7

8

CH0

CH1

CH2

CH3

CH4

CH5

CH6

CH7

+VDD

SDA

SCL

A1

A0

COM

REFIN / REFOUT

GND

16

15

14

13

12

11

10

9

ADS7828

ADS7828 3SBAS181C www.ti.com

ANALOG INPUTFull-Scale Input Scan Positive Input - Negative Input 0 VREF 0 VREF VAbsolute Input Range Positive Input –0.2 +VDD + 0.2 –0.2 +VDD + 0.2 V

Negative Input –0.2 +0.2 –0.2 +0.2 VCapacitance 25 25 pFLeakage Current ±1 ±1 µA

SYSTEM PERFORMANCENo Missing Codes 12 12 BitsIntegral Linearity Error ±1.0 ±2 ±0.5 ±1 LSB(1)

Differential Linearity Error ±1.0 ±0.5 –1, +2 LSBOffset Error ±1.0 ±3 ±0.75 ±2 LSBOffset Error Match ±0.2 ±1 ±0.2 ±1 LSBGain Error ±1.0 ±4 ±0.75 ±3 LSBGain Error Match ±0.2 ±1 ±0.2 ±1 LSBNoise 33 33 µVRMSPower-Supply Rejection 82 82 dB

SAMPLING DYNAMICSThroughput Frequency High Speed Mode: SCL = 3.4MHz 50 50 kHz

Fast Mode: SCL = 400kHz 8 8Standard Mode, SCL = 100kHz 2 2 kHz

Conversion Time 6 6 µs

AC ACCURACYTotal Harmonic Distortion VIN = 2.5VPP at 10kHz –82 –82 dB(2)

Signal-to-Ratio VIN = 2.5VPP at 10kHz 72 72 dBSignal-to-(Noise+Distortion) Ratio VIN = 2.5VPP at 10kHz 71 71 dBSpurious-Free Dynamic Range VIN = 2.5VPP at 10kHz 86 86 dBIsolation Channel-to-Channel 120 120 dB

VOLTAGE REFERENCE OUTPUTRange 2.475 2.5 2.525 2.475 2.5 2.525 VInternal Reference Drift 15 15 ppm/°COutput Impedance Internal Reference ON 110 110 Ω

Internal Reference OFF 1 1 GΩQuiescent Current Int. Ref. ON, SCL and SDA pulled HIGH 850 850 µA

VOLTAGE REFERENCE INPUTRange 0.05 VDD 0.05 VDD VResistance 1 1 GΩCurrent Drain High Speed Mode: SCL= 3.4MHz 20 20 µA

DIGITAL INPUT/OUTPUTLogic Family CMOS CMOSLogic Levels: VIH +VDD • 0.7 +VDD + 0.5 +VDD • 0.7 +VDD + 0.5 V

VIL –0.3 +VDD • 0.3 –0.3 +VDD • 0.3 V VOL Min. 3mA Sink Current 0.4 0.4 V

Input Leakage: IIH VIH = +VDD +0.5 10 10 µA IIL VIL = -0.3 –10 –10 µA

Data Format Straight StraightBinary Binary

ADS7828 HARDWARE ADDRESS 10010 10010 Binary

POWER-SUPPLY REQUIREMENTSPower-Supply Voltage, +VDD Specified Performance 2.7 3.6 2.7 3.6 VQuiescent Current High Speed Mode: SCL = 3.4MHz 225 320 225 320 µA

Fast Mode: SCL = 400kHz 100 100 µAStandard Mode, SCL = 100kHz 60 60 µA

Power Dissipation High Speed Mode: SCL = 3.4MHz 675 1000 675 1000 µWFast Mode: SCL = 400kHz 300 300 µW

Standard Mode, SCL = 100kHz 180 180 µWPower-Down Mode High Speed Mode: SCL = 3.4MHz 70 70 µAw/Wrong Address Selected Fast Mode: SCL = 400kHz 25 25 µA

Standard Mode, SCL = 100kHz 6 6 µAFull Power-Down SCL Pulled HIGH, SDA Pulled HIGH 400 3000 400 3000 nA

TEMPERATURE RANGESpecified Performance –40 85 –40 85 °C

ELECTRICAL CHARACTERISTICS: +2.7VAt TA = –40°C to +85°C, +VDD = +2.7V, VREF = +2.5V, SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless otherwise noted.

ADS7828E ADS7828EB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

NOTES: (1) LSB means Least Significant Bit. With VREF equal to 2.5V, 1LSB is 610µV.(2) THD measured out to the 9th-harmonic.


NOTES: (1) LSB means Least Significant Bit. With VREF equal to 5.0V, 1LSB is 1.22mV.(2) THD measured out to the 9th-harmonic.

ANALOG INPUTFull-Scale Input Scan Positive Input - Negative Input 0 VREF 0 VREF VAbsolute Input Range Positive Input –0.2 +VDD + 0.2 –0.2 +VDD + 0.2 V

Negative Input –0.2 +0.2 –0.2 +0.2 VCapacitance 25 25 pFLeakage Current ±1 ±1 µA

SYSTEM PERFORMANCENo Missing Codes 12 12 BitsIntegral Linearity Error ±1.0 ±2 ±0.5 ±1 LSB(1)

Differential Linearity Error ±1.0 ±0.5 –1, +2 LSBOffset Error ±1.0 ±3 ±0.75 ±2 LSBOffset Error Match ±1 ±1 LSBGain Error ±1.0 ±3 ±0.75 ±2 LSBGain Error Match ±1 ±1 LSBNoise 33 33 µVRMSPower-Supply Rejection 82 82 dB

SAMPLING DYNAMICSThroughput Frequency High Speed Mode: SCL = 3.4MHz 50 50 kHz

Fast Mode: SCL = 400kHz 8 8 kHzStandard Mode, SCL = 100kHz 2 2 kHz

Conversion Time 6 6 µs

AC ACCURACYTotal Harmonic Distortion VIN = 2.5VPP at 10kHz –82 –82 dB(2)

Signal-to-Ratio VIN = 2.5VPP at 10kHz 72 72 dBSignal-to-(Noise+Distortion) Ratio VIN = 2.5VPP at 10kHz 71 71 dBSpurious-Free Dynamic Range VIN = 2.5VPP at 10kHz 86 86 dBIsolation Channel-to-Channel 120 120 dB

VOLTAGE REFERENCE OUTPUTRange 2.475 2.5 2.525 2.475 2.5 2.525 VInternal Reference Drift 15 15 ppm/°COutput Impedance Internal Reference ON 110 110 Ω

Internal Reference OFF 1 1 GΩQuiescent Current Int. Ref. ON, SCL and SDA pulled HIGH 1300 1300 µA

VOLTAGE REFERENCE INPUTRange 0.05 VDD 0.05 VDD VResistance 1 1 GΩCurrent Drain High Speed Mode: SCL = 3.4MHz 20 20 µA

DIGITAL INPUT/OUTPUTLogic Family CMOS CMOS

Logic Levels: VIH +VDD • 0.7 +VDD + 0.5 +VDD • 0.7 +VDD + 0.5 V

VIL –0.3 +VDD • 0.3 –0.3 +VDD • 0.3 V VOL Min. 3mA Sink Current 0.4 0.4 V

Input Leakage: IIH VIH = +VDD +0.5 10 10 µA IIL VIL = -0.3 –10 –10 µA

Data Format Straight StraightBinary Binary

ADS7828 HARDWARE ADDRESS 10010 10010 Binary

POWER-SUPPLY REQUIREMENTSPower-Supply Voltage, +VDD Specified Performance 4.75 5 5.25 4.75 5 5.25 VQuiescent Current High Speed Mode: SCL = 3.4MHz 750 1000 750 1000 µA

Fast Mode: SCL = 400kHz 300 300 µAStandard Mode, SCL = 100kHz 150 150 µA

Power Dissipation High Speed Mode: SCL = 3.4MHz 3.75 5 3.75 5 mWFast Mode: SCL = 400kHz 1.5 1.5 mW

Standard Mode, SCL = 100kHz 0.75 0.75 mW

Power-Down Mode High Speed Mode: SCL = 3.4MHz 400 400 µA

w/Wrong Address Selected Fast Mode: SCL = 400kHz 150 150 µAStandard Mode, SCL = 100kHz 35 35 µA

Full Power-Down SCL Pulled HIGH, SDA Pulled HIGH 400 3000 400 3000 nA

TEMPERATURE RANGESpecified Performance –40 +85 –40 +85 °C

ELECTRICAL CHARACTERISTICS: +5VAt TA = –40°C to +85°C, +VDD = +5.0V, VREF = External +5.0V, SCL Clock Frequency = 3.4MHz (High-Speed Mode), unless otherwise noted.

ADS7828E ADS7828EB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS


PARAMETER SYMBOL CONDITIONS MIN MAX UNITS

SCL Clock Frequency fSCL Standard Mode 100 kHzFast Mode 400 kHz

High-Speed Mode, CB = 100pF max 3.4 MHzHigh-Speed Mode, CB = 400pF max 1.7 MHz

Bus Free Time Between a STOP and tBUF Standard Mode 4.7 µsSTART Condition Fast Mode 1.3 µs

Hold Time (Repeated) START tHD;STA Standard Mode 4.0 µsCondition Fast Mode 600 ns

High-Speed Mode 160 ns

LOW Period of the SCL Clock tLOW Standard Mode 4.7 µsFast Mode 1.3 µs

High-Speed Mode, CB = 100pF max(2) 160 nsHigh-Speed Mode, CB = 400pF max(2) 320 ns

HIGH Period of the SCL Clock tHIGH Standard Mode 4.0 µsFast Mode 600 ns

High-Speed Mode, CB = 100pF max(2) 60 nsHigh-Speed Mode, CB = 400pF max(2) 120 ns

Setup Time for a Repeated START tSU;STA Standard Mode 4.7 µsCondition Fast Mode 600 ns


Data Setup Time tSU;DAT Standard Mode 250 nsFast Mode 100 ns


Data Hold Time tHD;DAT Standard Mode 0 3.45 µsFast Mode 0 0.9 µs

High-Speed Mode, CB = 100pF max(2) 0(3) 70 nsHigh-Speed Mode, CB = 400pF max(2) 0(3) 150 ns

Rise Time of SCL Signal tRCL Standard Mode 1000 nsFast Mode 20 + 0.1CB 300 ns

High-Speed Mode, CB = 100pF max(2) 10 40 nsHigh-Speed Mode, CB = 400pF max(2) 20 80 ns

Rise Time of SCL Signal After a tRCL1 Standard Mode 1000 nsRepeated START Condition and Fast Mode 20 + 0.1CB 300 nsAfter an Acknowledge Bit High-Speed Mode, CB = 100pF max(2) 10 80 ns

High-Speed Mode, CB = 400pF max(2) 20 160 ns

Fall Time of SCL Signal tFCL Standard Mode 300 nsFast Mode 20 + 0.1CB 300 ns


TIMING CHARACTERISTICS(1)

At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted.

TIMING DIAGRAM

tR

tBUF

tLOWtF tHD; STA tSP

tHD; STA

tSU; STA

tHD; DAT tSU; DATtHIGH

tSU; STO

SCL

SDA

START REPEATEDSTART

STOP

NOTES: (1) All values referred to VIHMIN and VILMAX levels.(2) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated.(3) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An

input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.


Rise Time of SDA Signal tRDA Standard Mode 1000 nsFast Mode 20 + 0.1CB 300 ns


Fall Time of SDA Signal tFDA Standard Mode 300 nsFast Mode 20 + 0.1CB 300 ns


Setup Time for STOP Condition tSU; STO Standard Mode 4.0 µsFast Mode 600 ns


Capacitive Load for SDA and SCL CB 400 pFLine

Pulse Width of Spike Suppressed tSP Fast Mode 50 nsHigh-Speed Mode 10 ns

Noise Margin at the HIGH Level for Standard ModeEach Connected Device (Including VNH Fast Mode 0.2VDD VHysteresis) High-Speed Mode

Noise Margin at the LOW Level for Standard ModeEach Connected Device (Including VNL Fast Mode 0.1VDD VHysteresis) High-Speed Mode

NOTES: (1) All values referred to VIHMIN and VILMAX levels.(2) For bus line loads CB between 100pF and 400pF the timing parameters must be linearly interpolated.(3) A device must internally provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCLH signal. An

input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time.

TIMING CHARACTERISTICS(1) (Cont.)At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted.

PARAMETER SYMBOL CONDITIONS MIN MAX UNITS


TYPICAL CHARACTERISTICSTA = +25°C, VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted.

0.00

–40.00

–80.00

–120.0

Am

plitu

de (

dB)

0 10 20 25

Frequency (kHz)

FREQUENCY SPECTRUM(4096 Point FFT: fIN = 1kHz, 0dB)

2.00

1.50

1.00

0.50

0.00

–0.50

–1.00

–1.50

–2.00

ILE

(LS

B)

0 1024 2048 3072 4095

Output Code

INTEGRAL LINEARITY ERROR vs CODE(2.5V Internal Reference)

2.00

1.50

1.00

0.50

0.00

–0.50

–1.00

–1.50

–2.00

DLE

(LS

B)

0 1024 2048 3072 4095

Output Code

DIFFERENTIAL LINEARITY ERROR vs CODE(2.5V Internal Reference)

2.00

1.50

1.00

0.50

0.00

–0.50

–1.00

–1.50

–2.00

ILE

(LS

B)

0 1024 2048 3072 4095

Output Code

INTEGRAL LINEARITY ERROR vs CODE(2.5V External Reference)

2.00

1.50

1.00

0.50

0.00

–0.50

–1.00

–1.50

–2.00

DLE

(LS

B)

0 1024 2048 3072 4095

Output Code

DIFFERENTIAL LINEARITY ERROR vs CODE(2.5V External Reference)

1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

Del

ta fr

om 2

5°C

(LS

B)

–50 –25 0 25 50 75 100

Temperature (°C)

CHANGE IN OFFSET vs TEMPERATURE


TYPICAL CHARACTERISTICS (Cont.)TA = +25°C, VDD = +2.7V, VREF = External +2.5V, fSAMPLE = 50kHz, unless otherwise noted.

1.5

1.0

0.5

0.0

–0.5

–1.0

–1.5

Del

ta fr

om 2

5°C

(LS

B)

–50 –25 0 25 50 75 100

Temperature (°C)

CHANGE IN GAIN vs TEMPERATURE2.51875

2.51250

2.50625

2.50000

2.49375

2.48750

2.48125

Inte

rnal

Ref

eren

ce (

V)

–50 –25 0 25 50 75 100

Temperature (°C)

INTERNAL REFERENCE vs TEMPERATURE

750

600

450

300

150

0

–150

Sup

ply

Cur

rent

(nA

)

–50 –25 0 25 50 75 100 125

Temperature (°C)

POWER-DOWN SUPPLY CURRENTvs TEMPERATURE

400

350

300

250

200

150

100

Sup

ply

Cur

rent

(µA

)

–50 –25 0 25 50 75 100

Temperature (°C)

SUPPLY CURRENT vs TEMPERATURE

300

250

200

150

100

50

0

Sup

ply

Cur

rent

(µA

)

10 100 1k 10k

I2C Bus Rate (KHz)

SUPPLY CURRENT vs I2C BUS RATE INTERNAL VREF vs TURN-ON TIME

0 200 400 600 800 1000 1200 1400

Turn-On Time (µs)

Inte

rnal

VR

EF (

%)

100

80

60

40

20

0

No Cap (42µs) 12-Bit Settling

1µF Cap (1240µs) 12-Bit Settling


FIGURE 1. Simplified I/O of the ADS7828.

THEORY OF OPERATIONThe ADS7828 is a classic Successive Approximation Regis-ter (SAR) A/D converter. The architecture is based on ca-pacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µCMOS process.

The ADS7828 core is controlled by an internally generatedfree-running clock. When the ADS7828 is not performingconversions or being addressed, it keeps the A/D convertercore powered off, and the internal clock does not operate.

The simplified diagram of input and output for the ADS7828is shown in Figure 1.

ANALOG INPUT

When the converter enters the hold mode, the voltage on theselected CHx pin is captured on the internal capacitor array.The input current on the analog inputs depends on theconversion rate of the device. During the sample period, thesource must charge the internal sampling capacitor (typically25pF). After the capacitor has been fully charged, there is nofurther input current. The amount of charge transfer from theanalog source to the converter is a function of conversion rate.

REFERENCE

The ADS7828 can operate with an internal 2.5V reference oran external reference. If a +5V supply is used, an external+5V reference is required in order to provide full dynamicrange for a 0V to +VDD analog input. This external referencecan be as low as 50mV. When using a +2.7V supply, the

internal +2.5V reference will provide full dynamic range for a0V to +VDD analog input.

As the reference voltage is reduced, the analog voltageweight of each digital output code is reduced. This is oftenreferred to as the LSB (least significant bit) size and is equalto the reference voltage divided by 4096. This means thatany offset or gain error inherent in the A/D converter willappear to increase, in terms of LSB size, as the referencevoltage is reduced.

The noise inherent in the converter will also appear to increasewith lower LSB size. With a 2.5V reference, the internal noiseof the converter typically contributes only 0.32LSB peak-to-peak of potential error to the output code. When the externalreference is 50mV, the potential error contribution from theinternal noise will be 50 times larger—16LSBs. The errors dueto the internal noise are Gaussian in nature and can bereduced by averaging consecutive conversion results.

DIGITAL INTERFACE

The ADS7828 supports the I2C serial bus and data transmis-sion protocol, in all three defined modes: standard, fast, andhigh-speed. A device that sends data onto the bus is definedas a transmitter, and a device receiving data as a receiver.The device that controls the message is called a “master.”The devices that are controlled by the master are “slaves.”The bus must be controlled by a master device that gener-ates the serial clock (SCL), controls the bus access, andgenerates the START and STOP conditions. The ADS7828operates as a slave on the I2C bus. Connections to the busare made via the open-drain I/O lines SDA and SCL.

Microcontroller

+2.7V to +3.6V

1µF to10µF

+

2kΩ2kΩ

5Ω

1µF to10µF

+0.1µF

ADS7828

REFIN/REFOUT

CH0

VDD

SDA

SCL

A0

A1

GND

CH1

CH2

CH3

CH4

CH5

CH6

CH7

COM


FIGURE 2. Basic Operation of the ADS7828.

The following bus protocol has been defined (as shown inFigure 2):

• Data transfer may be initiated only when the bus is notbusy.

• During data transfer, the data line must remain stablewhenever the clock line is HIGH. Changes in the data linewhile the clock line is HIGH will be interpreted as controlsignals.

Accordingly, the following bus conditions have been defined:

Bus Not Busy: Both data and clock lines remain HIGH.

Start Data Transfer: A change in the state of the data line,from HIGH to LOW, while the clock is HIGH, defines aSTART condition.

Stop Data Transfer: A change in the state of the data line,from LOW to HIGH, while the clock line is HIGH, defines theSTOP condition.

Data Valid: The state of the data line represents valid data,when, after a START condition, the data line is stable for theduration of the HIGH period of the clock signal. There is oneclock pulse per bit of data.

Each data transfer is initiated with a START condition andterminated with a STOP condition. The number of data bytestransferred between START and STOP conditions is notlimited and is determined by the master device. The informa-tion is transferred byte-wise and each receiver acknowl-edges with a ninth-bit.

Within the I2C bus specifications a standard mode (100kHzclock rate), a fast mode (400kHz clock rate), and a high-speed mode (3.4MHz clock rate) are defined. The ADS7828works in all three modes.

Acknowledge: Each receiving device, when addressed, isobliged to generate an acknowledge after the reception ofeach byte. The master device must generate an extra clockpulse that is associated with this acknowledge bit.

A device that acknowledges must pull down the SDA lineduring the acknowledge clock pulse in such a way that theSDA line is stable LOW during the HIGH period of theacknowledge clock pulse. Of course, setup and hold times

must be taken into account. A master must signal an end ofdata to the slave by not generating an acknowledge bit on thelast byte that has been clocked out of the slave. In this case,the slave must leave the data line HIGH to enable the masterto generate the STOP condition.

Figure 2 details how data transfer is accomplished on the I2Cbus. Depending upon the state of the R/W bit, two types ofdata transfer are possible:

1. Data transfer from a master transmitter to a slavereceiver. The first byte transmitted by the master is theslave address. Next follows a number of data bytes. Theslave returns an acknowledge bit after the slave addressand each received byte.

2. Data transfer from a slave transmitter to a masterreceiver. The first byte, the slave address, is transmittedby the master. The slave then returns an acknowledge bit.Next, a number of data bytes are transmitted by the slaveto the master. The master returns an acknowledge bitafter all received bytes other than the last byte. At the endof the last received byte, a not-acknowledge is returned.

The master device generates all of the serial clock pulsesand the START and STOP conditions. A transfer is endedwith a STOP condition or a repeated START condition. Sincea repeated START condition is also the beginning of the nextserial transfer, the bus will not be released.

The ADS7828 may operate in the following two modes:

• Slave Receiver Mode: Serial data and clock are receivedthrough SDA and SCL. After each byte is received, anacknowledge bit is transmitted. START and STOP condi-tions are recognized as the beginning and end of a serialtransfer. Address recognition is performed by hardwareafter reception of the slave address and direction bit.

• Slave Transmitter Mode: The first byte (the slave ad-dress) is received and handled as in the slave receivermode. However, in this mode the direction bit will indicatethat the transfer direction is reversed. Serial data is trans-mitted on SDA by the ADS7828 while the serial clock isinput on SCL. START and STOP conditions are recog-nized as the beginning and end of a serial transfer.

SDA

SCL 1 2 76 8 9 1 2 3-8 8 9

Slave Address

MSB

Repeated If More Bytes Are Transferred

R/WDirection

Bit

AcknowledgementSignal from

Receiver

AcknowledgementSignal from

Receiver

STARTCondition

ACK ACK

STOP Conditionor Repeated

START Condition


ADDRESS BYTE COMMAND BYTE

The address byte is the first byte received following theSTART condition from the master device. The first five bits(MSBs) of the slave address are factory pre-set to 10010.The next two bits of the address byte are the device selectbits, A1 and A0. Input pins (A1-A0) on the ADS7828 deter-mine these two bits of the device address for a particularADS7828. A maximum of four devices with the same pre-setcode can therefore be connected on the same bus at onetime.

The A1-A0 Address Inputs can be connected to VDD or digitalground. The device address is set by the state of these pinsupon power-up of the ADS7828.

The last bit of the address byte (R/W) defines the operationto be performed. When set to a ‘1’ a read operation isselected; when set to a ‘0’ a write operation is selected.Following the START condition the ADS7828 monitors theSDA bus, checking the device type identifier being transmit-ted. Upon receiving the 10010 code, the appropriate deviceselect bits, and the R/W bit, the slave device outputs anacknowledge signal on the SDA line.

MSB 6 5 4 3 2 1 LSB

SD C2 C1 C0 PD1 PD0 X X

The ADS7828 operating mode is determined by a commandbyte which is illustrated above.

SD: Single-Ended/Differential Inputs0: Differential Inputs1: Single-Ended Inputs

C2 - C0: Channel SelectionsPD1 - 0: Power-Down Selection

X: Unused

See Table I for a power-down selection summary.

See Table II for a channel selection control summary.

MSB 6 5 4 3 2 1 LSB

1 0 0 1 0 A1 A0 R/W

PD1 PD0 DESCRIPTION

0 0 Power Down Between A/D Converter Conversions

0 1 Internal Reference OFF and A/D Converter ON

1 0 Internal Reference ON and A/D Converter OFF

1 1 Internal Reference ON and A/D Converter ON

CHANNEL SELECTION CONTROL

SD C2 C1 C0 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 COM

0 0 0 0 +IN –IN — — — — — — —

0 0 0 1 — — +IN –IN — — — — —

0 0 1 0 — — — — +IN –IN — — —

0 0 1 1 — — — — — — +IN –IN —

0 1 0 0 –IN +IN — — — — — — —

0 1 0 1 — — –IN +IN — — — — —

0 1 1 0 — — — — –IN +IN — — —

0 1 1 1 — — — — — — –IN +IN —

1 0 0 0 +IN — — — — — — — –IN

1 0 0 1 — — +IN — — — — — –IN

1 0 1 0 — — — — +IN — — — –IN

1 0 1 1 — — — — — — +IN — –IN

1 1 0 0 — +IN — — — — — — –IN

1 1 0 1 — — — +IN — — — — –IN

1 1 1 0 — — — — — +IN — — –IN

1 1 1 1 — — — — — — — +IN –IN

TABLE II. Channel Selection Control Addressed by Command Byte.

TABLE I. Power-Down Selection


INITIATING CONVERSION

Provided the master has write-addressed it, the ADS7828turns on the A/D converter’s section and begins conversionswhen it receives BIT 4 of the command byte shown in theCommand Byte. If the command byte is correct, the ADS7828will return an ACK condition.

READING DATA

Data can be read from the ADS7828 by read-addressing thepart (LSB of address byte set to 1) and receiving thetransmitted bytes. Converted data can only be read from theADS7828 once a conversion has been initiated as describedin the preceding section.

Each 12-bit data word is returned in two bytes, as shownbelow, where D11 is the MSB of the data word, and D0 is theLSB. Byte 0 is sent first, followed by Byte 1.

FIGURE 3. Typical Read Sequence in F/S Mode.

Sr A11 0 0 1 0 A0 R A 0 0 0 0 D11 D10 D9 D8 A D7 D6 . . .D1 D0 N P

S A11 0 0 1 0 A0 W A SD C2 C1 C0 PD1 PD0 X X A

From Master to Slave A = acknowledge (SDA LOW)N = not acknowledge (SDA HIGH)S = START ConditionP = STOP ConditionSr = repeated START condition

W = '0' (WRITE)R = '1' (READ)

From Slave to Master

Write-Addressing Byte Command Byte

ADC Power-Down Mode ADC Sampling Mode

ADC Converting Mode ADC Power-Down Mode(depending on power-down selection bits)

Read-Addressing Byte 2 x (8 Bits + ack/not-ack)

See Note (1)

NOTE: (1) To secure bus operation and loop back to the stage of write-addressing for next conversion, use repeated START.

MSB 6 5 4 3 2 1 LSB

BYTE 0 0 0 0 0 D11 D10 D9 D8

BYTE 1 D7 D6 D5 D4 D3 D2 D1 D0

READING IN F/S MODE

Figure 3 describes the interaction between the master andthe slave ADS7828 in Fast or Standard (F/S) mode. At theend of reading conversion data the ADS7828 can be issueda repeated START condition by the master to secure busoperation for subsequent conversions of the A/D converter.This would be the most efficient way to perform continuousconversions.


FIGURE 4. Typical Read Sequence in HS Mode.

READING IN HS MODE

High Speed (HS) mode is fast enough that codes can beread out one at a time. In HS mode, there is not enough timefor a single conversion to complete between the reception ofa repeated START condition and the read-addressing byte,so the ADS7828 stretches the clock after the read-address-ing byte has been fully received, holding it LOW until theconversion is complete.

See Figure 4 for a typical read sequence for HS mode.Included in the read sequence is the shift from F/S to HSmodes. It may be desirable to remain in HS mode afterreading a conversion; to do this, issue a repeated STARTinstead of a STOP at the end of the read sequence, since aSTOP causes the part to return to F/S mode.

Sr A11 0 0 1 0 A0 R A

S X0 0 0 0 1 X X N

Sr A11 0 0 1 0 A0 W A SD C2 C1 C0 PD1 PD0 X X A

0 0 0 0 D11 D10 D9 D8 A D7 D6 . . .D1 D0 N P

F/S Mode

HS Mode Master Code

HS Mode Enabled

HS Mode Enabled


ADC Converting Mode

Command ByteWrite-Addressing Byte

Read-Addressing Byte

HS Mode Enabled Return to F/S Mode(1)

ADC Power-Down Mode(depending on power-down selection bits)

2 x (8 Bits + ack/not-ack)


W = '0' (WRITE)R = '1' (READ)


NOTES: (1) To remain in HS mode, use repeated START instead of STOP.(2) SCLH is SCL in HS mode.

SCLH(2) is stretched LOW waiting for data conversion


Internal VREF vs Turn-On Time Typical Characteristic plot.If the PD1 bit has been set to logic ‘0’ while using theADS7828, then the settling time must be reconsideredafter PD1 is set to logic ‘1’. In other words, whenever theinternal reference is turned on after it has been turned off,the settling time must be long enough to get 12-bit accu-racy conversion.

3) When the internal reference is off, it is not turned on untilboth the first Command Byte with PD1 = ‘1’ is sent andthen a STOP condition or repeated START condition isissued. (The actual turn-on time occurs once the STOP orrepeated START condition is issued.) Any Command Bytewith PD1 = ‘1’ issued after the internal reference is turnedon serves only to keep the internal reference on. Other-wise, the internal reference would be turned off by anyCommand Byte with PD1 = ‘0’.

The example in Figure 5 can be generalized for a HS modeconversion cycle by simply swapping the timing of the con-version cycle.

If using an external reference, PD1 must be set to ‘0’, and theexternal reference must be settled. The typical sequence inFigure 3 or Figure 4 can then be used.

READING WITH REFERENCE ON/OFF

The internal reference defaults to off when the ADS7828power is on. To turn the internal reference on or off, seeTable I. If the reference (internal or external) is constantlyturned on and off, a proper amount of settling time must beadded before a normal conversion cycle can be started. Theexact amount of settling time needed varies depending onthe configuration.

See Figure 5 for an example of the proper internal referenceturn-on sequence before issuing the typical read sequencesrequired for the F/S mode when an internal reference isused.

When using an internal reference, there are three things thatmust be done:

1) In order to use the internal reference, the PD1 bit ofCommand Byte must always be set to logic ‘1’ for eachsample conversion that is issued by the sequence, asshown in Figure 3.

2) In order to achieve 12-bit accuracy conversion whenusing the internal reference, the internal referencesettling time must be considered, as shown in the

FIGURE 5. Internal Reference Turn-On Sequence and Typical Read Sequence (F/S mode shown).

Sr A11 0 0 1 0 A0 R A 0 0 0 0 D11 D10 D9 D8 A D7 D6 . . .D1 D0 N P

S A11 0 0 1 10 A0 W A SD C2 C1 C0 PD0 X X A

S A11 0 0 1 10 A0 W A XXXXXX X A P Wait until the requiredsettling time is reached

Internal Reference Turn-On Sequence

Settled Internal Reference

Settled Internal Reference

Internal ReferenceTurn-On

Settling Time

Typical Read Sequence(1)

in F/S Mode


W = '0' (WRITE)R = '1' (READ)





ADC Converting Mode ADC Power-Down Mode(depending on power-down selection bits)

Read-Addressing Byte 2 x (8 Bits + ack/not-ack)

seenote(2)

NOTES: (1) Typical read sequences can be reused after the internal reference is settled.

(2) To secure bus operation and loop back to the stage of write-addressing for next conversion, use repeated START.


LAYOUT

For optimum performance, care should be taken with thephysical layout of the ADS7828 circuitry. The basic SARarchitecture is sensitive to glitches or sudden changes on thepower supply, reference, ground connections, and digitalinputs that occur just prior to latching the output of the analogcomparator. Therefore, during any single conversion for an“n-bit” SAR converter, there are n “windows” in which largeexternal transient voltages can easily affect the conversionresult. Such glitches might originate from switching powersupplies, nearby digital logic, and high-power devices.

With this in mind, power to the ADS7828 should be clean andwell-bypassed. A 0.1µF ceramic bypass capacitor should beplaced as close to the device as possible. A 1µF to 10µFcapacitor may also be needed if the impedance of theconnection between +VDD and the power supply is high.

The ADS7828 architecture offers no inherent rejection ofnoise or voltage variation in regards to using an externalreference input. This is of particular concern when thereference input is tied to the power supply. Any noise andripple from the supply will appear directly in the digital results.While high-frequency noise can be filtered out, voltage varia-tion due to line frequency (50Hz or 60Hz) can be difficult toremove.

The GND pin should be connected to a clean ground point.In many cases, this will be the “analog” ground. Avoidconnections that are too near the grounding point of amicrocontroller or digital signal processor. The ideal layoutwill include an analog ground plane dedicated to the con-verter and associated analog circuitry.

PACKAGE OPTION ADDENDUM

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Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead/Ball Finish(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

ADS7828E/250 ACTIVE TSSOP PW 16 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS7828E

ADS7828E/250G4 ACTIVE TSSOP PW 16 250 Green (RoHS& no Sb/Br)


ADS7828E/2K5 ACTIVE TSSOP PW 16 2500 Green (RoHS& no Sb/Br)


ADS7828E/2K5G4 ACTIVE TSSOP PW 16 2500 Green (RoHS& no Sb/Br)


ADS7828EB/250 ACTIVE TSSOP PW 16 250 Green (RoHS& no Sb/Br)

CU NIPDAU Level-1-260C-UNLIM -40 to 85 ADS7828EB

ADS7828EB/250G4 ACTIVE TSSOP PW 16 250 Green (RoHS& no Sb/Br)


ADS7828EB/2K5 ACTIVE TSSOP PW 16 2500 Green (RoHS& no Sb/Br)


ADS7828EB/2K5G4 ACTIVE TSSOP PW 16 2500 Green (RoHS& no Sb/Br)


(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availabilityinformation and additional product content details.TBD: The Pb-Free/Green conversion plan has not been defined.Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement thatlead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used betweenthe die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weightin homogeneous material)

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PACKAGE OPTION ADDENDUM

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Addendum-Page 2

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finishvalue exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF ADS7828 :

• Automotive: ADS7828-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

http://focus.ti.com/docs/prod/folders/print/ads7828-q1.html

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

ADS7828E/250 TSSOP PW 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

ADS7828E/2K5 TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

ADS7828EB/250 TSSOP PW 16 250 180.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

ADS7828EB/2K5 TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 24-Apr-2013

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS7828E/250 TSSOP PW 16 250 210.0 185.0 35.0

ADS7828E/2K5 TSSOP PW 16 2500 367.0 367.0 35.0

ADS7828EB/250 TSSOP PW 16 250 210.0 185.0 35.0

ADS7828EB/2K5 TSSOP PW 16 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

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Pack Materials-Page 2

IMPORTANT NOTICE

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