Brandon Wang 11-14-2016

Co-Design and Co-analysis for Heterogeneous Integration

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•  2.5D Silicon Interposer

•  TSV based 3D-IC

•  TSV-Less Integration – No wafer thinning, less

yield loss –  Integrated Fan out WLP –  Face2face uBump or

Cu2Cu connection for 2-die stack ( c2w, w2w)

•  Monolithic 3D-IC

Examples of Heterogeneous Integration

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Example : InFO Design and Analysis Integrated Flow

Quantus InFO and Die RC Extraction

PVS Physical Sign off ( InFO + Cross Die )

InFO Implementation using Allegro SiP, with Die Abstracts from Innovus/Virtuoso

Tempus Multi-Die STA

SystemSI SSN Sim

PowerSI PDN/EMI

PowerDC Package Thermal

Voltus-SPA 1. System EMIR ( Die + InFO) 2. Layer Based Thermal Analysis (Die level temper distribution)

XtractIM RLCK Extraction

System Partitioning and Planning OrbitIO

Other Designated InFO features built in Allegro SiP •  Support the specific manufacturing requirements of InFO

–  Focus on very thin and balanced metal– minimizing warpage

–  Focus on localized metal density; meshed metal, meshed pads

•  Layer Compare - allow the InFO designer to compare GDS to Layout local to the tool; used as a designer’s check prior to sending artwork to TSMC

•  Speed/automation/fast turnaround, with iPVS integrated, to support in-design DRC check, with IC level sign off quality;

•  Intelligent stream outputs, including vectorized GDS2, Verilog, and CDL format to work seamlessly with IC tools;

•  Support Both InFO-S, and InFO_PoP designs

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Voltus with Embedded Sigrity

InFO: Voltus-SPA for chip-PKG co-analysis on EMIR/Thermal

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Example 2: M3D, or Massive Direct Inter Connects

3D-IC using fine-pitch contacts for inter-die P&R Optimization

How to partition so that the dies are similar in size for WL stacking

How to do CTS when it may across multiple dies, with different

processes?

How to have physical synthesis that

generates 3D-aware netlist?

What granularity for floor planning, and P&R?

How to sign off for timing across die at MMMC?

How to do DFT, together, or separately?

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Example: Si Photonics Design in 2.5D Interposer

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MEMS Sub-flow concept Top-down approach

Blocks to be carried on ANSYS® Multiphysics

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•  The Era of System design through heterogeneous integration – Mobile, IoT, Wearable in consumer applications will drive the TSV-less

3D integration technologies such as fanout WLP to mass production; – Cloud Data Server, networking infrastructure, and high performance

computing will drive TSV based/High density F2F interconnect based heterogeneous integration, including silicon photonics, Digital-Memory Stack, Logic on Logic, etc;

•  Co-design and Co-analysis cover wide range of system integration needs –  System Level Planning tool for heterogeneous integration – Co-Design and analyze IC in context of PCB/package system – Co-design and Optimization in Multi-die System In Package; – Cross DB physical verification, electrical analysis, thermal analysis

concurrently, such as MEM/IC Co-design and Thermal Aware EMIR; –  The availability of ultra high density interconnect will require more

holistic algorithm for multi-die design/optimization.

•  Heterogeneous Integration may introduce new disciplines in design practices/methodologies

Summary