*VHDL & ASIC DesignITSoC Lab.Prof. Young-Chul Kim

*Course scheduleVHDL & Digital System DesignTerm project #1: Digital watchMidterm: Presentation & demo project #1ISP & FPGA ImplementationTerm project #2: ISP Algorithm & designFinal: Presentation & demo project #2

*ContentsAgendaASIC DesignVHDL and BackgroundVHDL and ASIC Design EnvironmentModeling, Synthesis & FPGA ImplementationVHDL Evolution and Future

*Agenda

Mobile Society Change PC -> Mobile CommunicationComponent -> System

Design MethodologyASIC Design FlowSoC Design Flow

*Shift 1: From PC to Communications Centric-> Domain Specific ComputingWWW JavaConfigurableMulti-StandardInfo Plug...LANBroadbandNetworkServices MPEG 4-7100 Gop/s 5 Gtr/s 10 Watt100Mb/sWLAN

*Shift 2: Chip from Component -> System19607080902000t2010RT-ops FSMaspFPGACdspPPASIPHardwareASICICFilters AD/DARFmemorygateopampSoftwareDesign Softwareembedded CServices OOcC++NetworkVHDL System onSilicon Board

*Environmental Changes in Mobile SocietyPC EraBeginning of 8-bit/64K Memory PC era from late in 1970sInternet EraBeginning of PC Communication, E-mail (WS, PC), WWWMobile Phone EraBeginning of Analog Mobile Phone, Digital Phone era from mid of 1980s3rd Generation of IMT-2000 Any where, any time, any servicePost PC EraBeginning of various types of smart IT industry and network information appliances

*Post-PC Silicon System in 2010RF / Analog 32 Bit ASPPs DisplaySoundDataBioActuators50 GIPS-500GOPSwww gpsMore than IP assembly!! 100 MByteDistributed Memory>1GHzRe-configurable Interconnect FLEXIBILITY - REUSE - IPEmbedded Software10 M gateRe-configurableComputing10 M GateHardwiredLogic

*Key Enabling Technologies

Keys to 3Gand beyond

processing power

power consumption

memory capacity

RF-CMOS

System partitioning

Firmware

Conversion -Technology

System Architecture

PA-Technology

Cores

Memories

BiCMOS

*Productivity Gap in Hardware Design A growing gap between design complexity and design productivitySource: sematech97

*Increasing Designer Productivity

7 AreasA : Register-transfer level to layoutB : Low powerC : LibrariesD : Analog/mixed-signal designE : Intellectual property reuseF : Hardware/software coverification G : System-level specification

Logic transistors per chip ( millions )

10,000

0.001

1981

1995

2009

0.01

A, B

C, D

E

F

G

100,000

58% CAGR

21% CAGR

Productivity (thousands of transistors per staff month)

*ASIC Design The Silicon Evolution

*ASIC Design - Technology Diffusion

*ASIC Design - Profit LossSource: McKinsey

*ASIC Design-VLSI Crisisfeature size - decreases by a factor of 2 in every 4 years.chip size - increases5 mm 1977, 15-20 mm in 2000, 25-30 mm in 2010total transistor count rises by a factor of 2 in every 18 months.fabrication cost - doubles for each generationprogrammer productivity30 lines/day ($20/line) ~ 0.5 lines/daydesigner productivity30 transistors/day30 HDL lines/day, 300 gates/day, 1200 transistors/day

*ASIC Design-VLSI CrisisHDL based designsimulationlogic synthesisbehavioral synthesisFormal verificationEquivalence verification of HDL based designs of different abstract levels.Intellectual Propertyvendor librarysynthesizable core

*ASIC Design-Design ReuseMore than 100M gates in 40 nm10 1M gates per synthesis module20 - 100 synthesis modules per chipbehavioral synthesis100M gates by the years 2010Design Reuseconstant project team sizesshrinking project completion timesLarge portions of the chip will result from reusing existing blocks.

*ASIC Design-System DesignBuilding blocksimage/video processingspeech codeccommunicationsASIC Designbecomes a system integrationsystem level analysis of available building blocksBalancing of available IP building blocksproduct differentiation at the system level

*ASIC Design-Intellectual PropertyIP Development / Integration HouseDiverse market needse.g.> graphics chips with digital modem capabilityASIC Designbecomes a system integrationperformance analysis of availiable building blocksbalancing of available building blocksReusing IP Building Blocksonly viable approach to designing over 1M gates reasonable time.Reusing IP building blocks developed outside is the way to merge knowledge from different applications onto a single chip

*ASIC Design-Intellectual PropertyOn Silicon IP(hard IP)ASICs chip setsprogrammable DSPsOff Sillicon IP(soft IP)synthesizable corea reference implementation in silliconadds a credibilityFirm IP(soft IP)RTL level libraries

*ASIC Design-Levels of AbstractionArchitectual /Algorithmic described in terms of the algorithms the system performs.High lebel design tradeoffs, e.g. hardware /software codesign.RTLflow of data and control signals whthin / between functional blocks.schedules assignments at clock edges.Gateinterconnection of switching elements (gates).Switchdescribes logic behavior of transistor circuits.Evaluates conflicts caused by signal strengths of multiple nets.

*Market PressuresSize of Custommer Telecom Market: < US$ 2T

Products:Signal-Dominated HW Systems Under SW ControlProtable, Low-Power, Manufacturable, Time to Market

Average Lifetime of a Consumer Product: 6-18 mos.

Success Depends Critically on the Ability to Design these Systems FAST!

*When Does One Use Behavioral SynthesisUse behavioral synthesis whenAlgorithmic descripion existsComplex data flow and/or memory accessOperations can be movedDesigns specification still changingNeed to explore architecture, pipelining, etc.

*Behavioral SynthesisLooks at high-level constraintsLatency, Throughput, Clockperiod goalsExtracts control /data flow behavior (Scheduling)Assigns operations to resources and statesAssigns variables to storage elements (Allocation)optimization of storagedecides if temporary storage necessaryFSM generated automaticallydefines state /state transitionscycle /cycle implementation of behaviorSCHEDULINGCYC# OP 1 2 3 4HARDWARE ALLOCATION

*Behavioral Synthesis: Definition Collection of techniques for sequential optimizationmmoRinputclkEnableinputoutputFOR I in 0 TO 2 LOOPWAIT until clkevent and clk = 1;IF (rgb[i] < 248) THEN p = rgb[i] mod 8; q = filter(x,y)*8;END IF;...InstructionsOperationsVariablesArrayssignalsconstraintsSchedulingAllocationLoop pipeliningChainingMulti cycle operationsMemory managementReset styleClocking sytyleFunctional unitsRegistersMemoriesMultiplexersDW components

*Design Automation

Evolution in Computer Technology

- Performance, Storage Capacity, GUI Technology

Evolution in Integrated Circuits and Design

- Advanced Design technology and tools

Help Designers works and decision as an assistant

*HDL Design & Computer Programming

*What is Synthesis ?

One of the most important process in designs using HDL

Synthesis = Translation + Optimization (translation) (optimization)

Translation : Behavioral or RTL description

Structural or gate-level description

Optimization : in design area and delay

*2. VHDL, History and BackgroundASIC Technology Logic synthesisVHDLWhy VHDL synthesis is necessary ?Adv. & Disadv. of VHDL Reality of VHDL synthesis

*Advance inIC fabricationtechnologyAdvance inComputer & Design toolsASIC(Application Specific IC)AppearanceASIC Technology(1)

*full-customICASIC Technology(2)semi-customIC- Gate Array- Standard Cell- PLA, PAL- Increase in gate density - Enhancement in speed(performance)- Decrease in cost- FPGA(Field Programmable GA)- PLD(Programmable Logic Device)Minimize mask pattern in fabrication processASIP(co-design)ASIC

*Logic Synthesiscircuit designwith schematic editorsimulationschematic baseddesign processcircuit designwith HDL(Hardware Description Language)simulationlanguage based design processlogicsynthesis

*VHDL(Very High Speed IC HDL)- HDL workshop in 1981 Rise of necessity of new HDL development

- USA, Publication of Documents for Department of Defense Requirements for HDL

- Birth of VHDL version 7.2 (USA DoD) in 1984

Birth of IEEE Standard 1076-1987 VHDL in 1987

VHDL 1076-1993 VHDL established in 1993 (reflect additional requirements for synthesis)

*Why VHDL synthesis is necessary ?circuit designwith HDLsimulationlogicsynthesisAutomatic netlist extractionDecrease DAT HDL independent onCircuit complexityCircuitscomplexityEarly designError detectionEasy and Early Design changePerformanceEvaluation

*Advantage of VHDL Synthesis Reduced design cycle Reduced design error

Design quality enhancement - Search in ease different design types and methodology

Independence of vendor and fabrication technology Reduced design cost - design re-usability

Easy design management - Introduction of structured design concept using HDL

Agreement with USA standard(IFIP 172)

*Disadvantage of VHDL Synthesis Cultural change in design - Design process based on language - Main goal: Digital system design

Detection and modification of design errors - Difficult to understang logic synthesis results and synthesized circuit layout - Difficult to analyse propagation delay

*Reality of VHDL SynthesisOnce modeling in VHDL, synthesis tools make results completely expected or intended (?) E.g. A = B x C

VHDL is not a programming language -> design lang.

H/W design experience is very important

Results depend highly on synthesis tools

*2. VHDL & ASIC Design EnvironmentSynthesizable funtions & Basic synthesis principlesDesign hierarchyASIC design processUseful VHDL synthesis methodology

*Synthesizable functions Combinational logic functions - primitive logic gates, decoder, multiplexer - adder, subtractor , comparator, multiplier etc.

Sequential logic functions Counters and function using counters - up/down counter, timing generator, event counter etc.

Registers and latch functions - register, latch, shift register, accumulator etc.

Control logic circuits - sequencer, controller, finite state machine etc.

*Basic Synthesis Rules Not every VHDL code can be synthesized.

Code directly in VHDL what you want to design

Synthesized results may not satisfy timing delay constraint required

* detailed designabstract design

*ASIC

*ASIC Design Process(1) System development plan and functional decomposition - Analyse advs and disadvs of algorithms - Decompose entire design into H/W and S/W - functional definition of low level modules

Decide block diagrams and design specification - Decompose into detailed H/W function - With which VHDL designs are coded - Consider items for system evaluation such as gate count

*Example: High-level block diagram

*E.g. Block diagram of Sigal generator A

*ASIC Design Process(2) Test and Simulation Plan - Improve controllability and observability Improve yield - Ways to generate test inputs(e.g: 24-bit counter, )

Logic circuit design - Common() function identification Design in Macro - VHDL code and Simulation pattern generation for each function and block

*Logic design flow

*ASIC Design Process(3) Simulation - compile and link VHDL source codes debugging - Simulation of partial/whole design ( E.g : half-adder and AND gate ) Logic Synthesis - Select ASIC vendor (Use of corresponding component library) - Performance optimization and logic minimization

Verification - Gate propagation delay time analysis of physical layout result - I/O pin assignment, ERC ( Electrical Rule Checking )

*Guideline in VHDL SynthesisBe well informed of logical structure of certain block diagram before coding in VHDL .

Test with same test pattern in order to make sure that VHDL design and final gate-level design are same and correct.

*3. VHDL Modeling, Synthesis and FPGA Implementation ExampleVHDL modeling for syntheisSimulation and logic synthesis example of VHDL modelingFPGA implementationExample of performance optimization and area minimization

*VHDL Modeling for Synthesis Abstract behavioral-level modeling (Behavioral Descriptions)

Register transfer-level modeling (Dataflow Descriptions modeling)

Structural-level modeling (Structural Descriptions)

*architecture behavioral of eqcomp4 isbegincomp :process (a, b )beginif a = b thenequals

*architecture dataflow of eqcomp4 isbegin equals

*architecture structural of eqcomp4 issignal x : std_logic_vector (0 to 3);beginu0 : xnor2 port map (a(0), b(0), x(0));u1 : xnor2 port map (a(1), b(1), x(1));u2 : xnor2 port map (a(2), b(2), x(2));u3 : xnor2 port map (a(3), b(3), x(3));u4 : and4 port map (x(0), x(1), x(2), x(3), equals);end structural ;Structural-level modeling(Structural Descriptions)

*VHDL Modeling Ex: Full Adder 1-bit half-adder(HA) VHDL modeling - Data-flow Descriptions - Behavioral Descriptions

1-bit full-adder(FA) VHDL modeling - Structural Descriptions(2 HA + OR gate) - Behavioral Descriptions

*entity half_adder is port (a, b : in bit ;sum, carry :out bit );end half_adder ;half adder (1): entity declarationabsumcarryhalf adder

*architecture RTL_description of half_adder isbeginprocess beginsum

*architecture behav_description of half_adder isbegin process beginif (a = b) then sum

*Design Equations carry = a * b sum = a * /b + /a * b

Worst Case Path tPD = 8.5 ns for the path (a sum, a carry )

Utilization (using Package CY7C371-143JC)Total PIN signals4/38Macro-cells Used2/32Unique Product Terms3/160Ex. 1 & Ex. 2 VHDL synthesis results(logic equation, critical path, device utilization)

*propagation delaySimulation result (half adder)

*entity full_adder is port (x, y, c_in : in bit ;s_out, c_out : out bit ) ;end full_adder ;full adder(1) : entity declarationxys_outc_outfull adderc_in

*architecture structure of full_adder is signal temp_sum, temp_carry_1, temp_carry_2 : bit ;component half_adder port (a, b : in bit ;sum, carry : out bit ) ;end component ;component or2 port (i1, i2 : in bit ;o : out bit ) ;end component ;

beginport map ( ); ...end structure ;full adder(2): architecture body

*full adder(3): block diagram

*u0 : half_adderport map ( a => x, b => y, sum => temp_sum, carry => temp_carry_1);u1 : half_adderport map ( a => temp_sum, b => c_in, sum => s_out, carry => temp_carry_2 );u2 : or2port map ( i1 => temp_carry_1, i2 => temp_carry_2, o => c_out );full adder(4): structural descriptionsxytemp_sumTemp_carry_1U0absumcarry

*full adder(5): logic synthesis result

*architecture behav_description of full_adder isbegin process variable I : integer ;if (x = 1) then I

*full adder(7): logic synthesis result

*FPGA implementaion of VHDL modeling Standard Cell - warehouse store like structure

Gate Arrays - Prefabricated device except metal layer

PLD(Programmable Logic Devices) - 2-stage arrays : AND plane + OR plane - PROM(Programmable ROM), PLA, PAL

FPGA(Field Programmable Gate Arrays) - Kind of Expanded PLD

*logic cellFPGA

*SynthesizerVHDLmodelingNetlist orBoolian equationResult file(timing analyzer)Graphic wave formData fileDeviceselectionSynthesisconstraintsPlacement & Routing programDevice programming file(JEDEC format)Test benchesSimulation after layout(VHDL or other formats)VHDL simulator

*Device Selection

*VHDL (compilation)

*CPLD Implementation example(1)

*CPLD (2) - reduced

*Timing analysis result per path

*Analysis result resource utilization

*Performance optimization & area minimizationcost = areagate density performance = speedDelay of critical path area minimizationperformanceoptimizationASIC implementation with best performance and lowest cost

*Example: delay enhancementSum

*Example: resource sharing(1)Y

*Example: resource sharing(2)Y

*Example: Logic gate minimization(1)

*Example: logic gate minimization(2)C

*Example: Delay optimization(1)Delay minimization in critical pathSigA

*Example: Delay minimization(2)Separate with And/Or terms

*Example: Delay minimization(3)Minimization of propagation delay from A to Z

*Guideline for delay and area minimization Try in various design ways - Proper tradeoff according to design requirement

Select predesigned adder from component library - Impossible to change internal structure - technology dependent

Add carry lookahead circuit (or coding in VHDL) - Increased area at least up to 2.5 50% RESULT

*IntegrationNeed more accurate physical design information.Ex.: gate delayFast reflection on change in ASIC fabrication technologyTool correctness and performanceUnlimited number of syntheizable entities.More correct synthesis results from VHDL source codes.VHDL Evolution and Future(1)

*Top level design toolFormal verification Date path synthesisDSP( Digital Signal Processing ) Applicationbus-style/pipelined processorregister/register file synthesisVHDL Evolution and Future(2)