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1 st AMICSA Workshop 2 & 3 October 2006 1 Evaluation of a 12 bits Video Processor for Space Application J.-Y. Seyler, F. Malou, G. Villalon ( CNES, Toulouse - France ) Slide 2 2 1 st AMICSA Workshop 2 & 3 October 2006 Presentation Plan : The Context The Purpose You said CSP ??? CSP Functions Preliminary Tests Preliminary Selection From 5 to 3 candidates Characterization Principle Measurements Results 1 possible candidate Complementary Tests Lot Evaluation Tests Quality, Reliability & Radiations Evaluation Electrical Tests Radiations Validation Slide 3 3 1 st AMICSA Workshop 2 & 3 October 2006 Context (1/2) : In space applications, analog electronics for CCD signals processing uses usually specifically designed devices such as : Asics or Hybrid Circuits... Today : Performances needs are increasing ( maximum pixel frequency, linearity, noise... ) While the mean power consumption should be decreased CMOS CCD Signal Processor So, commercial CMOS CCD Signal Processor ( CSP ) are a possible solution to cope with all these constraints. Slide 4 4 1 st AMICSA Workshop 2 & 3 October 2006 Context (2/2) : In the last years, low power CMOS CSP where introduced on the market for wide diffusion applications ( digital imaging, video, ). BUT : according to their incomplete datasheets it is not possible to accept those devices in a space payloads without complementary measurements ! Measurements objectives : With a specifically developed electronic bench, characterization : of Critical Parameters ( linearity, noise ) and Sensibility to Environmental Influence. Slide 5 5 1 st AMICSA Workshop 2 & 3 October 2006 Video Processors CSPAFE In order to optimise the performance of the electronics of video equipments, we have tested several Video Processors ( or CSP = CCD Signal Processor or AFE = Analog Front End ). 1.PRELIMINARY TESTS : These tests were based on : Latchup sensitivity Electrical performances ( some tests at several temperatures ) They have then allowed to select one possible candidate. 2.LOT EVALUATION TESTS : So, we have bought several parts from the same lot ( 2 sub-lots ) and performed a Lot Evaluation : Lot Qualification ( COTS philosophy ) Radiation sensitivity ( Latchup, Total Dose, Single Event Upset ) Purpose : Slide 6 6 1 st AMICSA Workshop 2 & 3 October 2006 You said : CSP ??? : The Analog Video Signal Processing The CSP Function Slide 7 7 1 st AMICSA Workshop 2 & 3 October 2006 Analog Video Signal Processing : 1 single consumer Off-the-shelf electronics component may replace several functions Video Chain DetectorDetector Analog Processing Electronics Analog to Digital Conversion Detector Implementation Electronics Timing Generator Power Supply Interface to Digital Devices N bits CCD PROCESSOR Photons Slide 8 8 1 st AMICSA Workshop 2 & 3 October 2006 You said CSP ??? What is an CSP, CCD Signal Processor ? It is a Integrated Circuit which is usually composed of the following elements : Input DC value compensation ( Clamp ), Correlated Double Sampling ( CDS ), Signal scaling by Variable Gain Amplifier ( VGA ), Analog to Digital Converter ( ADC ), Offset Calibration Loop based on Dark Pixels. Additional functions : DAC, auxiliary A / D Slide 9 9 1 st AMICSA Workshop 2 & 3 October 2006 CSP Functions : Slide 10 10 1 st AMICSA Workshop 2 & 3 October 2006 Preliminary Selection : Latch-Up sensitivity Test Electrical Characterization Selection Criteria Slide 11 11 1 st AMICSA Workshop 2 & 3 October 2006 Preliminary Selection : Latch-Up sensitivity Test ( CNES Quality Dep t ) : Bibliographic survey Elimination of several fab-less candidates 5 types among 2 manufacturers Latch-up tests 3 candidates among 2 manufacturers Full Electrical Characterization : Inter-calibration with other bench ( on 1 part already tested ) Tests ( @ SODERN ) 1 only candidate left Slide 12 12 1 st AMICSA Workshop 2 & 3 October 2006 Criteria & Selected CSPs : Our need : 1 Channel only, Resolution = 12 bits, 20 MSamples / Second Offset calibration loop ( based on dark pixels ) Programmable Gain : ~ 0 40 dB. We have eventually selected 3 CSPs : Candidate 1 ( Analog Devices ): 70 mW Candidate 2 ( Texas Instruments ): 80 mW Candidate 3 ( Texas Instruments ): 75 mW, Low Latchup sensitivity Slide 13 13 1 st AMICSA Workshop 2 & 3 October 2006 SEL Sensitivity / LET : Slide 14 14 1 st AMICSA Workshop 2 & 3 October 2006 Preliminary Tests : Test Bench presentation General Performances of the CSP Complementary tests of the candidate Thermal Characterization & Radiation Tests Slide 15 15 1 st AMICSA Workshop 2 & 3 October 2006 Characterization Principle : Slide 16 16 1 st AMICSA Workshop 2 & 3 October 2006 Bench : Video stimuli waveform Performances : 9.25 Mhz maxi pixel frequency Better than +/- 2 LSB (12) integ. linearity Benchmark and Evaluation Board Slide 17 17 1 st AMICSA Workshop 2 & 3 October 2006 General Performances of the CSP : Differential Non Linearity Integral Non Linearity Noise Performance Slide 18 18 1 st AMICSA Workshop 2 & 3 October 2006 Differential Non Linearity Performance : Slide 19 19 1 st AMICSA Workshop 2 & 3 October 2006 Integral Non Linearity Performance : Slide 20 20 1 st AMICSA Workshop 2 & 3 October 2006 Noise Performance : Slide 21 21 1 st AMICSA Workshop 2 & 3 October 2006 Measurements Results : Differential Non Linearity performance Integral Non Linearity performance Noise performance Comparison versus Space application requirements : Compatible with high performances applications but with complementary measurements ! Slide 22 22 1 st AMICSA Workshop 2 & 3 October 2006 Complementary Tests : Complementary Electrical Tests Total Dose Tests Slide 23 23 1 st AMICSA Workshop 2 & 3 October 2006 Complementary Tests (1/3) : Complementary Electrical Tests : Some additional electrical tests ( @ room temp ) Tests at : - 20 C, + 25 C, + 70 C Total Dose Tests : Some concerns about dose rate ( Rebound Effect ? ) CSP Slide 24 24 1 st AMICSA Workshop 2 & 3 October 2006 Electrical Tests made at ambient temperature, and related with project specifications : Pleiades Satellites needs + Specific tests for next projects ( Post Pleiades & Scientific Payloads ) : Large Reset peak Saturated pixel Clamp efficiency ( V_ref influence for V_util = V_ref = C t ) Offset correction Complementary Tests (2/3) : Slide 25 25 1 st AMICSA Workshop 2 & 3 October 2006 Complementary Tests (3/3) : Slide 26 26 1 st AMICSA Workshop 2 & 3 October 2006 Lot Evaluation : Quality, Reliability Electrical Tests Radiations Validation Slide 27 27 1 st AMICSA Workshop 2 & 3 October 2006 The Future : Lot Evaluation (at CNES) Procurement of Commercial Quality Level & Extended Temperature Range ( -20,+85C ) Purpose : Quality, Reliability & Radiations Evaluation Slide 28 28 1 st AMICSA Workshop 2 & 3 October 2006 Quality, Reliability & Radiations Evaluation Procurement750P DC0501 250P DC044 Construction Analysis Radiation Test : TID + SEU 11P TID + 5P SEU DC0501 Performance Characterization 6P DC0440 Serialization Electrical Characterization -40C/20C / +25C / +75C/+125C Life Test10P Electrical Measurement -40C/+25C/+125C DPA Final Report 6P DC0501 13P DC0501 10P DC0501 1P Reference3P Slide 29 29 1 st AMICSA Workshop 2 & 3 October 2006 Specific Test Bench : Developed @ CNES Qual. laboratory for : Biasing the component ( Stimuli Generation ) Static & Dynamic performances. FPGA delivers different digital stimuli which are transferred through a 16bits Digital to Analog Converter at the input of the CSP. The EXA3000 ( ATE ) tester ensures the control signals generation, the data reception and the processing ( parameters extraction ) FPGA Ramp CCD Format DAC 16 bits 1 > f > 600 MSPS CSP under TEST EXA3000 DNL, INL Extraction Functional Characterization : AC DC D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Din Pin 8 Bits DAC Slide 30 30 1 st AMICSA Workshop 2 & 3 October 2006 Electrical Tests : Up rating / Electrical characterization at 5 temp. : - 20 C / + 25 C / + 75 C conformity with the manufacturers datasheet - 40 C & + 125 C possibility of temperature range extension ? Dynamic Life Test (10 parts) : 2000 hours, T = 125 C, Vcc = 3.3 V Intermediate electrical measurement : 168 h, 500 h, 1000 h @ Tamb = 25 C with F = 15 Msps. The final measurement will be done at 3 temperatures. Final DPA Construction Analysis ( 6 parts ) : Identify & describe the Front-End and Back-End technologies. Slide 31 31 1 st AMICSA Workshop 2 & 3 October 2006 Radiations Validation : Total Ionizing Dose : 11 parts ( 8 On, 2 Off, 1 Ref. ) with ONERA DESP Cobalt60 Source Total Dose : 15Krad ( Si ) & 30Krad ( 2 lots ) @ 30 rad / h Low Dose Rate ( because of the Rebound Effect found after 14 krads in previous TID test ) Annealing : 24 h / 25 C + 168 h / 100 C All the datasheet parameters : measured at ambient temperature & 15 Msps. Heavy Ions Tests : Previous tests showed that the CSP is not sensitive to Single Event Latch-up for a LET of 60 MeV / mg. cm Single Event Effect ( Transient, Upset or Functional Interrupt ) UCL ( Belgium ) heavy ions facilities + specific test bench ( stimuli, count, record events ) with TRAD support. Slide 32 32 1 st AMICSA Workshop 2 & 3 October 2006 Conclusion : At the end of the validation of the lot (beginning 2007), we will be able to answer to the question : Is our selected CSP, coming from commercial procurement recommended for usage in our spaceflight applications ???