1

Magnetometer Front-end ASIC (MFA)

Magnetometer Front-end ASIC (MFA)

Magnes, W.1), H. Hauer2), A. Valavanoglou1), M. Oberst2), H. Neubauer2), W. Baumjohann1) and P. Falkner3)

1) Space Research Institute, Austrian Academy of Sciences, Graz, Austria

2) Fraunhofer, Institute for Integrated Circuits, Erlangen, Germany3) European Space Research and Technology Centre (ESA/ESTEC), Noordwijk, The

Netherlands

AMICSA 2006AMICSA 2006

Xanthi, Greece, 3rd Oct. 2006

2

OverviewOverviewM

FA

…M

FA

…

Project goals

System level block diagram

Basic integration idea

Analog and digital realization

Test results of MFA1 chip

Noise performance

Total ionization dose (TID)

Single event effects (SEE)

Temperature

Chip and instrument summary

3

Project goalsProject goalsM

FA

…M

FA

…

Development of an instrument front-end ASIC for an external fluxgate (magnetic field) sensor

Reduction of mass and power dissipation

Instrument performance as good as of a standard fluxgate electronics (Venus Express, Themis, etc.)

Reduction of instrument costs (e.g. procurement of rad-hard components)

Radiation tolerant ASIC

Manufacturing on a European chip process (which was found with the 0.35µm austriamicrosystems CMOS process)

4

System level block diagramSystem level block diagramM

FA

…M

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…

Fluxgate-Delta-Sigma2-2 Cascaded (X-Axis)

Fluxgate-Delta-Sigma2-2 Cascaded (Y-Axis)

Fluxgate-Delta-Sigma2-2 Cascaded (Z-Axis)

Delta-SigmaH/K Channel

Sa

mpl

ing,

Err

or C

anc

ella

tion

, M

odul

ato

r C

ontr

ol a

ndF

eedb

ack

4 x

Prim

ary

Filt

erS

INC

^4 (

CIC

)

3 x Secondary Filterfor X,Y,Z

(6 x boxcar averaging)

Dat

a C

olle

ctor

,P

ack

agi

ng

and

T

ele

me

try

Uni

t

Command Decoder,Fluxgate and H/K Timing / Control

Analog ExcitationCircuit

MIXED ASIC

3.5 VAnalogSupply

ReferenceVoltage

TestBus I/F

SerialInterface

3.3 VDigitalSupply

8:1 MUXCLK

TLM

HT

LML

CLK

CM

D

Spare OP 1

Spare OP 2

Spare OP 3

Spare OP 4

1 x Secondary Filterfor H/K

CMD

XY

ZH

/K

Hardware ControlLNAPD / VMODEEN / RST

MIX

ED

AS

IC -

AN

AL

OG

MIX

ED

AS

IC - D

IGIT

AL

X,Y,Z,H/KLNA

LNA

LNA

5

Merging and integration ideaMerging and integration ideaM

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…M

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…

1-bitDAC

x(t)

y(t)1 bit 21 bits

y(n) y'(n)

--

D Modulator

FPGAINT1 INT2 COMP

LNA

dt

INTBPF

Sensor

BEX

-

fS : fD

SINCFILTER

16-24ADC

ASD

2f0

D-FF

fS=f0/2

32 :1

RFB

bits

dt dt Q D

Analog Fluxgate

6

Merging and integration ideaMerging and integration ideaM

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…M

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…

1-bitDAC

x(t)

y(t)1 bit 21 bits

y(n) y'(n)

--

D Modulator

FPGAINT1 INT2 COMP

LNA

dt

INTBPF

Sensor

BEX

-

fS : fD

SINCFILTER

16-24ADC

ASD

2f0

D-FF

fS=f0/2

32 :1

RFB

bits

dt dt Q D

Analog Fluxgate

7

Analog partAnalog partM

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…M

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…

Fluxgate-Delta-Sigma2-2 Cascaded (X-Axis)

Fluxgate-Delta-Sigma2-2 Cascaded (Y-Axis)

Fluxgate-Delta-Sigma2-2 Cascaded (Z-Axis)

Delta-SigmaH/K Channel

Sa

mpl

ing,

Err

or C

anc

ella

tion

, M

odul

ato

r C

ontr

ol a

ndF

eedb

ack

4 x

Prim

ary

Filt

erS

INC

^4 (

CIC

)

3 x Secondary Filterfor X,Y,Z

(6 x boxcar averaging)

Dat

a C

olle

ctor

,P

ack

agi

ng

and

T

ele

me

try

Uni

t

Command Decoder,Fluxgate and H/K Timing / Control

Analog ExcitationCircuit

MIXED ASIC

3.5 VAnalogSupply

ReferenceVoltage

TestBus I/F

SerialInterface

3.3 VDigitalSupply

8:1 MUXCLK

TLM

HT

LML

CLK

CM

D

Spare OP 1

Spare OP 2

Spare OP 3

Spare OP 4

1 x Secondary Filterfor H/K

CMD

XY

ZH

/K

Hardware ControlLNAPD / VMODEEN / RST

MIX

ED

AS

IC -

AN

AL

OG

MIX

ED

AS

IC - D

IGIT

AL

X,Y,Z,H/KLNA

LNA

LNA

8

Analog realizationAnalog realization

Y1

First Integrator

Sensor

GIASSE ASD G’111z

1

G12

1z

1

SFB Second Integrator

Y2

RFB

ASIC

Third Integrator

G211z

1

G22

1z

1

Forth Integrator

MFA

…M

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…

Linearized model of the modified 2-2 cascaded D modulator

RFB … External feedback resistor (= 12.5 kOhm if range of ±2000 nT)

SFB … Coil factor of the feedback coil (= 10nT/μA)

SSE … Sensitivity of the sense (secondary) coil (= 2μV/nT)

GIA … Input amplifier gain at 2f0 (= 10-20)

GASD … Rectification factor

G’’11 … Time discrete gain of first integrator

f0 … Excitation frequency (= 16.384 kHz)fI … Integrator one switching frequency (= 16F0=262.144 kHz)

Gain calculation for the D modulator: 016 ff I

I

S

C

CG 11''

5.0'21

211111 GGGSSR

G IASEFBFB

11110

11 ''32''2/

' GGf

fG I

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Digital partDigital partM

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…M

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…

Fluxgate-Delta-Sigma2-2 Cascaded (X-Axis)

Fluxgate-Delta-Sigma2-2 Cascaded (Y-Axis)

Fluxgate-Delta-Sigma2-2 Cascaded (Z-Axis)

Delta-SigmaH/K Channel

Sa

mpl

ing,

Err

or C

anc

ella

tion

, M

odul

ato

r C

ontr

ol a

ndF

eedb

ack

4 x

Prim

ary

Filt

erS

INC

^4 (

CIC

)

3 x Secondary Filterfor X,Y,Z

(6 x boxcar averaging)

Dat

a C

olle

ctor

,P

ack

agi

ng

and

T

ele

me

try

Uni

t

Command Decoder,Fluxgate and H/K Timing / Control

Analog ExcitationCircuit

MIXED ASIC

3.5 VAnalogSupply

ReferenceVoltage

TestBus I/F

SerialInterface

3.3 VDigitalSupply

8:1 MUXCLK

TLM

HT

LML

CLK

CM

D

Spare OP 1

Spare OP 2

Spare OP 3

Spare OP 4

1 x Secondary Filterfor H/K

CMD

XY

ZH

/K

Hardware ControlLNAPD / VMODEEN / RST

MIX

ED

AS

IC -

AN

AL

OG

MIX

ED

AS

IC - D

IGIT

AL

X,Y,Z,H/KLNA

LNA

LNA

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Digital realizationDigital realization

SerialInterface

CLK

TL

MH

TL

ML

CLK

CM

D

CMD

TLMH / TLML

ASIC Sec. Filter 3/4/5 - 8th order HBF

Decimation of 220-bit and 12/6/3 Hz out

2-2 Cascaded Fluxgate-Delta-Sigma

Error Cancellation Logic

Primary Filter - SINC^4

Decimation of 646-bit and 8192 Hz in;24-bit and 128 Hz out

Sec. Filter - Non Overlapping Averaging

Decimation of 224-bit and 64 Hz out

Sec. Filter - Non Overlapping Averaging

Decimation of 224-bit and 32 Hz out

to TLML out MUX

Sec. Filter - Non Overlapping Averaging

Decimation of 2/2/224-bit and 16/8/4 Hz out

to TLML out MUX

Sec. Filter - Non Overlapping Averaging

Decimation of 224-bit and 2 Hz out

to TLML out MUX

to TLML out MUX

to TLMH out

to TLML out MUX

MFA

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Digital filter structure Synchronous serial INTERFACE

Simple 4 wire interface

CMD (start/16bit data/parity/stop)

TLMH/L (start/16bit data/.../stop)

TLMH always 128Hz data output

TLML 128Hz…2Hz command able

32 Status bits included in data frame

10-1

100

101

102

103

-120

-100

-80

-60

-40

-20

0

Frequency [Hz]

Mag

nitu

de [

dB]

-3dB @ 29.125Hz

SINC4

11

SNDR voltage channelSNDR voltage channelM

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test

resu

lts

…MFA

test

resu

lts

…

-100 -80 -60 -40 -20 00

20

40

60

80

100S

ND

R (

dB)

Input (dBFS)

SNDRmax=92dB @ -6dBFS

12

100

101

102

103-120

-100

-80

-60

-40

-20

0

Frequency (Hz)

PS

D (

dBF

S/r

t(H

z))

Fluxgate Channel (G11=0.5)

Voltage Channel

Fluxgate Channel (G11=0.45)

80dB

/dec

= 4

th

orde

r

Power spectral densityPower spectral density

Characteristic noise shaping behavior of delta-sigma modulators

FS = ±2,000nT fluxgate channel

FS = ±1.25V voltage channel

Fluxgate channel limited by sensor noise

Flicker noise in first integrator (=1/f noise)

Correlated double sampling in MFA2 will solve this problem

MFA

test

resu

lts

…MFA

test

resu

lts

…

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Total ionisation dose (TID)Total ionisation dose (TID)

Co-60 gamma ray, Noordwijk (ESTEC), Nov. 2005

Altogether four MFA chips of the same lot were tested upon TID

Device Name

Test Cycle

Test BoardType of

OperationDose Rate

Max. Radiation Level

MFA102 1 voltage biased 98 rad(Si)/min 129.4 krad(Si)

MFA104 2 voltage biased 93 rad(Si)/min 261.5 krad(Si)

MFA1121 housekeeping biased 65 rad(Si)/min 81.0 krad(Si)

2 housekeeping biased 56 rad(Si)/min 144.2 krad(Si)

MFA109 3 housekeeping biased 90 rad(Si)/min 88.6 krad(Si)

All chips showed full functionality in terms of command ability, data transmission as well as modulator and test bus operation throughout the entire test run as well as after the irradiation.

An increase of the supply current on the 3.3 V digital supply as well as a decrease of the Signal-to-Noise and Distortion Ratio (SNDR) was measured for all four devices under test.

MFA

test

resu

lts

…MFA

test

resu

lts

…

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TID example MFA104TID example MFA104

Test parameters: Dose rate: 93rad(Si)/min; Total dose: 261.5krad(Si)

Current analog: constant at approx. 10mA

Current digital: increases 2.55mA – 4.13mA => +61%

SNDR: drops 72dB-62dB (4-5dB per 100krad)

Irradiation time [h]

Missing data interpolated using linear interpolation

SN

DR

of

HK

-channel [d

B]

10-1

100

101

102

103

104

10-5

10-4

10-3

10-2

10-1

100

PS

D [F

S/r

t(H

z)]

[Hz]

MFA 0104: beginning (r) and end (b) of TID

•red curve: PSD @ beginning; blue curve: PSD @ end•noise floor: increase 15 to about 65 μV/√Hz •fundamental sine 10 Hz and 30Hz harmonics: unchanged•all the other harmonics: larger – increase as noise floor

MFA

test

resu

lts

…MFA

test

resu

lts

…

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Singel event effects (SEE)Singel event effects (SEE)

Two MFA chips (MFA110 and MFA 118) from the same lot were irradiated at HIF Cyclotron Université Catholique de Louvain, Dec. 2005

19 cycles with 4 different ion spices within a LET range of 2.97 – 34 MeV*cm²/mg

MFA is susceptible to latch-ups beginning at a LET of 14.1 MeV*cm²/mg

Both chips showed full functionality after the irradiation, no permanent damage occured.

SEL without protection => IAmax 99 mA, IDmax 240 mA no permanent damage occured

Results correspond with results from Mullard Space Science Laboratory, University College London. AMS 0.35 µm ‘opto’-process with a 20 µm thick epitaxial layer

MFA

test

resu

lts

…MFA

test

resu

lts

…

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Cross-sectionCross-sectionM

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test

resu

lts

…MFA

test

resu

lts

…

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Temperature behaviorTemperature behaviorM

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test

resu

lts

…MFA

test

resu

lts

…

Scale factor drift in MFA1 design is too high : > 130pp/°C

Drift is caused by Pad resistor (ESD) On-resistance of output switches Feedback buffer amplifier

Changes in MFA2 design: 0-Ohm pad resistance Lager output switches (less on-resistance) Matched buffer amplifiers

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Chip and instrument summaryChip and instrument summary

Dig

ital

Par

t

Reference Generation

FluxgateChannel X

VoltageChannel

Clo

ck G

ener

atio

n &

Err

or

Can

cella

tio

n

FluxgateChannel Y

FluxgateChannel Z

MFA

…M

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…

Chip Type: CMOS 0.35µm

Layers: 2P4M

Chip area: 20mm²

Gate Equivalent: 25,000

FAB: austraimicrosystems

Package: CQFP-100

Supply: 3.3VA/3.3VD

Total power: 46mW

TID test up to: 260krad

SEL: >LET 14MeV/cm²mg-1

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Chip and instrument summaryChip and instrument summary

3-axis fluxgate magneto-meter with external sensor

Full synchron design

4 wire interface (CLK, CMD, TLMH, TLML)

Range: +/- 2000nT

Data rate: 128Hz..2Hz

Resolution: 22bit

DR: 92dB

SNDR: 86dB

Housekeeping

Range: +/-1.25V

Data rate for 1 chan: 128Hz

Data rate for 8:1 MUX: 2Hz

Resolution: 22bit

DR: 98dB

SNDR: 92dB

MFA

…M

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…

Dig

ital

Par

t

Reference Generation

FluxgateChannel X

VoltageChannel

Clo

ck G

ener

atio

n &

Err

or

Can

cella

tio

n

FluxgateChannel Y

FluxgateChannel Z

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AcknowledgementsAcknowledgements

The authors would like to thank the European Space Agency Science Payload and Advanced Concepts Office for funding this project under contract no. 18391/04/NL/HB

and,

the Fraunhofer Institute for Integrated Circuits for the cooperation as sub-contractor for the chip integration

and,

the Institute of Meteorology and extraterrestrial Physics of the Technical University in Brunswick for supplying a high-quality fluxgate sensor.