1 8086 electronic computers m. 2 “logic” pinout of 8086 cpu command bus address bus data bus...
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8086
Electronic Computers M
2
“Logic” pinout of 8086
CPU
Command bus
Address bus
Data bus
Reset Clock Ready
Int/Inta*
Hold/HoldaDMA
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SEGMENTS
ACCUMULATORS
CS
DS
SS
ES
AH AL
BH BL
CH CL
DH DL
AX
BX
CX
DX
8086 (segmented !) Registers
All memory addresses in the IAx architectures are computed as offsets from a base address stored in a segment register
4
SP
BP
SI
DI
BASE - STACK - INDEX
IP
FLAGSh FLAGSl
Registers
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Segments
00000
FFFFF
StackSegment
Word oriented Sstack
X+2X
X-2
SS
Segmentbase address
SP (offset)Push
Pop
• The stack grows downwards• The BP is mainly used to address the stack segment as a memory data segment
BP (offset)
CS
IP (offset)
Code Segment
DataSegment
DS
6
8 10 9 11 7 6
TF DF IF OF SF ZF
ZeroSign
Overflow
Int. en.
Direction
Trap
4
AF
2 0
PF CFCarry
ParityAux. carry
FLAGS
7
Address space: 1 MBSegmented memoryUsed segment: depends from the executed instruction
PartitioningRelocationProtection16 bit (offset) instructionsSegment changes are rare (locality principle)Relocatable code
Stack: word orientedTwo operands instructions (i.e.mov AX,Mi)
8086 characteristics
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OFFSET
BASE
OFFSET
BASE
5046
002B
5048
000B50460:2B
50460:050460:150460:250460:3
(Physical address = 5048B)
SEGMENTS
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00000
FFFFF
DS X
CS Y
SS Z
ES W
L
X
Z
W
KO
N
M
Y
E
SEGMENTS
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CSDSSSES
CSDSSSES
CODE
STACK
EXTRA
DATA
CODEDATA
EXTRA
STACK
DYNAMIC RELOCATION
11
16
S + [(B + I + O) mod 64K]
(0)
16
SEGMENT CS/DS/ES/SS
Effective address 20 bits
Modul 64K sum !!!!!!Each segment is therefore maximum 64K !
Address construction
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16
BASE
INDICE
OFFSET
SI/DI
BP/BX
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OPCODE MOD DISPL
EFFECT. ADDR.
BASED
OPCODE MOD DISPL
SI/DI
EFFECT. ADDR.
INDEXED
DISPL
EFFECT. ADDR.DIRECT
OPCODE MOD
BX/BP
Address construction
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OPCODE MOD DISPL
SI/DI
EFFECT. ADDR.
BASEDINDEXED
BX/BP
OPCODE MOD
BX/BP/SI/DIINDIRECT EFFECT. ADDR.
Address construction
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AXBX
DXSPBPDISI
SS
CSDSSSESIP
Internal
CSDSSSESIP
Internal registers
BUScontrol
Instruction queueEU
control
Temporary regs.
ALU
FLAGS
EU BIU
4 bytes 8088
BIU-EU
CX
15
8086 (read)bus cycle
Address Data in
BUS CYCLE
T1 T2 T3 T4
CLOCK
Memory: low, I/O: high
AD0-AD19
ALE
IO/M*
RD*
DT/R*
DEN*
16
8086 (write)bus cycles
Address Status
BUS CYCLE
T1 T2 T3 T4
CLOCK
Memory: low, I/O: high
A16-A19
AD0-AD15
ALE
IO/M*
WR*
Data out
Address
DT/R*
DEN*
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Demultiplexed bus
73
BD[0:15)
(Data bus)
AD[0:15]
A[16:19]BA [0:19]
(Address bus)
8088
MN/MAX*
ALE 4
16
DT/R*DEN*
Vcc
373
OE*
CK
245E
N*DIR
16
To avoid bus conflicts
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Readysignal
Address Data in
BUS CYCLE
T1 T2 T3 TW
CLOCK
AD0-AD15
ALE
READY
RD*
TW TW T4
Address StatusA16-A19
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I/O interfacing
I/OINTERFACE
D[0:7]
CS*
RD*
WR*
A[0:n-1]
DataBus
CommandBus
AddressBus
I/O peripheral
Standard CPU interface
Specific periheral interface
Signals
• An interface adapts the system bus to the peripheral bus
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I/O Interfaces
• Control Registers Within an interface there are several control registers addressed as memory cells (either with I/O or memory instructions) which instruct (program) the interface logical network on how it must behave to perform the interfacing
• Data BufferWithin the interface there are data buffers where transferred data (input or output) are temporarily stored for further forwarding to the destination (CPU or peripheral). Data Buffer are addressed as memory cells (either with I/O or memory instructions)
• Sincronization and Status Registers Normally the I/O peripherals work asincronously from the CPU. Therefore a synchronization mechanism must be implemented
There are therefore Status Registers addressed as memory cells (either with I/O or memory instructions) which indicate the status of the transfer (i.e. a new data from the peripheral has been stored in the data buffer or the peripheral has read the data provided by the CPU but also whether the peripheral is OK etc.)
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Generic I/O interface
CS*
RD*
WR*
DataBus
CommandBus
AddressBus
Peripheral
•
DEC0 1
EN*2 3
OE* BufferIn
CK BufferOut
OE* Status
CK Control
•
A B
Signals
CK
OE*
CK
OE*
Port
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I/O interface for 16 bit bus
• An 8 bit interface can be connected on the high or low bus• If on the low bus only even addresses can be used for addressing the interface. He
contrary for the high bus An example: two different intefaces located (CS* !!) at addresses 78H (low bus) e 81H (high bus alto) each one having 4 registers (read or write) A,B,C and D
Proc.16 bit
D08-D15
D00-D07
Per-2
Per-1
A B C D78 7A 7C 7E81 83 85 87
RegistersPer-1Per-2
As for the memories CS* depends also from A0 e BHE*Easy extension to 4(DLX) or 8 busses systems
BLE* = A0BHE*
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Interrupts• An interrupt is an event which “breaks” the normal program flow. The processor
must start an appropriate procedure (interrupt handler) which handles the event causing the interrupt. An example is the transfer of data from an A/D converter: as soon as a new conversion is ready the A/D converter sends a signal to the computer which in turn must send the appropriate signal to the interface to read the new data and store them in an internal buffer. After the end of the interrupt handler the interrupted program flow must be resumed. «Normal» interrupts can be inhibited and un-inhibited by a proper machine instruction
• Interrupt classes:
• Hardware Interrupt : interrupt like the one previously described. The hardware interrupts can be inhibited by mean of a programmable internal flag IEN (interrupt enable/disable). Obviously there can be multiple external devices each one generating one or more interrupts and the 8086 has only one common interrupt pin. The intterrupts sources must be therefore detected
• Exceptions : internal processor occurrences: i.e. division by 0, unknown op-code, page-fault (see later) etc.
• Software Interrupt : a processor can willingly trigger an internal interrupt interrupt (for instance for initiating an OS service). There are specific instructions for this purpose.
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Vectored interrupts
Interrupt 0 pointer
Interrupt 1 pointer
Interrupt n pointer
Each interrupt must be associated to a number (n: interrupt type – one byte - value 0..255) which through a table residing in memory(Interrupt Vector Table) indicates the address of the first instruction of its interrupts handler. Upon an interrupt the CPU:1) Inhibits the Interrupt Enable (no further interrupts allowed until explicit program command)2) Reads n from the external device which has activated the highest priority signal interrupt and
multiplies it by 4 (a pointer is 4 bytes long – CS:IP)3) Saves on the stack the return address and the flags (three 16 bit words). 4) Jumps through the IVT to the interrupts handler5) When the interrupt handler is completed (RTI instruction) interrupts are enabled again
Interrupt Vector Table
Memory address 0
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n - INT TYPE
ALE
INTA*
AD0-AD7
• ALE for READY• The first INTA* cycle freezes the interrupt situation
8086 Interrupts
8086
IR0IR1IR2
IRk
(IRi or)
Inta*
Int
Inta*
n
External interrupts
PriorityNetwork
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i.e. INT TYPE 00010000b = 10h = 16d
68
Interrupt vector n. 16 (16x4)=64
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66
65
64
63
62
61
CS8-CS15
CS0-CS7
IP8-IP15
IP0-IP7
8086 interrupts
N.B. stack downward oriented
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PIC (Programmable Interrupt Controller) 8259
CS*A0 WR*RD*D0-7CAS0-2INTINTA* SP/EN*
IR0IR1IR2IR3IR4IR5IR6IR7
• Up to 8 interrupt requests (IR0..IR7) which can be extended to 64 by a cascaded device
• 8259 INT/INTA* pins are connected to the same pins of the CPU. 8259 provides the interrupt type during the second INTA* pulse
• (IRi) can be either positive edge or level
• Two IO address locations (A0). Notice that the addressing in the I/O space in 16 LSB only and the addressing mechanism is the same of the memory (but for IO/M pin)
• Interrupts can be masked and prioritized
Like MemoriesFor internal address
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Priority resolution
INT
D0...D7(Data pin connected through the bus to the CPU data pins)
n
IRi
INTA*
The PIC “freezes” the interrupt requests: non further requests are accepted until after the second INTA*
The PIC, according to the freezed requests, provides the interrupt type associated to the max priority request
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IR handling
The basic 8259 behaviour allows an interrupt of higher priority to interrupt the handling of a lower priority interrupt (fully nested interrupts) provided the processor Interrupt Enable is «on». A further request on the same level is in any case inhibited until the service routine of this level is completed (which means . All IRi can be selectively masked
PriorityResolution
I M R
I S R
IRR
INT
INTA*
IR0IR1
IR7
IMR: Interrupt Mask Register
IRR: Interrupt Request Register (needed for rdge triggered interrupts)
ISR: In-Service Register When the i-th request is serviced (its interrupt handler is started) the corresponding bit is set in ISR
EOI (End of Interrupt) command: issued at the end of an interrupt handler to reset the corresponding ISR bit.Notice: a «command» is a byte sent to a specific address of PIC which is interpreted by the PIC as a command (see the generic interface slides)
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Programmazione del
PIC 8259(1)
1=level0=edge
1=single0=cascaded
1 con 8086/88
ICW1A0
0
7 6 5 4 3 2 1 0X X X 1 LTIM X SNGLICW4
7 6 5 4 3 2 1 0
ICW4
A0
1 BUF M/S AEOISFNM000 1
1=Special Fully Nested Mode0=Normal Mode
1=AEOI0=Norm.EOI
0 X
ICW2
5 interrupt type MSbits
A0
T3 X X XT4T5T6T71
7 6 5 4 3 2 1 0
No ICW3 ?
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8259 PIC programming (2)
A0
OCW1
7 6 5 4 3 2 1 0
1 M3 M2 M1 M0M4M5M6M7
INTERRUPT MASK 0=RESET; 1=SET
A0
OCW2 0 0 L2 L1 L00EOISLH
Livello interessato
0 1 1 Specific EOI [lev] 0 0 1 Non specific EOI
1 0 1 Rotation on non specific EOI1 0 0 Rotation on AEOI (set)0 0 0 Rotation on AEOI (reset)
1 1 1 Rotation on specific EOI [lev]1 1 0 Set priority [lev ]
0 1 0 NOP
7 6 5 4 3 2 1 0
Rotation => Priority rotationLev => interrupt level upon which the operation is performed
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PIC 8259 Priority (2)
7 6 5 4 3 2 1 0
ISR 1 0 0 0010 0
Priority3 2 1 0467 5
When ROTATE on specific EOI and then EOI specific (on level 3) we have the following situation
Priority modification only upon ROTATION
ISR 0 0 0010 0 0
Priority6 5 4712 0 3
7 6 5 4 3 2 1 0
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Q*D
CKINTREQ
RESET*CL
Q
"1"
I/O command
IRi
I.e. too narrow pulse
Edge-level transformation
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8255 parallel interface• Device implementing a programmable interface of three
independent 8 bit bidirectional (input or output) parallel ports. Each port has 3 programmable possible behaviours
CS*
WR*RD*
A0
A1RESET
D0 - D7
PA0-PA7
PB0-PB7
PC0-PC7
8
8
8
8
8255
• The interface has 4 internal registers for data and commands
Ports
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Internal registers
Port A, B or C data read if selectively programmed as input ports
Control register read
Port A, B or C data write if selectively programmed as output ports. Control register write
Inteface Programming
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Behaviours
• All three ports (A, B, C) can be programmed Mode 0.• Only ports can be programmed Mode 1. • If port A is programmed Mode 1 the signals for the handshake (see next slides) are
provided by pins PC7-PC4.• If port B is programmed Mode 1 the signals for the handshake (see next slides) are
provided by pins PC3-PC0.
• Mode 0: Basic Input/Output La CPU legge/scrive sulla porta senza alcun meccanismo di sincronizzazione con l’Unità Esterna ad essa connessa. Sono presenti dei latch sulle uscite ma non sugli ingressi. • Modo 1: Strobed Input/Output La CPU legge/scrive sulla porta sincronizzandosi con l’Unità Esterna mediante un protocollo ad “handshake”. L’operazione di I/O può essere gestita sia a “interrupt” sia a “polling”. Sono presenti dei latch sia sulle uscite sia sugli ingressi.• Modo 2: not examined
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Control Word
For instance: if port B must be programmed as mode 1-output, the free pins of the port C (lower) as inputs, port A mode 0-input and the pins of port C (upper) as outputs:
1 0 0 1 0 1 0 1
( 95H )
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Set/Reset of port C bits
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Mode 0
CS*,A1,A0
RD*
INPUT
D0-D7
D0-D7
WR*
CS*,A1,A0
OUTPUT
Input
Output
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Mode 1: “handshake”
Strobed Input
The peripheral must write its data in the input latch of port (A or B) through STB* (strobe). 8255 then signals to the CPU and the peripheral that the data was accepted activating IBF (Input Buffer Full). The 8255 activates the INTR (Interrupt Request): CPU will then read the written when . Upon CPU read IBF will be reset for a further transfer from the peripheral
ACK*
DATA_OUT
OBF*
8255
STB*
DATA_IN
IBF
Peripheral8INTR
Strobed Output
82558INTR
Upon INTR activation the CPU writed the data on the latch output port (A or B); 8255 signals to the peripheral and the CPU that new data are ready activating OBF* (Output Buffer Full). The peripheral read then the data through ACK* (acknowledge) upon whihc INTR is set again
Peripheral
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Strobed Input : waveforms
BD0:7 8255 PA0:7 (PB0:7)
Peripheral
STB*
IBFPC5 (1)
PC4 (2)
PC3 (0) RD*
INTRCPU
STB*
IBF
INTR
RD*
PA0:7(PB0:7)
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Strobed Output : waveforms
BD0:7 8255 PA0:7 (PB0:7)
ACK*
OBF*PC7 (1)
PC6 (2)
PC3 (0)WR*
INTRCPU
WR*
INTR
OBF*
ACK*
Peripheral
PA0:7(PB0:7)
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45
Direct Memory Access
• Bus Transfers controlled by an external agent
• HOLD freezes the microprocesso which tristates RD*, WR*, INTA*, IO/M*
• The microprocessor bus controller must be therefore completely substituted
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82(C)37
IORD*IOWR*MEMRD*MEMWR*READYHOLDHLDAAENADSTBCS*CLKRESETD0-7A0-7
DREQ0DACK0DREQ1DACK1DREQ2DACK2DREQ3DACK3EOP*
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Timing
clock
S0 S1 S2 S3 S4 S0
HOLD/HOLDA
AEN
ADSTB
DO-D7 (address)
A0-A7
DACK
IORD*-MEMWR*
IOWR*-MEMRD*
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CS*IORD*IOWR*D0-7
I/O device
CS*MEMRD*MEMWR*D0-7
IORD*IOWR*MEMRD*MEMWR*DACKADDR0-15
DMAController
8088
245/244
EN*
HOLDA
DECODER
DATA&
CONTR.
The DMA controller issues only memory addresses I/O and MEMORY commands simultaneous Memory
Fly-by
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DMA - FLY-BYCS_PERIPH = f(BADR0-15) * HOLDA! + DACKi * (HOLDA) (NB: HOLDA in the second term is implied by DACKi and then unnecessary
CS_MEM = f(BADR0-19) * HOLDA! + f(BADR0-15) * DACKi
Some DMA controllers do not provide fly-by mode. In this case the transfer is perfermed in two phases: first the data are read into a DMA controller register then the data are transferred to the destination
Processor generated DMA controller generated
Ai_PERIPH = BADRi * HOLDA! + Xi * DACKi
Xi indicates the port or register of the transfer
Processor generated
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An example
8088
MEM
8255
DMACNTR
IOWR,DACK0
MEMRD
DREQ0
INTb
(78H)
(0-64K)
HOLD
HOLDA
Port B mode 1DMA 0 channel
Single memory chip
CSmem = BADR19! *BADR18! *BADR17! *BADR16! *HOLDA! + DACK0 = BADR19! *BADR18! *BADR17!
*BADR16! + DACK0 ; (Only one memory device and therefore its CS coincides with DACKi) CS8255 = Decod(78H)*HOLDA!+DACK0 = Decod(78H)+DACK0;
A08255 = BADR0*HOLDA! + 1*DACK0 = BADR0*HOLDA! + DACK0 = BADR0 + DACK0 ; (Port B -> A0=1,
A1=0)A18255 = BADR1*HOLDA! + 0*DACK0 = BADR1*HOLDA!
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FLOW-THROUGH
CS*IORD*IOWR*D0-7
I/O DEVICE
CS*MEMRD*MEMWR*D0-7
IORD*IOWR*MEMRD*MEMWR*
ADDR0-15D0-7
DMA CNTR
8088
245/244
EN*
HOLDA
DECODER
DATAand
CONTR
Two successive cycles: one for MEM and one for I/O ……….. Temporary register
Memory - I/O
MEMORY DEVICE
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FLOW-THROUGH
CS*MEMRD*MEMWR*D0-7
MEMORY DEVICE 64 K
D0-7MEMRD*MEMWR*
ADDR0-15
DMA CNTR
8088
245/244
EN*
HOLDA
DECODER
DATAand
CONTR
DMA addresses only memory
Two successive MEMORY transfers
Memory to memory
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Behaviour
In case of transfers between MEMORY and I/O the addressing cycle takes place every 256 transfers
In case of MEMORY-MEMORy twice per cycle (source and destination)
EOP* signal (bidirectional) indicates the end of a channel program
IOWR*(MEMWR*)
EOP*
It can be sent directly to a 8259 (edge sensitive )
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Single transfer mode
After each transfer the bus is temporarily released at least for one cycle
Demand mode
Uninterrupted transfers until DREQ active
Block mode
Once the channel program is started it goes uninterrupted until its end
Cascade mode
Not analysed here
Behaviour
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CONTROL WORD
COMMAND REGISTER
7 6 5 4 3 2 1 0
MEM/MEM
ENABLE
CHAN. 0 HOLD
ADDRESS
CONTROLLERENABLE
COMPRESSEDTIMING
FIXED/ROT.PRIORITY
LATE/EXT.WRITE
DREQHI/LO
DACKHI/LO
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Mode register
MODE REGISTER
7 6 5 4 3 2 1 0
CHANNEL X SELECT
00 (VERIFIY)
01 WRITE (TO MEM)
10 READ (FROM MEM)
11 ILLEGALE
XX SE CASCADE MODE
0 AUTOINIT DISABLE
1 AUTOINIT ENABLE
0 AUTOINCR
1 AUTODECR
00 DEMAND
01 SINGLE
10 BLOCK
11 CASCADE
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Request RegisterREQUEST REGISTER
7 6 5 4 3 2 1 0
CHANNEL X SELECT
0 RESET REQUEST1 SET REQUEST
DON'T CARE
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Control words
7 6 5 4 3 2 1 0MASK REGISTER 1
CHAN. SELMASK BIT
DON'T CARE
7 6 5 4 3 2 1 0MASK REGISTER 2
CHAN 0
CHAN 1CHAN 2
CHAN 3
59
Status word
7 6 5 4 3 2 1 0
STATUS WORD
CHANNEL TCCHANNEL REQ
60
EOP* Open Drain
STOP*
INT EOP
8237
EOP*
EXT EOP
VCC
4K7
61
Internal RegistersA3 A2 A1 A0 IOR* IOW*
1 0 0 0 0 1 Read status register 1 0 0 0 1 0 Write command register 1 0 0 1 0 1 Illegale 1 0 0 1 1 0 Write request register 1 0 1 0 0 1 Illegale 1 0 1 0 1 0 Write mask register 1 0 1 1 0 1 Illegale 1 0 1 1 1 0 Write mode register 1 1 0 0 0 1 Illegale 1 1 0 0 1 0 Clear byte flip flop 1 1 0 1 0 1 Read temporary register 1 1 0 1 1 0 Master clear 1 1 1 0 0 1 Illegale 1 1 1 0 1 0 Clear mask register 2 1 1 1 1 0 1 Illegale 1 1 1 1 1 0 Write mask register 2
Addresses with A3 =1 => control
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Addresses
A3 A2 A1 A0 0 0 0 0 Base/current word addr. Ch. 0 0 0 0 1 Base/current word count Ch. 0 0 0 1 0 Base/current word addr. Ch. 1 0 0 1 1 Base/current word count Ch. 1 0 1 0 0 Base/current word addr. Ch. 2 0 1 0 1 Base/current word count Ch. 2 0 1 1 0 Base/current word addr. Ch. 3 0 1 1 1 Base/current word count Ch. 3
Addresses with A3 =o => data registers