1. 1 cycle mips performance - georgetown...
TRANSCRIPT
1. 1 cycle MIPS performance3. general pipelining8. MIPS pipe, LW12. MIPS performance, piped vsnon-piped14. arrays, piped15. hazards
required delay before using written data.
Positive edge-triggered FF:
output changes on rising clock
NEG-FFSamples
NEG-FFLatches
POS-FFSamples
POS-FFLatches
RegFile negtriggered FF
upstream, postriggered FF
downstream,pos triggeredFF
POS/NEGclock edges.
2-phase,ACTIVE
lw $1, ...nopnopnopadd $2, $1, ...
Could we possibly send data from pipeline stage to stage?
Sub is stuck in Fetch,repeatedly fetchedPC not incremented
Instruction written to 1st stage pipeline register is OR $0, $0, $0
Sub advances to Reg-Read at t == 5
PC incrementednext instruction fetched
add $1, _, _sub _, $1, _
Data available next tick.
Forwarding (feedback) works.
lw $1, (offset)(_)sub _, $1, _
WHY NOT forward Dmem.out?
DELAY = 200ps (memory) + 200ps (ALU)
forward from WB instead, insert NOP
Feedback paths to ALU go to both inputs. Hazard detection sets MUXes: Opcode needed in pipe stage registers for detection.
