0xf1d0 interim review

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0xf1d0 0xf1d0 Interim Review Interim Review Rod Green ( Rod Green ( [email protected] [email protected] ) ) Eric Haas ( Eric Haas ( [email protected] [email protected] ) ) Ming Luo ( Ming Luo ( [email protected] [email protected] ) ) James Shuma ( James Shuma ( [email protected] [email protected] ) )

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0xf1d0 Interim Review. Rod Green ( [email protected] ) Eric Haas ( [email protected] ) Ming Luo ( [email protected] ) James Shuma ( [email protected] ). Architectural Features and Design Goals. Architectural Features Modularity Design Goals Make it work. Modularity Parallelism - PowerPoint PPT Presentation

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Page 1: 0xf1d0 Interim Review

0xf1d00xf1d0Interim ReviewInterim Review

Rod Green (Rod Green ([email protected]@ece.cmu.edu))Eric Haas (Eric Haas ([email protected]@ece.cmu.edu))Ming Luo (Ming Luo ([email protected]@ece.cmu.edu))

James Shuma (James Shuma ([email protected]@ece.cmu.edu))

Page 2: 0xf1d0 Interim Review

Architectural Features and Architectural Features and Design GoalsDesign Goals

Architectural FeaturesArchitectural Features ModularityModularity

Design GoalsDesign Goals Make it work.Make it work. ModularityModularity ParallelismParallelism Make it run fast.Make it run fast.

Page 3: 0xf1d0 Interim Review

Performance Against Performance Against ScheduleSchedule

For more detail see http://www.ece.cmu.edu/~shuma/0xf1d0/sched.html

week week begins week ends Ming Luo Rod Green Eric Haas Jim Shuma IMPORTANT

5 10-Feb 14-Feb Design Review 2:30 Friday6 17-Feb 21-Feb full pinout (02/23/2002) protocols 5-minute overview in class

7 24-Feb 28-Feb FPGA+1 processor working decrypt softwareparent-child software head-fpga software Demo 1 on Friday

8 3-Mar 7-MarInterim reporthead/pc software

10 17-Mar 21-Mar all board components work MP3 head ported Demo 2 by Friday11 24-Mar 28-Mar routers MP3 leaf implemented final presentations begin

springbreak

12 7-Apr 11-Apr MP3 leaf portedEverything but hardware acceleration and PC applications done

13 14-Apr 18-Apr integrationhardware acceleration PC applications Completion by Thursday

14 21-Apr 25-Apr

taunting other group members about our early completion

Final exam TuesdayDemo 3 by Friday

9 10-Mar 14-MarDebugging last component started (everything else MP3 head implemented

Superlog test suite Interim Report to TA by Friday

31-Mar 4-Marall board components work together

15 28-Apr 2-May

Page 4: 0xf1d0 Interim Review

rdg’s Most Importantrdg’s Most ImportantTechnical Lessons LearnedTechnical Lessons Learned

General knowledge of MP3 General knowledge of MP3 algorithmalgorithm

General knowledge of hc11 General knowledge of hc11 architecturearchitecture

All knowledge learned from All knowledge learned from splitting mp3 code up and trying to splitting mp3 code up and trying to make it easier to portmake it easier to port

Page 5: 0xf1d0 Interim Review

rdg’s Codesign Lessons rdg’s Codesign Lessons LearnedLearned

Page 6: 0xf1d0 Interim Review

rdg’s Wish Listrdg’s Wish List Down with managers! Down with Down with managers! Down with

managers :)managers :)

Page 7: 0xf1d0 Interim Review

haas’s Most Importanthaas’s Most ImportantTechnical Lessons LearnedTechnical Lessons Learned

I am a slacker. So far, I haven't actually designed any of I am a slacker. So far, I haven't actually designed any of the components that are going to be used in our final the components that are going to be used in our final design. However, I have worked a lot on communication design. However, I have worked a lot on communication and I've designed a few prototypes to testconcepts put and I've designed a few prototypes to testconcepts put forth. There were some interesting timing issues that I forth. There were some interesting timing issues that I hadn't thought about that came up when we were working hadn't thought about that came up when we were working on designing our protocols. But really, the only thing I've on designing our protocols. But really, the only thing I've learned about technically is SuperLog. I've been reading learned about technically is SuperLog. I've been reading up on SuperLog these past few weeks, and I like the things up on SuperLog these past few weeks, and I like the things that SuperLog adds to Verilog. Unfortunatly, synplify that SuperLog adds to Verilog. Unfortunatly, synplify doesn't work for .slg files, though, so I'm going to have to doesn't work for .slg files, though, so I'm going to have to switch back to verilog for my next two milestones that are switch back to verilog for my next two milestones that are going to go on the FPGA. I've also been reminded about going to go on the FPGA. I've also been reminded about my tendancy to rewrite components at least a couple of my tendancy to rewrite components at least a couple of times before I'm satisified with them.times before I'm satisified with them.

Page 8: 0xf1d0 Interim Review

haas’s Codesign Lessons haas’s Codesign Lessons LearnedLearned

There doesn't seem to be as much There doesn't seem to be as much work on the hardware side for our work on the hardware side for our design as there is for software. Most design as there is for software. Most of the projects I've looked in this class of the projects I've looked in this class and elsewhere at seem to be similarly and elsewhere at seem to be similarly unbalanced one way or the other, unbalanced one way or the other, though, so this doesn't appear to be though, so this doesn't appear to be abnormal.abnormal.

Page 9: 0xf1d0 Interim Review

haas’s CAD Tools Lessons haas’s CAD Tools Lessons LearnedLearned

Since I'm the ``hardware guy,'' I have barely touched Since I'm the ``hardware guy,'' I have barely touched Hiware, so I can't really comment on it's usefulness or lact Hiware, so I can't really comment on it's usefulness or lact thereof. I haven't really exploited SuperLog anywhere thereof. I haven't really exploited SuperLog anywhere near the extent of its capabilities, but it seems to be near the extent of its capabilities, but it seems to be really nice from my perspective to do things from both really nice from my perspective to do things from both software and hardware design perspectives and still be software and hardware design perspectives and still be able to put the two together. Interfaces are a big win, as able to put the two together. Interfaces are a big win, as are the multiple types of fork and join. This is one tool are the multiple types of fork and join. This is one tool that I hope I'll get more of a chance to use in the future, that I hope I'll get more of a chance to use in the future, both in this class and afterwards. Max+Plus II is a strange both in this class and afterwards. Max+Plus II is a strange tool, it isn't quite intuitive, but it could be far worse. The tool, it isn't quite intuitive, but it could be far worse. The worst thing I've run into is that you have to import things worst thing I've run into is that you have to import things and compile and place them in a certain order, or things and compile and place them in a certain order, or things won't work the way you think that they should and won't work the way you think that they should and become a real pain to fix.become a real pain to fix.

Page 10: 0xf1d0 Interim Review

haas’s Wish Listhaas’s Wish List The only group member that I've The only group member that I've

really had a problem with is myself. really had a problem with is myself. We haven't had perfect We haven't had perfect communication, but we really communication, but we really haven't had the major problems that haven't had the major problems that I've had with classes I've taken or I've had with classes I've taken or projects I've worked on in the past, projects I've worked on in the past, but we haven't been perfect either. but we haven't been perfect either.

Page 11: 0xf1d0 Interim Review

mluo’s Most Importantmluo’s Most ImportantTechnical Lessons LearnedTechnical Lessons Learned

A fully wired up component does not A fully wired up component does not equal a working component.equal a working component.

How to communicate with the How to communicate with the processors and how they will processors and how they will communicate with each other and communicate with each other and the fpga.the fpga.

Make sure to see if the fpga works Make sure to see if the fpga works with the ram in, but not when it’s with the ram in, but not when it’s NOT in!NOT in!

Page 12: 0xf1d0 Interim Review

mluo’s Codesign Lessons mluo’s Codesign Lessons LearnedLearned

Page 13: 0xf1d0 Interim Review

mluo’s Codesign Lessons mluo’s Codesign Lessons LearnedLearned

When designing a huge system, try When designing a huge system, try to modularize things as much as to modularize things as much as possible. possible.

In order to facilitate the design of In order to facilitate the design of complicated components, it is best complicated components, it is best to make sure it works in simulation to make sure it works in simulation first, and then move on to actual first, and then move on to actual implementation.implementation.

Page 14: 0xf1d0 Interim Review

mluo’s CAD Tools Lessons mluo’s CAD Tools Lessons LearnedLearned

HIWare works, but only when all HIWare works, but only when all your settings are right.your settings are right.

MaxPlus+II is a pain to set up if MaxPlus+II is a pain to set up if you are not careful.you are not careful.

Page 15: 0xf1d0 Interim Review

mluo’s Wish Listmluo’s Wish List The successful completion of our The successful completion of our

project well within our rigorous project well within our rigorous completion schedule.completion schedule.

Page 16: 0xf1d0 Interim Review

shuma’s Most Importantshuma’s Most ImportantTechnical Lessons LearnedTechnical Lessons Learned

Processors are really complexProcessors are really complex Even when you think you’re writing Even when you think you’re writing

synthesizable Verilog and Synplify synthesizable Verilog and Synplify doesn’t complain, you might end doesn’t complain, you might end up with nothing but wires running up with nothing but wires running straight from input to output. straight from input to output. Check the synthesized logic.Check the synthesized logic.

Page 17: 0xf1d0 Interim Review

shuma’s Codesign Lessons shuma’s Codesign Lessons LearnedLearned

To make a complex system:To make a complex system: Build a frameworkBuild a framework Build high-level descriptions of Build high-level descriptions of

modulesmodules Iteratively implement those high-level Iteratively implement those high-level

modulesmodules

Page 18: 0xf1d0 Interim Review

shuma’s CAD Tools shuma’s CAD Tools Lessons LearnedLessons Learned

Hiware is not a CAD tool.Hiware is not a CAD tool. Superlog will be really useful Superlog will be really useful

someday.someday.

Page 19: 0xf1d0 Interim Review

shuma’s Wish Listshuma’s Wish List Perfect communicationPerfect communication

When people need help, they say so.When people need help, they say so. When people think others aren’t When people think others aren’t

performing, they say so.performing, they say so. When people are being lazy, they say When people are being lazy, they say

so.so.

Page 20: 0xf1d0 Interim Review

jsmolens+545’s Most jsmolens+545’s Most Important Technical Important Technical LessonsLessons

When in doubt, give it dirty looks.When in doubt, give it dirty looks.

Page 21: 0xf1d0 Interim Review

jsmolens+545’s Codesign jsmolens+545’s Codesign Lessons LearnedLessons Learned

I believe that there I believe that there shouldshould be a be a universal code sign, so that people universal code sign, so that people know when code is nearby.know when code is nearby.

Page 22: 0xf1d0 Interim Review

jsmolens+545’s CAD Tools jsmolens+545’s CAD Tools Lessons LearnedLessons Learned

SystemC is the best CAD tool there SystemC is the best CAD tool there has been and will ever be.has been and will ever be.

Code should Code should alwaysalways be self- be self-commentingcommenting

Page 23: 0xf1d0 Interim Review

jsmolens+545’s Wish Listjsmolens+545’s Wish List I wish I had more groups like I wish I had more groups like

0xf1d0.0xf1d0.