Packaging Roadmap:

The impact of miniaturization

Bob Pfahl, iNEMICelestica-iNEMI

Technology ForumMay 15, 2007

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The Challenges for the Next DecadeThe Challenges for the Next Decade• Addressing the consumer experience using the converged

digital technology base• Adopting to changing industry structure• Creating new product markets with social value

• Energy

• Healthcare

• Security

• Closing technology gaps

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The End of Semiconductor ScalingThe End of Semiconductor Scaling

• The anticipated end to semiconductor scaling will create a major technology shift in the industry:

• Implementation of advanced, non-classical CMOS devices with enhanced drive current

• Identification, selection, and implementation of advanced devices (beyond-CMOS)

• Increased need for improved cooling• Potential need for high speed optical communications • Innovative packaging for:

– Nano size devices– Hetro systems

• Innovation must begin today to meet these needs

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• Active Device Technology

• Thermal Management

• Communications Bandwidth

• Design and Simulation Tools

• Sustainability Metrics

• Next Generation Packaging Technology

Six Identified Strategic GapsSix Identified Strategic Gaps

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Active Device TechnologyActive Device Technology

• Implementation of advanced, non-classical CMOS devices with enhanced drive current

• Identification, selection, and implementation of advanced devices (beyond-CMOS)

• Device technology drives the following strategic system gaps

Multi-wall carbon nanotubes (NanoDynamics Inc.)

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Thermal ManagementThermal Management

• Increased need for improved cooling • Improved materials and design concepts• Focus is on local hot spots• Must design from device to system level

BN coated with Al203 (ALD Nanosolutions Inc)

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Communications BandwidthCommunications Bandwidth

• Copper?• RF?• Optical?

• Where?• When?• How Fast?• At what cost?

The 2007 Roadmap does not provide guidance

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Sustainability Metrics Sustainability Metrics

• Development & implementation of scientific methodologies:

– Assess true environmental impacts of materials

– Potential trade-offs for alternatives

• Develop a common, straightforward definition of sustainability

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Design and Simulation ToolsDesign and Simulation ToolsDesign & simulation tools are main roadblocks to more rapid

introduction of new technologies:– Mechanical & reliability modeling

– Thermal & thermo-fluid simulation

– Co-design of mechanical, thermal & electrical performance of the entire chip, package & associated heat removal structures

– Simulation tools for nano devices & materials

– Improved design tools for emerging technologies like embedded passives & optoelectronic PWBs

– Integrated design & simulation tools (circuit, EM, thermal, mechanical, manufacturing, etc.) for higher functionality in mixed-mode wireless chips & modules

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Next Generation Packaging TechnologyNext Generation Packaging Technology

Source: Professor Dr. Reichl, Fraunhofer IZM, Berlin Germany

Innovative Miniaturized Packaging

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Progress is Exceeding Roadmap ForecastProgress is Exceeding Roadmap Forecast

• 3D packaging– Techniques for 3D packaging are proliferating

• Flexible/wearable electronics• Wafer thinning• Wafer level packaging• System level integration in package

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Major ChallengesMajor Challenges

• Handling for ultra-thin die• Cost targets for new package types• Co-design tools for SiP, 3D packaging, TSV, etc.• Handling increasing thermal density (particularly

for 3D packaging)• Incorporation of new materials• Signal integrity for complex SiP

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• Packaging has become the limiting element in system cost and performance

• The assembly and packaging role is expanding to include system level integration functions.

• As traditional Moore’s law scaling become more difficult innovation in assembly and packaging can take up the slack.

Packaging is now a limiting factor but it is Packaging is now a limiting factor but it is enabling for more than Mooreenabling for more than Moore

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Interacting with people and environmentNon-digital content System-in-Package (SiP)

MooreMoore’’s Law Scaling Cannot Maintain the Pace of Progresss Law Scaling Cannot Maintain the Pace of Progress

Beyond CMOS

Information Processing Digital content System-on-Chip (SOC)

BiochipsSensorsActuators

HVPowerAnalog/RF Passives

More than Moore : Functional Diversification

130nm

90nm

65nm

45nm

32nm

Λ...22nm

Mor

e M

oore

: Sc

alin

gn

Combine SOC & SiP :

Higher Valu

e Sys

tem

Baseline CMOS: CPU, Memory, Logic

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System IntegrationSystem Integration

Cos

t / fu

nctio

n Ti

me

to m

arke

t

System complexity

System on Chip

SiP and 3D PackagingMEMS

Bio-InterfacePower supply

Source: Fraunhofer IZM

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SystemSystem--inin--Package DefinitionPackage Definition

System in Package (SiP) is a combination of multiple active electronic components of different functionality, assembled into a single unit, that provides multiple functions associated with a system or sub-system.

A SiP may optionally contain passives, MEMS, optical components and other packages and devices.

Note that this definition rules out stacked memory die. However, many of the technology drivers are the same.

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SiP SiP -- Situation AnalysisSituation Analysis

• Market: In 2004, 1.89 Billion SiPs were assembled. By 2008, this number is expected to reach 3.25 Billion, growing at an average rate of about 12% per year.

• Technology: SiP applications have become the technology driver for small components, packaging, assembly processes and for high density substrates.

• Growth: System-in-Package (SiP) has emerged as the fastest growing packaging technology segment although still representing a relatively small percentage of the unit volume.

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Horizontal Placement

StackedStructure

Interposer Type

Interposer-less Type

Wire Bonding Type Flip Chip Type

Wire Bonding Type

Wire Bonding +Flip Chip Type Flip Chip Type

Terminal Through Via Type

Source: 20030710 K. Nishi, Hitachi, JEITA, Revised by H. Utsunomiya

Embedded StructureChip(WLP) Embedded + Chip on Surface Type

3D Chip EmbeddedType

WLP Embedded + Chip on Surface Type

Categories of SiPCategories of SiP

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Source: Fraunhofer IZM

Packages may include:Sub-system packages Stacked thin packages containing passives and active chipsMechanical, optical and other non electrical functionsComplete systems or sub-systems with embedded componentsBare dieSoC

SiP may include SoC and other traditional packagesSiP: MultiSiP: Multi--level System Integrationlevel System Integration

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Wafer Wafer Level Level SiP SiP -- VisionVision

MEMSEnergy source

ASIC +

memories

Embedded passives

Cooling

MEMSEnergy source

ASIC +

memories

Embedded passives

Cooling

Source: LETI

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3D Stacked Die Package3D Stacked Die Package

Die thickness : 60 umSubstrate (BT) thickness : 130 umSolder ball Stand-off : 50 um

Substrate Base Substrate Base SiPSiP ( up to 7/ 8 die)( up to 7/ 8 die)

Die thickness : 60 umSubstrate (BT) thickness : 130 umSolder ball Stand-off : 50 um

Substrate Base Substrate Base SiPSiP ( up to 7/ 8 die)( up to 7/ 8 die)

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Projection for stacked die SiP packagesProjection for stacked die SiP packages2014 through 20202014 through 2020

Low cost/handheld (# die / stack) 14 14 15 15 16 16 17

High performance (# die / stack) 5 5 6 6 6 7 7

Low cost/handheld (# die / SiP) 15 15 16 16 17 17 18

Limited by thermal density

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SiP presents new Design Challenges for signal integrity, SiP presents new Design Challenges for signal integrity, power integrity and shieldingpower integrity and shielding

• Signal integrity for high density interconnect • Cross talk• Impedance discontinuities (reflections)• Timing skew• Parasitic capacitance, resistance and inductance in long

traces (inductance change for each layer for wire bonded stacked die)

• Power integrity• Voltage drop for high speed signals (lead and trace

inductance limits power delivery)• Ground noise due to high frequency current variations

• Shielding• Radiated noise within the package at high frequency• External electromagnetic noise sources

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Interconnect Challenges for Complex SiPsInterconnect Challenges for Complex SiPs

Die

MEMS

Passives

RF

Fluidics

Optics

Bio/organic

3D SiP

Evolutionary and revolutionary interconnect technologies are needed to enable the migration of microsystems from conventional state-of-art to 3D SiP.

New circuit elements and components place expanded demands on the environment provided by the package

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Potential Solutions for Interconnect ChallengesPotential Solutions for Interconnect Challenges

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Many variations of SiP package interconnect are in Many variations of SiP package interconnect are in use or in development todayuse or in development today

POP (WB Type)

POP (FC Type + Interposer)

POP (Film Type)

POP (only for Memory)

PIP - Molded PIP - Spacer

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Interconnect Requirements may be satisfied by Interconnect Requirements may be satisfied by Wave Guide Optical SolutionsWave Guide Optical Solutions

Waveguide

Solder bump

Die

Mirror

VCSEL/PD

Substrate

Polymer pin

SubstrateSubstrate

Lens

Substrate Substrate

Fiber

Board-level integrated optical devices Fiber-to-the-chip

Quasi free-space optical I/O

Lens assisted quasi free-space optical I/O

Surface-normal optical waveguide I/O

Opticalsource/PD

Examples of guided wave optical interconnects for chip-to-chip interconnection.

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Low k ILD may Require Improved Underfill or Low k ILD may Require Improved Underfill or Compliant I/O connectionsCompliant I/O connections

Si die Si die

The use of compliant electrical I/O can potentially eliminate the need for underfill reducing cost and processing complexity as I/O density rises.

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SiP Presents New Challenges for Thermal ManagementSiP Presents New Challenges for Thermal Management

• High performance generates high thermal density• Heat removal requires much greater volume than the

semiconductor– Increased volume means increased wiring length causing

higher interconnect latency, higher power dissipation, lower bandwidth, and higher interconnect losses

– These consequences of increased volume generates more heat to restore the same performance

• Projection for 14nm node– Power density >100W/cm2 – Junction to ambient thermal resistance <0.2degrees C/W

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ThermofluidicThermofluidic Heat Sinks may be the SolutionHeat Sinks may be the Solution

Conventional thermal Interconnects

Back-side integratedfluidic heat sink and Back and front-side inlets/outlets

Thermal interface Material

Back-side integratedfluidic heat sink using TIM and inlets/outlets

tube

Die

fluidic I/O

Examples of thermofluidic heat-sink integration with CMOS technology.

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Test Challenges of SiPTest Challenges of SiP

• Test cost• BIST and other embedded test

approaches• Thermal management• Test access• Contactor/ connection issues• Single chip testing in SiP

configurations• Time to market

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iNEMI Response to Packaging GapsiNEMI Response to Packaging Gaps

• Minaturization Focus Area− Board and System Manufacturing

Test TIG − Thermal Management TIG− SIP TIG

−Reliability protocols− Field failure Pareto

− Board Assembly TIG−Warm assembly−Nano solder

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• Packaging has become the limiting element in system cost and performance − Does not scale like silicon− Off chip speed limited by interconnect

• The Assembly and packaging role is expanding to include system level integration functions.− Cooling− Embedded passive/active devices

• Assembly & packaging can take up the slack− 3D packaging− Wafer level SiP

Packaging is now a limiting factor but it is Packaging is now a limiting factor but it is enabling for more than Mooreenabling for more than Moore

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www.inemi.orgEmail contacts:

Jim McElroy jmcelroy@inemi.org

Bob Pfahlbob.pfahl@inemi.org