#04-2020-1002-119 midterm review i · three variable maps concept p2.4 k-map • number of squares...
TRANSCRIPT
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02.07.20 11:22CSCI 150 Introduction to Digital and Computer
System Design Midterm Review I
Jetic Gū2020 Summer Semester (S2)
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Overview• Focus: Review
• Architecture: Combinational Logic Circuit
• Textbook v4: Ch1-4; v5: Ch1-3
• Core Ideas:
1. Digital Information Representation (Lecture 1)
2. Combinational Logic Circuits (Lecture 2)
3. Combinational Functional Blocks, Arithmetic Blocks (Lecture 3)
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Lecture 1: Digital Information Representation
Summary
P1 Digital Rep.
Analog vs Digital circuits; Modern computer architectures; Embedded systems;Number Systems; Conversions;
Arithmetic Operations; Alphanumeric Codes
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Analog vs Digital circuits• Digital Circuits
• Process digital signals
• Current/Voltage represent discrete logical and numeric values
Concep
t
P1.1 Digital Rep.
• Analog Circuits
• Process analog signals
• Current/Voltage vary continuously to represent information
-1
-0.5
0
0.5
1
0
0.25
0.5
0.75
1
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CPU
Von Neumann ArchitectureA very rough example
Demo
P1.1 Digital Rep.
1. Von Neumann Architecture
Input/Output devices
Control Unit
Datapath
Memory
also called arithmetic unit, logical unit, etc.
Calculate 1+1: X1: 1 (00010001) X2: 1 (00100001) X3: X1+X2 (01110110)
M1: 1 (00000001)
1+1=2
M3: 2 (00000010)
CPU exe.M2: 1 (00000001)
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Computer
Concep
t
P1.1 Digital Rep.
1. Von Neumann Architecture
• Input/Output devices
• Interaction (Mouth, hands and feet, eyes, etc.)
• CPU + Memory
• Processing information, thinking (Brain, short-term memory)
• Storage?
• Part of I/O devices (Books, long-term memory)
What’s it like compared to a human?
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Embedded Systems
Concep
t
P1.1 Digital Rep.
• Similar to computers: processes information
• Difference
• Function is usually simpler, and very very specific
• Not programmable
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Decimal System
• Numbers as strings of digits, each ranging from 0-9
• The decimal system is of base(radix) 10
Review
P1.2 Number Systems
7 2 4 0 5.7 2 4 0 52 1 0 −1−22 1 0 −1−2
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= 7 × 102 + 2 × 101 + 4 × 100 + 0 × 10−1 + 5 × 10−2
Decimal System
• Numbers as strings of digits, each ranging from 0-9
• The decimal system is of base(radix) 10
Review
P1.2 Number Systems
7 2 4 0 5.
7 2 4 0 52 1 0 −1−2
2 1 0 −1 −2
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Numbers of base N
• Default base: 10
• When there are numbers represented in different bases, attach base
• Decimal: 754.05 -> (754.05)10
• e.g. Base 5: (432.1)5 = ?
Concep
t
P1.2 Number Systems
= 4 × 52 + 3 × 51 + 2 × 50 + 1 × 5−1 = (117.2)10
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Binary Systems in Computers
• Every 8bit is called a Byte
• 1,024 = 210 is called K (Kilo)
• 1,024 x 1,024 = 220 is called M (Mega)
• 1,024 x 1,024 x 1,024 = 240 is called G (Giga)
• Tera, Peta, Exa, Zetta, Yotta
Concep
t
P1.2 Number Systems
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Binary Systems in Computers
• What is the difference between MBps and Mbps?
• MegaBytes per second vs MegaBits per second
• 8x difference!
Concep
t
P1.2 Number Systems !
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Octal and Hexadecimal Systems
• Octal: base 8
• digits: 0-7
• Hexadecimal: base 16
• digits: 0-9, A-F (10-15)
Concep
t
P1.2 Number Systems
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Conversions
• Binary-to-Octal: 3bits per octal digitHexadecimal: 4bits per hexa digitDecimal: use the chart
• Decimal-to-Binary: use the chartOct/Hex: do binary first
Concep
t
P1.2 Number Systems
10 9 8 7 6 5 4 3 2 1
1024 512 256 128 64 32 16 8 4 2
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Arithmetics
• The same as decimal (mostly)
•
Concep
t
P1.3 Arithmetics
0010+0011
0101
0101−0011
0010Example (binary)
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Arithmetics
Demo
P1.3 Arithmetics
OCTAL Multiplication
00762× 00054
046723710043772
5 × 2 = 125 × 6 + 1 = 375 × 7 + 3 = 46
Octal Octal Decimal
. . .
10 = (12)831 = (37)838 = (46)8
. . .
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Signed & Unsigned Integers
• Unsigned 8bit:
• (11111111)2 = 255
• Signed 8bit (only in digital circuits):
• 127 -> '01111111'
• -127 -> '11111111'
Concep
t
P1.4 Representations
10001111First digit: • 0 for positive • 1 for negative
(binary, 8bit, signed)
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Signed & Unsigned Integers
• Unsigned 8bit integer: 0 - 255
• Signed 8bit integer: -128 - 127
• Unsigned 32bit integer: 0 - 4,294,967,295
• Signed 32bit integer: -2,147,483,648 - 2,147,483,647
• Unless otherwise specified, treat as unsigned
Concep
t
P1.4 Representations
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Binary Coded Decimal
• Decimal numbers, each digit represented in 4bit binary, but separately
• 185 = (0001 1000 0101)BCD = (10111001)2
• Used in places where using decimals directly is more convenient, such as digital watches etc.
Concep
t
P1.4 Representations
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ASCII
Demo
P1.4 Representations
• American Standard Code for Information Interchange
• Assign each character with a 8bit binary code (e.g. '0'-'9', 'A'-'Z', 'a'-'z')
• The first bit is always 0
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Parity CodeP1.4 Representations
Demo
• For error detection in data communication
• e.g. resulting from packet loss or other forms of interference
• One parity bit for n-bits
• An extra even parity bit: whether the number of 1s is not even
• An extra odd parity: whether the number of 1s is not odd
• Can be placed in any fixed position
• Does it always work?
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Parity CodeP1.4 Representations
Demo
Original 7bits with Even parity with Odd parity
1000001 01000001 11000001
1010100 11010100 01010100
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Circuits
• Circuits
• Digital and Analog
• Integrated systems
• Von Neumann computers
• Embedded systems
Review
P1.5 Lect 1 Summary
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Number Systems
• Number systems of base N
• Binary systems
• Octal and Hexadecimal systems
• Arithmetics
Review
P1.5 Lect 1 Summary
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Number Systems in DC
• Bit, Byte, Representation ranges
• Signed and Unsigned Binary Integers
• BCD, ASCII, UTF8
• Parity bit
Review
P1.5 Lect 1 Summary
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Digital to Analog Conversion
• Frequency: number of cycles per second
• Sample rate: number of samples per unit time
• Bitrate: number of bits per second
Review
P1.5 Lect 1 Summary
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Lecture 2: Combinational Logic Circuits
Summary
P2 Logic Circuits
Logic Gates; Boolean Algebra; Minterm/Maxterm; K-Map; Some Other Gate Types
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First 3 Gates
Concep
t
P2.1 Logic Gates
Z = X ⋅ YXY
Z = X + YXY
Z = XX
AND Gate
OR Gate
NOT Gate
Input Output
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Truth Table
Example
P2.1 Logic Gates
Truth Table
0 0 0
0 1 1
1 0 1
1 1 1
XY Z
ZYX = (X ⋅ Y) + (X + Y)
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Basic Identities• Boolean Algebra solving
• Identify rules applicable to the expression
• Apply rules that can help you simplify the expression
• Simplification: reducing the number of variables and operators in an expression without changing it’s truth table values
• Atomic element: an element that can’t have the number of its variables and operators reduced any further
Concep
t
P2.2 Boolean Algebra
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Basic Identities
1.
2.
3.
4.
5.
X + 0 = X
X ⋅ 1 = X
X + 1 = 1
X ⋅ 0 = 0
X + X = X
Concep
t
P2.2 Boolean Algebra
6.
7.
8.
9.
X ⋅ X = X
X + X = 1
X ⋅ X = 0
X = X
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Basic Identities• Communicative
10.
11.
• Associative
12.
13.
X + Y = Y + X
XY = YX
X + (Y + Z) = (X + Y) + Z
X(YZ) = (XY)Z
Concep
t
P2.2 Boolean Algebra
• Distributive
14.
15.
• DeMorgan’s
16.
17.
X(Y + Z) = XY + XZ
X + (YZ) = (X + Y)(X + Z)
X + Y = X ⋅ Y
X ⋅ Y = X + Y
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Basic Identities
A.
B.
C.
X + XY = X
XY + XY = X
X + XY = X + Y
Samples
P2.2 Boolean Algebra
D.
E.
F.
X(X + Y) = X
(X + Y)(X + Y) = X
X(X + Y) = XY
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Complementation
• : complement (invert) representation for a function , obtained from an interchange of 1s to 0s and 0s to 1s for the values of in the truth table
• Apply DeMorgan’s Rule
16.
17.
F FF
X1 + X2 + . . . + Xn = X1 ⋅ X2 ⋅ . . . ⋅ Xn
X1 ⋅ X2 ⋅ . . . ⋅ Xn = X1 + X2 + . . . + Xn
Concep
t
P2.2 Boolean Algebra
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Algebraic Manipulation
Difficulty: Simple
Simplify the following expressions
•
•
X ⋅ Y + XYZ + XY
X + Y(Z + X + Z)
Exerci
se
P2.2 Boolean Algebra
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Algebraic Manipulation
Difficulty: Mid
Simplify the following expressions
•
•
WX(Z + YZ) + X(W + WYZ)
(AB + AB)(CD + CD) + AC
Exerci
se
P2.2 Boolean Algebra
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Algebraic Manipulation
Difficulty: Mid
Simplify the following expressions
•
•
A ⋅ C + ABC + BC
A + B + C ⋅ ABC
Exerci
se
P2.2 Boolean Algebra
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Algebraic Manipulation
Difficulty: Mid
Simplify the following expressions
•
•
ABC + AC
A ⋅ BD + A ⋅ CD + BD
Exerci
se
P2.2 Boolean Algebra
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Algebraic Manipulation
Difficulty: HARDCORE
Prove the identity of each of the following Boolean equations
•
•
•
ABC + BC ⋅ D + BC + CD = B + CD
WY + WYZ + WXZ + WXY = WY + WXZ + XYZ + XYZ
AD + AB + CD + BC = (A + B + C + D)(A + B + C + D)
Exerci
se
P2.2 Boolean Algebra
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Standard Forms
• Equivalent expressions can be written in a variety of waysStandard forms: typical such ways that incorporates some unique characteristics -> simplify the implementation of these designs
• Product terms (AND terms): e.g. Literals with inverts connected through only AND operators
• Sum terms (OR terms): e.g. Literals with inverts connected through only OR operators
XYZ
X + Y + Z
Concep
t
P2.3 Standard Forms
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Minterms and Maxterms
• MintermProduct term; Contains all variables; Has only one Positive row in the truth table
Concep
t
P2.3 Standard Forms
XY
X Y
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
m0 = XY m1 = XY m2 = XY m3 = XY(00)2=0
(01)2=1
(10)2=2
(11)2=3
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Minterms and Maxterms
• MaxtermSum term; Contains all variables; Has only one Negative row in the truth table
Concep
t
P2.3 Standard Forms
X Y
0 0 0 1 1 1
0 1 1 0 1 1
1 0 1 1 0 1
1 1 1 1 1 0
M3 = X + YM2 = X + YM1 = X + YM0 = X + Y
Mi = mi
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Minterms and Maxterms• e.g.
• Sum of Minterms
• e.g.
• Product of Maxterm
• e.g.
M3 = X + Y + Z = XYZ = m3
F = XYZ + XYZ + XYZ + XYZ = m0 + m2 + m5 + m7= Σm(0,2,5,7)
F = (X + Y + Z)(X + Y + Z)(X + Y + Z)(X + Y + Z)= M0M2M5M7= ΠM(0,2,5,7)
Concep
t
P2.3 Standard Forms
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Two Variable Maps
Concep
t
P2.4 K-Map
2-4 / Two-Level Circuit Optimization 63
than sum- of- products and product- of- sums, the gate- input count must be deter-mined directly from the implementation.
Regardless of the cost criteria used, we see later that the simplest expression is not necessarily unique. It is sometimes possible to !nd two or more expressions that satisfy the cost criterion applied. In that case, either solution is satisfactory from the cost standpoint.
Map Structures
We will consider maps for two, three, and four variables as shown in Figure"2-12. The number of squares in each map is equal to the number of minterms in the corre-sponding function. In our discussion of minterms, we de!ned a minterm mi to go with the row of the truth table with i in binary as the variable values. This use of i to
(a) (b)
0
1
0 1Y
X
X Y X Y
X YX Y
(c) (d)
ZX
ZX
0
6 4
13
57
2
X Z
02
8 10
1 3911
(f)(e)
00
01
00 01YZ
WX
Y
Z
W
11 10
11
10
X
X Z
0 1
2 3 X
Y
0
1
0 1Y
X
Y
X
Z
0 1 3 2
4 5 7 6
YZ
X
0
00 01 11 10
1
1 3 2
4 5 7 6
8 9 1011
12 13 1415
0
FIGURE!2-12Map Structures
M02_MANO0637_05_SE_C02.indd 63 23/01/15 1:47 PM
• Number of squares in each map is equal to the number of minterms for the same number of variables, light blue digit above is the index (of minterm)
• Two squares are adjacent if they only differ in one variable
• Binary value inside at each position indicates the truth table value for that term
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Three Variable Maps
Concep
t
P2.4 K-Map
• Number of squares in each map is equal to the number of minterms for the same number of variables, light blue digit above is the index (of minterm)
• Two squares are adjacent if they only differ in one variable
• Binary value inside at each position indicates the truth table value for that term
2-4 / Two-Level Circuit Optimization 63
than sum- of- products and product- of- sums, the gate- input count must be deter-mined directly from the implementation.
Regardless of the cost criteria used, we see later that the simplest expression is not necessarily unique. It is sometimes possible to !nd two or more expressions that satisfy the cost criterion applied. In that case, either solution is satisfactory from the cost standpoint.
Map Structures
We will consider maps for two, three, and four variables as shown in Figure"2-12. The number of squares in each map is equal to the number of minterms in the corre-sponding function. In our discussion of minterms, we de!ned a minterm mi to go with the row of the truth table with i in binary as the variable values. This use of i to
(a) (b)
0
1
0 1Y
X
X Y X Y
X YX Y
(c) (d)
ZX
ZX
0
6 4
13
57
2
X Z
02
8 10
1 3911
(f)(e)
00
01
00 01YZ
WX
Y
Z
W
11 10
11
10
X
X Z
0 1
2 3 X
Y
0
1
0 1Y
X
Y
X
Z
0 1 3 2
4 5 7 6
YZ
X
0
00 01 11 10
1
1 3 2
4 5 7 6
8 9 1011
12 13 1415
0
FIGURE!2-12Map Structures
M02_MANO0637_05_SE_C02.indd 63 23/01/15 1:47 PM
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Four Variable Maps
Concep
t
P2.4 K-Map
2-4 / Two-Level Circuit Optimization 63
than sum- of- products and product- of- sums, the gate- input count must be deter-mined directly from the implementation.
Regardless of the cost criteria used, we see later that the simplest expression is not necessarily unique. It is sometimes possible to !nd two or more expressions that satisfy the cost criterion applied. In that case, either solution is satisfactory from the cost standpoint.
Map Structures
We will consider maps for two, three, and four variables as shown in Figure"2-12. The number of squares in each map is equal to the number of minterms in the corre-sponding function. In our discussion of minterms, we de!ned a minterm mi to go with the row of the truth table with i in binary as the variable values. This use of i to
(a) (b)
0
1
0 1Y
X
X Y X Y
X YX Y
(c) (d)
ZX
ZX
0
6 4
13
57
2
X Z
02
8 10
1 3911
(f)(e)
00
01
00 01YZ
WX
Y
Z
W
11 10
11
10
X
X Z
0 1
2 3 X
Y
0
1
0 1Y
X
Y
X
Z
0 1 3 2
4 5 7 6
YZ
X
0
00 01 11 10
1
1 3 2
4 5 7 6
8 9 1011
12 13 1415
0
FIGURE!2-12Map Structures
M02_MANO0637_05_SE_C02.indd 63 23/01/15 1:47 PM
• Number of squares in each map is equal to the number of minterms for the same number of variables, light blue digit above is the index (of minterm)
• Two squares are adjacent if they only differ in one variable
• Binary value inside at each position indicates the truth table value for that term
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K Map Optimisation
Concep
t
P2.4 K-Map
• Step 1: Enter the values
• Step 2: Identify the set of largest rectangles in which all values are 1, covering all 1s
• Step 3: Read off the selected rectangles. If rectangle has odd length edges (excluding 1), split
F(X, Y, Z) = Σm(0,1,2,3,4,5)
1
1
1
1
1 1
= X + Y
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XOR Gate
Concep
t
P2.5 Other Gates
XOR GateExclusive-OR Z = X ⊕ YX
YXOR Truth Table
0 0 0
0 1 1
1 0 1
1 1 0
Z = X ⊕ YYX= XY + XY
•
•
•
X ⊕ 0 = X
X ⊕ X = X
X ⊕ Y = X ⊕ Y
•
•
•
X ⊕ 1 = X
X ⊕ X = 1
X ⊕ Y = X ⊕ Y
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XOR Gate
Concep
t
P2.5 Other Gates
•
•
•
X ⊕ 0 = X
X ⊕ X = X
X ⊕ Y = X ⊕ Y
•
•
•
X ⊕ 1 = X
X ⊕ X = 1
X ⊕ Y = X ⊕ Y
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N-Gates
Concep
t
P2.5 Other Gates
NAND Gate Z = X ⋅ YXY
Z = XXNOT Gate
NOR Gate Z = X + YXY
XNOR Gate Z = X ⊕ YXY
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Boolean AlgebraI. AND, OR, NOT Operators and Gates
• Simple digital circuit implementation
• Algebraic manipulation using Binary Identities
II. Standard Forms
• Minterm & Maxterm
• Sum of Products & Product of Sums
III. Optimisation Using K-Map (For 2,3,4 Variables)
IV. XOR, NAND, NOR, XNOR
Review
P2.6 Lect 2 Summary
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Lecture 3: Combinational Logic Design
Summary
P3 Comb. Design
5 Steps Systematic Design Procedures; Functional Blocks; Decoder, Enabler, Multiplexer; Arithmetic Blocks
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Systematic Design Procedures1. Specification: Write a specification for the circuit
2. Formulation: Derive relationship between inputs and outputs of the systeme.g. using truth table or Boolean expressions
3. Optimisation: Apply optimisation, minimise the number of logic gates and literals required
4. Technology Mapping: Transform design to new diagram using available implementation technology
5. Verification: Verify the correctness of the final design in meeting the specifications
Concep
t
P3.1 Comb. Design
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Hierarchical Design
• "divide-and-conquer"
• Circuit is broken up into individual functional pieces (blocks)
• Each block has explicitly defined Interface (I/O) and Behaviour
• A single block can be reused multiple times to simplify design process
• If a single block is too complex, it can be further divided into smaller blocks, to allow for easier designs
Concep
t
P3.1 Comb. Design
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Value-Fixing, Transferring, and Inverting
Concep
t
P3.2 Elementary Func.
① Value-Fixing: giving a constant value to a wire
• ; ;
② Transferring: giving a variable (wire) value from another variable (wire)
• ;
③ Inverting: inverting the value of a variable
•
F = 0 F = 1
F = X
F = X
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Vector Denotation
Concep
t
P3.2 Elementary Func.
④ Multiple-bit Function
• Functions we’ve seen so far has only one-bit output: 0/1
• Certain functions may have -bit output
• , each is a one-bit function
• Curtain Motor Control Circuit:
n
F(n − 1 : 0) = (Fn−1, Fn−2, . . . , F0) Fi
F = (FMotor1, FMotor2
, FLight)
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Taking part of the Vector
Concep
t
P1 Elementary Func.124 CHAPTER 3 / COMBINATIONAL LOGIC!DESIGN
least signi!cant bit, providing the vector F = (F3, F2, F1, F0). Suppose that F consists of rudimentary functions F3 = 0, F2 = 1, F1 = A, and F0 = A. Then we can write F as the vector (0, 1, A, A). For A = 0, F = (0, 1, 0, 1) and for A = 1, F = (0, 1, 1, 0). This multiple-bit function can be referred to as F(3:0) or simply as F and is imple-mented in Figure 3-8(a). For convenience in schematics, we often represent a set of multiple, related wires by using a single line of greater thickness with a slash, across the line. An integer giving the number of wires represented accompanies the slash as shown in Figure 3-8(b). In order to connect the values 0, 1, X, and X to the appropri-ate bits of F, we break F up into four wires, each labeled with the bit of F. Also, in the process of transferring, we may wish to use only a subset of the elements in F—for example, F2 and F1. The notation for the bits of F can be used for this purpose, as shown in Figure 3-8(c). In Figure 3-8(d), a more complex case illustrates the use of F3, F1, F0 at a destination. Note that since F3, F1, and F0 are not all together, we cannot use the range notation F(3:0) to denote this subvector. Instead, we must use a combi-nation of two subvectors, F(3), F(1:0), denoted by subscripts 3, 1:0. The actual nota-tion used for vectors and subvectors varies among the schematic drawing tools or HDL tools available. Figure 3-8 illustrates just one approach. For a speci!c tool, the documentation should be consulted.
Value !xing, transferring, and inverting have a variety of applications in logic design. Value !xing involves replacing one or more variables with constant values 1 and 0. Value !xing may be permanent or temporary. In permanent value !xing, the value can never be changed. In temporary value !xing, the values can be changed, often by mechanisms somewhat different from those employed in ordi-nary logical operation. A major application of !xed and temporary value !xing is in programmable logic devices. Any logic function that is within the capacity of the programmable device can be implemented by !xing a set of values, as illustrated in the next example.
EXAMPLE 3-4 Lecture-Hall Lighting Control Using Value Fixing
The Problem: The design of a part of the control for the lighting of a lecture hall speci!es that the switches that control the normal lights be programmable. There are to be three different modes of operation for the two switches. Switch P is on the po-dium in the front of the hall and switch R is adjacent to a door at the rear of the
0 F3
1 F2
A F1
A F0
(a)
0
1
A
A
1
2 34
F
0
(b)
4 2:1 F(2:1)2
F(c)
4 3,1:0 F(3), F(1:0)3
F(d)
FIGURE 3-8Implementation of Multibit Rudimentary Functions
M03_MANO0637_05_SE_C03.indd 124 23/01/15 1:51 PM
④ Multiple-bit Function
124 CHAPTER 3 / COMBINATIONAL LOGIC!DESIGN
least signi!cant bit, providing the vector F = (F3, F2, F1, F0). Suppose that F consists of rudimentary functions F3 = 0, F2 = 1, F1 = A, and F0 = A. Then we can write F as the vector (0, 1, A, A). For A = 0, F = (0, 1, 0, 1) and for A = 1, F = (0, 1, 1, 0). This multiple-bit function can be referred to as F(3:0) or simply as F and is imple-mented in Figure 3-8(a). For convenience in schematics, we often represent a set of multiple, related wires by using a single line of greater thickness with a slash, across the line. An integer giving the number of wires represented accompanies the slash as shown in Figure 3-8(b). In order to connect the values 0, 1, X, and X to the appropri-ate bits of F, we break F up into four wires, each labeled with the bit of F. Also, in the process of transferring, we may wish to use only a subset of the elements in F—for example, F2 and F1. The notation for the bits of F can be used for this purpose, as shown in Figure 3-8(c). In Figure 3-8(d), a more complex case illustrates the use of F3, F1, F0 at a destination. Note that since F3, F1, and F0 are not all together, we cannot use the range notation F(3:0) to denote this subvector. Instead, we must use a combi-nation of two subvectors, F(3), F(1:0), denoted by subscripts 3, 1:0. The actual nota-tion used for vectors and subvectors varies among the schematic drawing tools or HDL tools available. Figure 3-8 illustrates just one approach. For a speci!c tool, the documentation should be consulted.
Value !xing, transferring, and inverting have a variety of applications in logic design. Value !xing involves replacing one or more variables with constant values 1 and 0. Value !xing may be permanent or temporary. In permanent value !xing, the value can never be changed. In temporary value !xing, the values can be changed, often by mechanisms somewhat different from those employed in ordi-nary logical operation. A major application of !xed and temporary value !xing is in programmable logic devices. Any logic function that is within the capacity of the programmable device can be implemented by !xing a set of values, as illustrated in the next example.
EXAMPLE 3-4 Lecture-Hall Lighting Control Using Value Fixing
The Problem: The design of a part of the control for the lighting of a lecture hall speci!es that the switches that control the normal lights be programmable. There are to be three different modes of operation for the two switches. Switch P is on the po-dium in the front of the hall and switch R is adjacent to a door at the rear of the
0 F3
1 F2
A F1
A F0
(a)
0
1
A
A
1
2 34
F
0
(b)
4 2:1 F(2:1)2
F(c)
4 3,1:0 F(3), F(1:0)3
F(d)
FIGURE 3-8Implementation of Multibit Rudimentary Functions
M03_MANO0637_05_SE_C03.indd 124 23/01/15 1:51 PM
Output: (F2, F1)
Output: (F3, F1, F0)
124 CHAPTER 3 / COMBINATIONAL LOGIC!DESIGN
least signi!cant bit, providing the vector F = (F3, F2, F1, F0). Suppose that F consists of rudimentary functions F3 = 0, F2 = 1, F1 = A, and F0 = A. Then we can write F as the vector (0, 1, A, A). For A = 0, F = (0, 1, 0, 1) and for A = 1, F = (0, 1, 1, 0). This multiple-bit function can be referred to as F(3:0) or simply as F and is imple-mented in Figure 3-8(a). For convenience in schematics, we often represent a set of multiple, related wires by using a single line of greater thickness with a slash, across the line. An integer giving the number of wires represented accompanies the slash as shown in Figure 3-8(b). In order to connect the values 0, 1, X, and X to the appropri-ate bits of F, we break F up into four wires, each labeled with the bit of F. Also, in the process of transferring, we may wish to use only a subset of the elements in F—for example, F2 and F1. The notation for the bits of F can be used for this purpose, as shown in Figure 3-8(c). In Figure 3-8(d), a more complex case illustrates the use of F3, F1, F0 at a destination. Note that since F3, F1, and F0 are not all together, we cannot use the range notation F(3:0) to denote this subvector. Instead, we must use a combi-nation of two subvectors, F(3), F(1:0), denoted by subscripts 3, 1:0. The actual nota-tion used for vectors and subvectors varies among the schematic drawing tools or HDL tools available. Figure 3-8 illustrates just one approach. For a speci!c tool, the documentation should be consulted.
Value !xing, transferring, and inverting have a variety of applications in logic design. Value !xing involves replacing one or more variables with constant values 1 and 0. Value !xing may be permanent or temporary. In permanent value !xing, the value can never be changed. In temporary value !xing, the values can be changed, often by mechanisms somewhat different from those employed in ordi-nary logical operation. A major application of !xed and temporary value !xing is in programmable logic devices. Any logic function that is within the capacity of the programmable device can be implemented by !xing a set of values, as illustrated in the next example.
EXAMPLE 3-4 Lecture-Hall Lighting Control Using Value Fixing
The Problem: The design of a part of the control for the lighting of a lecture hall speci!es that the switches that control the normal lights be programmable. There are to be three different modes of operation for the two switches. Switch P is on the po-dium in the front of the hall and switch R is adjacent to a door at the rear of the
0 F3
1 F2
A F1
A F0
(a)
0
1
A
A
1
2 34
F
0
(b)
4 2:1 F(2:1)2
F(c)
4 3,1:0 F(3), F(1:0)3
F(d)
FIGURE 3-8Implementation of Multibit Rudimentary Functions
M03_MANO0637_05_SE_C03.indd 124 23/01/15 1:51 PM
Dimension
Selected Indices
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Enabler
Concep
t
P3.2 Elementary Func.
⑤ Enabler
• Transferring function, but with an additional signal acting as switchEN
EN X F
0 X 0
1 0 0
1 1 1
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Enabler
Concep
t
P3.2 Elementary Func.
⑤ Enabler
• Transferring function, but with an additional signal acting as switchEN
ENX
F ENX
F
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Decoder• -bit input, bits output
•
• Design: use hierarchical designs!
n 2n
Di = mi
Concep
t
P3.3 Adv. Func. Blocks
A1 A0 D0 D1 D2 D3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
3-5 / Decoding 129
each output. In the logic diagram in Figure 3-13(b), each minterm is implemented by a 2-input AND gate. These AND gates are connected to two 1–to–2-line decoders, one for each of the lines driving the AND gate inputs.
Large decoders can be constructed by simply implementing each minterm function using a single AND gate with more inputs. Unfortunately, as decoders become larger, this approach gives a high gate-input cost. In this section, we give a! procedure that uses design hierarchy and collections of AND gates to con-struct!any decoder with n inputs and 2n outputs. The resulting decoder has the same or a lower gate-input cost than the one constructed by simply enlarging each AND gate.
To construct a 3–to–8-line decoder (n = 3), we can use a 2–to–4-line decoder and a 1–to–2-line decoder feeding eight 2-input AND gates to form the minterms. Hierarchically, the 2–to–4-line decoder can be implemented using two 1–to–2-line decoders feeding four 2-input AND gates, as observed in Figure 3-13. The resulting structure is shown in Figure 3-14.
The general procedure is as follows:
1. Let k = n.
2. If k is even, divide k by 2 to obtain k/2. Use 2k AND gates driven by two decod-ers of output size 2k/2. If k is odd, obtain (k + 1)/2 and (k - 1)/2. Use 2k AND
AD0 ! A
D0
D1 ! A
D1
0 1 01 0 1
(a) (b)
A
FIGURE 3-12A 1–to–2-Line Decoder
A1
0011
A0
0101
D0
1000
D1
0100
D2
0010
D3
0001
(a)
(b)
A
D A1A0
A1A0
A1A0
A1A0D
D
D
1
A0
FIGURE 3-13A 2–to–4-Line Decoder
M03_MANO0637_05_SE_C03.indd 129 23/01/15 1:51 PM
3-to-8 Decoder
01234567
0
1
2
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Encoder
• Inverse operation of a decoder
• inputs, only one is giving positive input1
• outputs
2n
n
Concep
t
P3.3 Adv. Func. Blocks
1. In reality, could be less
A0
A1
A2
A0
A1
A2
3-to-8 Decoder
01234567
0
1
2
Octal-to-Binary
Encoder
01234567
0
1
2
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EncoderP3.3 Adv. Func. Blocks
Octal-to-Binary
Encoder
01234567
0
1
2
D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
Concep
t
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7
![Page 63: #04-2020-1002-119 Midterm Review I · Three Variable Maps Concept P2.4 K-Map • Number of squares in each map is equal to the number of minterms for the same number of variables,](https://reader034.vdocuments.mx/reader034/viewer/2022042418/5f340a7fafafab324a69292b/html5/thumbnails/63.jpg)
Priority Encoder
• Additional Validity Output
• Indicating whether the input is valid (contains 1)
• Priority
• Ignores if
V
D<i Di = 1
P3.3 Adv. Func. Blocks
Concep
t
Priority Encoder
0
1
2
3
0
1
V
![Page 64: #04-2020-1002-119 Midterm Review I · Three Variable Maps Concept P2.4 K-Map • Number of squares in each map is equal to the number of minterms for the same number of variables,](https://reader034.vdocuments.mx/reader034/viewer/2022042418/5f340a7fafafab324a69292b/html5/thumbnails/64.jpg)
Priority EncoderP3.3 Adv. Func. Blocks
Priority Encoder
0
1
2
3
0
1
V
Concep
t
D3 D2 D1 D0 A1 A0 V
0 0 0 0 0 0 0
0 0 0 1 0 0 1
0 0 1 X 0 1 1
0 1 X X 1 0 1
1 X X X 1 1 1
V = D3 + D2 + D1 + D0
A1 = D3 + D3D2 = D2 + D3
A0 = D3D2D1 + D3
= D2D1 + D3
![Page 65: #04-2020-1002-119 Midterm Review I · Three Variable Maps Concept P2.4 K-Map • Number of squares in each map is equal to the number of minterms for the same number of variables,](https://reader034.vdocuments.mx/reader034/viewer/2022042418/5f340a7fafafab324a69292b/html5/thumbnails/65.jpg)
Multiplexer
• Multiple -variable input vectors
• Single -variable output vector
• Switches: which input vectors to output
n
n
Concep
t
P3.3 Adv. Func. Blocks
n
n
…
n
n
01
I0
I1
S
Y