The Principles Of The Principles Of BB SSBoundaryBoundary--ScanScan

LLLesson 2Lesson 2October 2009

The Test ChallengeThe Test Challenge

Find the failures before your customers do!

More than 90% of the PCBs produced will contain at least one structural fault

Ref: Charles Robinson and Amit Verma, Teradyne Inc., APEX 2002

October 2009

The functional testing approachThe functional testing approachAdvantages

Exercises the product the way it will be used in the field functionallyExercises the product the way it will be used in the field functionally

Very effective at assuring quality standards are met

DisadvantagesDisadvantages

Test prepared manually, often requiring input from the design engineer

Faults found at functional test may be difficult to diagnose, requiring designer participation

Most factories have a bone-pile of boards that fail functional test

October 2009

The structural testing approachThe structural testing approachAdvantages

Tests are generated automatically, by intelligent software tools,Tests are generated automatically, by intelligent software tools, using an exhaustive list of the potential structural faults on the board

Detection and diagnosis of faults can be precise and to the pin level

Disadvantages

Intended to detect manufacturing faults only solder problems, incorrect parts, etc. (not design faults)

Only valuable if sufficient test point access is available Only valuable if sufficient test point access is available

October 2009

Traditional structural testingTraditional structural testingPotentially

defectivewire bond

Openunder BGA

Short topower or ground

ESDdamage

BGABGA

Power or

Inner board layersBridging

GND

In-circuit testing will have difficulty finding these types of faults

Inner board layers,blind vias

Bridgingfault

In circuit testing will have difficulty finding these types of faultsBoundary-scan can help!

October 2009

Test Finds Finds short,Detects

test coverage with boundary-scan

BGA

wire bond open,

s-a-0 or s-a-1ESD damage

BGATAP

Power orGND

Provides access toblind vias, inner layers

Finds solder bridgeunder BGA

FFixture is greatly simplified or eliminated

October 2009

Adopted in 1990 by the IEEE as Standard 1149.1

IEEE 1149.1 BoundaryIEEE 1149.1 Boundary--Scan StandardScan StandardAdopted in 1990 by the IEEE as Standard 1149.1

Prepared by the Joint Test Action Group (JTAG) Originally for testing boards and devices

1149.1 is an IC standard1149.1 is an IC standardSerial 4-wire (5th is optional) TAP interface That Provides Access To

Device I/O PinsDefines a set of operations outside the chips normal operation

Semiconductor manufacturer is responsible for:Designing device for compliance to the IEEE 1149.1 Standard

Many components are now Boundary-Scan compliantMany components are now Boundary Scan compliantMicroprocessors, CPLDs, ASICs, FPGAs, DSPs & MemoryFLASH Memory is programmable, via Boundary-Scan

Providing A Compliant BSDL fileProviding A Compliant BSDL file

October 2009

What is IEEE 1149.1 boundaryWhat is IEEE 1149.1 boundary--scan?scan? A chip level standard adopted A chip-level standard, adopted

by the IEEE in 1990 4 (or 5) added pins form the Test

Access Port (TAP) Additional logic inside the IC: scan

cells on I/Os, controller & registers

Data from the boundary-scan

IC Core

source (on TDI) can be loaded into the device

and read from the device pins on TDO

TDOTDI Bypass

Instruction Reg.TDO

Optional 5th line TRST active low asynchronous reset TMS

TCKController

ID Register

Every I/O on a compliant IC becomes a test point TRST

October 2009

IEEE 1149.1 ArchitectureIEEE 1149.1 Architecture

Internal

Core Logic

Shift-DRShift Bypass

Shift IR Identification

Bypass

TDI TDOShift IR Identification

Instruction

TAPTMSTCK

TDI TDO

ControllerTCK

October 2009

IEEE 1149.1 State MachineIEEE 1149.1 State MachineTest-Logic Data Register Instruction RegisterTest Logic

Reset

Run-TestIdle

SelectIR-scan

SelectDR-scan

1

0 1 1 1

00

0

Data Register Instruction Register

Capture-IR

Shift-IR

Capture-DR

Shift-DR

1

1

1

1

00

00

Exit1-IR

Pause-DR

Exit1-DR

Pause-IR

11

1

0

0

0

0

Exit2-IRExit2-DR

Update-DR Update-IR

1

1

1

1

00

TMS: 0,1

Update DR1 1 00

October 2009

The Instruction RegisterThe Instruction RegisterDecoded Output to

Selected Data Registers

Internal

core logic

Hold ElementsIdentification

Instruction

TAPcontroller

TMS

TCK

TDI TDOBypass

Decoder

TDI TDOTMS Clock-DR Shift RegisterTDITMS

TCK

TRST

TestAccess

Port

TAP

Clock-DRShift-DRUpdate-DRCapture-DRTCKClock-IRShift-IRUpdate-IR

0 1IR Length 2>

TRST(optional) controller Capture-IR

Select

October 2009

BoundaryBoundary--Scan InstructionsScan Instructions

Instruction Code Selected Data Register

Bypass/

111..11 Bypass (Initialized state)mandatorySample/Preload

Extest

Intest

000..00Boundary-ScanBoundary-Scan

Boundary-Scan

mandatory

IdcodeRunBistScan

Identification or BypassInternal BISTInternal Scan

optional

Usercode

ClampHighZ

Internal ScanIdentificationBypass: outputs from BS cellsBypass: outputs in High Z stateHighZ Bypass: outputs in High-Z state

October 2009

The BoundaryThe Boundary--Scan (DATA) RegisterScan (DATA) RegisterX-Bit Shift Register

A Data Register Selected by One Of The

Instructions:

- EXTEST

SAMPLE PRELOAD

Internal

core logic

- SAMPLE PRELOAD

- INTEST

- ????

TDI TDOBypass

Identification

Instruction

Parallel Input and/or Output TMSTCK

TAPcontroller

October 2009

Cell Types of the Boundary RegisterCell Types of the Boundary Register

TDI TDO

CELL CELLINPUT

CORE LOGIC

CELL

CELL

2-STATE OUTPUT

INPUT

CLOCK

CELL CELLLOGIC CELL

CELL

CELL

3-STATE OUTPUTCELLINTERNAL

BI-DIRECTIONAL

CELLCELL

October 2009

Bypass (DATA) RegisterBypass (DATA) RegisterOne Bit Shift Stage

Selected by BYPASS Instruction Internal

No Parallel Output

Captures a Hardwired 0

core logic

Identification

TDI TDOBypass

GShift-DR

Instruction

TAP

controller

TMS

TCK

_11 1DTDI

0

C DRTDO

C1Clock DR

October 2009

Identification RegisterIdentification RegisterMain Function: Identify the Device

32-Bit Shift Register

Selected by IDCODE Instruction

No Parallel Output

Captures a 32 Bit Hardwired Word

Internal

core logicCaptures a 32 Bit Hardwired Word

If No Identification Register

Is Present, The BYPASS Instruction Identification

TDI TDOBypass

Must be SelectedInstruction

TAPcontroller

TMS

TCK

**Part of infrastructure test

October 2009

Device identification code structureDevice identification code structure

Version Part Number Manufacturer 1

31 28 27 12 11 1 0

4 Bits 16 Bits 11 Bits 1 Bit

Compressed FormOf JEDEC Code

Manufacturers Own Coding

Version Code

GShift-DR

Of JEDEC CodeOwn Coding

_11 1D

0 / 1TDI

Clock DR

TDO

C1Clock DR

October 2009

Applying boundaryApplying boundary--scan to the PCBscan to the PCB Example of a PCBScan device #1 Example of a PCB

with one boundary-scan chain

Typically only a

Scan device #1

Scan device #2TDI

TDOTMS

TCK

T

A

P

Typically, only a fraction of the ICs need to be scan-compliant

TCK

Scan device #3

October 2009

Alternate partitioning (2 chains)Alternate partitioning (2 chains) Chains are testedScan device #1 Chains are tested

concurrently for max throughput with no loss of test

Scan device #1

Scan device #2TDI

TDOTMS

T

A

P

1

coverage

Up to 4 chains with single QuadPOD

TCK

Provides valuable design flexibility*

*To be discussed

Scan device #3

*To be discussed in DFT sectionTDI

TDOTMS

TCK

T

A

P

2

TCK

October 2009

TAP2D I/O

Board LevelBoard LevelApplicationsApplications Digital I/O

scan moduleApplications Applications

Testing

TAP1

uP

+

ClustersR

Connector Infrastructure Interconnections

TAP

FPGA

PLD

Memory A/D buses & control signals

P

R

SD

Flash memories

Programming

CPLDs, FPGAsSD

F

Cluster Cluster

F

Connector(w/ AutoWrite)

October 2009

Infrastructure Capture test Infrastructure Capture test TCKTCK

TMSTMS

Test logic reset

Select-DRRun-test/idle

Select-IRCapture-IR

Shift-IRExit-1

October 2009

BoundaryBoundary--Scan Test PrincipleScan Test PrincipleStage 1 Shift Data to Output cellStage 1 Shift Data to Output cell

1

core core0

1 0

October 2009

BoundaryBoundary--Scan Test PrincipleScan Test PrincipleStage 2 Update Data from Output Cell to NetStage 2 Update Data from Output Cell to Net

11

core core

1

0 0

October 2009

BoundaryBoundary--Scan Test PrincipleScan Test PrincipleStage 3 Capture Data from Net to Input cell

1 11

core core0 00

October 2009

Stage 4 Shift Captured Data OutBoundaryBoundary--Scan Test PrincipleScan Test Principle

Stage 4 Shift Captured Data Out

1

core core0

0 1

October 2009

Ieee 1149 4

Extensions to the IEEE 1149.1 StandardExtensions to the IEEE 1149.1 StandardIeee 1149.4 Released in 1999 Analog testing, voltage measurement and current driving

Drive and sense analog values via 2 additional pins and busses internal to the ICU / Up until now, very limited deployment/nonexistent

JTAG offers analog evaluation kits

Ieee 1149.6 Approved March 20, 2003 For high-speed AC-coupled nets and differential signaling

Ieee 1532Ieee 1532 Latest version: Dec. 11, 2002 Standardizes PLD programming among various vendors

Allows concurrent programming, mixed vendor chains BSDL files include the programming algorithms BSDL files include the programming algorithms

October 2009

The ShowThe Show

October 2009