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313 * TATF T TTTFFF29 F () * T TFTCache 58(2) -- *PAi() S[Ai]P lockPAi struct node { int A; //=0 int* S[MAX]; // } lock; (Fetch&increment) * Lock( plock, myAddress ) { myAddress = fetch&increment( plockA ); // while ( *(plockS[myAddress]) != 1 ); // }5658

63BARRIER(bar_name, p){ LOCK(bar_name.lock); if (bar_name.counter == 0) bar_name.flag = 0; mycount = bar_name.counter++; UNLOCK(bar_name.lock); if ( mycount == p ) { bar_name.counter = 0; bar_name.flag = 1; } else while (bar_name.flag == 0);}BARRIER(bar_name, p){ mysense = !(mysense); //initvalue=0 LOCK(bar_name.lock); mycount = bar_name.counter++; if ( mycount == p ) { UNLOCK(bar_name.lock); bar_name.counter = 0; bar_name.flag = mysense; } else { UNLOCK(bar_name.lock); while ( bar_name.flag != mysense ); }} * () CacheBusRdBusRd[]426363 (1) *(P) * ()(2) * ([]) Cache *(Cache) (3) */// *///7 PCacheSM Cache1 CacheI/O(DMA) PCache 2Cache *(PCache) (I/O) *() ()()7(P1P2) WTP2P1 WBP1P2 83 * P * () () MEM PMEM PMEM C P1 C Pn WR RWR P(/)8R1P0P1R2R4W3W3R4R3W2W2R5R1R49 *Cache PP P1121 *MEM 1) 2) 3)39:1)2)3R()

3P122 * * *PW(PW) PWRR(RR)R1P0P1W1W2R2W3R1R2W2R3W4R3 *R1P0P1W1W2S2W3S2R3W3S3W4S4R212PW RRS 13 Cache *Cache -- [] *Cache 2 *P 2 Cache 13Cache14 *Cache(V)--() Cache (I)Cache[]VI *CacheCache *VIPrWr/BusWBPrRd/PrWr/BusWBPrRd/BusRdBusWB/BusRd/BusWB/BusRd/A/BACacheB CPU *Cache/ PrRdPrWrCaInvd()BusRdBusWB1415MSI1(1)Cache * (M)Cache (S)Cache (I)Cache[]17CacheP0 CacheISIISSISMIIP1 CacheIISISISSIMIP2 CacheIIISISSSIIM1516(2) *CacheCPUPrRd()iiMPrWr()Cache *Cache/ PrRdPrWrCaInvd() BusRdBusWBBusRdX([+])CPUCachePrRdPrWrCaInvdCPUCacheBusRdBusRdXBusWB18(3) *PrRdIBusRd(M/S) (ISS/M) *PrWrS/IBusRdX(M) (I/S/MM)M *CaInvdMBusWB(S)(M/SI) *BusRd(M) (M/SS) *BusRdX(M) (M/SI) *BusWB19(4) PrRd/PrRd/MIPrRd/BusRdS FlushCache() BusRdXSICaInvd/BusWBCaInvd/BusRd/BusRd/FlushBusRdX/FlushBusRdX/25PrWr/(BusRdX+newPrWr)PrWr/(BusRdX+newPrWr)PrWr/1920 *PiP1 CacheuP2 CacheuP3 CacheuIIIP1uSIIBusRdP3uSISBusRdP3uIIMBusRdXP1uSISBusRdP3 CacheP2uSSSBusRd BusRdXBusRd(5) *SBusRdXBusUpgr() *PrWr20IBusRdX

23MESI(2)Cache (M)Cache (E)Cache (S)Cache (I)Cache[]CacheP0 CacheISSISEIIMIIP1 CacheISISSIEIIMIP2 CacheIISSSIIEIIM(1) MSIE() EPrWr24(3) *PrRdIBusRd(M/E/S) (IESE/S/M) (S) *PrWrS/IBusRdX(E) (I/E/S/MM) *CaInvdMBusWB(E/S)(M/E/SI) *BusRd(SM) (M/E/SS) *BusRdX(M) (M/E/SI) *BusWB26Dragon28(1) Cache(2)Cache (E)Cache (Sc)Cache(ScSc) (Sm)Cache (M)CacheCacheP0 CacheIEIIScScIScSmSmSmIScScIScScMIIP1 CacheIIEIScIScScIScScSmSmSmScIScIMIP2 CacheIIIEIScScScScIScScIScSmSmSmIIM26EMCacheScMESISSmMESIM27(3) *PrRd() *PrRdMissBusRdSc/E[S] *PrWrSc/SmBusUpd(E/M) (Sc/SmSm/M[S]E/MM) *PrWrMissBusRdSm/M(S) *CaInvdSm/MBusWB(E/Sc/Sm/MI) *BusRd(SSm/M) (E/ScScM/SmSm) *BusUpd()(S)(Sc/SmSc) *BusWB(Sc)PrRdMissCacheCachePrWrScSmPrWr

2729 * (/) (/)1 * () * 3134302 *() /kMEMk // //MEM / * MESIMSIMSI(SPrWrBusUpgr[BusRdX]) Cache MESIMSI(10%)MSI * 150% ()324Cache * () * () () * (23) *Cache 3234 Cache *Cache () * Cache * ()()(FIFO) *35Cache *MESI() *Cache *I/VM---- ()CPUCmdAddr(SRAM)DataSystem Bus361Cache *Cache * P--PCache (P) * (P)(M/E/S/I) --PBUS BUS --RAM ()382 2(1) *() *() -- =max{Cache} Cache = 1(M)Cache * =(max) Cache44 *Cache *Cache -- Cache CacheCache *L2$I/OL1$P1L2$L1$PnL2$I/OL1$P1L2$L1$Pn----44L1$L1$L2$45 * Cache(I$D$) *Cache Cache Cache Cache * CacheCache Cache 461 * -- Ln$L1$ L1$ *2 1Ln$L1$L1$ 2 L1$ * 1Ln$ 2Ln$ L1$MI Li$472 * * --P PrRdPrWrCaInvdPrUgrPrRdX CacheL1$L2$PrRdBusRdBusWB(M)(M)PrWrPrRdL1$L2$BusRdXBusWB(S)PrWr(S)(M)(M)PrWrPrRdXPrUgrL1$L2$BusWBPrWrSICaInvdMISIMI(M)(M)48 * --P BusRdBusRdXBusWB * // L1$L2$BusRdXBusRdMIMSBusRd(MI)MSMISBusRdXMIE/SIMI/E/SI Cache4849 *()1 * 123{I12}{I13}{I33}{I22}{I23}{I11}{I21}{I31}{I32}49()(/)50 * (--) 2 * * () (W)5051 *2 2 * ()1 *P P() *P *P *51522 *PP (loca) (Test&Set) * lock: t&s register, loca //loca1 bnz lock //(1) ret //(0) * unlock: st loca, #0 //0loca ret //54t&s[loca]reg1[loca]ZF=test reg,052564 *P P (Fetch&increment)(1)() -- *PTi() TiSP lockPTi struct node { int T; // int S; // } lock;585657 * Lock( plock, myTicket ) { myTicket = fetch&increment( plockP ); // while ( myTicket != plockS ); // } * () * Unlock( plock ) { plockS++ ; }59 * Unlock( plock, myAddress ) { plockS[myAddress + 1] = 1; } *O(p)Test-Test&Set O(p) * 60 21 * P R(W)P(V) * P *()() P1 P2 . a=f(x) /*set a*/ while (flag == 0 ) flag=1 b=g(a)/*use a*/60612 * -() RW(-) *W() R(-) *R/W P1 P2 . a=f(x) /*set a*/ b=g(a)/*use a*/ *()621 *FLAG=1 (FLAG)(CNT) CNT *CNT=p()FLAG=1 *CNT+1 () some computation BARRIER(bar1, p); //P1P0(flag=1) some computation BARRIER(bar1, p); //P0flag=0P1() ()62642 * struct tree_node { int count = 0; int l_sense; struct tree_node *parent; } g_tree[p]; //MEM

private int sense = 1;private struct tree_node *myleaf;BARRIER() { barrier_creat(myleaf); barrier_helper(myleaf); sense = !sense; //}barrier_helper(struct tree_node *mynode){ if ( fetch&incment(mynode->count) == k-1 ) { // if ( mynode->parent != NULL ) barrier_helper(mynode->parent); mynode->count = 0; mynode->l_sense = !mynode->l_sense; } else while ( sense != mynode->parent->l_sense );}(PP)6465 * 3 * * *P * (/)