UNIVERSITY OF MORATUWA

Faculty of Engineering

Non-GPA Module 3992: Industrial Training

TRAINING REPORT

Zamrath M.N.M.

100618D

Department of Electronic and Telecommunication

Training Establishment : Atrenta Lanka (Pvt) Ltd

Training Period : 18.11.2013 – 02.05.2014

Date of Submission : 23.06.2014

Preface

This is a report compiled after the successful completion of 24 weeks of industrial training.

This contains the overall description about the training including training establishment,

training experience, etc. in an industry sounds more in EDA where I worked.

First chapter is about the training establishment which overviews the history of the company,

evolution in their functions and development, organizational structure and some fundamental

description. This gives an insight on the company what they are capable of as strengths and

weaknesses being described.

Second chapter goes through the experience and knowledge gained in the training place. This

is just a summary over viewing the training sessions, projects involved and the verification

processes that I have been working with. Most of the illustration has been brought here in

first person point of view as it would be more understandable rather than describing in

passive.

Third chapter is to conclude the report briefly describing the training program. The

contribution from the company in the program is also briefly described here. Moreover the

weaknesses noticed and the suggestions to overcome these are also given herewith.

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Acknowledgement

First and foremost I would like to make this opportunity to thank my parents and my family

members who kept my expectations high and make me confident enough to achieve a training

place in this magnitude. Effort of the department head Ajith Pasqual and other staff members

organizing training program for all the undergraduates is also highly commended. My special

thanks go to the colleagues who worked together and batch representative who led us in

organizing an effective training program.

I would also like to thank the Industrial Training Division including the director Eng. N.A.

Wijeyewickrema and other officials for providing us a structured training program. And

NAITA is also highly acknowledged for their contribution towards training program and

preparing vacancies for short term technical trainees.

My sincere gratitude goes to the country manager of Atrenta Farazy Fahmy to organize the

training program in industrial environment. As far as training program’s flow is concerned

the contribution of Vetharaniam Kathircamalan is also highly appreciated. I would like to

thank to Eng. Charitha Deshapriya for guide me throughout the training period being training

in charge of me. Again my special thanks goes to the project’s in charges where I worked

with and every individual who was backing me to build my industrial personality.

Last but not least I would like to thank my colleagues who worked with me to provide better

contribution in return for the support the company made. We would like to thank the

company as a whole as they made our 24 weeks of training more memorable.

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Table of Contents

Preface 2

Acknowledgement 3

List of Figures6

List of Tables 8

1. Training Establishment 9

1.1 Company Profile 9

1.2 History 11

1.3 Mission, Vision and Values 11

1.4 Products 12

1.5 Organization Structure 12

1.6 R&D Center in Sri Lanka 13

1.7 Sri Lankan community as a whole 14

1.8 Strength of Atrenta 15

1.9 Weaknesses of Atrenta with suggestions to improve 16

2. Training Establishment 18

2.1 Phases of Training 18

2.1.1 Phase1 – Introductory sessions and trainings 18

2.1.1.1 Company’s product related trainings 18

2.1.1.2 Development related trainings 19

2.1.1.3 Other sessions 21

2.1.1.4 Post analysis of Phase1 and key personnel involved 22

2.1.2 Phase2 – Projects contributed 24

2.1.2.1 Asynchronous FIFO for Clock Domain Crossing 24

2.1.2.2 UART module31

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2.1.2.3 Verifying ETChecker modifications 31

2.1.2.4 Post analysis on Phase2 and key personnel involved 39

2.1.3 Phase3 – Verification Training 40

2.1.3.1 Initial training on DFT 40

2.1.3.2 Rules validated 45

2.1.3.3 Post analysis of Phase3 and key personnel involved 60

2.2 Industrial Exposure and Professional Practices 61

2.3 Administrational and Office Practices 63

3. Conclusion 65

3.1 Improvements from last year’s internship program 66

3.2 Weaknesses Noticed and Suggestions to Improve 66

Annex I 67

Annex II 69

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List of Figures

Figure 1.1: Geographical distribution of Atrenta 9

Figure 1.2: Old and new logos respectively 9

Figure 1.3: Directions to the headquarters 10

Figure 1.4: Map of Sri Lanka branch 10

Figure 1.5: Structure of Organization 13

Figure 1.6: Corporate customers of Atrenta 15

Figure 2.1: Main modules in Asynchronous FIFO 25

Figure 2.2: Traversal of Pointers 26

Figure 2.3: Inspection on asff_rddata and asff_rdptr 27

Figure 2.4: Read enable signal illustration 28

Figure 2.5: Asynchronous Reset operation 29

Figure 2.6: Synchronous Reset operation 30

Figure 2.7: UART module 31

Figure 2.8: An example illustrating controllability conditions 34

Figure 2.9: SFF type ‘hitPointTypeList’ walk 35

Figure 2.10: A reported place where the detection is not occurred 37

Figure 2.11: Top module used for verification 38

Figure 2.12: Hierarchical display to the 3rd level 39

Figure 2.13: Apply test mode constraint 42

Figure 2.14: dftSGDCSTX_071 validation 45

Figure 2.15: Async_15 validation 46

Figure 2.16: Scan_38 validation 47

Figure 2.17: Scan_39 reported bug 48

Figure 2.18: Scan_40 validation 49

Figure 2.19: Intel LSSD validation 50

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Figure 2.20: Hierarchy on which Latch Scannability is validated 51

Figure 2.21: For case00 and case01 (test scenarios) 52

Figure 2.22: For case02 and case03 (test scenarios) 52

Figure 2.23: Concatenated report for latch scannabilities of above test cases 53

Figure 2.24: Issue reported to Chandan related to Async_1553

Figure 2.25: Typical Async_02_capture violation 56

Figure 2.26: Incremental schematic for the first scenario 57

Figure 2.27: Robustness audit report extraction 57

Figure 2.28: Schematic for scenario 2 and 3 respectively 58

Figure 2.29: Clock_16 reported bug 59

Figure 2.30: Incorrect Robustness audit 60

Figure 2.31: Clock_16 reported bug 59

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List of Tables

Table 2.1: Personnel involved in each areas of training in Phase1 23

Table 2.2: Key personnel involved in each areas in Phase2 10

Table 2.3: Training areas with personnel involved in Phase3 61

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1 Training Establishment

Atrenta Inc. is a SoC realizing company which embodied with number of sales offices, R&D

centers and support offices in several locations across the globe. Company provides software

solutions which aims to improve design efficiency of complex Systems on Chips (SoC) in

terms of performance, power, area, etc. at an early stage. The main customers are world’s

leading semiconductor and consumer electronics companies such as Intel, Fujitsu, IBM, etc.

since they are keen on finding the least expensive path to silicon.

Since the global movement in smart devices get boost up, the demand in reliable but accurate

and sensible SoC also increased. This makes the EDA tool industries to be more competitive

than ever. In that trend, Atrenta invests heavily which evidences a 75% of its employees’

involvement in R&D. Main R&D centers for Atrenta Inc. is given below. San Jose (US),

Grenoble (France), Noida (India), Colombo (Sri Lanka) and Shanghai (China) are the places

where the development works are carried out to date. The sales center for Atrenta can be

found in Israel, UK, Japan, Korea, Taiwan including the places above mentioned.

Figure 1.1: Geographical distribution of Atrenta

1.1 Company Profile

Name of the Company : Atrenta Incorporation

Corporate Logo :

Figure 1.2: Old and new logos respectively

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Company Slogan : Old – The SoC Realization Company

New – Insight. Efficiency. Confidence.

Corporate Headquarters : Atrenta Inc.

2077 Gateway Place, Ste 300

San Jose, California 95110

USA

+1-408-453-3333

Location of the Headquarters :

Figure 1.3: Directions to the headquarters

Local Office : Atrenta Lanka (Pvt) Ltd

3, 2/1 Lukshmi Gardens

Colombo 8

Sri Lanka

+94 11 2674880

Location :

Figure 1.4: Map of Sri Lanka Branch

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1.2 History

“Interra” a design service company had been launched by Dr. Ajoy Bose, has come a long

way to reach the name “Atrenta”. He had been working 15 years of career at giant companies

such as AT&T Labs and Cadence. Once a semiconductor company which was a customer of

“Interra” came with a contract to make a tool which will automatically evaluate the

reusability of RTL IPs. He met the requirement and realized that there was a huge demand in

such tools and there he found “Atrenta” with headquarters in San Jose, USA in 2001.

In the same year the company could locate a R&D center in Noida, India as well. This R&D

center now has around 200 professional from premier technical institutes in India. This

subsidiary is 100% owned by Atrenta Inc. USA. In 2001 itself, Atrenta could launch first

SpyGlass product as a lint checking tool for RTL designs. Eight years later Atrenta could

launch the second product named GenSys as a tool for IP integration and reuse.

In 2011, Atrenta launched a world class R&D center comprising only PhD students in

Grenoble, France whereas there are about 25 researchers are working to date. In the same

time frame, Atrenta launched a R&D center in Sri Lanka. Now it has around 50 professionals

who are experts in different fields related to the company. In 2012, Atrenta acquired

“NextOp” in China and began R&D operations in China as well.

In its growth Atrenta holds two out of ten top viewed articles in EE times. SpyGlass was

commended as the most comprehensive tool for RTL analysis in Design Automation

Conference (DAC) 2012. Currently Atrenta is considered to be the large privately owned

company in EDA industry.

1.3 Mission, Vision and Values

Mission – Atrenta will be known for its relentless focus to deliver high quality, innovative

products that help to enable design of the most advanced electronic products in the world.

Our customers routinely benefit from improved quality, predictability and reduced cost. We

maximize value for every customer, employee and shareholder

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Vision – To be the recognized leading supplier of innovative products addressing early stage

IC & system design. Atrenta products will be widely used because of their clear financial and

business benefits. These products are known for their quality and ease of use.

Values –

Respect for the individual

Integrity

Focus on the customer

Teamwork

Empowerment and Accountability

Innovation and Creativity

1.4 Products

The main products of Atrenta include SpyGlass, GenSys and BugScope. SpyGlass is the most

profitable character that Atrenta had ever since its inception. It is a software platform that can

be used to predict and notify the users in RTL design before going to the Silicon level. This

will cut down unnecessary expenses that would be wasted in causing defects at Silicon level

where the reverse engineering is impossible incurring huge money. SpyGlass itself contains

around nine policies including Lint, Advanced Lint, DFT, etc. which cover various aspects in

designing proper testable circuits in Silicon level. Other than above stated products there are

some custom products as well such as ETChecker. More description on these products are

delivered in this report at its related topics.

1.5 Organizational Structure

Atrenta is a multinational company which has been spread across the globe. Therefore to

deliver the required customer service Atrenta has a profoundly laid out hierarchical

organizational structure. The company founder as well as the chairman and the CEO of the

company, Dr. Ajoy Bose is at the top of the hierarchy. After him there are nine vice

presidents who perform different functions on their own expertise areas. Under Managing

Directors the R&D centers of each geographical area are governed accordingly.

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Figure 1.5: Structure of organization

1.6 R&D Center in Sri Lanka

Since Sri Lanka has a strong supply of fresh graduates each year with required professional

level, Atrenta has decided to expand the R&D centers by establishing a subsidiary inside the

country. The center has been registered as Atrenta Lanka (Pvt) Ltd in November 2012 at

Borella.

Managing Director of this center is Dr. Peter Suaris who is a veteran in roles such as Scientist

and Engineering with 30 years of experience in EDA industry. Currently he is residing in

USA. Eng. Farazy Fahmy who is the Country Manager takes care of the operations,

developments as well as management in the R&D center. Vetharaniam Kathircamalan works

under him playing the role Administration Manager.

Mainly the work force of the company is divided in to two distinct groups as Software

division and Verification division. There are about 50 professionals working in R&D center

in Sri Lanka either being Product Validation Engineers or Software Engineers in above stated

two divisions. Since the operations are carried out globally it’s quite normal that the

professionals communicate and work together with foreign officials often.

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1.7 Sri Lankan society as a whole

Contribution to the economy

Due to the expansion of Atrenta in to Sri Lanka, EDA tool market which is considered to be a

biggest driving force of today’s world market was realized. There were numerous

investments in this field before launching Atrenta R&D center where the survival in the Sri

Lankan economy was not successful in all those occasions. Despite being far away from the

near possible chance on improving in this field, the rapid growth of Atrenta locally as well as

globally made this dream come true. The door to the Semiconductor industry has opened up

now in Sri Lanka which gears the technological advancement in Electronic industry with

respect to EDA tools industry.

Solution to brain drain

Since there is a lack of opportunities in Electronic Industry for the graduate students in Sri

Lanka, the brain drain is still an unsolved problem. The establishment of Atrenta made the

fresh graduates; who are well experienced and talented in this field; an opportunity to be

recruited to a world class multinational company and be thrived in their career development.

Atrenta also provides a premium salary scheme in which the output of the employees is taken

in to consideration and rewarded as par with the requirements and goals decided. The extra

activities planned throughout a calendar year makes the employees retention rate at a high

rate as well.

Training and Development

Atrenta has a well marched work force to train new employees once they make in to the

company. The training programs are scheduled at least for one month. The direct

involvement of management in these programs is evidenced. Further the training sessions on

various aspects by industry experts are conducted in order to keep track the career

developments of each individual. They offer short term technical training in Electronic and

Software fields in local branch as well.

Promoting Post Graduate studies

Since there is a lack in resources related to this area, there is a clear tendency of graduate

students to seek opportunities in overseas. Therefore Atrenta has decided to initiate a program

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in order to promote post graduation in Sri Lanka by sponsoring FPGA based IP development

projects carried out by University of Moratuwa’s post graduate students.

1.8 Strengths of Atrenta

Corporate Customers

Being Atrenta’s corporate customers alone give a strength to the company. 19 out of 20 world

class electronic manufacturers make sure their products are ‘SpyGlass clean’ which implies

their products do not contain silicon level design errors at an early stage. The quarter a year

performance benchmark in terms of customer growth shows us the upward increment. In their

operations, customers give positive feedbacks and suggestions in order to improve the

functional support of our products.

Figure 1.6: Corporate customers of Atrenta

SpyGlass

SpyGlass is the most profitable product that Atrenta has. This is because there is no

replacement to this product to this extension in EDA tool industry. SpyGlass has been

drawing attention in EDA and Semiconductor industry as deliver the best solution in SoC

design flow. Atrenta has recently redesigned the logo and the theme with SpyGlass as to give

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the more prominence to this product which in turn shows how much Atrenta values this

product.

Work force

Atrenta values personal contribution. Therefore each and every personnel in Atrenta carry

down their jobs under well established milestones as to evaluate themselves how good at their

appearance. Atrenta recruits the best professionals in the industry in order to ensure the

quality as well as the customer satisfaction which makes the company being well ahead in the

competition.

Multicultural environment

Being in a multinational and multicultural environment in this format gives you the feeling of

belongingness to one family of highly professional of this magnitude. The introduction to

several expertises in EDA tool market is possible as all the projects and activities are directly

linked to them. This platform makes the employees to get on with foreign officials with

different culture which in turn lead to a better relationship and understanding between them.

This global presence evidences the strategic layout of network in Atrenta. The headquarters is

in the fountain of modern technology in Silicon Valley. The R&D centers in India and Sri

Lanka are assisted by the knowledge expertise from France in order to bring the technically

skilled personnel up. With the development works under the iceberg, Atrenta has several

sales and distribution network across the globe including hubs in Israel, China, Korea, Japan,

etc.

1.9 Weaknesses of Atrenta with suggestions to overcome

Difficulties in global connection

Since the most of the operations are performed through globally, sometimes the employees

find it difficult to manage. Since the existence of international time difference between

different geographical areas the communication is hardly possible. Clarifications would take

one day to reach with a solution. A suggestion would be to cluster the operations at one place

which seeks frequent communication between team members.

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Global Management

Since Atrenta is multinational company where its operations are spread over the global, the

management of the company is expected to be tidier as to deliver the required outputs. The

frequent at which the company’s top management visits the branches should be increased.

This will be resulted in motivated workforce. One would suggest the frequency to be more

than twice a year.

Focus on One Product

Atrenta has shown a huge performance break through related to SpyGlass. Ever since

company’s inception this product makes profit. Therefore the company started to market the

company using this product where it came up with new logo and theme using SpyGlass. But

this is not recommended in a highly competitive environment as this brings risk of being stick

to one particular product. Further since there are products other than SpyGlass, due to their

marketing strategy customers would be less incentive on other products which would bring

down the morale of the employees as well. Therefore this should be avoided and company

should promote the company itself by using SpyGlass in order to market other products as

well.

Uncontrolled Development in Software

SpyGlass has been growing ever since its inception where the improvements, integration of

numerous features, rule checks and new methodologies are being added to the software as per

customer requirements. If this is not properly managed, software can be grown to an extent

where the customers would be unsatisfied due to their low performance. This could be

avoided if Atrenta uses a sustainable software portfolio in their expansion.

Less awareness

EDA industry is totally new in Sri Lanka. This means that awareness of the people on Atrenta

also not as the company realized. This would bring down the expectations of the company’s

top management. Therefore it’s vital to have different activities which involve people in Sri

Lanka which could make the CSR activities also alive. One suggestion I made in a meeting

with country manager is to increase the number of short term technical training positions per

year. A proper marketing strategy covering these areas would result in high demand in the

available positions in the company as well as in investment opportunities.

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2 Training Experience

In Atrenta the work flow has been divided into two main divisions such as software and

verification. All the development operations related to Atrenta Lanka (pvt) ltd are undertaken

in their office in Colombo-8. My entire 24 weeks of training was spent in the above

mentioned office. But since the company has several subsidiaries throughout the world, I had

to interact with the developers in overseas too in case the works need expert’s assistance.

2.1 Phases of training

2.1.1 Phase1 – Introductory sessions and trainings

In the initial period, interns were instructed to go through several presentation related

sessions to understand the roles of software and tools used in the company’s development

process. The sessions were conducted by the employees including country manager of the

company as described in the below sub topics along with respective training personnel.

2.1.1.1 Company’s product related trainings

Atrenta (pvt) ltd owns three main products namely SpyGlass®, GenSys® and BugScope™.

The introductions to each product were given by different personnel who have more

experience in respective areas as company’s management decides.

2.1.1.1.1 SpyGlass

In this session brief introduction in to the products was given. Initially focused on Linux

based environment familiarization as all the developments are centralized and carried out on

this environment. Along with this “Getting started with SpyGlass” presentation was done by

a senior Engineer Sandun C Rajapakshe.

After this a lab session for SpyGlass was provided and the central access was granted to carry

out the lab related to the SpyGlass. This is a product which focuses on predict errors and

optimization earlier from ASIC design to synthesize the code. Received the lab sessions

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through central repository and could complete the lab session successfully where could show

the progress with the lab session completion.

2.1.1.1.3 GenSys

In this session the product GenSys was introduced and overviewed. The assembly related to

Structured, RTL structuring and Logic insertion were briefly described. System Verilog

supports for GenSys was also overviewed later in another presentation.

2.1.1.1.4 BugScope

From all of above products, BugScope is a new acquired product to the company. The

relevant materials to learn BugScope were provided and went through “BugScope overview”

presentation to grasp the basic concepts behind the software. There was an online training

session with the cooperation with Noida, India division as required resource persons were not

available in Colombo division.

2.1.1.2 Development related trainings

2.1.1.2.1 VerilogHDL training

Verilog is the mostly used language for the verification purposes in Atrenta Lanka division.

Began from very basic concepts and went upto some of the advanced topics in Verilog such

as parameter usage for different environments and its importance as to instantiate modules

with parameters with hash tag. The presentations related to these were conducted by

personnel Sandun Rathnayake and Aabid Rushdi.

After the presentations a design task was given on which we had to design a simple protocol

decoder where if the transmitter receives correct two predefined headers, the module should

transmit the receiving data and stop if it receives two predefined tails. The task was

completed and demonstrated to the relevant officials. Furthermore several advanced exercises

were provided later on and could complete and demonstrated using ModelSim.

2.1.1.2.2 Altera® development board

Provided with the Altera® PCI development kit to be familiarized with FPGA tool kits.

Along with this Quartus II version B software was provided to work with developments. One

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of the useful software provided along with Quartus II was ModelSim® simulator. This

software was used for the test bench related simulations in my internship period.

2.1.1.2.3 Concorde®

This is the synthesis engine in SpyGlass®. This was overviewed in this session as bottom to

top synthesis flow tool. In this session Elaboration and Uniquification processes were briefly

described by an employee Thilini Peelikumbura.

2.1.1.2.4 Perl

This is the language used to implement GUI of the Atrenta’s products. The session contained

the basic overview of the language and showed how to write Perl with few examples. This

session was conducted by a senior employee Kasuni Mettananda. After this session an

exercise was given by Eng Charitha Deshapriya.

A file was given with approximately 3000 lines where as each has 5 entries. Objective of the

exercise was to construct a new file and there the duplicate policies with one of them being

‘InBuilt’ should be merged, alone ‘InBuilt’ name should be replaced by ‘Spyglass’ and others

as it is should be written. This was supposed to do using a scripting language and I preferred

to do this using Perl. I worked on this and demonstrated to the relevant officials as well.

2.1.1.2.5 System Verilog

The presentation was conducted by Eng. Nadun M Ellawala on which the importance of

System Verilog over other HDL languages was discussed. Along with this System Verilog

support in SpyGlass as well as GenSys was overviewed. Finally ended up with discussing

few examples including usage of constructs in System Verilog.

After the presentations the task given was to construct an ALU (Arithmetic and Logic Unit)

which perform signed mode as well as unsigned mode operations using System Verilog.

Another constraint in this exercise was to design the ALU using System Verilog constructs

such as typedef, enum, struct. I could come up with my own design and demonstrated to the

relevant personnel using ModelSim simulation as well.

2.1.1.2.6 VHDL

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In this training the motivation behind using VHDL over other HDL languages was discussed

such as being a strictly typed language, One entity can have multiple architecture, etc. The

basic structure of a VHDL file was also discussed.

2.1.1.2.7 CDC – Clock Domain Crossing

In this presentation conventional flop synchronization scheme under CDC synchronization

scheme was discussed. Along with this flow of SpyGlass’s CDC verification was also

discussed. This presentation was done by Eng. Kosala Samarasekera.

2.1.1.2.8 DFT – Design For Testability

The presentation was conducted by Eng. Mohamaed Mafraz. In this, scan testing with stuck

at fault model and transition fault model under catching DFT bugs were briefly discussed.

Furthermore given with the “VLSI design for testability” printed book to read chapter 2 and 3

to get the basic idea behind the discussed areas.

I could complete the parts given from the above referenced book and after that I was given

some of the examples given in the above book. I could complete within time and could show

the learning I made through exercises. Further in the line more discussions on DFT were

carried out by Eng. Mafraz to make me comfortable with the above concepts. Received

Hands on lab session for DFT. Went through the document while performing the tasks given

in the labs. Wrote down the learning for each steps I went through and sent to the Senior

Verification Engineer Vetharaniam Kathircamalan for review. Later in the training I was

assigned to the DFT team.

2.1.1.3 Other Sessions

2.1.1.3.1 Git session

Company was using CVS as the primary VCS(Version Control System) until Git VCS was

introduced. When the transition from CVS to Git was happened Atrenta top management has

arranged few training sessions in cooperation with Noida, India branch. I could attend that

session too where started from very beginning and went up to some of the advanced topics in

Git such as visibility of modified files in each stages like add, commit for other branches.

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After the session went on following instructions given to create my own repository and

perform operations which I had learnt in the session. Asked clarifications from some

employees when I needed.

2.1.1.3.2 Sessions on company’s global move

When the Piyush Sancheti, vice president of marketing in Atrenta was in a two days visit to

Sri Lanka branch he took two sessions for employees in the company. The first session was

about “SoC design trends and challenges” where he spoke about speed global move of EDA

tool design market, how the small but reliable smart devices made the increase in EDA tool

demand and focus in RTL signoff rather than layout signoff. In the second session he pictured

the company’s strength and emerging products as to face the global movement towards the

EDA tools.

2.1.1.3.3 Company’s committee meeting

I could participate to the company’s annual meeting on how they accomplished goals and

targets in the previous year. Here various aspects of financial parameters were discussed and

it was a great opportunity to get an understanding on company’s comparison with previous

figures and reconciliation are done in a real industrial environment. This session started by

stating $22 million revenue generation as opposed to the budgeted revenue which was $17

million.

2.1.1.4 Post analysis of Phase1 and key personnel involved

The training in initial period was scheduled by the training in charge and company’s

management. I could comprehensively understand the EDA tool market and the way Atrenta

operates in realizing in order to fulfill the ASIC and SoC needs. Through hands on training

related to the main product of the company; i.e. SpyGlass; I could get familiar in the normal

workflow. Apart from the sessions described above the presentations on ‘ASIC flow’

conducted by Eng. Sandun Rathnayake, Training on ‘Low power’ conducted by Eng.

Susantha Mihiranga Wijesekara, Tech session on ‘C++ 11 features’ by Eng. Chand

Priyankara, ‘Software architecture in SpyGlass’ by Eng. Ajanthan Thalaiyasingam,

‘SpyGlass – Console UI Basics’ by software engineer Mrs. Divya Narula from Atrenta global

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GUI team and ‘Flow testing’ by another foreign official also empowered me to had a

thorough training on the company’s development process.

With the training, sessions, exercises and supervision on development tools, I could possibly

come to a state where I could manage myself to do basic stuffs with less intervention of

employees. Above development tools under different category were covered by engineers

who are expertise in their respective areas. We had the freedom in clarifying unclear points

related to the subject area as well as in the general areas.

The list of key personnel who involved in my initial training period is as follows.

Table 2.1: Personnel involved in each areas of training in Phase1

Training Personnel

ASIC design flow Sandun Rathnayake

SpyGlass Sandun C Rajapakshe

VerilogHDL Aabid Rushdi

Verilog exercises Charitha Deshapriya/ Aabid Rushdi

Concorde Thilini Peelikumbura

Perl Kasuni Mettananda

Perl exercise Charitha Deshapriya

System Verilog Nadun M Ellawala

System Verilog exercise Nadun M Ellawala

C++ 11 features Chand Priyankara

CDC Kosala Samarasekera

DFT Mohamed Mafraz

Low Power Susantha Mihiranga Wijesekara

SpyGlass – Console UI Basics Divya Narula (India)

Software Architecture in SpyGlass Ajanthan Thalaiyasingam

Company’s Global Move Piyush Sancheti (India)

Overall Vetharaniam Kathircamalan

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2.1.2 Phase2 – Projects contributed

Throughout the initial training period every intern were closely observed and given with

feedback on their work accomplishments. I too had been assigned to a senior verification

engineer Charitha Deshapriya where he closely reviewed my progress and gave feedbacks

accordingly. After the initial training on development tools was finished, I was again

consulted and reviewed by a company’s senior verification engineer Vetharaniam

Kathircamalan. After this period, I was assigned to few projects including projects

undergoing at the point of time where I started.

2.1.2.1 Asynchronous FIFO for Clock Domain Crossing

This is a project that was undergoing at the time I joined the company. During my initial

training period I was asked to follow the meetings related to Asynchronous FIFO. In a

meeting I was assigned to create test benches for this project. Though I was appointed so,

there were well industrial standard oriented test benches which had been created for this

project. But at that point of time my task was to create fresh test benches which could analyze

sensitive parts in the modules of Asynchronous FIFO.

2.1.2.1.1 Background

In a chip itself, there could be modules working on different clocks’ frequencies/phases.

When they interact with each other, underflow or overflow of data could be arisen due to

their above discrepancy in clocks. Therefore a Clock Domain Crossing (CDC) module which

is capable in controlling these situations or in other words performing as a timing buffer is

required. Asynchronous FIFO is a module which acts as a CDC buffer.

2.1.2.1.2 Project description in brief

This project is intended on developing an Asynchronous FIFO which meets above

bottlenecks.

The main control signals involved:

Write operation

o Write enable (asff_wren)

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o Write reset (asff_wrreset_n)

Read operation

o Read enable (asff_rden)

o Read reset (asff_rdreset_n)

The flag signals generated:

Write operation

o FIFO is full (asff_full)

o FIFO is available for writing (asff_wravail)

o FIFO is overflowed (asff_overflow)

Read operation

o FIFO is empty (asff_empt)

o FIFO is available for reading (asff_rdavail)

o FIFO is underflowed (asff_underflow)

The main modules involved in Asynchronous FIFO:

Write interface

Read interface

Memory

Synchronizer

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Write I/F

(Front End)

Read I/F

(Back End)

Wr to Rd Sync

Rd to Wr Sync

Storage/mem

Wr Data

Wr Address

Wr clk

Wr En

Rd Data

Rd Address

Rd clk

Rd En

Wr Pointer

Rd Pointer Sync

Wr Pointer Sync

Rd Pointer

asff_wren

asff_wrdata

asff_wrrst_n

asff_wrclk

asff_full

asff_wravail

asff_overflow

asff_rddata

asff_empt

asff_rdavail

asff_underflow

asff_rdrst_n

asff_rden

asff_rdclkasff_rdclk

asff_wrclk

Gray encoder Gray decoderSynchronizerPointer In Pointer Out

CLK 2

Figure 2.1: Main modules in Asynchronous FIFO

2.1.2.1.3 Tasks completed

Eng. Aruna Rubasinghe was appointed as the project in charge for me. He referenced me

resources related to Asynchronous FIFO such as CDC, resets, de-assertion, metastability, etc.

I could go through the references provided me and gave him the status after all.

I came up with a fresh test bench for FIFO module and illustrated to the Senior verification

engineer Vetharaniam Kathircamalan. I showed the test bench with simulations using

ModelSim software. Since the code was not up to the industrial standard, I was asked to

rewrite the code meeting those standards.

2.1.2.1.3.1 Functionality of pointers

Figure 2.2: Traversal of Pointers

The Asynchronous FIFO in CDC works using Synchronize architecture of FIFO module. I.e.

synchronizing read and write pointers between clock domains. Thus the flags are generated

after comparing the read and write pointers.

Later in the week I could possibly test the functionality of pointers in FIFO and sent to the

management for review.

The observations are listed below along with the feedback I received (In red).

First I tested whether the pointers are working properly. For that I just enabled the

‘asff_wr_en’ and fetched input data continuously (20 – 130 ps). Since the

DEPTHLN2 is 3 and hence the size of the memory is 8x8, the maximum it can fetch

in to the memory is 8 bytes. In that the ‘wr_ptr’ is incremented as expected.

Then the ‘asff_rd_en’ is set (130 – 320 ps) and allowed to be read whole the memory.

In that the ‘rd_ptr’ is also incremented as expected. And at this stage (280 ps + 4 ps

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Clock Domain 2Clock Domain 1

(clock offset)) both pointers are at 3’b000. But the problem at this stage is since the

‘rd_ptr’ initially points on first element in the memory and since that time it should

point on the second element in the memory when the first element is trigerred (but

since it is not happening here) the cycle of reading extends to one more element

(reads nine elements). The next element in the memory from where the limit created

by the wr_ptr is also read by the rd_ptr (if it is end of the memory then the first

element).

Closely look at the time gap between 280 – 300 ps with respect to asff_rddata and

rd_ptr.

                See how empty flag works and conditions on how we use a FIFO

Figure 2.3: inspection on asff_rddata and asff_rdptr

At 320 ps the ‘asff_rd_en’ is set low and ‘asff_wr_en’ is set high. Similar problem

occurs again here. It is expected (as to comply with the write flow) once the first data

is fetched to the memory the ‘rd_ptr’ should be set to 3’b001. But that is not evident

here. Therefore we can see another one step reading further the memory fetching.

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                Check if this has anything to do with read enable signal

Figure 2.4: Read enable signal illustration

2.1.2.1.3.2 Functional verification

Project in charge of FIFO (foreign personnel) has sent a check list to be verified in terms of

functional aspects. Below is an extraction of the check list related to me.

1. Async FIFO Functional Verification  (Zamrath & Sandun & Aruna)

1. Noraml read and write operation 

1. with read clock faster than write clock

2. with write clock faster than read clock 

3. read and write clock with same frequency but phase mismatch 

2. Underflow and Overflow condition 

3. Reset Function

1. During normal operation

2. After underflow 

3. After overflow 

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4. All of the above with parameter changes 

1. Data width change

2. Synchronizer Depth Change 

3. Resest Scheme Change 

2. Async FIFO CDC Verification (Zamrath & Aruna & Kosala)

1. Setup without warning

2. Structural Run

3. Formal Run

4. All of the above for 

1. Synchronizer depth change 

2. Reset Scheme change 

I could successfully construct test benches and simulate them using ModelSim. Out of above

some of them can be illustrated as follows.

2.1.2.1.3.2.1 Asynchronous/Synchronous Reset

In asynchronous configured FIFO module, the entire operations of FIFO will go to the reset

mode as soon as the user assert read or write reset to low. At that point of time flags that have

been stated above will change their states. What I had to verify was, asynchronous and

synchronous reset functioning under normal, underflow and overflow conditions of FIFO

with small test benches for each criteria. I could successfully simulate and verify above

criterion and sent them for the management review.

Figure 2.5: Asynchronous Reset operation

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Figure 2.6: Synchronous Reset operation

2.1.2.1.3.2.2 Underflow and Overflow condition

This is to verify the underflow and overflow are functioning properly. When the actual

memory is filled up fully or being empty due to the discrepancy exists between clocks, this

flags could be flagged. I verified this too by sending data while only write enable (asff_rden)

signal was asserted with some frequency of clock. This makes the FIFO memory being filled

up until to flag ‘asff_overflow’. Then the read enable (asff_wren) signal was asserted and

observed the ‘asff_underflow’ was flagged when the memory goes out of data.

2.1.2.1.3.2.3 CDC verification

As I was instructed I could test the module with the newer version of SpyGlass. In this test I

found zero errors unlike what I saw in old version of SpyGlass. But there were several

warnings related to the CDC such as convergence, etc. I reported this to the project in charge.

He convinced me that he would work on that to meet zero warnings in functional

environment.

2.1.2.1.3.2.4 Pointer round trip verification

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When the read enable (asff_rden) and write enable (asff_wren) both are enabled at a same

clock frequency when the parameter ASFF_DEPTHLN2 is equal to 3 (i.e. buffer size of the

FIFO is 8) then the read and write operations are expected to happen sequentially without any

interruptions. But this was violated as we could observe one or two clock discontinuity in the

time line even for lesser ASFF_DEPTHLN2 values. The investigation revealed that it is

because of the round trip propagation delay which was exceeded 8 clock cycles. I worked on

this and reported that it could be reduced if we were to reduce synchronizer depth of read or

write. But since it is the standard that we had to follow that was not allowed. I reasoned the

fact to senior verification engineer Vetharaniam Kathircamalan.

2.1.2.2 UART module

I was asked to start up the project related to UART module by Eng Sandun Rathnayake. This

was intended on integrating with Asynchronous FIFO module. I could possibly finish the

receiver part of the UART module. I illustrated this to the project in charge using simulation

results of ModelSim. (Please refer Annex I for the code)

Figure 2.7: UART module

2.1.2.3 Verifying ETChecker modifications

In EDA tool industry; there are many competitors as this area of interest has a boom in the

market in recent past. Many of them were fresh starters. Out of them there are companies

who are recognized as market leaders. Synopsis and Mentor Graphics are such giant

competitors in EDA tool industry.

31

Mentor Graphic uses some of our products despite the competition. They do not need all the

rules and policies we offer with SpyGlass. They need only some of them. Therefore the

company had gone on with an agreement to supply a custom product which has only the rules

and policies that they recommend. This custom product is recognized as ETChecker.

After the completion of hands on lab related to SpyGlass, I was appointed to the ETChecker

team with the supervision of a senior employee Dananjaya Wettewa.

2.1.2.3.1 Background

In this section I was supposed to verify the following changes as the migration of ETChecker

from 5.0.0.3 to 5.1.1.6 was happened. One of the senior employees in the Atrenta Chandan

Kumar communicated with me to deliver the below tasks.

1. Report file change

2. Common walk change

3. Rule to detect (.*) usage in instantiations

Prior to these tasks being done, I was given with the PRD of ETChecker (document) to get on

with the rules described in the validation.

2.1.2.3.2 Learning on ETChecker

With the help of a senior employee Dananjaya Wettewa and with PRD of ETChecker, I could

carry on learning related to ETChecker rules. To get a better understanding I worked out

these rules in the working copy of ETChecker’s central repository. I changed some of the

parameters to see whether the rules are giving correct outputs. At the mean time I reported

some of the deficiencies existed in the rules as well as in the PRD. The following is a

summery on the learning I gained in lv.walk of ETChecker.

An extraction (from PRD) of lv.walk syntax for input file is given below.

lv.walk -label <string>

-simValues TXFX | T1FX | TXF1 | T1F1 |

TXF1C1 | T1F1C1, T1F1FC1, T1F1FC0, T1F1AX \

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-startItemList Mod.Inst.pin | Mod.Inst.net [Mod.Inst.pin |

Mod.Inst.net] \

-startRTLRegD Mod.Inst.reg | Mod.reg \

-startRTLRegCLK Mod.Inst.reg | Mod.reg \

-startRTLRegQ Mod.Inst.reg | Mod.reg \

-startRTLRegSetRst Mod.Inst.reg | Mod.reg \

-controllability connected | unblocked | Controlling \

-direction fanin | fanout \

-stopPointTypeList ELTIn ELTOut BLKIn BLKOut CombLoop

TMCombLoop TMStopPoint ETCE TM CGD InputDI

OutputDI DI(IS) DI(OS) ControlFlop ObservationFlop

ClkEnPin CDB ICS TCI ECCI IntScanInst

MultiInputGate IntTestclkSrc SFFClk memClk SeqCell

MDrv,ClkNet,ArrayLatch,LACGC,NoAWTArrayLatch

ArrayLatchClock

-hitPointTypeList PI PO ELTIn ELTOut BLKIn BLKOut CombLoop

TMCombLoop TMStopPoint ETCE TM CGD InputDI

OutputDI DI(IS) DI(OS) ControlFlop ObservationFlop

ClkEnPin CDB ICS TCI ECCI IntScanInst

MultiInputGate IntTestclkSrc SFFClk MemClk

SeqCell MDrv ClkNet ArrayLatch, LACGC,

NoAWTArrayLatch, ArrayLatchClock

-stopOnFirstHit Yes | (No)

As name implies lv.walk command makes the observer to through the circuit design within

the constraint imposed with lv.walk command. “-label” specifies a name on which the

lv.walk on different paths can be separately recognized. “-simValues” specifies the mode of

simulation value when the walk through the path is occur. “-startItemList” specifies the initial

33

points where the walk starts. “-startRTLRegD”, “-startRTLRegCLK”, “-startRTLRegQ” and

“-startRTLRegSetRst” specifies the point of a flip flop as specifying an initial point on a flip

flop is not obvious.

“-controllability” identifies the method of traversal through the combinational circuit. One of

the examples I tried with ETChecker rules is given below.

Figure 2.8: An example illustrating controllability conditions

Where ‘Sel’ and ‘in3’ are asserted as 1’b1 whereas ‘in2’ and ‘in4’ are asserted as 1’b0.

“-direction” means the direction on which the traversal happens. If that is ‘fanin’, the

traversal happens through inputs to output of all combinational and sequential logics. The

‘fanout’ gives the direction in the other way around. “-stopPointTypeList” specifies the

points where the traversal should stop its walk. “-hitPointTypeList” specifies the types of

elements we need to identify in the walk through. “stopOnFirstHit” on the other hand tells

whether the traversal stop once it detected one of the object specified in “-stopOnFirstHit”.

An example I tried in the working environment is given below.

34

lv.NonScanInstance -name FF1 -rtlReg

lv.RetimingFlop -name FF3 -rtlReg

lv.walk -startItemList a b c d

-controllability unblocked

-direction fanin

-hitPointTypeList PI SFF

Figure 2.9: SFF type ‘hitPointTypeList’ walk

If “SFF” the type we are looking for, then all the flops that are neither declared nor inferred

with “NonScanInstance” or “RetimingFlop” will be counted. If any instance is declared to be

“RetimingFlop” then the path will be transparent through that instance. And if “SFF”, then

both “SFFP” and “SFFN” are counted through the traversal. The output would be in the

following form.

HitObjects{

top.FF2 // (SFFP)

top.FF4 // (SFFN)

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top.FF5 // (through retiming FF)

}

2.1.2.3.3 Tasks covered

With the learning on ETChecker, I was supposed to validate the tasks given in 2.1.2.3.1. I

could possibly finish this with the help of supervising employee Dananjaya Wettewa and

foreign official Chandan Kumar. The below is a workout on each task given above.

The first two out of above validation items emerged due to the migration of the product

versions from 5.0.0.3 to 5.1.1.6 and are listed below.

2.1.2.3.3.1 Report file change

In previous versions (5.0.0.3) a report called wavier was also generated unlike in the current

latest version (5.1.1.6). Now they are concatenated.

2.1.2.3.3.2 Common walk change

A problem was reported as in the lv_walk_issue (refer) from the product customer Mentor.

This has to change in the development (binary) as this is not agile in the kernel. (Currently

this is issue is being inspected)

The required HitObject list to be produced originally.

HitObjects {

TOP.BOB.NB1 0

TOP.JOE.NJ4 0

TOP.JOE.NJ6 0

TOP.N3 0

}

But due to the migration the output was as follows.

HitObjects {

TOP.JOE.NJ6 0

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}

One place where the detection is not occurred is shown in the diagram below.

Figure 2.10: A reported place where the detection is not occurred

2.1.2.3.3.3 Rule to detect (.*) usage in instantiation

Normally in System Verilog, following syntax is possible.

module A(….); //a net list

B b(.*);

endmodule

But due to replacing ports in B as well when makes changes to the ports in A (when

validation happen the ports tend to be changed) the detection of (.*) is required. Therefore

have to build tools to detect and report to the users.

Built 8 different test cases to verify as follows.

Case 1: implicit (.*) in top module

Case 2: non-implicit i.e. no (.*) in any module

Case 3: in etp.sgdc –lv.ELTCoreModule –name “LogicCalculator” while (.*) in

LogicCalcultor module (2nd level)

37

Case 4: in etp.sgdc –lv.ELTCoreModule –name “NumericalCalculator” while (.*) in

LogicCalcultor module (2nd level)

Case 5: in etp.sgdc –lv.BlockModule –name “top” while (.*) in LogicCalcultor module (2nd

level)

Case 6: in etp.sgdc –lv.BlockModule –name “LogicCalculator” while (.*) in LogicCalcultor

module (2nd level)

Case 7: in etp.sgdc –lv.BlockModule –name “NumericalCalculator” while (.*) in

LogicCalcultor module (2nd level)

Case 8: in etp.sgdc –lv.BlockModule –name “LogicCalculator” while (.*) in OrGateOut

module (3rd level)

Figure 2.11: Top module used for verification

Figure 2.12: Hierarchical display to the 3rd level

38

All cases displayed the desired results with the GUI tests are also being passed. i.e.

When the violation is selected it correctly points to the declaration of modules

(instances).

Created HDL for reference is provided in Annex II.

2.1.2.4 Post analysis on Phase2 and key personnel involved

This phase was intended on making interns more familiar with the working environment with

more supervision of the personnel in the company. The first project I was appointed is

Asynchronous FIFO where as there were five personnel involved in that project. In the initial

period of my arrival, one of the project members Eng. Kushan Weerasekera assisted me in

writing test benches. The supervision of Eng. Aruna Rubasinghe was quite useful as he

guided me throughout the project duration. During this period Eng. Sandun Rathnayake

appointed me to build a fresh UART module with reference to the project. But due to the

training programs and Asynchronous FIFO project, I could not proceed after the completion

of receiver part of the module. Before the DFT verification training, I was appointed in the

ETChecker team to get familiar with the basic structures of the verification.

Table 2.2: Key personnel involved in each areas in Phase2

Training Personnel

Asynchronous FIFO project Aruna Rubasinghe

Writing test benches Kushan Weerasekera

FIFO works appointment Vetharaniam Kathircamalan

UART module Sandun Rathnayake

ETChecker validation in charge Dananjaya Wettewa

ETChecker validation advisor Chandan Kumar (US)

Overall supervision Charitha Deshapriya

39

2.1.3 Phase3 – Verification Training

With the completion of the projects and validations on ETChecker, I was appointed to the

DFT (Design For Testability) team under the supervision of Eng. Ajanthan Thalaiyasingam

after a discussion held between Eng. Vetharaniam Kathircamalan and Director of Engineers

Chandan Kumar. The initial part of the DFT training was carried out by Eng. Mohamed

Mafraz. Since he signed off and went abroad, the verification works had been shifted to

Ajanthan Thalaiyasingam.

2.1.3.1 Initial training on DFT

2.1.3.1.1 Hands on training guide on DFT

I received the hands on training guide. Vetharaniam Kathircamalan guided me on this. Once I

finished with the training guide, I sent the learning points to Vetharaniam Kathircamalan and

Chandan Kumar for the management review. Below is the extraction of that.

DFT analysis for Stuck-at-test (Project – Socrates RefDesCore)

@Design setup

Import sources Setup.spp

Run design read again Run design read

Resolve black boxes (29 ERRORS were appeared)

- To reduce black boxes, should provide technology libraries. After providing

‘lsi_10k_sglib’ # black boxes is 1.

Goals in DFT:

1. dft_setup

@Goal setup Select goal

Select methodology Spyglass sub-methodology

Setup goal Edit settings directly Return to setup wizard

40

This is to resolve black boxes.

In a spread sheet, we can see user defined and undefined black boxes. (If we want to define,

define)

Can identify potential clock in the design. From this we can exclude

o System clock (PLL driven)

o Enable signals from being tested as clocks

After deselecting above two signals now we can assign test_clock to all qualified

‘real’ clocks. Finally generate the .sgdc file. (Basic_constraints.sgdc)

.sgdc constraints are created for the test signals.

Next: create black box related constraints.

o Apply scan_wrap sgdc constraint on all modules except PLL

o ‘Yes’ for unsaved constraint generation. (Scanwrap.sgdc)

2. dft_stuck_at_coverage_audit

@Goal setup Setup goal

Add .sgdc files:

Scanwrap.sgdc scan_wrap constraints

Basic_constraints.sgdc clock and test mode

Noscan.sgdc exclude few flops from being in scan chain

Select goal Run selected goal(s)

View report generated by the coverage_audit rule.

FC – 69.7% and TC – 70.3%

Report guides to improve FC and TC.

3. dft_best_practice

Try to understand if the design followed certain good design practices. (To increase the

effectiveness of ATPG)

Good practices: Test clock should not be used as data

41

Asynchronous combinational loop that is broken

Test clock should not drive the set/reset of flop

4. dft_latch

Latches can become non-transparent and untestable and hence lower the coverage.

Reason for this is design specific.

E.g. Mux infront of latches is not constrained

Can be fixed by adding Latches.sgdc file

5. dft_scan_ready

Analyzing clock and asynchronous controllability during scan phase

Two important factors that reduce the fault coverage.

E.g. IN2 should be set to ‘1’ (A test mode constraint)

IN1

IN2

Figure 2.13: Apply test mode constraints

Right mouse click on IN2 show input cone to primary inputs

Right mouse click on extended wire set SGDC constraints

Auto fixing clock_11and Async_07 violations

Generates new RTL in a separate directory

@Goal setup Setup goal Common parameter dftAutoFix

6. dft_test_points

Provides reports on test points to increase coverage

7. dft_block_check

Check whether the lower level constraints good at SoC level

42

2.1.3.1.2 Basic structure of a test case

Ajanthan assisted me in get on with the validation working environment. First of all he

guided me how the unit test cases are worked out in order to validate that. All unit test cases

have the following files in common.

1. Makefile – Invoking an executable file to run the process

2. Testfile – Verify the test case when ‘shell_run=no’

3. test.v – The RTL code to be tested

4. test.sgdc – This contains the constraints to run RTL in SpyGlass

5. test.prj – Gives options such as rules, policies, etc. to run the regression

6. GOLD – When build using ‘make’ command a temporary file ‘TEST’ is created and

it will be compared with this to make sure the previous output does not deviate unless

there had been a modification.

Apart from above files various other backup and temporary files are being used to provide

different functions. This test case can be used to validate the existing SpyGlass version. It can

be done in three different ways.

1. Using ‘Makefile’ – We can enter the command ‘make 64bit=yes force’ to give a fresh

build to the unit test case. This uses the ‘test.prj’ file in order to run the process.

During the process a folder called ‘Work’ is created. If the command consists ‘64bit’

then another folder ‘Linux4’ is created inside the temporary ‘Work’ folder. Otherwise

‘Linux2’ is created. Inside this folder all the output files of SpyGlass are loaded

including ‘TEST’ file.

2. Using SpyGlass GUI – With ‘spyglass *’ commands we can open up the GUI console

of SpyGlass and perform the validation. Here the validation is performed by referring

to the message tree, comparing with GOLD file’s output, using Incremental

Schematic, checking whether there exist correct links between message reported and

the component highlighted, looking in to generated files, etc.

3. Using ‘Testfile’ – This is somewhat similar process to ‘Makefile’.

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2.1.3.1.3 Regression analysis

In DFT itself there are around 7000 unit test cases. For a modification or addition of rules in

DFT policy, those all unit test cases should have been run. It’s of course very tedious if we

are to validate one at a time every time there is a modification is to be validated. Therefore

the validation is automated using ‘Regression’ where all the unit test cases will be fetched in

to a separate central setup and perform the analysis at once. This process will identify and

notify us the places where the abnormalities exist if there are any.

‘Condor setup’ is the machine which is being used for this purpose. The Sri Lanka condor

machine has 20 cores which run parallelly. The all the test cases are divided into queues with

a defined ticket size (say 40), then the number of queues is around 170. These queues are

then fed into these accordingly.

I was well instructed to keep up to date copy of the DFT repository before fire the regression

on dft, dft/dev and dft/test areas. ‘.list0’, ‘.list1’ and ‘.listd’ files contain the paths to the test

cases. Newly added test cases’ paths also should be added to these files (normally ‘.listd’).

‘.list1’ depends on the outputs of ‘.list0’. Therefore when submit the files to the regression it

should be in the following order.

condor_submit_0.csh

condor_submit_d.csh

condor_submit_1.csh

At the end, the following files are expected to be created.

1. results.txt – gives us how many test cases have been passed

2. diff_file.txt – shows the places where the differences exist between TEST and

GOLD

3. STATUS – shows the status of all the test cases such as PASS, FAIL,

CRASH, ERROR, etc.

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2.1.3.2 Rules validated

DFT is a main policy out of around 10 policies in SpyGlass. It governs various DFT issues in

IC designs well prior to the sign off of the product. There are two divisions working on this

policy with software developers and verification engineers. Once a rule is needed freshly or

an existing rule need an improvement, then developers will do the job and hand it over to the

verification engineers in order to validate the functionalities. I could work with the above

mentioned personnel to validate the improved or developed new rules. Those rules are

described below.

2.1.3.2.1 dftSGDCSTX_071

Russ a personnel who was using clock_shaper in Intel had reported an issue. This resulted in

introducing new Sanity rule where if a clock_shaper command without ‘-register’ then that

particular sgdc command should be ignored. I could come up with my own test cases to

validate the above modification with the supervision of some senior employees.

Figure 2.14: dftSGDCSTX_071 validation

2.1.3.2.2 Async_15

Intel has requested to create a new rule where within an IP, separate control must be

maintained for the asynchronous set or reset of latches in a particular test_mode condition.

This can be illustrated as follows.

45

Figure 2.15: Async_15 validation

The bases on which this rule is validated are listed below. (Please note that FF – Flipflop and

L – Latch)

1. Asynchronous FF

2. Synchronous FF

3. With inversion delay of a same source for FF and L

4. or two FFs and for a L

5. Always @(-without rst-) in L

6. One FF’s reset is set for a L

7. Always @(-with rst-) in L but not in the block (instead another rst)

8. Same rst for two Ls

2.1.3.2.3 Scan_38, Scan_39 and Scan_40

Scan_38:

Several new rules had been requested by Intel in Penang. Scan_38 is one of them whereas a

scan chain should start with a flip flop which is being triggered by positive edge of a test

clock. For an example the following design will flag a violation since the scan chain starts

from a negative edge triggered flip flop.

46

Figure 2.16: Scan_38 validation

The bases on which this rule is validated is given below. (Please note that N – Negedge Scancell P- Posedge Scancell)

1. NPP of orientation

2. PNP of orientation

3. NPPP of orientation with combinational circuits in between

4. No testclock is introduced in .sgdc file

5. Chain of registers instead of Scan cell chain

Scan_39:

During these validations a senior software engineer Rajesh Kumar from Noida, India was

appointed to supervise the interns. He facilitated in questions and clarifications raised in

several occasions related to DFT area.

During the validation of Scan_39 rule I found out a bug (described below). The following is

the mail I sent to Chandan and Rajesh and the replies from each are also extracted.

Mail I sent:

In Scan_39 verification I observed following outcome which I suspect as a possible bug (if

not pardon me for lack of knowledge).

47

Figure 2.17: Scan_39 reported bug

Where the .sgdc file being,

current_design top

     clock -name clk -testclock

     scan_chain -scanin in1 -scanout d2

     scan_chain -scanin d2 -scanout op1

Output:

Scan chains with scanchain_id:'1' (scanin=>'top.in1', scanout=>'top.d2',

condition=>'testmode') and scanchain    _id:'2' (scanin=>'top.d2', scanout=>'top.op1',

condition=>'testmode') share '1' flip-flop

Would not you expect no flags here according to Scan_39?

Rajesh replied,

Very good observation indeed, as per my understanding this is a case where the result needs a

discussion. It is neither correct nor incorrect there is explanation for both in support of

violation and against it. Let’s wait for Chandan’s views too, he will join office tomorrow.

Chandan replied,

Yes, this is a bug. I will fix this and let you know once it is done.

A week later Chandan again replied,

Issue is now fixed.

48

- Description :Skip if term is not ff-op because if scan chain terminates at net connected

with ff-Dpin and another starts as the same net then that flip-flop will only part of

second chain and not first --> reported by Zamrath

- Test case: dft/test/Ruledecks/dft/Verilog/Scan_39/non_overlapping_1_physical_chain

Zamrath – Can you please validate the fix at your end as well?

After the confirmation mail, I could carry out the validation with existing unit test cases referenced by Chandan.

Scan_40:

Scan chains can be fully triggered at either positive or negative. But at a crossing of positive

to negative clock triggered scan chains, a ‘copy flip-flop’ is a must. This is to guarantee a

reliable chain operation.

Figure 2.18: Scan_40 validation

If either the f3a’s input is not the output of f3 or that net is not consisted with even number of

inverters then a violation is said to happen. This will issue a violation message under

Scan_40. Understood the basic concept and validated the rule on the following bases.

1. No violation

2. Simple violation

3. Negative to positive

4. MUX between FF_(L-1) and FF_L

5. After rectifying what has been

given in all_case_netlist_01

6. Two ffs are in different scan chains

7. Two negative edge scan chains

8. Comb in between scan chains

9. With two clocks

10. With dftStrictTestClkDomains

49

11. FF_(L-1)’s and FF_L’s d pins are

connected

12. Above with inversion

13. Two FF_(L-1) for FF_L

14. Only two scans

15. More in one scan chain

2.1.3.2.4 Intel LSSD support in DFT

This is another request made by Russ Roan of Intel on behalf of Kavita Rachakatla. The

validation of this modification was brought down in two phases. This modification introduces

the scannability of latches in addition to the ‘pipeline’ extension.

When test clocks are inferred at outputs of ICG cells using ‘pipeline’ constraint then the

registers driven by them will be considered to be scannable.

Figure 2.19: Intel LSSD validation

The ‘pipeline_depth’ constraint in sgdc file can only be specified with the exact value which

is the depth of the registers which are presented before ICGC. But the ‘pipeline_depth_range’

comes handy in use as the user can specify a value range on which it will automatically

define a depth of registers which match the design. The impact on latch scannability was also

validated along with the functional validation of ‘pipeline’.

2.1.3.2.4.1 Functional validation on ‘pipeline’

The bases on which this modification is tested is listed below.

1. Case 00 – default case where ‘-pipeline_depth’ is left without defining.

50

gating_cell_enable

pipeline_depth

phased_clocks

2. Case 01 – There are two ‘gating_cell_enable’ and one ‘-pipeline_depth’ is left without

defining.

3. Case 02 – Normal operation of ‘-pipeline_depth’ (two latches are placed before and

after CGC)

4. Case 03 – Normal operation of ‘-pipeline_depth_range’ (two latches are placed before

and after CGC)

5. Case 04 – ‘pipeline_depth_range 0 5’ and placing a CGC after 6th flop

6. Case 05 – ‘pipeline_depth_range 3 6’ and placing a CGC before 2nd flop

7. Case 06 – ‘pipeline_depth_range 0 5’ and placing many CGCs in between

8. Case 07 – Check whether both are working together

9. Case 08 – Negative value for ‘-pipeline_depth’

10. Case 09 – Negative values for ‘-pipeline_depth_range’

11. Case 10 – More valid values for ‘-pipeline_depth’

12. Case 11 – More valid values for ‘-pipeline_depth_range’

13. Case 12 – One valid value for ‘-pipeline_depth_range’

14. Case 13 – Zero valid values for ‘-pipeline_depth’

15. Case 14 – Zero valid values for ‘-pipeline_depth_range’

16. Case 15 – Two CGCs and ‘-pipeline_depth’ for one CGC and ‘-

pipeline_depth_range’ for other one

2.1.3.2.4.2 Latch Scannability

51

Figure 2.20: Hierarchy on which Latch Scannability is validated

I tried each and every base with SpyGlass and checked whether the scannability report of

each scenario produced the correct output except in the case01. The scannability of latches

for few test scenarios is given below. Please refer the following designs for case00, case01

and for case02, case03 respectively.

Figure 2.21: For case00 and case01 (test scenarios)

52

Figure 2.22: For case02 and case03 (test scenarios)

Figure 2.23: Concatenated report for latch scannabilities of above test cases

The case01 is the only place where the required output is not obtained. When

‘dftTreatLatchesAsTransparent on’, all the latches are required to be unscannable. But in the

above observations it is ‘LD_SCN_I’, i.e. scannable. This issue was discussed with a senior

engineer and they asked me to report this to Chandan Kumar.

2.1.3.2.5 Spread sheet validation

During Async_15 validation, I asked from Chandan Kumar When two FFs and one L have

been controlled by a common source the msg tree points the correct numbers of those

elements attached to the common source. But for incremental schematic only one FF and one

L is highlighted as follows.

53

Figure 2.24: Issue reported to Chandan related to Async_15

What his response to this was “Yes, this is expected. Reason being that if we highlight all

ffs/latches then schematic may become too ‘noisy’. This is an ideal case of putting

spreadsheet support but till then, we only highlight one ff and one latch as an example.”

Months later the development related to the spread sheet had been made available for the

validation. Chandan Kumar has sent an email to Ajanthan Thalaiyasingam saying inputs from

me and Vaibhav Dipankar who is also a trainee in Noida, India is needed for this task. I

communicated with Vaibhav in this regard. At that point of time I had validated the following

rules in advance.

1. Async_07

2. Async_08

3. Async_09

4. Async_13

5. Atpeed_20

6. Clock_11

7. Clock_11_capture

8. Topology_10

What was required to be done is validate whether the exact number of severities are flagged

in GUI and in the temporary file ‘TEST’ when building. There are main three types of

severities in SpyGlass such as ‘Error’, ‘Warning’ and ‘Info’. Spread sheet support

modification adds another severity named ‘Data’.

54

Along with these validations I was asked to fire a regression on DFT by Ajanthan. It was

expected that the test cases related to the above rules should be failed as the ‘Data’ severities

also have been added to the ‘TEST’ file. But the difference should have happened only in the

‘Data’ severity additions. It needed a closer investigation. Apart from spread sheet effects,

few abnormalities were evident in some test cases. I reported those to Ajanthan and he took

corrective actions on those too.

Validation on the following rules was also completed after that.

1. Info_noScan

2. Info_forcedScan

3. Info_noAtspeed

4. Async_11

Building using 'make' command and running through gui using .prj file produced no

difference in result for above rules. And the 'Data' severity results of output

(Work/Linux4/TEST) tally with what has been produced by gui. I reported this too to the

DFT team and finalized.

2.1.3.2.6 Metric Possibilities for Robust Tests

To be more specific, this was the last part of my internship at Atrenta. The engineer in charge

on DFT for interns resigned from Atrenta as he got a scholarship to pursue PhD at NICTA.

After that all the development and verification works related to DFT in Sri Lanka division

was done by Computer Science Engineering Intern Lahiru Lasadun and me with the guidance

of Chandan and Rajesh. I created another copy (using git) of work place of Lahiru and carried

out validation whenever a modification was done.

In previous versions of SpyGlass when a violation is raised for a particular flip flop, the

traversal through that path is blocked and just flags the violation message with respect to that

flip flop. If a user needs to correct such violations then the user should run SpyGlass again

and again in each such modification. Because there could be several violations under a

particular rule but still masked due to a violation occurred on their way. Until such violation

is corrected others might not unveiled.

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Therefore the developers worked on this to output a summary of all such violations in a file

named ‘Robustness audit’ for ‘fullpolicy’ specified SpyGlass execution. This is in the form of

percentages which are listed under each rule. There were several rules under DFT and

DFT_DSM policies which were vulnerable to these modifications. The rules on which this

change is validated are listed below. (These are rules; which were taken as bases; validated

by me and there were more other rules to be validated)

1. Async_02_capture

2. Async_11

3. Clock_04

4. Clock_08

5. Clock_16

6. Clock_17

7. Scan_07

8. Atspeed_03 and Atspeed_04

In all of above the ‘robust’ change is validated with respect to the generated ‘Robustness

audit’ report in SpyGlass environment and in GOLD file using ‘make’ command as well as

using the incremental schematic. At the completion (until resign from the training) sent a

report containing the full summary of validation of each rule with the scenarios and their

observations.

If the unit test cases comes under each rule are not adequate for ‘Robust’ validation then I

created my own to validate the functionalities. The scenarios created under such

circumstances are listed below.

Async_02_capture:

1. Two flip-flops out of 3 are affected due to violation

2. Two flip-flops converge to a ff’s reset

3. Two flip-flops’ asynchronous pins are driven by one flip-flop’s output

4. Two flip-flops’ asynchronous pins are driven by flip-flops’ output but through

different combinational logic

5. One flip-flop which is violating is ‘no_scan’ and one which is violated is ‘no_scan’

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6. Latches come in place of violating flip-flops

7. Black boxes come in place of violating flip-flops

For an example, consider the first scenario.

Figure 2.25: Typical Async_02_capture violation

The above figure gives a typical way of Async_02_capture rule violations. To be violation

free on above rule, the flip flops, black boxes and latches should be avoid from the

asynchronous paths of all the flip flops.

Figure 2.26: Incremental schematic for the first scenario

As to the ‘Async_02_capture’ rule there are two flip flops whose asynchronous pins’ fanin

cones contain flip flops. “Metric possibilities for robust test” document looks at this

modification in the above angle. But one can modify this as to count the number of flip flops

who are part of such fan in cones which is wrong. For this particular example both would

give the following output.

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Figure 2.27: Robustness audit report extraction

For an instance consider the second and third scenarios.

Figure 2.28: Schematic for scenario 2 and 3 respectively

Since the developer had not been confused with the wordings the output percentages are in

the forms of 33.33% and 66.67% respectively which are correct.

Async_11:

1. Three flip-flops out of six are affected due to violation

2. Two flip-flops’ (out of above three – reset) asynchronous pins are connected

3. Two flip-flops’ (out of above three – data) data pins are connected

4. Two flip-flops’ (out of above three – data) data pins are AND’ed before feed in to a

reset of one flop

5. One flop’s (FF3’s) data and reset pins are connected together after removing one flip-

flop (F3)

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6. FF2’s asynchronous pin to FF3’s data pin and other way around.

7. AND gate with FF3’s asynchronous pin with F3’s data pin

8. Using MUXs between FF2 and F2 / FF3 and F3

9. DFF1’s asynchronous pin fan-out and FF1’s data pin fan-in of AND gate (still three

violations)

10. Two AND gates between DFF1 and FF1 connection (still three violations)

Clock_04:

1. Two flip-flops’ (out of three) data pins are driven by two clocks

2. Two flip-flops’ (out of three) data pins are driven by one clock in above (i) design

3. Two clocks are converged so as to feed a data pin of one flop out of two flops

4. Clock blocked by a flop (for the design in (i))

5. Clock blocked by a MUX

6. One flip-flop is defined to be ‘no_scan’

Clock_16:

A bug was detected while validating ‘Robust test’ under this rule. This was reported and

rectified. The bug is described below.

This is related to the unit test case in the following path.

dft/test/Ruledecks/dft/Verilog/Clock_16/case0

The top module diagram is,

59

Figure 2.29: Clock_16 reported bug

As the “Metric_Possibilities_for_Robust_Tests-v6.docx” says for the Clock_16 rule, “Count

the # of FFs with a  data path from a FF that is clocked on opposite edge”

As we can figure out, “q2” and “q3” flip-flops are victims of Clock_04 violation whereas

“q1” is a victim of Clock_16 violation. BTW for the robustness testing (as the above

reference suggests) “q2” is flagged though “q1” is the one which should be flagged. We can

see that in the following too. There, even though the percentages per rule are correct, the

overall percentage is incorrect.

Figure 2.30: Incorrect Robustness audit

Clock_17:

1. Output to d pin of a flip-flop

2. Using two test-clocks

3. Using tri-state buffer at the merging point

60

4. Flip-flops are at both parallel nets

5. Flip-flop with ‘no_scan’ constraint

6. Interchange ‘d’ and ‘clk’ pins’ fan-ins of gating flip-flop (q1)

7. Sequential two violations

8. Sequential two violations with combinational logic in-between

9. Sequential two violations with combinational logic in-between

10. Two gating flip-flops with one being defined as ‘clock_shaper’

11. Feeding more flip-flops from one merge point

2.1.3.3 Post analysis of Phase3 and key personnel involved

In this phase, I was given the freedom of doing things alone but with a minimal supervision.

Initially Eng. Ajanthan Thalaiyasingam assisted me in familiarizing with the working

environment. I had the opportunity to work with internationally recognized highly

experienced engineers in EDA industry. In some circumstances I had to communicate with

the people from research center in Noida, India as well as US. In the later part of the training,

company recruited one new employee to the DFT team and I was appointed to guide him in

the validation of DFT.

Table 2.3: Training areas with personnel involved in Phase3

Training Personnel

Inception of DFT Mohamed Mafraz

Hands on Training for DFT Vetharaniam Kathircamalan

Validation works allocation and guidance Ajanthan Thalaiyasingam

Appointed officer for clarifications Rajesh Kumar (Noida, India)

Team member Vaibhav Dipankar (Noida, India)

Team member from development Lahiru Lasadun

Overall supervision Chandan Kumar (US/India)

61

2.2 Industrial Exposure and Professional Practices

It was a 24 weeks of short term technical training which we were advised about. But the time

I spent in Atrenta did not make me feel that lengthy descriptions. One thing I could not

understand was how the migration of university life to a working life had happened in that

speed. The exposure I got within nearly a six months period of time is immense to word like

this. The training experience related to the field of interest which has been described

throughout the 2.1 section was fully accompanied by the things those are included in this

section. Experience in this magnitude would have been an impossible task to achieve

otherwise.

2.2.1 Development Working Environment

At the very beginning of the training I was provided with all the instructions to cater with the

works flow of Atrenta. Interns were provided with a separate laptop with VNC (Virtual

Network Computing) technology connection to link with the central access. Daily works

were performed through this platform. It is a UNIX based operating system containing

SpyGlass as well as other useful software. A separate account was maintained in order to

perform independent works on my own with the guidance of training in charge.

2.2.2 Conference Calls

During my stay at Atrenta whenever I need a clarification to be questioned I used, provided

outlook account which connects other party by Microsoft exchange server. Sometimes this

was tedious to express the thoughts or directly questioning was easier than mailing to others.

At those circumstances I was informed to contact intended developers via conference call. I

had this type of conferences individually as well as with the team. This made me to improve

my communication skills in discussing technical issues with qualified and experienced

engineers at the other end.

2.2.3 Communication Meetings and Technical Meetings

The top management of Atrenta makes sure that each and every individual is on the track to

achieve its milestones by properly conducting meetings. Purpose is to make sure employees

have properly grasped the objectives of company to become success in the long run.

Therefore the actual and expected figures of each minutes of financial statements is

62

discussed. This gives me the real time impression on industry such as their approach in

addressing the employees through these figures. On the other hand Atrenta conducts technical

related meetings in which the employees can clarify their views on this subject area from

industry experienced and skilled seniors of the company. As a guideline Atrenta conducts

sessions by personnel in the company on their expertise. I got few opportunities to participate

in these sessions.

2.2.4 Presentation on Training

At the last part of the training I was asked to conduct a session including the experience and

knowledge acquired during training period. I had to go back in daily diary and mail history to

refresh the memory in Atrenta from very first day and prepared the presentation. Presentation

was announced to the every official in the local branch. Employees gathered in the

conference room and I could conduct the presentation with answers directed to the occasional

questions raised by them.

2.2.5 Working with Legendary Companies

The verification phase of DFT was initially guided by Eng. Ajanthan Thalaiyasingam who

was a developer in DFT. Most of the improvements were suggested by Intel in Penang. They

use DFT extensively. Whenever they need a modification to be done or introduce a new rule

in some concerned areas they report Atrenta. I could also involve in their verification which

gave me a great pleasure to work with them in this extent. One of the other companies that I

worked with was MentorGraphic which is a giant company in EDA tool industry. In there I

verified ETChecker which is a custom product provided to MentorGraphic. Along with these

companies there were other companies as well which gave me the opportunity to work in

their development tasks.

2.3 Administrational and Office Practices

2.3.1 Daily record of in and out time

The normal scheduled hours in local branch are 8.00 am to 5.00 pm as mentioned in the

contract. As the company’s culture is more like human oriented in managing employees more

emphasis is given on employees’ contribution than working hours. On this comprehension it

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is normal that an employee comes late or early in the morning but covering average 9 hours

and make sure the required input is given. By the way all the personnel in the company is

required to record office in-time and out-time with signature on daily basis.

2.3.2 Inventories

By the time I stepped in to Atrenta I was provided with all the necessaries what a new

employee would get. It included a separate laptop, power cable, battery, work station,

telephone with extension, etc. In addition to that when it comes to projects inventories like

FPGA was also provided. It was my responsibility to make sure the inventories are not

misplaced or damaged and reusable after my resignation. I communicated with IT assistant

when there was a problem with the inventories stated above.

2.3.3 Contract of employment and termination

After the interview I had in Atrenta before the internship I was informed that I have been

selected for the short term technical training. After few days I was requested to meet the

Human Resource Assistant in order to sign the employment letter. I went there and signed the

document provided such as terms of conduct, employment letter, invention permit letter, etc.

Photocopies of the original documents were given for the references. At the end of the

training I was again asked to sign few documents including termination letter.

2.3.4 Pay slips and EPF account

During my stay at Atrenta, I was entitled to a monthly allowance which was being remitted to

the provided bank account. They got my signature on two pay slips where one of them was

given back to me for reference. A portion of that was credited to another account which is

normally known as EPF (Employees’ Providence Fund). This is on intension of continuing

until my retirement with the commencement of work after the university education.

2.3.5 Other activities

Atrenta had provided several other facilities in order to help the employees brainstorm. In

that a table tennis board, carom boards, a dining room with sweet items including biscuits,

etc. had been provided. This helped us increase concentration and alertness, develop technical

thinking skills, providing social and recreational interaction moreover as a means of reducing

depression in the working place which results in high productivity. All the facilities stated

64

above were offered to all the interns as well. Our responsibility was to manage our time in in-

and-out works in the office making sure that times on other activities lead to high

productivity in our task completion.

65

3 Conclusion

It was a dream venue that I wanted to work with. The opportunity came was not just in time

incident. It had a long process which gave me the real experience in recruitment. Once the

internship period was announced, first of all I tried to comprehend the profession which

matches me most with the strength and weaknesses I have. At the end I took the decision on

going with the ‘Electronic’ tagged company. Before I applied to Atrenta I have

communicated with people who had experience in this regard. They convinced me that

Atrenta would be a one-off opportunity that I would be delighted with. So I decided to raise

my hand on applying to Atrenta with three other batch mates for two positions that Atrenta

offer.

In the interview process I could manage myself to answer a small quiz on ‘digital design’.

With that I was taken through stiff questionnaires from a senior verification engineer in the

company including technical aspects. Moreover they announced after couple of days only one

person is recruited and I was the one who was get selected. That was a wordless moment.

Being in Atrenta family gave me the real exposure on evolving a company of this magnitude

to a higher margin in the industry. Though Atrenta started with few engineers in November of

2012 the number of skilled graduated and skilled employees working at Atrenta is now grown

up to 50. This evidences the fact how attractive the company was of hiring high skilled

workforce in this short period. During my stay the company was expanded their workplace

by fabricating and partitioning another floor in the same building. It was followed by a

change in working place which made the working place more enthusiastic.

Every personnel in the company assisted the interns wherever it was needed. We never saw a

gap between senior employees and interns. Such was the culture they had been evolved with.

Not only local officers but also in verification progresses I got to know foreign expertise in

Atrenta through conversations happened between us. Being in a Research and Development

center in the country I was provided with the resources an average employee is provided. I

could manage my work flow flexibly as the employees are given the freedom to decide the

work style. The collaborative native in discussions, conferences, meetings, etc. paves the way

of building my professional career. The team including officials from local office and

overseas gave me the feeling of being in a team in industry level. One of the senior directors

in the company commended the interns for their great contribution at the end of the training.

66

3.1 Improvement from last year’s internship program

In last year training program, only two interns from our department were selected as the first

group of internship in Atrenta. They worked together in verification processes. As Atrenta

has two divisions such as Software and Verification, the recruitment of interns should have

been considered upon these factors too. But since this was not considered, last year’s interns

had suggested recruiting interns in both divisions. As par to this suggestion Atrenta could

recruit interns in both divisions in this year. This was very useful as in modifications or

improvement of products; we both could assist each others to resolve their concerns

collaboratively. Since the internship program last year was the first time Atrenta offered, the

facilities provided was a concern to the interns as they have indicated in their suggestions.

But this year this was not the case as adequate facilities for an average employee had been

granted.

3.2 Weaknesses Noticed and Suggestions to Improve

This is the second time that Atrenta is offering internships for short term technical trainees.

Thus far Atrenta could maintain its standard in the program without ruining the company

image by recruiting undergraduates who undergoes stiff quizzes and questionnaires

interviews and providing timely managed training. This should be undoubtedly commended

as they could do this within one year of experience. But for the sake of gratitude I would like

the following few points are also taken into account before the recruitment.

Last time there were two verification interns but this time it was reduced to one. If the

number of interns could be increased the interns could perform their tasks as a team

which would give them more exposure in the industrial environment. This could be in

turn a benefit to the company as well, as more undergraduates would come to know

about the environment of the new ventured company.

The verification works carried out in training could not be pursued further after the

training in the final year. This is due to the lack of resources available in this

magnitude in university. This could be overcome by investing in a research laboratory

in digital electronics related to EDA industry. This would be beneficial to the

company as well, as more students will be aware about the industry.

Frequent progress reviews would give interns an opportunity to review themselves.

This would be resulted in highly motivated trainees in their respective functions.

67

Annex I

68

69

Annex II

module LogicCalculator(input in1,in2, output o1);

OrGateOut orGateOut (in1, in2, o1);

AndGate andGate (in1, in2, o1);

endmodule

module OrGateOut (input in1, in2, output o1);

OrGateIn orGateIn(.*);

endmodule

module OrGateIn (input in1, in2, output o1);

assign o1 = in1 | in2;

endmodule

module AndGate (input in1,in2, output o1);

assign o1 = in1 & in2;

endmodule

module NumericalCalculator(input in1, in2, output o1);

Addition addition(in1, in2, o1);

Subtraction subtraction(in1, in2, o1);

endmodule

module Addition(input in1, in2, output o1);

assign o1 = in1 + in2;

endmodule

module Subtraction(input in1, in2, output o1);

70

assign o1 = in1 - in2;

endmodule

module top(input in1, in2, output o1);

LogicCalculator(in1, in2, o1);

NumericalCalculator(in1, in2, o1);

endmodule

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