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- - - - - compter-aided circuit analysis results are only as accurate as the models used. With the

rapid development of fabrication technologies that enable the use of deep submicron

devices, updated models are needed by circuit designers. It is generally necessary to

extract model parameters fram measureed transistor data obtained for a given fabrication

process.

In this thesis, the procedure of extraction and optimization of the BSIM3 model

parameters for the Mitel 1.5pm process using the TMA's AURORA software is described.

The accuracy of the optimized set of parameters of the BSIM3 MOSFET model for use

in the Spectre simulator is demonstrated by comparing the simulation results with the

existing levelî model, as well as meamrement for the different size transistors, which

h l u d e Mde-long transistors, wide-short transistors as well as narrow-long transistors.

Two amplifers, a twestage amplifier and a folded-cascode amplifier fabricated by using

the Mitel 1.Spm process, are discussed. The method of testing and simulating these two

amplifiers is described. The accuracies of the optimued BSIM3 model parameters used

in simulating the integrated circuits are evaluated and shown by comparing simulation

results using the BSIM3 model and the level3 model, respectively, with measurement.

This work concludes that the simulation results ushg the optimized set of BSIM3

model parameters are more accurate than those using the level3 model related to

measurement.

Table of Contents

List of Tables

List of Figures

Chapter 1 Introduction

1.1 Historical Background

1.2 Research Presented

1.3 Thesis Outline

Chapter 2 Parameter Extraction and ûptimization

2.1 BSIM3 Model

2.1.1 Threshold Voltage

2.1.2 Subthreshold Current

2.1.3 Drain Saturation Voltage

2.1.4 Drain Current for the Triode Region

2.1.5 Drain Current for Saturation Region

2.2 Extracting SPICE Parameters for the BSIM3 Model

2.2.1 First Optimization Step

2.2.2 Second -on Step

2.2.3 T M Ophimion Step

2.2.4 Fourth Optimization Step

i

iv

vii

L - -r

2.2.7 Seventh Optimization Step

2.2.8 Eighth ûptimization Step

2.2.9 Ninth Optimization Step

2.2.10 Tenth Optimization Step

2.2.1 1 Eleventh Optimization Step

2.2.12 Twelfth Opthkation Step

2.2.13 Thirteenth ûptimization Step

2.2.14 Fourteenth Optimization Step

2.2.15 Fifteenth ûptimization Step

2.2.16 Sixteenth ûptimization Step

2.2.17 Seventeenth Optimization Step

2.2.18 Eighteenth Optimization Step

2.3 o p b h t i o n and Adjustment Results for Spectre

Chapter 3 Accuracy of the Simulation Results with Spectre

3.1 Simulation Results for Wide-Long Devices

3.2 Simulation Results for Wide-Short Devices

3.3 Simulation Results for Narrow-Long Devices

Chpter 4 Analyzing the Test Amplifsers

4. 1 Two-Stage Amplifier

5.1 DC Open Loop Voltage Gain

5.1.1 Test Method and Verifying the Test Technique

5.1.2 Cornparhg Simulation with Measurement

5.2 Large Signai Output Voltage Swing

5.3 Output Resistance of the Test Amplifiers

5.3.1 Memement and Simulation Results for the TSA

5.3.2 Measurement and Simulation results for the FCA

5.4 Frequency Response of the Amplifiers

5.4.1 Measurernent and Simulation of the TSA

5.4.2 Measurement and Simulation for the FCA

5.5 Large Signal Common Mode Characteristics of the TSA

5.5.1 Common Mode Gain and CMRR for the TSA

5.5.2 Common Mode Gain and CMRR for the FCA

Chapter 6 Conclusions

References

Appendix A Extracting Steps and Fitting Results

Appendix B ûptimization and Adjustment Results for Spectre

Appendix C Parameters of the MOS Level3 Model

Appendix D Parameters of the BSIM3 Model

iii

and the Test Technique

LIST OF TABLES

Table

3.1-1 Cornparison of the simulation results with measurement for

NMOS devices with W/L=50/50

Cornparison of the simulation results with measurement for

PMOS devices with W/L=50/50

Cornparison of the simulation results with measurement for

NMOS devices with W/L=50/ 1.5

Cornparison of the simulation results with measurement for

PMOS devices with W/L=50/1.5, Vgs=-2V

Cornparison of the sirnufat ion results w ith measurement for

PMOS devices with W/L=50/1.5, Vgs=-4V

Cornparison of the simulation results with measurement for

NMOS devices with W/L= lS/lO, Vgs=2V

Cornparison of the simulation results with measurement for

NMOS devices with W/L= 1.51 10, Vgs=4V

Cornparison of the simulation results with measurement for

iv

Page

26

27

29

29

30

31

32

Performance characteristics of the FCA 39

Cornparison of the simulated dc voltage gains with the load

resistances and the open circuit for the TSA 44

Cornparison of the measured dc voltage gains with the

simuiaîicm results from the different rnodels for the TSA 44

Comparison of the simulated dc gains with the different load

resistances and the open circuit 45

Comparison of the measured dc gain with the simulated results

from using the different models for the FCA 46

Cornparison of the simulated transconductances using different

bias resistors R from the BSIM3 model with measurement

for the FCA 47

Measured and sirnulated output voltage swing for the TSA 48

Measured and simulated output voltage swing for the FCA 48

Cornparison of the simulated and measured magnitude of the

output impedances with frequencies for the TSA 53

Cornparison of the magnitude of the output impedances fiom the

BSIM3 model with fiequency with those from the level3 model

for the FCA 55

DC gains with the load resistmces and the caiculated output

the different models for frequency response, for the TSA 59

5.4-2 Cornparison of the measurernent with the simulation results of

the frequency response for the different models for the FCA 60

5.5- 1 Camparison of the measurement with the simulation of the

BSIM3 model for the conmon mode gain with input magnitude

for the TSA 63

5.5-2 Cornparison of the measurement with the simulation with

fiequencies for the common mode gain for the TSA 63

5.5-3 Cornparison of the measurement of the common mode rejection

ratio with the simulation result fiom the BSIM3 model

for the TSA 64

5.5-4 Cornparison of the measuhement with the simulation results

of the BSIM3 mode1 for the common mode gain at lOOHz with

input signal for the FCA 66

5.5-5 Comparison of the measurement with the simulation results

with frequency for the common mode gain for FCA 66

5.5-6 Cornparison the measmement of the common mode rejection

ratio with the simulation result fkom the BSIM3 mode1

for the FCA

Large signal model of an n-channel device

Resulting fit to wide-long devices with W/L=50/50

Resuiting fit to wide-short devices with W/L=50/3

Resulting fit to wide-short devices with W/L=SO/l .S

R d t i n g fit to narrow-long devices with W/L= 1 .S/lO

Device test circuits used in simulation with Spectre

Simulation r d t s with Spectre using the extracteci

BSIM3 model parameters

Comparison of sunulation results of the different models

for an NMOS device with W/L=50/50

Comparison of simulation results by using the different models

for a PMOS device with W/L=50/50

Comparison of simulation results fkom the different models

for an NMOS device with W/L=50/1.5

Comparison of simulation results fiom the different models

for a PMOS device with W/L=50/1.5

Comparison of simulation resuits by using the different m d e k

for an NMOS device with W/L=1.5/10

Cornparisan of simulation r d t s using the different modeis

fa a PMOS device with W/L=1.5/10

vii

Circuit for testing dc gain using SPA

Simulation circuit for dc gain

DC tranfer characteristics of the TSA

Measured and simulated dc characteristic of the FCA

Cornparison of simulated results of dc characteristic for FCA

Test circuit for short-circuit

Measured and simulation results using the BSIM3 mode1

for short-circuit

Circuit for testing output resistance

Simulation results of the output resistance by using the different

models for the TSA 49

Simulated and measured currents 50

Test circuit of the dc gain with load resistance 50

Test circuit used in both the simulation and the measurement

for measuring the output resistance with frequency for the TSA 51

Compatison of the simulation results with memement for

the sinewave test voltage for the TSA 52

Simulated current with the test voltage for the FCA 54

Simulateci curreat with the test voltage for the sinewave test

signal for the FCA 54

viii

5.4-2 Frequency response of the TSA 58

5.4-3 Frequency response of the FCA 60

5.5-1 Test circuit of the cornmon mode gain for the TSA 62

5.5-2 Measured and simulated results of the cornmon mode

gain for the TSA 62

5.5-3 Shulated outputsignal for the common mode gain using

the BSIM3 mode1 for the FCA 65

5.5-4 Measured result with 100Hz, 400mv peak to peak input sinewave

signal for the common mode gain test for the FCA 65

1 would like to express my gratitude and appreciation to my thesis supervisor, Professor

J. P. Burgess, for his support, guidance and valuable advice.

1 am also gratefd to each member of the VLSI group for their help and

suggestions.

Finaiiy, 1 would like to thank Mite1 Semiconductor Components Division for

providing the measured data, used for the mode1 parameter extraction and optimization.

coniputer-aided circuit analysis resdts are only as accurate as the models used. With the

rapid develapment of fabrication technologies that has enabled the use of deep submicron

devices, updated rnodels are needed by circuit designers.

There are two comma problems faced in simulating MOS circuits, particularly

analog circuits. The first is the develapment of modek which are suitable for the new

fabrication technologies using short channel devices. The second problem is the

specifcation of mode1 parameters. Although most MOS models are based on physical

th-, some parameters do not have weii defined physicaliy-based values, and there are

other parameters for which the physical values do not give the best fit to actuG device

characteristics. So, it is generally necessary to extract model parameters from measured

transistor data o W e d for a given fabrication process [l].

The common level3 model is suitable priniarily for simulating devices with

channel lengths dom to 2pm, and does not work well for simulating the device output

resistance 131. A new model is desired to meet the needs of simulating the characteristics

of short channel devices. The BSIM3 model was developed for this purpose, and is

reputed to have the following advantages [Z, 8, 101. Firstly. it is suitable for simulating

devices with channel 1ength.fram lmg to about 0.2pa S e d y , ït can represent not only

the m e n t but also the output resistance accurately so that it is suitable for both digital

and d o g applidcms. Tbirdly, it has more model parameters to represent narrow

channel devices and gives a more accurate mpresentation of these devices than the level3

The Spectre simulator provided by Cadence Design System supports eight

MOSFET models [2], including levell, level2, level3, level8, BSIM1, BSIM1-5, BSIM2

and BSIM3. However, the BSIM3 model parameters are not available for the Mitel 1.5 y m

process sttpported by the Canadian Microelectronics Corporation (CMC). It is desired to

extract an o p h i z d set of paramaeas fa the BSIM3 model for this process to enable the

BSIM3 model to be used in the simulation of analog and digital circuits.

1.1 HISTORICAL BACKGROUND

The modeling of MOS transistors for computer-aided design has been driven by needs of

digital and analog circuit designers for many years, and many models have been

developed and applied in circuit sirnulation.

The levell, the level2 and the level3 models have been in existence for many

years. The levell model [3] used in the SPICE simulator is basically the rnodel proposed

by Shichan and Hodges [4] in 1968, which contains fairly simple expressions and is

most suitable for preliminary analysis. The level2 model was developed by Meyer [SI in

1971. This model contains expressions fiom detailed device physics and eliminated the

simplification mode in the levell model. It gives a more accurate expression for drain

curent by taking into account the effect of the voltage in the charnel on the charge due

to the uncovered accepta a t m in the depletion region However, this rnodel does not

work well for srnail geometry transistors [q. The basic equations of the level3 model

were proposed by Dang 171. This model represents an attempt to pursue the semi-

threshold voltage and mobility. But this mode1 only approximates device physics and

relies on the praper choh of the empirical parameters to reproduce device characteristics

[ a

The BSIM1 model is based on îhe device physics of srnall-geometry MOS

transistors [q, 19-IO], and was developed by Sheu in 1985. It is adequate for mdelling

MOS transistars with dimensians limited to Le 1 prn and ta= 15nm, and achieves accuracy

for shorter transistors by substituthg polynomid functions of the bias voltages for the

parameters of the simple model. It replaces each single parameter with a triplet of

paranieters representing the wide-long parameter, length correction panuneter, and width

correction parameter. This causes the model to have numerous parameters, many of which

do not have a direct physical interpretation Also, the model does not correctly predict the

device output resistance and has a constant current offset in the strong inversion region,

which may cause large errors in simulation results when the transistor operates at low

currents 131.

To overcome probiems of the BSIMl model, the BSIM2 mode1 was developed by

Jeng [Il] in 1990. The BSIM2 model is a BSIM1-based, semi-empincal model intended

for deepsubmicrometer transistors. This model overcomes some of the shortcomings of

the BSIM 1 model and is suitable for simulating the drain current and output resistance

of MOS transistors with gate oxide thicknesses as thin as 3.611.. and channel length as

smaii as 0.2pn However, this model sometirnes produces negative conductances in the

The BSIM3 model [2] is a physics-based, predictive, and computationally efficient

advanced MOS transistor model for VLSI circuits. The BSIM3 model abandons the

approach of representing single parameters with a triplet of parameters and, therefore, has

fewer pmmdm than the BSIMl and the BSIMZ modeis. It is suitable for simulating the

characteristics of MOSFETs with long to submicron channel length.

1 RESEARCH PRESENTED

The overall objective for this research is to produce an opthized set of parameters of the

BSIM3 MOSFET model f a the Mitel 1Spm p'ocess for use in the Spectre simulator, and

&O to document the accuracy of the resultanî BSIM3 model and parameter set. This will

involve cornparisons with the existing level3 model as well as measurement and

simulation resultts for two IC test amplifiers fabricated with the Mite1 1.5 pm process.

This work will involve the following main steps;

1. Extract the -3 model patametm using the measured transistor data for the

Mite1 1 .5 pm process;

2. Adjust the extracted BSIM3 model parametes (intended for the SPICE

simulator) in order to optimize the parameter set to be used in the Spectre simulator.

Spectre is 3-5 times faster than traditional versions of the SPICE sirnulator 1131;

3. Evaluate the accuracy of die simulation results o b i m i using the BSIM3 model

with Spectre for different size transistors;

4. Design a folded-cascode test amplifier for fabrication using the Mite1 1.5pm

4

the folded-cascode amplifier, and the CMC standard two-stage amplifier, fabricated with

the Mitel 1.5pm process, by comparing the measurement with the simulation results using

the BSIM3 model and the level3 model, respectively.

This thesis is divided into six chapters.

Chapter two describes the BSIM3 model and the model parameter extraction as

well as optimization.

Chapter three focuses on evaluating the accuracy of the optimized- set of

parameters of the BSIM3 model used for simulating n-channel and p-channel devices in

the Spectre simulator by comparing with measurement data and also with the simulated

results using the MOS level3 model.

Chapter four describes the two test amplifiers, the folded-cascode amplifier and

the two-stage ampLüïer.

Qiagter five demonstrates the accuracy of the optimized parameters of the BSIM3

model used to simulate the two integrated circuit test amplifiers with the Spectre

simulator by cornparhg the simuiated results with measured results as well as the results

using the level3 model.

Qiapter six conclusions camxnhg the accuracy of the optirnized model

parameters used in simulaîing the MOSFET 1-V characteristics and the integrated test

ampiifier circuits.

and uptimize a set of parameters for the BSIM3 model for the Mitel 1 . 5 ~ process. The

measured MOS transistor data used in this extraction was provided by Mitel.

The material contained in this chapter:

1. Introduces the BSIM3 rnodel and model equations briefly;

2. Shows extraction steps in obtaining a set of parameters of the BSIM3 model

using the AURORA software;

3. Discusses some parameters which need to be optimized and adjusted

for use in the Spectre simulator.

2.1 B S W MODEL

The f o d a t i o n of the BSIM3 model is based on the device physics of small-geometry

MOS transistors. Special effects included are: 1. Vertical field dependence of carrier

mobility; 2. Carrier velocity saturation; 3. Nonuniform depletion; 4. Lateral nonuniforrn

doping; 5. Depletion charge sharing by the drain and the source; 6. Drain-induced banier

lowering 7. Peak-chmel doping concentration; 8. Channel length modulation; 9. Channel

width reduction; 10. Subthreshold conduction; 11. Source/drain parasitic resistance.

Figure 2.1-1 is the equivalent circuit of the MOSFET suitable for transient analysis

[3]. The ID, equations describe the basic DC effects of the MOSFET. The effects of the

gate capacitance, and source and drain diodes are considered separately from the DC ID,

equations. The defdtion of the BSIM3 rnodel parameters refers to Appendix D.

Flgure 2.1-1 Large signai mode1 of an n-channel device

2.1.1 THWISHOLD VOLTAGE

There are 11 parameters in the threshold voltage expression. These include threshold

voltage at zero body bias, vtho, narrow width coefficients, k3, k3b, wO, and coefficients

of short-channel effects, dvtû, dvtl, dvt2. The substraîe voltage effect and the nonuniforni

substrate doping effect are also included by using parameters kl , k2, and nlx in the

threshold voltage calcdation. The threshold voltage is modeled by [2]: 1 1

where

where npeak is the peak-channel doping concentration.

Three subthreshold ment modeIs can be selected by setting up the subthmod parameter.

If subthmod is set to O, the drain current is zero when the gate voltage is less than the

threshold voltage. If subthmod is set up to 1, the subthreshold m e n t is always calculated

and added to the drain current for the sirmg-inversion region, regardless of the operating

region. If subthmod is set to 2, a transition region between the subthreshold region and

the strong-inversion region is created. This transition region provides smwth switching

between the subthreshold and the strong-inversion regions. The subthreshold current

expression for subthmod=2 is given by [2]: If Vos, s Va,-V,,, the drain current is:

If V--Vdo3( s V,, s Vihidi+vdIbl, the device is operated in the transition region

and the drain current is given by:

where Lw is the subthreshoId current evaluateû at vOST3vgbwgbwvdib,, and 1- is the strong-

inversion drain current evaluated at V,,, = Vw,,+Vd,, g* and g*, are the

2.1.3 DRAIN SATURATION VOLTAGE

There are two expressions for the saturation voltage V,,, which depends on the drain-

source resistance parameter %, [2].

where

where rdsO is the total drain-source resistance, and rdsw is the width dependence of

drain-source resistance.

2.1.4 DRAIN CURRENT FOR THE TRIODE REGION

The total drain cment is the sum of the strong- and weak-inversion drain current. The

strong inversion region is separated into the triode and saturation regions. When V,,, z

O and V,, s VDSAT, the transistor operates in the triode region. In this region, the effect

of the source-drain parasitic resistance is included in the drain current expression which

is given by [Z]:

where & is the drain current in the triode region without the presence of source and

drain parasitic resistance.

2.1.5 DRAIN CURRENT FOR SATURATION REGION

When the voltage V,,, > 0, and V,, r V,,,, the transistor operates in the saturation

region. The drain current is given by [2j:

where

Two different modes for caiculating Va can be selected; satrnod= 1 or satmod=2.

If satmod= 1, Va is calculated by:

If satrnod=2, Va is given by:

2.2 EXTRACTING SPICE PARAMETERS FOR TEE BSIM3 MODEL

In this extraction procedure, parameters were extracted sequentially, one at a tirne or in

small groups. The value of each pararneter was assurned f i e d and accurate for use in

exîracting M i e r parameters. A small portion of the mode1 and data from a limited part

of a device's operating range were used in extracting each pararneter.

The basic measured data used in this research was provided by the Mite1

which were obtained from 5 different size transistors for n-channel and p-channel devices,

respectively. These data files included linear region 1-V characteristics, saturation 1-V

characteristics as well as gate characteristics at high V,. Further details on the data files

are in Appendix E.

A total of 18 optimization steps was required to complete this process. The

detailed extraction results are shown in Appendix A.

2.2.1 FIRST OPTIMIZATION STEP

The wide-long gate characteristics (W/L=SOp/50p) at zero back-bias were used to extract

the parameters vth0, uO, ua and ub in this step. The parameter K3 was set to zero to turn

off its effect and the effect of uc was not considered due to zero back-bias, V,,=O. The

parameter rdsO was fixed to be zero, and the initial values of the parameters rdsw, keta

were zero. Thus, the drain current c m be sirnplified as follows:

Po hfi= V +Vth V +vth

1 +ua( " )+ub( C )'+""vBS tox fox

For this wide-long device, the short- and narrow- channel effects were negligible.

111- OCICiVlLU J L b p WCW b V W A U U W b U A W p U i L I l A u b Y A U T U A W ) UU, UV ( Y A U U A . A A A w w a U w U A A u A s

(W/L=SO/l.S) gate characteristics at zero back-bias were fitted. In order to get the

opsimization to fit the measwed data properly, the parameters vth0, ua and ub were also

fitted in this step. However, only the optimized value of dl was wanted. The values of

vth0, ua and ub were discarded and the previous values were brought back.

2.2.3 THIRD OPTIMIZATION STEP

The third m o n step fitted the narrow-long (W/L=l.Sp/lOp) characteristics in the

linear region at zero back-bias with the parameter dw and also the parameters vthû, ua,

and ub in order to get the m o n to fit the measund data properly. The parameters

vthû, ua and ub were reverted to theu vaiues from step 1.

2.2.4 FOURTH OPTIMIZATION STEP

This step refitted the wide-long gate characteristics at zero back-bias, W/L=SOp/SOp, with

parameters vth0, u0, ua, and ub. The parameters dl and dw were obtained from the

previous two steps. This irnplied that the effective channel length and the effective width

were ccmsidered when the parameters vth0, u0, ua, and ub were fitted in this step, and the

parameter values of vih0, uo, ua, and ub were closer to the accurate values, so they were

kept in this step and would be use. to extract d e r parameters in the next step.

2.2.5 F'IFîH OPTLMlZATION STEP

The parameters kl and k2 were extracted by using the linear region 1-V characteristics

2.2.6 S I X T E OPTIMIZATION STEP

This step fitted the wide-long gate characteristics (W/L=50p/50p) at al1 back-biases with

pinamtas kl, k2, ua, ub and uc. AU the parameters optimized in this step were effective

parameters for îhe next step. The resulting fit was very poor at the substrate voltage

eqwî to -W. SO, to obtain aptimization, the parameter vth0 was refined in this step for

p-channel transistors.

2.2.7 SEVENTH OPTIMIZATION STEP

This step was to extract the parameters vth0, ua, ub, uc, dl, rdsw, dvt0, dvtl, dvt2 and

nix. Ihe wide-gate (W-SOpm) characteristics with different lengths (L=50p, 3 y or 5 p,

1 . 5 ~ ) at al1 back-biases wae fitted. The channel length of the p-channel device was 5 y m

instead of 3pm used for the n-channel device in order to obtain the best fit.

This step is unique to the BSIM3 mode1 to fit multiple devices. It is necessary to

use three different size devices for obtaining parameters dvt0, dvtl, and dvt2.

2.2.8 EIGHTE OPTIMIZATION STEP

This optimizaton step fitted the narrow-long gate characteristics at ail back-biases (V,=O,

-2.N. -N) with parameters dw, k3, wû, k3b and rds0. The W/L ratio of the measured

devices is l.Sp/lOp, which is the most narrow and langest one provided by Mitel.

22.9 NINTa OPTiMtZATION STOP

Step nine fitted the wide-long drain charaderistics at zero back-bias with parameters vsat

15

devices, and implications for the values of dl and dw because of the way a0 modifies the

effective threshold voltage. It means that fitting to the saturation region ruins the fit in

the linear region.

2.2.10 TENTH OPTIMIZATION STEP

The tenth -on step was to re-extract pararneters vth0, ua, ub, uc, dl, rdsw, dvt0,

dvt 1, dvt2 and nlx. The wide gate (W=50p) charaderistics with different lengths (L=SO p ,

3p or 5p, and 1 . 5 ~ ) at all back-biases were fitted. Because the parameters vsat and a0

were extracted in step 9, the pararneters needed to be refitted. Ideally, each succeeding

strategy step has no affect on the quality of the fits to previous strategy steps. However,

same parameters extracted in the previous step were somewhat affected. The curent in

the linear region can be expressed by[7]:

From the above equations, it is obvious that the parameters a0 and k l modify A,, which

modifies tbe effective tfiresh01d voltage. If a0 is exim%d, the value is changed. Thus, the

threshold voltage should be different, and ail related parameters should be different from

This step was to reurtrad the parameters dw, k3, wû, k3b, rds0 for narrow-long devices

with W/L=l.Sp/101.~. The m o n for re-extracting these parameters is that the parameter

dw was damaged by the new value of aO. Step 11 is identical to the tenth step.

23-12 TWELF'ïH OPTLMIZATION STEP

The twewi step fitted the wide channel (W-50p) drain 1-V characteristics, with lengths

(L= 1.5 p, 3 p or 5 p) varied at zero back-bias with parameters vsat, al, and p h This step

attempted to fit Gd in the lower V, portion of the curve where channel length modulation

effects dominate.

2.2.13 THI'RTEENTH OPTLMIZATION STEP

This step was to fit the wide channel (W=50p) drain 1-V characteristics, varying channel

lengths (L-1.5 p, 3 p or Sv) at zero back-bias with parameters pclm, pdibl 1 , pdibl2, and

drout. Parameters pdibll, pdib12 and drout are relevant in the medium V, region where

drain-induced barrier lowering effects dominate, but step 13 fitted over the whole range

of V, and also used parameter pclm.

2.2.14 FOURTEENTH OPTIMI[ZATfON STEP

This step repeated step 13 but fitted to the target log (Gd), without fitting to ID.

2.2.15 OPTIMIZATION STEP

Siep 15 concluded the Gd optimization steps by fitting the wide channe1 (W=SOy) drain

are relevant in the high V, region when substrate current-induced body effects dominate,

so TMA restricts the range of V, to above 4.5 volts.

2.2.16 OPTlMIZATION STEP

The parameters nfador, voff, vglow, and vghigh were extracted in this step by using the

wide channel (50prn) subthreshold region, varying channel lengths at zero back-bias.

2.2.17 SEVENTEENTE OPTIMIZATION STEP

This step was to extract the parameters etaO, etab and dsub by using the wide channel

gate characteristics at high VdS vafying Iengths and ali back-biases.

2.2.18 EIGHTEENTH OPTIMIZATION STEP

The last optimization step fitted the drain characteristics of the wide channel devices

(50pm) for three different lengths and non-zero back biases with the parameter keta.

IXhe final drain characteristic fittings for four representative different size devices

using the AURORA SPICE simulator are shown in Fig. 2.2-1 through Fig.2.24. The

resuit fittings for both K and P- devices with Wfi=50p/50p are shown in Fig.2.2-1. The

result nttings for an NMOS device with W/L=50p/3p and a PMOS device with

W&=5ûp/Sp are shown in Fig.2.2-2. Fig. 2.2-3 shows the resulting fits of the device with

W/L-50p/1.5pI for both NMOS and PMOS. Fig.2.24 shows the fit for the narrow

chanrile1 devices, W/M.S p/lOp for the n~hannel device, W/L=3 pl10 p for the p-channel

device.

(a) (b) Figure 2.2-1 Resuiting fit to wi&-long devices with W/L=SOp/SOp. (a) NMOS. (b) PMOS

Figure 2.2-2 Resulting fit to wi&-short devices. (a) NMO W/L=50p13p. (b) PMOS W/L-5015

Figure 2.2-3 Resulting fit to wide-short devices with W/L=SOp/1.5p: (a) NMOS; (b) PMOS

19

Flgure 2&l Resulting fit to namw-iong devices: (a) NMOS with W/L= 1 .S/lO; (b) PMOS with W/L=3/10

2.3 OPTIMIZATION AND ADJUSTMENT RESULTS FOR SPECTRE

The set of the parameters for the BSIM3 mode1 obtained from the TMA's extraction

software was next used to simulate n- and p-channel transistor 1-V characteristics in the

Spectre simulator. Simulation circuits are shown in Fig. 2.3-1. Sample results for n- and

p-charnel devices are shown in Fig. 2.3-2. It is clear that the simulation results do not

always agree well with the measured data. The simulation results were almost the same

as the fitted plot in Fig.2.2-1 for wide-long devices (NMOS and PMOS), but there are

some problems for short channel devices. There may be two reasons for these problems.

(a) Figure 2.3-1 Device test circuits used in simulation

(b) with Spectre; (a) NMOS, (b) PMOS

Figure 2.3-2 Simulation resuits with Spectre ushg tbe extracted BSIM3 model parameters which were not adjusted: (a) nchannel transistor with W/L=SOp/l.Sp; (b) nchannel tratisistor with W/L40p/SOp; (c) p- channel transistor with W/L-SOp/l.Sp; and (d) p-channel transistor with W/L=SOp/SOp

Fhst of A, certain extracted parameters are not accurate ( Appendix A). A typical

extraction procedure was used to extract the BSIM3 model parameters. For example, the

extraction procedure found the threshold voltage and mobility-related parameters u0, ua,

ub and uc in the linear operation region, and then, used these values to fmd the channel

length modulation, channel-width reduction, then, found the velocity saturation, and so

on. "Several difficulties may be encountered with this procedure. First, the sequential

method of extraction does not account for the interaction of parameters, or for the effect

models) may not be taken into account when extracting mobility, and it is often found

that the m o b ' i reduction parameters obtained in the Wear region are not appropriate

in saturationM[l]. Since there is interaction between the parameter values, several

cambiflfftions of values provide a working fit to the measured characteristics. Thus, it is

not always clear which vahies are tnily correct.

Secondly, different simulators were used in optunization and simulation,

respectively. The SPICE simulator was used to extract the parameters by the TMA

optimization program, and these parameters were used to simulate 1-V characteristics with

the Spectre simulator. Basically, SPICE and Spectre are compatible, but they are not

exactïy the same. For example [2], in SPICE for the level 1-3 models, if kp is given but

not uo, uo is not calculated from kp. The default value of uo is used. If both kp and uo

are specified, SPICE does not check the consistency between them. In Spectre, kp and uo

are always consistent. This can cause the simulation results of Spectre and SPICE to be

different. SPICE uses kp to evaluate the drain cment while it uses uo to evaluate the

drain saturation voltage V,, Often only kp is specified in the model. SPICE then

assigns a default value to uo, but Spectre calculates uo from kp. This usually causes drain

currents to be different in Spectre and in SPICE. Doubtless, there are some additional

differences m the SPICE and Spectre simulations with the BSIM3 model. Consequently,

to improve the match betwea imniilntion and a number of parameters were

M e r adjusted through comparing the simulation results with measurement.

adjusted parameter values were obtained by trial and error in order to provide a better

match between simulation resuits and rneasured data Some parameters which affect the

1-V characteristics significantly are discussed in Appendix B.

The reascms for having to carry out the parameter adjustment process, are to accommodate

some ciifferences in the BSIM3 model hplementation in Spectre and in SPICE as used

in the AURORA parameter extraction/optllnization software. This optimization and

adjustment process is complicated by the fact that a large number of parameters are inter-

related, and different combinations of parameters can make the simulation results match

the measurement data with the same accuracy. The aptiniized and adjusted parmeters for

the Spectre BSIM3 model produced in this project are clearly more accurate than the

extracted values, as the simulation results confimi. The detailed discussion on accuracy

of simulation results is presented in chapter 3.

Spectre is presented and discussed for simulating different geometrical devices in

comparison with measurement. The leve13 mode1 parameters are given in Appendix C and

the parameters of the BSIM3 m d e l are given in Appendix D.

3.1 SIMULATION RESULTS FOR WIDELONG DEVICES

Simulated and measured of 1-V characteristics for a wide-long device (W/L=SOCr/SOp)

using the BSIM3 model and the level3 model with the Spectre simulator are shown in

Fig. 3.1-1 for an n-channel transistor. Table 3.1-1 compares the simulated results of the

drain cument at several drain voltages of the BSIM3 model and the level3 model,

respectively, and summarizes their fiactional errors for n-channe1 devices. The table

shows that the simulation results for both the BSIM3 model and the MOS level3 model

agree quite well with measurements for these wide-long devices. Overall the fractional

errors are smaller at Vgs=4V than at Vgs=ZV for both models. The level3 model is

actualiy better h n the BSIM3 mode1 at Vgs=2V, in which the fractional errors are from

6.32% to 7.1 1 % for the level3 model, but ftom 9.16% to 9.45% for the BSIM3 model.

Tbe level3 model is aiso mare accurate than for the BSIM3 model at Vgs-SV, as shown

in Fig. 3.1-1, the fractional mm is about 2% and 1% for the BSIM3 mode1 and the level3

mode& mqxztively. The fractional enor is calculated by:

(a) BSIM3 mode1 (b) MOS Level3 mode1 mgure 3.1-1 Cornparison of simulation results for an NMOS device with W/L=50p/50p using different models for VbseO; (a) simulated resuit of the BSM.3 mocàel; (b) simulated result of the MOS level3 model

VDs(Vl

(a) BSIM3 model

- -

(b) MOS Level3 model Fîgure 3.1-2 Comparkon of simulation d t s for a PMOS &vice with ~ / ~ = 5 0 ~ / 5 0 ~ using different rnodels for VbsmO; (a) the BSIM3 model; (b) the level3 model

A siniilar set of simulated and measured results for a wide-long PMOS device

with W/L=SOp/SOp are presented in Fig. 3.1-2, and Table 3.1-2 summarizes these results.

The agreement of the simulated results and measurement for p-channel devices with

W&=SOp/SOp is very good for both the models with Specîre. Again, the simulation results

for Vgs=-4V are somewhat better than for Vgs=-2V and Vgs=-SV. Also the level3 model

is better than the BSIM3 modet.

Where I L is an average of 9 measurements. I d , , and Id-" are the simulation

results using the BSIM3 model and the level3 model, respectively.

33 SIMULATION RESULTS FOR WIDESHORT DEVICES

Figure 3.2-1 and Table 3.2-1 present the measured data and the simulated results obtained

from the different models for n-channel devices with W/L=5Op/lS p. These results

indicate that the results of the BSIM3 mode1 agree with the measured data, but the

27

Figure 3.2-2 and Table 3.2-2 present the simuiated data obtained fiom the BSIM3

mode1 and the level3 model, respectively, as weU as measured data, for short channel

PMOS devices with W/b50p/15p. The acciaacy of the sixrïulaîio91 TeSults for the BSIM3

model is again greater than the level3 model.

(a) BSïM3 mode1 fb) MOS Level3 mode1 Figure 3.2-1 Cornparison of Spectre simulated d t s for different models for an NMOS device with W/L-50p/15p at Vbs-O; (a) simuiated resuh from the BSM3 model; (b) simulated result from the feveî3 model

(a) BSIM3 model (b) MOS Level3 mode1 Figure 3.2-2 Comparisoa of the Spectre smiulation redts with mameü data for a p-channel device with W/L=50p/lSp at Vbs-O; (a) simulated result with the BSïM3 modei; (b) simulated result witb the fevel3 mode1

Table 3&2 (a) Compiirisoa of tbe simulatim resuits for the different models with measurement for PMOS devices with W/L=SOp/l.Sp at Vbs-O, Vgs--2V

3.3 SIMULATION RESULTS FOR NARROW-LONG DEVICES

Figure 3.3-1 and Table 3.3-1 compare simulatecl data from the both models with measured

data for narrow n-channel devices with W/L=l.Sp/lOp. The agreement of the BSIM3

model is much better than that of the level3 model. The fractional error of the simulation

results relative to the measured data for the BSIM3 model is lower than 5%. However,

it is up to 29% for the MOS Level3 model.

(a) BSIM3 model (b) MOS LeveD model FIgure 33-1 Cornparison of the Spectre simdated d î s with mmsumi data for an NMOS device with W/L= 1.5p/lOp at %=O; (a) simulated resuh using the BSIM3 dt; (b) simulation d t s using tbe IeveD model

(a) BSIM3 mode1 (b) MOS LeveO model Elgure 33-2 CamparisIm of the Spectre simulation d t s witb Merent models with measured data for a PMOS &vice with W/L-1.5p/lOp at Vbs-O; (a) simulation of the BSIM3 model; (b) simuIation of the level3 mode1

Figure 3.3-2 and Table 3.3-2 compare simulated data using the BSIM3 model and

the level3 mode1 with measured data for p-channel devices with W/L=l.S p/lOp. The

simulation r d t s using the BSTM3 mode1 agree with the measured data well, with error

about 4% at Vgs=-4V. The simulation results using the 1eve13 mode1 are much worse,

with fiactional errors typicslly over 35%.

Table 33-l(a) Cornparisan of the simulation r d t s of the different models with meamernent for NMOS devices with W/L=l.Sp/lOp. at Vbs-O, Vgs=2V

TaMe 3.3-2 Cornparison of the simulation resuits using different models with measurement for PMOS devices with W/L= l.Sp/lOp at Vbs-O; (a)Vgs=-2V; (b) Vgs=4V

From the comprison of the differenî size devices, it can be seen that the simulation

resuhs from the BSIM3 model are much be-tter than from the level3 mode1 for wide-short

devices and narrow-lang devices; for wide-long devices, the simulation results using the

BSIM3 mode1 and the MOS level3 model have comparable accufacies.

32

the level3 model for the n-channel and the p-charnel devices has been discussed. To

evaluaîe the accmcy of the BSIM3 model used in sirnuMg integrated circuit amplMers,

two amplifiers were measured and simuiateâ using the BSIM3 model and the MOS level3

model in the Spectre simulator, respectively. One of the amplifiers is the two-stage

atnpmer (TSA) 115-173, [19], which is a representative amplifier design provided by

CMC. The other one is the folded-cascode amplifier (FCA) [15],[17-181 which was

designed for this project. Both amplifiers were fabncated in the Mitel 1.5prn process.

This chapter discusses some important theoretical and performance characteristics

of TSA and FCA and compares approximate hand-calculation values with the simulation

results obtained fiom the BSIM3 model and the level3 model, respectively. The hand

caîcuiaîed values were calculated using the following equations and the parameters were

obtained from dierent models.

4.1 TWO-STAGE AMPLIF'IER

The TSA consists of 8 MOSFETs as shown in Fig.4.1-1, It is constructed with a

differential amplifier as an input stage and a current-sink CMOS inverter as an output

stage. The important relationships describiig the performance of the TSA cm be

summarized by [17]:

First-stage gain:

Secand-stage gain:

Gain bandwidth:

Slew rate:

Conmon-mode range (CMR):

Large signal output swing positive:

Large signai output swing negative:

Output resistance:

Figure 4.1-1 Schematic of the two-stage amplifier

Table 4.1-1 shows the mputed and simulated results using the parameters from

the BSIM3 model and the level.3 model, respectively. It is obvious that the computed and

the simulated DC open loop gains and output resistances using the level3 model

parameters n e much pater than those using the BSIM3 model parameters. The

accuracies of the level3 model and the BSIM3 model will be discussed in Chapter 5.

Table 4.1-1 Performance characteristics of the TSA

BSIM3 mode1 ~dca lcu ia ted Simulated Hand-caiculated Simuîated

D c o ~ e n l w ~ l m 5.6422* 10' 2.0995" 10' 1.4021*106 0.722*106

Gain Bandwidth (Hz) 4.029M 1.89M 3.7858M 3.98 1M

Slew rate (VIFS) 1.929 1.932 1.929 1.9215

1 Negative CMR (V) 1 -1.187 -122 11 -1.187 -1.24

II II

Output resistance (0) i l 1 1 3.518M 4.564M

with a current mirror circuit, a p-channel input differential pair and the folded-cascode

output stage as shown in Fig. 4.2-1 [15J,[18].

Elgui.g 4.2-1 Sdietnatic of the folded-C8SCOde amplifier; For traasistors M3, M4, M5, M6, M7, Mg, M10, Ml 1, the subsaate and source terminal are tied together

The output resistance of the FCA is very high due to the cascode configuration of the

output stage. This stage can be s e m as two subcircuits in order to analyze its output

resistance. The first subcircuit is an irnproved Wilson cullent mirror using p-channel MOS

transistors, farmed by M3, M4, M3c, and M4c. Its output resistance can be expressed[l5]:

tt resistance of the FCA can be fond by comb'ig in paralle

(4 .2-2)

!1 the mal1 signa

output resistance r, with the output resistaace r- Therefore, the small signal output

resistance of the FCA is given by [IS]:

It is assumed in the above caiculations that a l l the transistors are operating in saturation.

The srnall-signal voltage gain of the FCA is given by [15]:

The dominant frequency of the FCA is given by [15] :

Where C, is load capacitance connected to the amplifer output terminal ( not shown

It is assumed that the input common-mode voltage range is defhed by the input voltage

over which both Ml and M2 transistors in saturation The maximum input voltage

expression [17J is:

The expression of the minimum input common-mode voltage c m be written as 1171:

The slew-rate performance of the FCA depends upon the value of the current 1, and the

capacitance fkom the output node to ac ground. The slew rate is given by [18]:

'm S ~ W -lu& =- (4.2-9)

The minimum output voltage of the FCA is equal to the negative power supply, which

is -2.511, since when transistors M4 (M3) M4c (M3c) are cutoff, the pull-down transistors

M2c (Mlc) and M7 (M6) can pull the output voltage to - 2 5 . For the large signal swing

in the saturation region. Thus, the output voltage can be written as (171:

The calculateci and sirnulateci r d t s for these important characteristics and

bhaviours of the FCA are summarized in Table 4.2-1. The calculated values are

comparable with the simulation resuits using the BSIM3 rnodel and the level3 model,

respectively. However, the computed and simulated DC open loop gains, output

resistances, as well as cutoff f'requencies using the level3 model parameters differ

simcantly from those using the BSIM3 rnodel parameters. Further discussion is

presented in Chapter 5.

TaMe 4.2-1 Perfommnce chatacteristics of the FCA

Negative CMR (V)

Positive owpa swing (V)

Ne@ve output swing (V) 1 - 2 .N -2.479 1 -2.5 -2.469

a11V L W I U Y r U W U s u s L w - - 6 W Ç Y I V YCYCYIAVCVAY Y- -1 "Y.- Y- IY u mi--

design of the op amp itself. To comple-tely evaluate the op amp, many characteristics such

as dc apen loop voltage gain, frequency response, as well as output resistance should be

tested. The typical characteristics of two test ampW~ers were measued and simulated to

evaluate and investigate the accuracy of the simulation results using the BSIM3 model

and the level3 model, respectively. Following are the main investigations carried out by

memernent and simulation for the different models:

1. Large signal differential dc input transfer characteristics to determine the

incrernenta. dc gain and the output voltage swing.

2. Smdl signal differential ac transfer function which includes gain versus

frequency and phase versus frequency.

3. Output resistance.

4. Large signal cornmon mode characteristics.

5.1 DC OPEN LOOP VOLTAGE GAIN

The dc open loop voltage gain of the two amplifiers, the FCA and the TSA were

measured and simulated. Since these amplifiers have high differenial dc gain and large

output resistance, this memement is one of the most difficult steps to perform

successfûiiy. The test niethod and the rneasured and simulated results are discussed in the

following sections.

5.1.1 TEST METHOD AND VERIFYING THE TEST TECHNIQUE

A g e n d rnethod for messuring the open loop voltage gain is to employ a scope to read

open locrp gain and high output resistance due to the low input resistance of the scope.

If the output resistance of the amplifier is high, the gain depends on the input resistance

of the scope, therefore, the rneasured open 1- gain does not represent the real open

1- gain,

A semiconductor parameter andyzer (SPA) (HP4145A) was used in this

measurement. The SPA has 4 stimulus/measurement units (SMUI, SMU2, SMU3 and

SMU4) and 2 voltage sources (VS1 and VS2). Each SMU can be set up to function as

a voltage source/current monitor (VSICM), current source/voltage monitor (CSfVM), or

source cornmon (COM). When a SMU operates in the VS/CM mode, its residual

resistance is only 0.4Q. When a SMU works in CS/VM mode, its input resistance is

larger than 101'Q. The functions and the very high input resistance of the SPA are

suitable for measuring the dc open loop voltage gain of the amplifiers. The operation

modes of the SPA is shown in Appendix F.

A very srnail input signal is needed to obtain an output voltage in the linear

region. An attenuator was employed between the SMU and the input terminal of the

amplifier. To ver@ thaî the attenuator technique worked correctly, the input voltage and

the output voltage were measured for different attenuation values. The test circuit and

the test results of the ratio of the output voltage to the input voltage are presented in

Appendix F.

SMU1 worked as a VS/CM mode and a sweep voltage was applied to the noninverting

input temrinal; SMU2 was connected to the output terminal of the op amp and operated

in CS/VM mode to measure the output voltage; S m 3 was set up in VS/CM mode to

supply the input offset voltage. The VS1 and VS2 supplied +2Sv and -2.5v, respectively.

In this conneciion, the common mode input is not equal to zero, v,=(v2+v,)/2,

so the output voltage is a cumbination of the differential and the common mode outputs.

However, the common mode gain is much d e r than the differential gain, and both the

inputs v, and v, are very small in the linear region, and the effect of the cornmon mode

output can be neglected. It can be considered that îhe output is only the differential signal

output.

Figure 5.1-1 Circuit for t&g dc gain using SPA

5.1.2-1 DC VOLTAGE GAIN OF THE TSA

Figure 5.13 Simulation circuit for dc gain

The simulation circuit is shown in Fig. 5.1-2. The measured and simulated results are

shown in Fig. 5.1-3.

To cornpan the simutation r d t s with the measurernent, the simulation conditions

an exad value. It is spegfed to be equal to or p a t e r than 10'2Q when the SMU works

in the CS/VM mode. The load resstances were set to 10%. lû'% and open,

respectively, whüc the dc transfer behaviour was simulateci in order to compare with

nieasuremenf. For the TSA, the simulated dc gain s h o w in Table 5.1- 1 does not change

with these values of load resistance for the both models. This implies that the output

resistance of the TSA is much d e r than 10I2Q, and the load resistance does not affect

the dc gain. The cornparison of the measurement and simulation results is presented in

Table 5.1-2. It shows that the simulation result from the BSIM3 model is much more

accurate than that from the level3 rnodel. The fractional error is 0.97% for the BSIM3

model, but the simulation result using the level3 model is 34 tirnes larger than the

measurement. The fiactional error is calculated by:

. . . . . . . . . . . . . . . . . . . . . . a : , . . * 1s ..... . . . j ...... . . j ........ j ........ .i ......... j ................. ; ......... ;.. ... ..i ..... .i

. . . a . . . . . . . . . . . . . . . . . . ! i : . . . . . . . . . . . . . ....... ...... ........ ...... ...... ..................................... ( : ..: :. : . . . . . . . . . . . . . . . . . . . : . . ; . . . . . . . . . . . ...... ...... ........ ........ ....... . ...... ........ Q5. : ..; : " - -....., ............ . . . . . . . . . . . . E . . . . . . . . . . . . . . . . . . . - . . a : . . . . . . . . . .................. . . . . . . . ....... ....... .............. ............... ) 0 . : ; ,.,: 1 v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i :,*+ i

. . . . ... ...... ......... ......... ....... ......................................... WQ5. ...!.. i ; : i...: . . . . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . . -1 ......... ; ......... ; ........ j ......... : ....... ....... ;.. ..... .; ......... i ............... . . . . . . . . . . . . . . . . . . ! . . . . . . . . . . . . . . . . ................. -,#J ........ i ...... ..;. ....... i. ....... j . . . ... j . . . : ......... i ...... ..i ........ ; . . . . . . . . . . . . . . . . . . . . . : : i ; ; ; ; ; . . .

4. ....... : ......... : ......... :. ...... ......... ........ ....... :.. ... ..: ....... .: . . . . . . .

V L p r l M r 10-3

Flgure 5.14 DC d e r characteristics of the TSA; the oaet voltage applied to the inverting input terminal was -1mV for measuring

Table 5.1-2 Cornpariscm of îhe measured dc voltage gain with the simulation results using the different models for the TSA, the measured value is an average of 20 measurements

5.1.2-2 DC VOLTAGE GAIN OF THE FCA

The method of measuring the dc voltage gain of the FCA is similar to that used for the

TSA. The rneasufemenf and the simuiated r d t from the BSIM3 model are shown in Fig.

5.1-4. The simulation results for the different models are shown in Fig. 5.1-5.

Table 5.1-3 presents the simulation results of the dc gains with two load

resistances and for open circuit. It is obvious that the simulated dc voltage gains wiîh the

load resXstances are very close to the open circuit gain for the BSIM3 d e l . However,

for the level3 model, the simulated dc gains depend on the load resistances. The reason

is that the sirnuîated output resistance from the level3 model is very high, approximately

0.7*10'2Q, so that the dc voltage gain is affectai by the load resistance.

The results in Table 5.1-4 consist of the measured data and the simulated dc

voltage gains obtaineâ from the different models. It can be seen from this table that the

fractional e r ra of the simulation result from the BSIM3 m d e l related to measurement

12

1

o.!

(a) (b) Figure 5.14 Measured and Simulated dc characteristic of the FCA; the load resistance was 10"Q in simulation, the offset voltage was 12mV in measunment: (a) Noninverthg input, (b) lnverting input

Figure 5.1-5 Cornparison of the simulated r d t s of dc characteristic for FCA

Table 5.1-3 Comparing the simulated dc gains with the different load resistances and the open circuit using the BSIM3 mode1 and the level3 mode4 respeaively, for the FCA

Load resistance

10l2Q

BSIM3 mode1 Level3 mode1

1.5993275* l d 6.19157*107

10nR 1.6007754* 1d 9.84329" IO7

open circuit n----- 1.6009365*1d 1.05336* IO8

One of the possible causes for the observed gain differences is tolerances in the

fabrication process. One particular parameter is the sheet resistance, the vaiue of which

depends cntically on the fabrication process. The resistor R as show in Fig.4.2-1 is built

using Po1ysilican 'ho, and the sheet ressiwce of this laya is 100QIsq. nominal, 75R/sq.

for the lower specification limit, and 125Q/sq. for the upper specification limit. This

resistor is a critical coapcmau in this circuit, because it provides the bias current, which

aetamins the &vice operathg points. Therefore, the gain of the amplifier is affected by

the value of this resistance.

To investigate this situation further, the short-circuit tramconductance of the FCA

was measured and simuiate!d under DC conditions, using the circuit shown in Fig. 5.1-6.

Since the FCA is btisically an opemtional-transcondudance amplifier due to the very high

output resistance, this test focuses directly on the transconductance to study the

ciifferences between simulation and measurement for the DC gain. Fig. 5.1-7 shows the

measured result and the simulated results using the BSIM3 mode1 with different bias

resistances fa short circuit. The input signal was a sweep voltage from -50mV to + 5 W

in this Table 5.1-5 presents the measured transconductance and the simulated results

with Merent resisti.mces, 408K (759/sq.), W K (lOOQ/sq.), as weil as 680K (1250/sq.).

Using 6ûûK9 for R gives a simulation result for transconductance of 138.3pA/V. This

would reduce the erra fkom -56% to -45% and would account for some of the difference.

-

bias current is 36.9pA, and the simulated result for a bias resistance R of 680Kn is

37.7pA. The simulated nominal DC cment is 45.3pA for R-544KQ. These r d t s

suggest that in the measured FCA, the bias mistance R is adually 680KQ or larger,

rather than the anticipatecl 544KQ no& value.

- -

FigS.l-6 Test circuit for short-circuit Fïg.S.1-7 Measured and simulated redts using the BSIM3 model for short-circuit

Table 5.14 Cornparison of the simuiated ttatlsconductances using different bias resistors R from the BSIM3 model with meamment for the FCA

5.2 LARGE SIGNAL OUTPUT VOLTAGE SWING

The fnaximum output voltage swing is the positive lirnit and the minimum output voltage

swing i . the negative limit. The large signal output voltages were simulated and rnemed

for the TSA and the FCA, respectively.

The output swing can be obtained fiani the dc transfer characteristics of Fig. 5.1-3

47

FCA, respectivvely. The me8su1d voltages in the both direction are very close to the

simulation resuits. The fractional mors of the simulation compared to the measurement

results for the BSIM3 mode1 are 1.61% and 0.48% in the positive and the negative

directions, respectively, for the TSA. Table 5.2-2 shows that the measured output voltage

swing agrees with the simulated results well for the FCA. The fractional errors of the

simulation results compared to measurement using both models are less than 1%.

Table 5.2-1 Me8sute.d and simuiated output voltage swing foi the TSA

Table 5.2-2 Measured and simuiated output voltage swing for the FCA

Simuiated -LeveD

2.206

Negative (V) -2.479 -2.479 -2.469

Simuiated-Level3

2.446

-2.5

Measured

-71 Negative Or) 11 -2.492 I

5.3 OUTPUT RESISTANCE OF THE TEST AMPLfFIIERS

Simulated-BSIM3

2.3%

-2.497

Generally, a test voltage can be applied to the output terminal of the tested amplifier and

the current I, can be measureâ. Then, the magnitude of the output impedance

VLs/Ical can be obtained by analysis of the circuit in Fig. 5.3-1. The offset voltage

is applied to the input terminal to drive AVin to zero, and the current E, is only caused

by the voltage source V, This method can be used in simulation, but is only suitable

- - -- r -- - ---- - z -

kinds of V, signals can be applied to the b. output terminal of the amplifier, one is a b t

sweep voltage and the other is a sinewave. = - - - Figure 5.3-1 Circuit for testing output resistance

5.3.1 MEASUREMENT AND SIMULATION RESULTS FOR THE TSA

The test circuit of the Fig. 5.3-1 was used to simulate the output raistance of the TSA.

Fig. 5.3-2 shows the simulatecl results of the test voltage with its related current by using

the Merent models. The computed output resistances are 386KQ and 4564KP with the

BSIM3 model and the level3 model, respectively.

(a) BSIM.3 mode1 (b) Levei3 mode1 Flgure 53-2 Simulation results of the output mistance by irsing the different models for the TSA; the test voltage is a sweep voltage from -lV to +IV: (a) the simulation result of the BSIM3 model, (b) the simulation result of the level3 model

It is diffidt to measure output resistance directly by using the test circuit shown

that the dc gain of the amplifier depends on the load resistance as show in Fig. 5.3-4.

The dc voltage gain can be expressed in Eq. 5.3-1 when the amplifier operates in its

where A is the open loop dc gain without the load resistance.

The output resistance can be calculated by measuring the dc gains with load resistances.

To obtain the dc voltage gain with the load resistance for the TSA, the test circuit

shown in Fig. 5.3-4 was employed and the load resistor was 336.X 8. The rneasured DC

output resistance çomputed from Eq. 5.3-2 is presented in Table 5.3-1.

4 .................................................................................................. . . . . . . . . . . . . . . . . . . . . . . . . . . 1 : : . . . . . . . . . . . . . . . . . . 3 ........,.........>......... . ...................................................................... SEJIJl siribsp vol- . . i / I

,cthldmdmukuhgesMniodsl I : : . ! -. ?., ss. Llt

V m M

Figure 53-3 Simulated and masmed amenis Figure 5.3-4 Test circuit of the dc gain with load R

Fig. 5.3-5 was used to rneasure the output hpedance with frequency.

The output impedance of the amplifier is calculated by analyzing Fig. 5.3-5 and

the equation is given by:

zv r art v =

O" R +Z kown O

Where Gis the total impedance of the output impedance of the ampiifier ( Z d in parallel

with the input impedance of the scope. Then,

vou t

(a) (b) FIgure 53-5 Test circuit used for measuring the output resistance with frequency for the TSA; R,, is 179.4Kf2: (a) Measining circuit, (b) SimuMing circua, a 1OpF capacitance is added to represent the bonding ad.

Fig. 5.3-5(a) was used in measurement and Fig. 5.3-5(b) was used in simulation

for testing the output irnpedance of the TSA. Fig.5.3-6 compares the simulation results

rneasurement than that from the level3 model.

1 . . . . . . . . , . . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . %. . . . . . . . . . . . . . . . , . , -. . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . .

. . . . . . . . . . . -1 I

O O B l O.@ 0.03 0.01 0.05 0.06 0.07 0.01) 0.08 0.1

Tirme (Sec.)

Flgure 5.3-6 Camparison of the simulated resulrs with the measurement for the sinewave test voltage with 1V amplitiulP. and SOHz Wquency for the TSA, Soiid line represents the measurement, ,., line represents the simulation r d t ushg the level3 model; -line repmeas the simulation result ushg the BSiM3 model

Table 5.3-1 shows the magnitude of the measured and simulated output

impedances for DC and selected frequencies. Two important differences between the

simulated output impedances using the BSIM3 model and the level3 model are obvious

in this table: (1) the simulated output impedance of the level3 model is higher than that

of the BSIM3 model, it is about 11 times larger in the DC condition; (2) the simulated

output impedance of the level3 model decreases more quickly with frequency, from

4.564MQ to 59.5k8 with frequency changing fkom O to 5ûûH.z. However, the simulated

values change from 386kQ to 80.66kQ in the same frequency range for the BSIM3

model. It can be explained that the DC output resistance from the level3 model is very

h g e and it causes the output capacrtance to have a more significant affect, therefore, the

simulation results from the level3 mode1 change significantly with frequency.

large noise level present. It is evident in this table that the output impedances of the

simulation resutts from the BSIM3 model are reasonably close to measurement, with

f r s i c t i d enor of 9.2% for 50Hz frequeacy. In this case, the simulation resdt fiom the

level3 model is 4.1 times larger than the measurement. The fiactional error is 32.6% for

the BSIM3 model and is 50.29% for the level3 model for 500Hz frequency. Overall, the

simulated output impedances from the BSLM3 model are more accurate than those

simulated by using the level3 model in both the DC and the sinewave tests.

TaMe 53-1 Cornparison of the simulated and measured magnitude of the output impedances with frequencies for the TSA

5.3.2 MEASUREMENT AND SIMULA'I'ION RESULTS FOR THIE FCA

The methoci used to simulate the output resistance of the TSA was applied to sirnulate the

FCA. The simulating circuit for both the DC test signal and the ac test signal is shown

in Fig.5.3-1. The simulation result of the test current with the test voltage from the

BSIM3 model is shown in Fig. 5.3-7 (a). Careful examination of the simulated curve

shows that the ouiput resistancce is not a constant for the test voltage changing from -0 .9~

lower voltage region, YK5Mll. 'le output resistance rs about lo;sJMU Ior tne test voltage

from 4.2V to +0.2V, and it is 1033MB for the test voltage fiom O to +0.9V.

The simulation result of the level3 model is show in Fig. 5.3-7(b). The calculated

outpd resistaoce fiom sirmilaticm is 7.Ol28* 1@MO, which is mueh greitter than that from

the BSIM3 model. A sinewave was also appfied to test the output impedance of the FCA.

Representative r d t s are shown in Fig. 5.3-8 and arc Summarued in Table 5.3-2.

(a) (b) J3gure 53-7 Simulation resuh of the test voltage to its related curent for the K A : (a) the simulation result of the BSIM3 model, (b) the result of the level3 model

OUrPUTRESISTANCETEST

>

P -1

. . . . . . . . . . . . . . . . . . . . . . . . . . . - . . . . . . . . . l(\,/.\./VV\

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . O . a i a? tu 0.4 as 0.0 a7 as 0.0 i

= to9 (81

........ ......... ......... ....... =,O-llo a1 0 2 tu a4 os oa 0.7 aa ao 1

ml

O ~ 1 M Q J û 4 4 5 û â ~ 7 Q I Q O 1 (9

Tme (Sec.)

Figure 53-8 Sirmilation resuhs of the ciirrent with the test voltage for tbe FCA, the test signal is a sinewave with 5Hz frequency and 1V amplinide: (a) the test voltage, (b) the simulated cunent of the BSIM3 model, (c) the simulated cucrent of the levei3 model

There are two important observations conceniing Table 5.3-2: (1) the output

inipedances of the sirnulated r d t s fiom the BSIM3 model do not change with fiequency

when the frequencies change from 5- to 500H.z. But, the simulated output impedance

from the level3 model decreases with fiequency, changing fiom 4.906*1@~Q to

6.7182* 1@MQ in this frequency region; (2) the simulaîed output impedance of the level3

model is much larger than that of the BSFM3 model in the dc and low frequencies.

These results can be explained in terms of the open loop fiequency response. The

open loop dc voltage gain of the simulated result fiom the level3 model is much higher

than that of the simulated result fkom the BSIM3 model. A s s u h g that the gain-

bandwidîhs are about the same for these two different modeis, the cutoff frequency should

be much lower for the level3 model, therefore, the voltage gain decreases rapidly with

frequency for this model.

In practicai measmement, the test circuit show in Fig. 5.3-4 was used to measure

the output resistance of the FCA. To obtain the dc gain of the FCA with load resistance,

a 12.5Mn resistor was connected to the output terminal, and the dc gain was measured

55

output impedance for a sinewave test signal was nat IiLeasured due to the very high output

impedance of the FCA.

Fîgure 53-9 Measurement of the gains with the load resistances

The measured and the simulated dc voltage gain with the load resistance, and the

calculated output resistances by Eq. 5.3-2 using the measured and the simulated dc gains

are shown in Table 5.3-3. This table shows that the output resistance calculated by using

the simulated dc gains with the load resistance from the BSIM3 model is close to the

measurement. But there is a significant difference between the calculated value from the

level3 model and the calculated value using the measured data, giving a value

approximateIy 700 tirnes larger. These results are also consistent with the dc simulation

results presented ewlier in Table 5.3-2.

-1 12485*1@

LUolrdzlP ) 1.02748*1@

5.4 F'REQUENCY RESPONSE OF THE AMPLIFIERS

The frequency response of an arnpWier is a very important characteristic, since the gain

of an amplifier is a function of the frequency of the input signal. To evaluate the ac

performance of the FCA and the TSA, the fiequency response was rneasured, and also

simulated using the BSM3 model and the leveI3 model, respectively.

Gl,, (sirnulated)

1.92599* ld

1.6* 1@

Rout

5.4.1 MEASUREMENT AND SIMULATION OF THE TSA

Gim-LevtU(Sim~lated) '

1.877504* 103

1.05336*108

(b)

BSIM3

1.038* IO'M

Measured

1 .oz~*~c?M

The measurement and the simulation circuits shown in Fig. 5.4-1 were used for testing

frequency response. In simulation, the load capacitance was 17.5pF which includes the

equivalent input capacitance of the scope and the bonding pad. In this case, the dc gains

are smailer than the values obtained in dc measurement and simulation due to different

load impedances.

The simulation and measurement resuits are show in Fig.5.4-2. The broken lines

represent the measured data, the solid lines are the sunulation results fiom the BSIM3

LeveB

7.013*1@M

output voltage is too low to read from the scope at hi& frequency, the highest testing

frequency is lûûKHz in practicai meammxm& The phase response is shown in Fig. 5.4-

2(b). It can be seen that the simulateci result from the BSIM3 model is close to

measurement. However, the simulateci phase from the level3 model shows simcant

Mation in the lower frequency region (lower than 1ûûûHz).

Figure 5-41 Test cù&& fa frequency response; (a) Rauicai test circuit; @) Simulation circuit

Figure 5.4-2 Frequency response of the TSA: (a) Gain with frequency, (b) Phase with frequency

58

bandwidth for the TSA. It is obvious in this table that the simulation results for gain

bandwidth fiom the BSIM3 model are closer to measufemenf than the results of the level3

model. The fractional error of the gain fiom the BSIM3 model to measurement is 15%

compared to -67.6% for the level3 model.

Table 5.4-1 Compmkm of masumma and simutation results for frequency response for the TSA

II A0 fa) ftww

Memuement 1.766*10' 2.2075

BSIM3 mode1 1 1 527* 10' 123.5 1.8858

Levei3 mode1 8 3.70

5.4.2 MEASUREMENT AND SIMULATION FOR THE FCA

For rneasuring frequency respanse of the FCA, several points must be considered. Firstly,

its output resbimx is very hi& so the gain depends strongly on the load resistance. As

mentioned previously, the input resistance of the sape is very smali relative to the output

resistance of the FCA. Secondly, the minimum amplitude of the input signal is limited

by the output of the functicm generator. The minimum output of the function generator

is SOniV, which is 50 times gr- than the minimum voltage step of the SPA. To obtain

the frequency response for the FCA, an additional load resistor was connected to the

output terminal of the amplifier in the test circuits shown in Fig. 5.4-1. This load

resistance of 8.24M8 was used to reduce the output voltage in order to keep the FCA

working in the linear regioa

Fig. 5.4-3 shows the fiequency response with the specified load resistance.

(a) (b) lFIgure 5.4-3 Frequency response of the niheasured and the simulatecl r d t s for the FCA, Fü includes the a d load resistance and the mput resistance of the scope (a) Gain with frequency (b) Phase with fiequency

Table 5.4-2 Compkm of the simulation d t s with measurement for frequency response for the FCA

-

r& for low f r e q d e s using the BSIM3 model and the level3 model are very close,

56.91dB from the BSIM3 model and 56.63dB from the leve13 model, respectively.

However, the co~espanding mea~uted resdt is somewhat lower at 52.54dB. These results

also show that the gain bandwidth obtained with the level3 model is 2.31 tirnes larger

than measurement, and 2.38 times larger than measurement for the BSIM3 model.

Since the load resistance is very smnii in this test condition, the effect of the

output resistanoe of die amplifier should be negligible, thus the gain should only depend

on the load resistance. Therefore, the total current sugplied by the amplifier flows through

measured tramconductance is 94.7pA/V. The result for the level3 model indicated a

transconductance of 144.5pA/V. These values confirm that similar differences exist

between the voltage gain and the transconductance resuits.

5.5 LARGE SIGNAL COMMON MODE CHARACTERISTICS

To evaluate the large signai comrnon mode input characteristic, the TSA and the FCA

were measmeci and simulated using the BSIM3 model and the level3 model, respectively.

The comrnon mode gain and the common mode rejection ratio will be discussed in the

following material.

5.5.1 COMMON MODE GAIN AND CMRR FOR THE TSA

The test and simulation circuits used for common-mode gain are shown in Fig. 5.5-1.

Fig.5.5-2 shows the measurement and the simulation results using the BSIM3 model and

the level3 model, respectively, for a sinewave input with 500mV amplitude and 5OHz

fiequency. It cm be seen fiom the output voltage waves in Fig. 5.5-2 that the simulation

result of the BSIM3 mode1 matches with measurement much better than that of the level3

model. Firstly, the common mode output voltage of the BSIM3 model is closer to

measurement, comparing Fig. 5.5-2(a) and (b). Secondly, the output inverts relative to

input for both the measmernent and the simulation r d t obtained fiom the BSIM3 model.

However, the simulation result of the level3 mode1 shown in Fig.5.5-2(c) is quite different

in both magnitude and phase from the In this case, the cornnion mode gain

is about 0.08 for the level3 model and is much snaller than the measurement, and its

fiactional -or related to measurement is up to 83.3 96. This error was found to increase

61

Stops

1WD.W

I A - - - - - -

(a) (b) Figure 551 T a c i w b oftbe commn nmde gain for the TSA: (a) Practical test circuit, the offset input voitage was provided by RI, R2 and the 9V bsttery (b) Simulation circuit

(cl Ffgare 53-2 Measured and simuiaîed d t s of the common mode gain for the TSA; Input IV@-p) sinewave with SOhz frequency: (a) Measured result, (b) Simulation result of the BSlM3 model, (c) Simulation result of the level.3 mode1

measured common-mode gains and the simulated results fiom the BSM3 model are

essentiaiiy constant when the input signal changes from 400mV to 1V (peak-peak), the

fiactional error of the simulation to the measurement is fiom 8.6% to 1 1.38%.

Table 5.5-2 shows the sirnuiation results and measurement for the comrnon-mode

gain with frequencies. In this test, the input magnitude is 400mV. The comrnon-mode

gains were found to dwease with increasing frequency over this range for both the

measured results and the simulated results. The fiactional error of the simulation result

to the meastuement ranges from approximately 8.6% to 36%.

Table 5.5-1 Cornparison of the measurement with the simulation resuits of the BSIM3 model for the common mode gain at 50Hz with input magnitude for the TSA

TaMe 5.5-2 Compism of the m e m e n t with the simulation results wiih frequencies for the common mode gain for the TSA ( V--400mV)

d

hput ('VI

400m

Gain-measurement

0.478

601)m

1 Gain-BSIM3 I 1-1

B 0.486

error %

8.6

[OA361 800m ! 0.488

10.29

I O A 3 6 7 1 0.436 1 1

10.66

11.38 0.492

show in Fig.5.5-1 and shown in Table 5.5-1 and Table 5.5-2. The differentiai voltage

gains were obtained in the pevious frequency response test step in section 5.4.1. The

CMRR can be obtained by:

Table 5.5-3 shows the cornparison of the CMRR simulation results with measurement

for the TSA. The simulation results for the CMRR ( nondB forrn) show fractional errors

from -9.4% to -25%.

Tabie 5.5-3 Coniparison the measurement of the common mode rejection ratio witb the simulation result from the BSIM.3 model for the TSA

5.5.2 COMMON MODE GAIN AND CMRR FOR THE FCA

The common-mode gains of the FCA were measured and simulated using the circuits of

Fig. 5.5-1 and connecting an add i t i d 8.24MQ resistance in the output terminal of the

FCA to make the conditions be the same for the comon mode gain test and the

differential gain test in c x b to caldate the CMRR. Fig. 5.5-3 shows the simulation

results using the BSIM3 model for a sinewave input. Fig. 5.5-3(a) presents the input

BSIM3 model. Fig. 5.5-4 is the measured result. It can be seen fram these figures that the

simulated and measured outputs invert relative to input, but the simulated common-moâe

gain from the BSIM3 model is very much smder than measurement.

(a) (b) Flgure 5.5-3 Simuiated output signal for the commun-& gain test using the BSIM3 model for the FCA; (a) Simuiated output with the input sinewave with 4omV and lOOHz iiequency, (b) Simulated outputs with 4 0 W , 600mV and 1V peak to peak sinewave inputs at lûûHz frequency

Figure 5.5-4 Measured r d t with 100Hz, 4ûûmV peak to peak input sinewave signal for tbe wxumon mode gain test for the FCA

measured common-mode gains and the simulated resdts fiom the BSIM3 rnodel are

essentially constant when the input signal changes from 4ûûmV to IV.

Table 5.5-5 shows the simulation and measurement results for the common-mode

gains with the seleded frequency. In In test, the input voltage is 4 W . The comrnon-

mode gains were faund to incrase with frequency for the simulation results fiom the

BSIM3 model, but the measured resdts do not change much with fiequency in this

frequency range.

Table 5.5-4 Cornparison of the measurement with the simulation r d t s of the BSïM3 model for the cornmon mode gain at lOOHz with input magnitude for the FCA

Tabie 5.5-5 Cornparisaai of the measurement with the simulation d t s with freQuencies for the common mode gain for the FCA ( Vw=400mV)

Table 5.5-6 shows the comparison of the CMRR simulation results with

measureaieat for the FCA. The simulation results for CMRR are very much larger than

measurement, 146.82âB compared to 56.54dB at lOOHz frequency.

This significant diierence between the simulation and measurement can be

e x p l a . as foliows: (1) in simulation, die transistors of this folded-cascode amplifier are

perfectly matched, (Ml and M2, M3 and M4, M6 and M7), and the simulated output

voltage should be very smaU in comrnon mode, thus the conmon mode signal gain should

be extremely smail, causing the CMRR to be extremely hi&, 146.82dB at 100Hz; (2) in

practice, the circuit exhibits a much higher common-mode gain because the transistor

pairs are n a exactly matched due to fabrication tolerances. This rnisrnatch eff- for the

FCA appears to dominate the measured cornmon-mode gain results, which cannot be

predicted by the basic simulations canied out here.

This raises the question of why the relatively good agreement between simulation

with the BSIM3 mode1 and measurement was obtained for the common mode gains for

the TSA. The circuit structure of the TSA is inherently less symnietrical than the FCA.

Consequently the common-mode performance of the TSA is dominated by circuit

behaviour rathex than mismatch effects due to fabrication tolerances. Thus it should be

expected that simuiation would provide an appropriate masure of common mode

performance for the TSA.

L

for the BSIM3 model for use with the Cadence Spectre simulator for integrated circuits

fabricated in the Mitel 1.5pm process. The accuracy of the model parameters set has been

documented through comparative simulations and measurements.

The B S W model has been discussed with emphasis on the drain current in the

different operathg regions. A step-by-step procedure fa exiracting a set of BSIM3 model

parameters has been desaibed and the r d t i ng fits demonstrated. The resulting fits have

been obtained for wide-long devices, wide-short devices as well as narrow-long devices

using the AURORA optiniization program.

The simulation r d t s obtained fkom the AURORA software containhg the SPICE

simulator were in good agreement with the original measured data. Rowever, when the

extracted model parameters were used directly in the Spectre simulator, a significantly

poorer overall match resulted An ad- process was carried out in order to irnprove

the simulation results with Spectre.

Simulation r d t s with the level3 model were also presented and compared with

the results obtained with the BSIM3 model in the Spectre simulator. The simulation

d t s of the BSIM3 model are much better than that of the MOS level3 model for wide-

short devices and narrow-long devices. For example, the error in the simulation results

with the BSIM3 model relative to measmement is about 596, but is up to 21 % for the

level3 modei, for ncchannel devices with W/L= 5Op/l.5 p; and the errm are 5% and 27%

for the BSIM3 mode1 and the level3 model, respectively, for narrow channel devices with

A variety of tests was carried out to evduate the accuracy of the BSIM3 model

used to simulate the performance of two andog inîegrated circuit ampuer test structures.

The measurement process and the ampifier test results were presented and documented

in Chpas 4 and 5. It was found that the simulated resuits obtained with this optimized

BSIM3 model parameter set agree with actual measuled test circuit performance with

significantly improved acmacies, in comprison with simulated resdts obtained with the

standard level3 model. For example, the fractional error is 0.1 % with the BSIM3 model

relative to measurement, and is 34 times larger with the level3 model relative to

measurement for the dc open Ioop gain of the two-stage ampMier. The error of the dc

gain of the folded-cascode is -56% with the BSIM3 model. It was suggested that

fabrication tolerances are involved in part of this error. However, the simulated dc gain

with the level3 model is 958 times larger than measurement.

One important factor with the BSIM3 model relative to the level3 mode1 relates

to output resistance. For exarnple, the simulated output resistance using the BSIM3 model

is close to meamrenient with an mor -0.87% for the FCA under DC conditions.

However, with the level3 model the simulated output resistance is about 700 times larger

than measmement.

In the CMRR of common mode gain, the results for the TSA showed that the

BSIM3 model was significantly better than the level3 model, giving mors at 50Hz for

examplle of 8.6% and 83.3% respedively. It was also nated that the common made results

Overali, the results of this work with analog circuits have confiied that the

BSIM3 model gives a considerably more accurate representation of MOS device

behaviour than the standard level3 model.

Following are some suggestions for additional work that could be carried out to

investigate the applicability and accutacy of the BSIM3 model further:

(1) The simulation results for voltage gain from the BSIM3 model for the FCA

were more accurate than that from the level3 model, however, the error related to

memuement is larger than expected. Some reasons for this were given in Chapter 5, and

a more detailed study of this should involve fabrication of additional amplifiers to allow

the value of the bias reSiSCa R to be measured and hence determine more completely the

effects of fabrication tolerances.

(2) The simuIaîion result for the cornmon-mode gain using the BSIM3 model does

not agree with measurement for the FCA, since fabrication tolerances are the determining

factor in this circuit's -on moâe performance. m e r approaches based on parameter

tolerances wouid have to be investigated to attempt to simulate the c o m o n mode

performance of this circuit.

(3) Additional ampiifîer performance factors such as slew rate, PSRR, and noise

could be investigated to firrther study the accuacy of the B S I . 3 model.

(4) It is ho@ that in a further release of the AURORA software, it will be

possible to lin. the parameter extraction process with the Spectre simulator, thus

providing an optimized set of BSIM3 model parameters for this shdator directly.

7 0

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Chapter 6 pp. 273-283, Chapter 8 pp. 387-396, HOLT, RINEHART AND

WINSTONJNC., 1987

Roberts and Sedra, SPICEfOr Micruelecîronic Circuit, Third Edition,, Chapter 10

pp. 462475, Saunders College Publishing, 1992

Geigez Randall L., AUen PhiUp E., and Strader Noel R., VZSI design techniques

Jbr anahg and cfrgitcrl circuits, Chapes 6 pp. 480-487, McGraw-Hdl,hc., 1990,

Extracting Steps and Fitting Results

The following 18 steps are based on the processe~ in the TMA's AUROM software using

measwed data for the Mitel 1.5 p m process [14].

First optimizatioif step

The wide-long gate characteristics (W/L=SOp/5Op) at zero back-bias are used to extract

the parameters vth0,uO,ua and ub in this step. The parameter K3 is set to zero to turn off

its effect and the effect of uc is not considered due to zero back-bias, V==O. The

parameter rd& is fixed to be zero, and the initial values of the parameters rdsw, keta are

zero. Fig. A. 1 shows the Ming results.

Figure A. 1 Resuiting fit for vht0, uo, ua, ub: (a) NMOS; (b) PMOS

Second Optimization Step

The second step is to extract the parameter dl, and dso vt.0, ua, ub. The wide-short gate

(W/L= 50p/lSp) characteristics at zero back-bias are fitted, but only the extracted value

(a) 0) Figure A.2 Resulting fit for VthO, ua, ub, and dl: (a) NMOS; (b) PMOS

Third Optimization Step

The third optirnization step fits the narrow-long characteristics in linear region at zero

back-bias with parameter dw. The parameters vth0, ua, and ub also are fitted in order to

get the optimization to fit the measured data property, but they are reverted the values

from step 1. The resulting fits are s h o w in Fig. A.3.

-6 Fint II lm DW (Ui?El DATA) . 25:

l0

PU)S

--malumd 2 -

WIL'W~O ---rUMrq f*

v b - O

v a 0.1

1 -

(a) (b) Figure A.3 Resulting fit for dw: (a) NMOS; (b) PMOS

inis sep r e m me me-long gare cnaracrensucs ar zero D~CK-DIW, W/L=~U p/3up, w m

parameters vth0, uO, ua, and ub. Fig. A.4 is the resulting fit.

. - Figure A.4 Re-fit vth0, uO, ua, ub: (a) WOS; (b) PMOS

Fifth Optimization Step

This step is to extract the parameters vth0, kl, and k2 fiom the wide-long (WIL=SOp/SOp)

gate characteristics at al1 back-biases. Fig. A S shows resulting fit.

Flgure A 5 Resulting fit vth0, kl, k2: (a) NMOS; (b) PMOS

parameters kl , k2, ua, ub and uc.

nie dl parameters opbized in this step are & d v e parameters for the next step.

For n-channel devices, the resulting fit agrees with the measured data weli without

refitting vth0, as show in Fig. A.6@). Bot the resulting fit is very poor at the substrate

voltage equal to -5v, as shown in Fig. A.6(a). So, the parameter vthO is refitted in this

step for p-chamiel transistors in order to obtain the optimization to fît the measured data

properly. The resulting fit with refitting vth0 for PMOS is shown m fig.A.6(c). It is better

than the fit shown in Fig.A.d(a).

(a) Figure A.6(a) Resulting fit for kl, B, ua, ub, and uc without re-fitting vtM)

Figure A.6 Resulting fits for kl,k2,ua,ub,uc: (b) NMOS; (c) PMOS with refitting vthO

Seventh Optimization step

This step is to extract the parameters vth0, ua, ub, uc, dl, rdsw, dvtû, dvtl, dvt2 and nix.

The wide-gate (W=SOpm) characteristics with âifferent lengths (L=U)p, 3 p or 5 p, 1.5 p)

at ali back-biases are fitted. The channel length of the p-channel device is 5pm instead

of 3pm used for the n-channel device in order to obtain the best fit in this step.

This step is unique to the BSIMJ mode1 fits to multiple devices. It is necessary

to use three different size devices for obtaining parameters dvt0, dvtl, and dvt2. The

resulting fits are shown in Fig. A.7-1, Fig. A.7-2, and Fig. A.7-3.

1 - - Wh- -

- 13- m-o.-26+

% va-ai

(a) (b) Flgure A.7-1 Resuiting fit for vth0, ua, ub, uc, dl, rdsw, dvt0, dvtl, dvt.2, nlx:

(a )NMOS; (b) PMOS

(a) Figure A.7-2 Resulting

(b) fit for vth0, ua, ub, UC, dl, rdsw, dm, dvtl, dvt2, nix:

(a) NMOS; (b) PMOS

Figure A.7-3 Resulting fit for vth0, ua, ub, uc. dl, rdsw, dvt0, dvt 1, dvt2, nlx: (a) NMOS; (b) PMOS

Eighth Optimization step

This optimization step fits the narrow-long ( W/L=l.Sp/lOp) gate characteristics at al1

back-biases (V,=O, -2.5 -5) with parameters dw, k3, wO, k3b and rdsO. Fig. A.8 shows

the resulting fit for this step.

-6 DW.KÎ.WO.tüB.FIDS0 (MITEL DATA)

Figure A.8 Resulting fit for dw, k3, wo, k3b, rds0: (a) NMOS; (b) PMOS

Ninth Optimization step

This step fits the wide-long ( W/L=50p/50pm) drain characteristics at zero back- bias with

79

(a) Figure A 9 Resuiting fit for vsat, ao: (a) NMOS; (b) PMOS

Tenth Optimization step

The tenth optimization step is to re-extract the parameters vth0, ua, ub, uc, dl, rdsw, dvt0,

dvtl, dvt2 and nlx. The wide gate (W=50p) characteristics with different lengths (L=50p,

3 p or 5 p, and 1.5 p) at ail back-biases are fitted. The resulting fits are shown in Fig. A. 10.

Figure A.lO-1 Resulting fit vthq ua, ub,uc, dl, rdsw, dvt0, dvtl, dvt2, and nîx: (a) NMOS; (b) PMOS

80

WlOB '- -

as- 6 . =-ga W.--

b - Q * - # Vb-aQq-8 5 - *-a1

Fîgure A.10-2 Resuiting fit fa vth0, ua, ub, uc, di, rdsw, ddv90, dvtl, dvt2, and nlx: (a) NMOS; (b) PMOS

Elgure A.1û-3 Fit for vth0, ua, ub, uc, dl, tdsw, dvt0, dvtl, dvt2, and nlx: (a) NMOS; (b) PMOS

Eleventh Optimization Step

This optimization step is to re-extract the parameters dw, k3, wû, k3b, rd& for narrow

long devices with W/L= 1.5 p/lO p. The r d t i n g fit is shown in Fig. A. 1 1.

Figure A.11 R d t i a g fit for dw, k3, wû, k3b, rd&: (a) NMOS; (b) PMOS

Twelfth Optimization Step

The twelfth step fits the wide channel(W~50p) drain 1-V charactenstics, varying lengths

(L= 1.5 p, 3 p or 5 p) at zero back-bias with parameters vsat, al, and pclm. The resulting fits

are shown in Fig. A.12.

(a) Figure A.12-1 Resuiting fit for vsat, al, pclm: (a) NMOS; (b) PMOS

(a) Figure A.12-2 R d t i n g fit for vsat,

(b) S, and pclm: (a) NMOS; (b) PMOS

Thirteenth Optimization Step

This step is to fit the wide channel (W150y) drain 1-V characteristics, varying channel

lengths (L=1.5p, 3p or 5p) at zero back-bias with parameters pclm, pdibll, pcûbl2, and

drout. The resulting fits are shown in Fig. A.13.

(a) Cb) Figure A.13-1 R d t i n g fit for pclm, pdibll, pdibl2 and b u t : (a) NMOS; (b) PMOS

(a) (b) Figure A.13-2 Resulting fit for pclm, pdibll, pdibi2, and b u t : (a) NMOS; (b) PMOS

Fourteenth Optimization Step

The fourteenth step repeats step 13 but fits to the target log (Gd), without fitting to ID.

The resulting fits are shown in Fig. A. 14.

Flgure A.14-1 Resulting fit for pcim, pdibll, pdibl2, drout: (a) NMOS; (b) PMOS

Figure A.14-2 Resulting fit for pclm, pdibl, pdibl2, drout: (a) NMOS; (b) PMOS

Fifteenth Optimization S tep

Step 15 concludes the Gd optimization steps by fitting the wide channel(W=SOp) drain

1-V characteristics, varying lengths (for n-channel L=1.5p and L=3p, for p-channel L= 1 . 5 ~

and L=5p) at zero back-bias with parameters pscbel and pscbe2. Fig. A. 15 shows the

resulting fits for pscbel and pscbe2.

W PSCBEI.PStBE2 IMITEL DATAI 0.014y 1

Fagure A.15-1 Plus of (a) I, showing fit (b) 1/Gd showing fit for pscbe 1 and pscbe2 for n-channel

85

Figure A.15-2 Rdting fit for pscbel and pscbe2 for PMOS: (a) ïD howingwing& (b) &!Gd showing fit

Figure A.15-3 Fit for parameters pscbel a d pscbe2 for n-dumnel transistor: (a) I,, fit; (b) llGd fit

Sixteenth Optimization Step

This optimization step is to extract the parameters nfactor, voff, vglow, and vghigh by

using the wide channel subîbreshold region, varying lengths at zero back-bias. The

resuiting fits are shown in Fig. A. 16.

Rgure A.16-1 Resulting fit for nfactor, voff, vglow, vghish: (a) NMOS; (b) PMOS

87

Figure A.16-2 ReSuiting fit for parameters nfactor, voff, vglow, vghigh: (a) NMOS; (b) PMOS

Seventeenth Optimization Step

This step is to extract the parameters dao, etab, and dsub by using the wide channel gate

characteristics at high V, varying lengths and aU back-biases. The resulting fits are

- shown in Fig. A. 17.

Figure A.17-1 Resulting fit for panuneters eta0, etab, and dsub: (a) NMOS, (b) PMOS

88

(a) (b) Figure A.17-2 Resulting fit for eta0, etab, and dsub: (a) NMOS; (b) PMOS

Figure A.17-3 R d t i n g fit for eta0, etab and dsub: (a) NMOS; (b) PMOS

Eighteenth Optimization Step

The last optimization step fits the drain characteristics of the wide channe1 devices for

three different lengîhs and non-zero back biases with the parameter keta. Fig. A.18 shows

the final drain characteristic fits for four different size devices, the wide-long devices with

- - - - - - - - - - - . - - - - . . ,- --r- , -r- , --- - - - - - - , - - - ,- -, - - - - - - -

both NMOS and PMOS. the narrow-long device for NMOS W/L-1.5p/lOp. and

W/L=3pJlOp for PMOS.

Flgure A.18-1 ReSulting fit to wide-long device with W/L-S0/50: (a) NMOS; (b) PMOS

(a) (b) Figure A.18-3 Resulting fit to wide-short device with W/L=50/1.5: (a) NMOS; (b) PMOS

Elgure A.lû-4 Resulting fît to narrow-long &vice: (a) NMOS with W/L=l+S/lO; (b) PMOS with W/L=3/10

To match the simulation results with the Spectre simulator to measwernent, some

extracted parameters of the BSIM3 mode1 were optimued and adjusted.

1 THRESHOLD VOLTAGE WITH CHANNEL LENGTH

As the chanael hgth bganes shoster, the drainfsource depletion regions begin to control

a significant fiaction of the charge under the gate. This can affect the threshold voltage.

The extracsion results indicate that the threshold voltage vthO increases with length for a

fixed channel width for n-channel transistors. The threshold voltage of PMOS transistors

also depenâs on the channel length, and inmeases with decreasing channel length, s h o w

in Figure 1-1. Drain currents with the threshold voltage vrhO are shown in Figure 1-2.

Figure 1-1 M e . thresboId Voltage Variation with Channel Lengths (a) NMOS (b) PMOS

Figure 1-2 Simutation resuits 4th Spectre for Id variation with vth0: (a) NMOS device with W/L=50p/15p1 solid line represents tbe smiulatim r d t with vW-û.830N; and brolcen line repseats the simulation result with vth0=0.728W, (b) PMOS &vice with W/L-5Op/1 Jp, solid line represents the simulation r e d t with vth0=0.678V, broken iine represents the simulation resuit with vth0=-0.568V.

2 EFFECT OF pscbel

The parameter pscbel, the first coefficient of substrate body m e n t effect, affects the 1-V

characteristics in the lower gate voltage and high drain voltage region for short channel

transistors. Considering Fig. 2.3-2 (a) and (c) (in QiapterZ), the drain current for both

NMOS and PMOS transistors inmeases quickly in this region because the value of pscbel

is too small. The 1-V characteristics were improved in this region by adjusting the

parameter pscbel. Fig. 2-1 (a) shows simulation results for an n-channel device in which

pscbel was changed from 5.2704*10" to 8.447*1@. Fig. 2-l(b) shows simulation results

for a p-channel transistor with pscblel equal to 3.3346*1@ and 5.8346*1@, respectively.

It is evident in these figures that before pscbel was adjusted, the drain current

increases quickly for drain voltages above 4V, with simcant errors. The solid lines

represent the simulation results using the adjusted value of the parameter pscbel and the

other parameters were not adjusted. Consequently, these changes significantly improve

measurement. The M e r adjusting is discusseâ in the foîîowing sections,

UV- - - -1-

3 EFFECT OF THE PARAMETER dvtl

There is some error between the simulation results and the measurement of the drain

current for short-channel devices as s h o w in Fig. 2-1. The parameter dvtl, the second

coefficient of short-channel eflects, was changed in order to match the simulation results

with the mea~u~ed data. The value of dvtl affects the drain current significantly for short

channel devices. The drain m e n t ais0 can increase by changing the parameters u0, v?hO,

or others. But the drain current of long-çhannel devices is affected if the parameter uo or

vthO is changed. The parameter dvtl changes only affect simulation resuits for short-

channel devices. To better match the simulation resuits with measmement, the parameter

Fig. 3-1 shows the simuiation results for an n-channel devia with W/L-50p/l.Sp.

Figure 3-1 Simulation tesults with Spectre for different dvtl for an n-charme1 transistor with W/L=SOp/l.Sp: The solid lines represent the simulation d t s for dvtl equal to 0.2207, which is used as the parameter value in the BSIM3 model. (a) Vgs-lV; (b) Vgs-2V and Vgs-3V

Figure 3-2 shows the simulation r d t s with different values of the parameter dvtl

'for a p-channel. The solid lines represent the simulation r d t s for the parameter dvtl

equal to 0.29536, which is used as the parameter value in the BSIM3 rnodel. The broken

lines represent the simulation r d t s for dvtl equd to 0.69536, which was obtained from

parameter extraction.

Frorn the figures, it is obvious that the dope of the drain current for simulation

results is s d e r than the meaSUTements in the saturation region. This problem can be

solved by changing the value of the parameter drout, the DIBL (Drain-induced barrier

lowering) effect on output resistance coefficient. The foilowing section shows how the

parameter &out afYects simulation results.

- -

However, it is also clear in Fig. 2.3-2(b) (in Chapter2) that the simulation results do not

(a) (b) Figure 3-2 Simulation resuiîs witb Spectre with different dvtl for a p-channel device with W/L=50/1.5:

(a) at Vgs=-IV, (b) at Vgs=-SV and Vgs=-3V

agree with meaSurementS well for a widelong &vice, in which the simulation results are

greater than the measurements. To -ove simulation results for long-channel devices,

the parameters vthO and uO were adjusted. These changes affect simulation results for a

short-channel device. Thus, some parameters that related to the short-channel device had

to be adjusted in order to get a better match not ody for long devices but also for short

devices.

4 EFFECT OF 'l'HE PARAMETER &out

a? 10-5 wh.ncliit(ll0

II PY)8

, & l m

3 , ,&10.45s3s -'- -.-~-.-._._._,_,

2 - - - -.m.-._. -.-.-.-._._ '-'-.-._._< - - - - - - - - _______ -.-.-.-.

1 - -lml1Q.- --------- ---------:

05 -& -; -& J -& 4 -1; -; -O> 8 m M

The parameter drout, the DIBL effect on output resistance coefficient, affects the 1-V

lom3 w ~ u r ~ u b

-- 1s. - m m

2 ,m44eSa -&l*.1961(

M#) fv)

characteristics in the saturation region as shown in Fig. 4-1. This parameter does not

affect the drain ment in the low drain voltage region, but it affects the drain curent in

the high drain voltage region for short channel devices. It means that drout affects the

. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - . - - - A -

devices. The simulation results for an n-channel device are show in Fig. 4-l(a), in which

the parameter drout was adjusted fiom 0.5076 to 0.4076. Fig. 4-2(b) shows simulation

results for a pchannel transistor, in which the parameter &out was changed from 0.48249

to 0.38749. The solid lines represent the simulation results using adjusted values for the

parameter drout. The simulation results match the measurements weli.

Figure 4-1 Simulation results with Spectre using different values of the parameter drcnit: (a) N-chamel device with WfL-50/1.5, solid lines represent drout-0.4076, broken lines represent &out=0.5076; (b) P- channe1 device with w/i-50/1.5, solid lines represent drou~0.38749, broken luies represent drout=0.48249

5 EFFECT OF THE PARAMETER vo#

The parameter wfl, the threshold voltage offset, affects the drain current significantly in

the low gate voltage region for a narrow device. The extracted value of the parameter WH

for an n-channel device is 0.0698, which is too small to get good simulation results at

low gate voltage. If the value of the parameter w# was changed ftom -0.0698 to -0.188,

the simulation results matched the measurements well as show in Fig. 5-1. This

'il

Figure 5-1 Drain current variation with the parameter voff for a narrow device witb Wb-l.Sp/lOp

6 EFFECT OF THE PARAMETERS vsuf, wO

The parameter vsat, the carrier saturation velocity, was adjusted for bot. NMOS and

PMOS to match the simulation results with the measured data better for a short-charnel

device. This parameter affects simulation resdts for a short channel device more than a

long channel device. For example, if the parameter vsat was changed from 1.0863*1@

to l.l77*lû' for an n-channel device with W/L=50p/lSp, the drain current increases from

2.382mA to 2.42mA at Vgs=2V and Vds=W; for a device with W/L=50p/50p, the drain

current changes from 39.23pA to 39.24pA at the sarne voltage condition. The parameter

wO, the narrow width coefficient, was also adjusted in order to match the simulation

results with measured data for nmow channel devices.

---- - - - - - --- - - - - = . . - -. - - - - - - - - - L

/tooIs.sun4/dfLYlocai_Vl.4/lib/mitell5.1 .O~els/spectre/mitell5.~pectre.

This mode1 set was releaseà by Canadian Microelectronics Corporation in July 25,

The NMOS Lam43 modd parameters:

.MODEL Mitelnmos mos3 type Id ldif wd xl vto tpg nsub cgdo cgso capmod XPart tox j s 4 cjsw mj mjsw pb rsh rd rs gapl gap2 delta eta kama nfs

n 1 -94 le-07 8.059e-07 - 1.279e-07 - 1.269e-07 0.8404 1 *O 1.345e+16 2.716e-10 2.71k-10 mey er 0.5 2.671e-08 2.50e-03 3.161e-W 2.145e-10 0.3570 0.2847 0.7191 202.6 462 462 4.73e-04 6.36eN2 1.721 2.223e-02 0.2620 5.161e+ll

The NMOS mode1 fiie used in Spectre

.mode1 Mitelnmos nmos level-3.0 ld- 1.94 l e 4 7 wd=-1.279e-07 A=- 1.269e-07 \ vtox0.8404 tpg-1.0 nsub=1.345e+ 16 cgdo=2.716e-10 \

cgsot2.716e-10 tox=2.671e-û8 js=2,50e-03 cj=3.161e-04 \

cjsw-2. M e - 10 mj=0.3570 mjsw=0.2847 pbzO.7 19 1 rd=462 \

rs=462 gap 1 =4.73e-O4 gap2=6.3&+02 delta= 1.72 1 eta=2.223e-02 \

kappa-0.2620 nfs=5.161e+ 1 1 theta=4.090e-02 vmax=2.383e+05 \

xj-2.197e-07 u0=527.2 xpart=0.5 ldif=8.059e-07 capmod=meyer \

type level Id ldif wd xl vto tpg nsub cgdo cgso capmod XPart tox j s cj cjsw mj mjsw pb rsh rd rs

@PI gap2 delta eta kappa nfs theta max xj UO

P 3.0 1.735e-O7 8.265e-07 -2,179e-07 - 1 -267e-OT 4.728 1 -1.0 3.947e+ 16 2.534e-10 2.534e-10 me yer 0.5 2.672e-08 2.50e-03 2.898e-04 Z.OS2e- 10 0.3566 0.2450 0.2259 393.4 896 896 4.73e-04 6.36e+02 1.829 1 S22e-02 9.994 9.275e+ 10 O. IO49 2.79Se+05 l.762e-W 193.7

vto=-0.728 1 tpg=- 1 .O nsub=3.947e+ 16 cgdos2.534e- 10 \ cgso=2.534e-10 tox=2.672e-08 js=2.50e-03 cj-2.898e-04 \

cjsw=2.052e-10 mjs0.3566 mjsw=0.2450 pbe0.2259 rd-896 rs=896 \

gapl=4.73e-û4 gap2=6,36e+02 delta- 1.829 eta= 1.522e-02 \

kappa=9.994 nfs=9.275e+ 10 thetauo. 1049 vmax=2.795e+05 \

xj= 1.76242-07 uo= 193.7 xpart ~ 0 . 5 ldif=8.26Se-07 capmod-meyer

g-1

g-

theta

eta

lit1

dvtO

dvt 1

dvt2

a0

al

a2

keta

nsub

tox

Threshold voltage at zero body bias

Surface potential at strong inversion

Body-effect coefficient

Charge-sharing parameter

Narrow width coefficient

Narrow width coefficient

Narrow width coefficient

Lateral nonuniforni doping coefficient

Body-effect coefficient near the surface

Body-effect coefficient in the bulk

Drain-induced barrier lowering coefficient

Effective drain voltage coefficient

Depth of current path

First coefficient of short-channel effects

Second coefficient of short-channe1 effects

Body-bias coefficient of short-channel effects

Nonuniforrn depletion width effect coefficient

No-saturation coefficient

No-saturation coefficient

Body-bias coefficient for non-uniform depletion width

effect

Substrate doping concentration

Peak channel doping concentration

Sou.rce/drain junction depth

Lateral diffusion for one side

Width reduction for one side

Gate oxide thickness

A L

ldd

rdsO

rdsw

uo

vsat

ua

ub

UC

satmod

bulkmod

&out

alpha

em

p c h pdibl 1

pdibl2

pscbel

pscbe2

Pvag

subuimod

vghigh

vglow

cdsc

cdscb4

nfactor

cit=O

voff

U n U W y U A 6 U W y b A i

m Total length of lightfy doped drain region

B Total drain-source raistance

D*pm Width dependence of drain-source resistance

cm2/V*s Low-field surface mobiity at ' tnom'

m/s Carrier saturation velocity at ' tnom'

m/v First-oder mobiity reduction coefficient

m2/g Second-der mobility reduction coefficient

Body-bias dependence of mobility

Saturation model selector

Bulk-charge effect model selector

DIBL effect on output resistance coefficient

Reference voltage muitiplication factor

Maximum electric field

Channel length modulation coefficient

Fist coefficient of drain-induced barrier lowering

Second coefficient of drain-induced barrier lowering

First coefficient of substrate current body effect

Second coefficient of substrate current body effect

Gate dependence of Early voltage

Subthreshold model selector

Upper bound of transition region

Lower bound of transition region

Source]&ain and channel coupling capacitance

Body-bias dependence of ' cdsc'

Subthreshold swing coefficient

Interface trap parameter for subthreshold swing

Threshold voltage offset

104

cgso

mjsw

capmod

Y-- "WI**"."I.* YYVYYVYI IVLY *"e*VI.

Band gap temperature coefficient

Band gap temperature offset

Body-bias dependence of ' etO'

Bulk junction reverse saturation current density

Bulk junction reverse saturation current

Explosim current density

Gate-source overlap capacitance

Gate-drain overlap capacitance

Gate-bulk overlap capacitance

Zero-bias junction bottom capacitance density

Buik junction bottorn grading coefficient

Bulk junction built-in potential

Zero-bias junction sidewall capacitance density

Bulk junction sidewall grading coefficient.

Intnnsic charge model

Drain/source channel charge partition in saturation for

BSIM charge model, use 0.0 for 40160, 0.5 for 50/50, or

1.0 for 0/100.

Drain/source channel charge partition in saturation for

charge models

vaiues usea ror me Ypectre sunulator m Analog m s t LZJ. The parameters vsat, Who,

dvtl, pscbel, drout, dsub and voff are adjusted for NMOS.

Table 1-1 NMOS B S W mode1 Parameters

Parameter Extracted Adjusted 'mical

vtM) 0.8187 0.8307

ki 055678 0.55678 0.53

dvtO 0.9653 0.9653 2.2

dvt 1 0.3157 0.2257 0.53

dl 3 .O 144e-7 3.01 14e-7 O

--

~ b e 2 1.k-2 1.0e-3 l.Oe-5

a0 0.47712 0.477 12 1

al O O O

a2 1 1 1

tox 2.671e-8 2.671e-8 1 Se-8

xj 2.0e-7 2.0e-7 1%-7

voff -0.069784 -0.188 -0.11

vglow -0. 10438 -0.1044 -0.12

Idd O O O

eta 0.3 0.3 0.3

dvt2 -0.1938 -0.1938 -0.032

lteta 4.8983e-3 -8.8983e-3 4.7e-2

w0= 1.4637e-06 nlx=2.487 le-7 etac0.3 dvt0=0.9953 dvt l=O.2207 \

da=-1.93800000E-01 a0=0.47712 al=0 a2= 1 keta=-8.89830000E-03 \

npeak=lel7 xj=S.Oe-07 dl=3.0114e-07 dw=1.1923e-O8 toxz2.671e-O8 \

vdd=5 xt=lSe-7 ldd=O rds0-0 rdsw=2105 u0=597 vglow=-1.0500000E-01 \

vghigh=l.lSE-ûl vsat=l.l77eS ua44942e-09 ub=5.87e-19 uc=7.2413e-3 \

satmod=2 drout=O.4076 alpha= 1 9 em4e7 pch= 1.3724 pdibll =O.2463 \

pdibl2= 1 -4542e-02 pscbel=8.447e8 pscbe2= le-3 pvag =O subthmod=2 \

nfactor=0.6314 cdscb=O cdsc=2.4e-04 cit=O voff=-0.6780E-01 \

eta0=3.6555e-2 etaba4.0909e-2 ute=-l.50000000E+00 k3b=-7.62 10E+00 \

dsub=0.4076 cgdo=2.716e- 10 cgso-2.716e- 10 js=2.50e-O3 cj=3.16 le-04 \ cjsw-2.14Se-10 mj=0.3570 mjsw=0.2847 pb=O.7 19 1 xpart=O.S \

capmod=bsim x q ~ O . 5

----+- ---..-- - -r----- The adjusted parameter values for vth0, vsat, dvtl, drout, wO, drout and pscbel

were obtained by trial and error in order to provide a better match between simulation

results and measured data.

Table 2-1 PMOS BSïM3 mode1 parameters

Parameter Extracted Optimized Typicai

vth0 056855 0.6785

kl 1.6122 1.6122 0.53

d x 2.487 le-7 2.487le-7 1.74e-7

dvîû 1.05 18 1.0518 2.2

dvt 1 0.69536 0.29536 0.53

a2 0.5393 0.5393 0.08

tox 2.67le-8 2.67 le-8 I Se-8

xi 2.e-7 2.k-7 1 .Se-7

npeak 1.0e+ 17 l.ûe+ 17 1.0e+ 17

von

vglow -7.926 le-2 -7.9261e-2 -0.12

u0 217.7 220 250

Idd O O O

eta 0.3 0.3 0.3

dvt2 -1.0 -1.0 -0.032

keta -3.857e-2 -3.857e-2 4.7e-2

k3=36.054 wOe3.6890e-06 nlx~2.487 le-7 eta=0.3 dvt0= 1 .O5 18 b u h o d = 1 \

dvtlz0.29536 dvt2=- 1.00000000E+OO aOz0.26326 al =O a2=0.5393 \ keta=-3.85700000E-02 npeak= 1 .Oel7 xj= 1.762e-07 dI=2.8592e-07 \

dw-6.1978e48 tox-2.671e-08 vdd=5 xt-1.55e-7 ldd=O rds0=100 rdsw=O \

uO=220 vglow-7.926100E-02 vghigh=O. 101 8 vsat= 1 -795e5 ua-2.9949e-09 \

ub= 1 S8Sge- 18 uc=0.022944 satmod=2 drout =O. 38749 alpha= 1.9 em=4e7 \

pch=3.0564 N b 1 1 =O.65@ @b12=7.2743e-3 pscbe 1 =S. 8346e8 pscbe2= le-4 \

pvag=û subthrnod=2 cdscb4 nfactorzl cit=O voff=-5.2676OûûûE-O2 \

eta0~4.6488 etab=-3.97270E+00 ute=-1.500E+00 k3b=-6.14920000E+00 \

dsub-6.0427 cgdo=2.534e-10 cgso=2.534e-10 js=2.50e-03 cj=2.898e-04 \

cjsw=2.052e-10 mjz0.3566 mjsw=0.2450 pb=0.2259 xpart=0.5 caprnod=bsh \

xqc-0.5 cdsc=2.4e-04

r ne measurea aara was proviaea oy Mirel Lorporation.

There are three directories which represent difTerent wafer numbers for the

measurements, for each of the NMOS and the PMOS devices:

The data files of waferl is in the directory named 24457-10.

The data files of wafer2 is in the directory named 24622-23.

The data files of wafer3 is in the directory named 23808-13.

Each wafer has three sites, and each site includes 10 devices with different sizes,

respectively . The narne of the data file is defmed as: M-NX,mX2SVX3X4

M:

N:

X,:

m:

X,:

Sv:

x3: x-4:

Measurement Fie

Measurement done at normal temperature

Measurement site (1, 2, or 3)

Measurement for an MOS device

Device type, n or p ( n represents n-channel, p represents p-channel)

Process operating at 5 volts

Partidar transistor size (1-10)

Represents a measurement setup (1- Gate characteristics,

2- Drain characteristics, 3 Subthreshold characteristics)

Gate characteristics: I,, with V,, ( from O to 5V, step 0.1V ) for Vm=O.lV,

V==O, -2.5, -SV,

Drain characteristics: I,, with V,, ( fkom O to 5V, step 0.25V) for V,,=l, 2, 3, 4, SV,

VmzO, -2.5 -SV,

Subthreshold characteristics: 1, with Vos ( from O to SV, step 0.05V)

for Vm=O.l, 2.6, 5.1V, VBs=O, -2.5, -SV;

For each site, there are 10 device sizes as foiiow:

1 - W/L=SOp/5Op

2 - W/L=5Op/1.5p

3 - W/L=l.Sp/lOp

4 - w/L=50p/3p

5 - W/L=3p/lOp

6 - W/L=50p/1.7p

7 - W/L=SOp/1.8p

8 - W/L=5Op/2p

9 - W/L=5Op/5p

10- W/L=SOp/lOp

OUT

A iyl v

Al +

COM - . O L

SMU CuIrent Source

O

Figure 1 Operation modes of the SPA

+

SBJl Voltage souzce/Current moni tor

I

1

Figure 2 Test circuit using the SPA

Vol tagoMoni tor

-

resistances which is VJi$,,=RJ(R,+RJ. The ratios of the resistances for Curve 1 and

Curve 2 shown in Fig. 3 are 0.0202 and 0.0386, respectively. The test results are

pre~enfed in Table 1.

Fîgure 3 Measurement of the input and the output of the attenuators

Table 1 Measmernent of the input voltage and the output voltage for the attenuator by using the SPA, the ratio of the attenuatm is 20.76/1027.3=0.0202

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