your first priority i want to hear from you…
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Course Webpage
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https://www.seas.upenn.edu/~ese570/
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ESE 570: Digital Integrated Circuits and VLSI Fundamentals
Lec 1: September 1, 2021Introduction and Overview
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Your First Priority
! Your first priority is your health" You should abide by all health guidelines
" Wear a mask" Wash your hands
" Don’t touch your face" Maintain social physical distancing
" Careful and thoughtful social interaction is encouraged!" Stay home if you’re sick
" Part of your health is your mental and emotional health" See https://caps.wellness.upenn.edu/selfhelp/ for help
" For more: https://coronavirus.upenn.edu/
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I want to hear from you…
! Accessibility Survey in Canvas" Submit by Saturday for full HW credit
! Will you be in a different time zone?! Will you have trouble seeing or hearing video
lectures?! Are there any other accessibility issues I should
know about?
! Let me know any concerns -- I will do everything I can to ensure you achieve the learning objectives
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Where I come from
! Analog VLSI Circuit Design (analog design)! Convex Optimization (system design)
" System Hierarchical Optimization! Biomedical Electronics ! Biometric Data Acquisition (signal processing)
" Compressive Sampling
! ADC Design (mixed signal)! Low Energy Circuits (digital design)
" Adiabatic Charging
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Where I come from
! Analog VLSI Circuit Design (analog design)! Convex Optimization (system design)
" System Hierarchical Optimization! Biomedical Electronics ! Biometric Data Acquisition (signal processing)
" Compressive Sampling
! ADC Design (mixed signal)! Low Energy Circuits (digital design)
" Adiabatic Charging
CIRCUITS, CIRCUITS, CIRCUITS
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Lecture Outline
! Course Topics Overview! Learning Objectives! Course Structure! Course Policies! Course Content! Industry Trends ! Design Example
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VLSI Design
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300 mm (12 in.)
Oracle SPARC M7 Processor
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Course Topics Overview
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Design
Implementation/Fabrication
Course Progression
Course Topics
CMOS Fabrication
MOS Transistor, Capacitor and Interconnect Models
Two Transistor Logic Circuits (Inverters)Static Dynamic
Logic Circuits, Gates, Latches
Regular StructuresROMs, RAMs, PLAs
μPs, Custom LogicVLSI Sub-systems
System-Related IssuesReliability
ManufacturabilityTestability
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Learning Objectives
! Apply principles of hierarchical digital CMOS VLSI, from the transistor up to the system level, to the understanding of CMOS circuits and systems that are suitable for CMOS fabrication.
! Apply the models for state-of-the-art(ish) VLSI components, fabrication steps, hierarchical design flow and semiconductor business economics to judge the manufacturability of a design and estimate its manufacturing costs.
! Design digital circuits that are manufacturable in CMOS.! Design simulated experiments using Cadence to verify the integrity of a
CMOS circuit and its layout.! Apply the Cadence VLSI CAD tool suite layout digital circuits for CMOS
fabrication and verify said circuits with layout parasitic elements.! Apply course knowledge and the Cadence VLSI CAD tools in a team based
capstone design project that involves much the same design flow they would encounter in a semiconductor design industrial setting. Capstone project is presented in a formal report due at the end of the semester.
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Learning Objectives
! In other words…
!Design in CADENCE*
*All the way to layout/manufacturability
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What is Cadence?
! Industry standard CAD software for IC design! Schematic capture
" Create netlist (software code describing schematic)! SPECTRE/SPICE simulator
" Mathematical solver of differential equations describing fundamentals (Ex. KCL/KVL, Ohm’s law, etc.)
! Design physical mask layers used for fabrication! Extract parasitics from physical layout for
simulation
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Schematic Capture
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Schematic Capture
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Layout in Cadence
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Course Structure
! MW Lecture, 3:30-5:00pm in Towne 337" Recordings posted in Canvas afterwards
! Website (http://www.seas.upenn.edu/~ese570/)" Course calendar is used for all handouts (lectures slides,
assignments, and readings)" Canvas used for assignment submission, grades and
lecture videos" Piazza used for announcements and discussions
" Use for Zoom links for OHs
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Course Structure
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! Course Staff (complete info on course website)! Instructor: Tania Khanna
" Virtual OH: T 1-2pm" In person OH: W 1-2:30 pm " Or OH by appointment" Email: [email protected]
" Best way to reach me
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TA Introduction: Adzo Fiagbenu
! Hello, ESE 570 😀.! My name is Adzo (Ah-joe)
Fiagbenu! I am an electrical engineering
master’s student who took the course in Fall 2020. I am excited to help you in the capacity of a TA this semester, while learning from and with you.
! Fun fact: My pet and I shared the same name because we have a lot in common 😀.
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! In person/virtual OH: Th 12:30-2:30pm
! Virtual OH: Sa 12-2pm
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TA Introduction: AJ Geers
! I am a second year ESE PhD student
• Advised by Dr. Aflatouni• Research in electronic-
photonic integrated circuits
! I took this course in Spring 2019 and TA’ed in Spring 2020
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! In person OH: W 5-7pm ! Virtual OH: F 8-10am
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Course Structure
! Lectures " Statistically speaking, you will do better if you come to
lecture" Better if interactive, everyone engaged
" Asking and answering questions
" Actively thinking about material
! Textbook" Digital Integrated Circuits, A Design Perspective, Jan M.
Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, 2nd
edition" Additional useful texts on course website
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Course Structure
! Cadence" Technology: AMI .6u C5N (3M, 2P, high-res)" Schematic simulation (SPECTRE simulator)
" Design, analysis and test
" Layout and verification" Analog extracted simulation" Verilog (optional)
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Course Structure - Assignments/Exams
! Homework – 1 week long (8 total) [25%]" Due Sundays at midnight" HW 1 out now
! Projects – 2+ weeks long [50%]" Design oriented" Projects
" Two projects combine to design and layout combinational logic block used in FPGAs
" Proj 1 – 20%, Proj 2 – 30%
! Midterm exam [25%]" In class (alternate/makeup for remote students)
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Course Policies
See web page for full details! Turn homework in Canvas
" Anything handwritten/drawn must be clearly legible" Submit CAD generated figures, graphs, results when
specified" Late Policy – allowed 4 late days for whole semester
" Can only use a max of one day on projects
! Individual work " CAD drawings, simulations, analysis, writeups" May discuss strategies, but acknowledge help
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Course Content
! Introduction! Fabrication! MOS Transistor Theory and
Models! MOS Models and IV
characteristics! Inverters: Static Characteristics
and Performance! Inverters: Dynamic
Characteristics and Performance! Combinational Logic Types
(CMOS, Ratioed, Pass) and Performance
! Sequential Logic! Dynamic Logic! VLSI design and Scaling! Memory Design
! I/O Circuits and Inductive Noise
! CLK Generation! Transmission Lines
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Course Content
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https://www.seas.upenn.edu/~ese570/fall2021/syllabus.html
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Industry Trends
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Microprocessor Trans Count 1971-2015
27Kenneth R. Laker, University of Pennsylvania, updated 20Jan15
Curve shows transistor count doubling every
two yearsPentium
40048006
8080Mot 6800
8086
Mot 6800080286
80386
80486
MOS 6502Zilog Z80
80186
AMD K5Pentium II
Pentium IIIAMD K7
Pentium 4AMD K8
AMD K10 AMD 6-Core Opteron 24004-Core i7
2-Core Itanium 26-Core i76-Core i716-Core SPARC T3
10-Core Xenon IBM 4-Core z196IBM 8-Core POWER7
4-Core Itanium Tukwilla
2015: Oracle SPARC M7, 20 nm CMOS,32-Core, 10B 3-D FinFET transistors.
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Intel Cost Scaling
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http://www.anandtech.com/show/8367/intels-14nm-technology-in-detail
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Trend – “Minimum” Feature Size vs. Year
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Process Node/”Minimum” Feature
Year1960 1980 2000 2020 2040
100 µm
10 µm
1 µm
0.1 µm
10 nm
1 nm
0.1 nm
Integrated Circuit History
0.18 µm in 1999
“Distant” Future?
ITRS Roadmap
Transition Region
Quantum Devices
Atomic Dimensions
“Minimum” Feature Measure = line/gate conductor width or half-pitch (adjacent 1st metal layer lines or adjacent transistor gates)
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Present!
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More Moore # Scaling
! Geometrical Scaling" continued shrinking of horizontal and vertical physical
feature sizes! Equivalent Scaling
" 3-dimensional device structure improvements and new materials that affect the electrical performance of the chip even if no geometrical scaling
! Design Equivalent Scaling" design technologies that enable high performance, low
power, high reliability, low cost, and high design productivity even if neither geometrical nor equivalent scaling can be used
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22nm 3D FinFET Transistor
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Tri-Gate transistors with multiple fins connected together
increases total drive strength for higher performance
http://download.intel.com/newsroom/kits/22nm/pdfs/22nm-Details_Presentation.pdf
High-k gate
dielectric
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ITRS 2.0 Report 2015
! “After 2021, the report forecasts, it will no longer be economically desirable for companies to continue traditional transistor miniaturization in microprocessors.”
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BUT…
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BUT…
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More than Moore # Functional Diversification
! Interacting with the outside world" Electromagnetic/Optical
" Radio-frequency domain up to the THz range" Optical domain from the infrared to the near ultraviolet
" Hard radiation (EUV, X-ray, γ-ray)
" Mechanical parameters (sensors/actuators)" MEMS/NEMS position, speed,
acceleration, rotation, pressure, stress, etc.
" Chemical composition (sensors/actuators)" Biological parameters (sensors/actuators)
! Power/Energy" Integration of renewable sources, Energy storage, Smart
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More-than-Moore
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“More-than-Moore”, International Road Map (IRC) White Paper, 2011.
International Technology Roadmap for Semiconductors
Scal
ing
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“More-than-Moore”
! Components Complement Digital Processing/Storage Elements in an Integrated System
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Semiconductor System Integration – More Than Moore's Law
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1010
109
108
107
106
105
104
103
102
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Transistors/cm2
1010
109
108
107
106
105
104
103
102
10
Components/cm
2
1970 1980 1990 2000 2010 2020
MultichipModule
System-on-package
(SOP)
R. Tummala, “Moore's Law Meets Its Match”, IEEE Spectrum, June, 2006
SOP law for system integration. As components shrink and boards all but disappear, component density will double every year or so.
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Societal Needs
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Improvement Trends for VLSI SoCs Enabled by Geometrical and Equivalent Scaling! TRENDS:! Higher Integration level
" exponentially increased number of components/transistors per chip/package.
! Performance Scaling" combination of Geometrical
(shrinking of dimensions) and Equivalent (innovation) Scaling.
! System implementation" SoC + increased use of SiP -
> SOP
! CONSEQUENCES:! Higher Speed
" CPU clock rate at multiple GHz + parallel processing.
! Increased Compactness & less weight" increasing
system integration.
! Lower Power" Decreasing energy
requirement per function.
! Lower Cost" Decreasing cost per
function.40Penn ESE 570 Fall 2021 - Khanna
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Trends in Practice at ISSCC (HW 1)
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Design Example
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Sample Problems
! What does this circuit do?
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Sample Problems
! What does this circuit do? How fast does it operate?
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Sample Problems (con’t)
! What does this circuit do? How are A, B, C related?
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Sample Problems (con’t)
! What does this circuit do? How are A, B, C related?
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Sample Problems (con’t)
! What’s wrong here? How do we fix it?
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VLSI Design Cycle or Flow
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Verilog/SPICE
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VLSI Design Cycle or Flow
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Verilog/SPICE
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Functional Specification:
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! 8-bit Ripple Adder
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Illustrative Circuit Design Example: VLSI Design
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Illustrative Circuit Design Example: System Requirements
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Functional Specification:
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Illustrative Circuit Design Example: Architecture Definition
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Illustrative Circuit Design Example: Logic Design
! Gate Level Schematic of One-Bit Full Adder Circuit
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VLSI Design Cycle or Flow
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Verilog/SPICE
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Design Specifications:
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Illustrative Circuit Design Example: System Requirements
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1. Propagation Delay Times of SUM and CARRY_Out signals: ≤ 1.2 ns2. Rise and Fall Times of SUM and CARRY_Out signals: ≤ 1.2 ns3. Circuit Die Area: ≤ 1500 um2
4. Dynamic Power Dissipation (@ VDD = 5 V and f max = 20 MHz): ≤ 1 mW
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Functional Specification:
Design Specifications (in 0.8 twin-well CMOS):
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Illustrative Circuit Design Example: VLSI Design
! Transistor Level Schematic of One-Bit Full Adder Circuit
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N1 N2
N1 N2
SUMOUTCOUT
COUT
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Illustrative Circuit Design Example: VLSI Design and Layout
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! Initial Layout of One-Bit Full Adder Circuit
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COUT
Dynamic Power Dissipation (@ VDD = 5V, f max = 20 MHz): = 0.7 mW ≤ 1 mW
≤ 1500 um2
Illustrative Circuit Design Example: VLSI Design and Layout
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Post Layout Simulation (Analog extracted)
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Schematic to layout
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Post Layout Simulation (Analog extracted)
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Layout to schematic
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Spec NOTmet
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Illustrative Circuit Design Example: Design Verification
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Admin
! Find web, get text, assigned reading…" http://www.seas.upenn.edu/~ese570" https://piazza.com/upenn/fall2021/ese570/" https://canvas.upenn.edu/
! Submit Accessibility Survey" Due Saturday Sept 4
! HW 1 posted now" Due next week Sept 12
! Remaining Questions?
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