xmc1300 data sheet - infineon technologies
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Data SheetV2.0 2017-10
Microcontrol lers
XMC1300 AB-StepMicrocontroller Seriesfor Industrial Applications
XMC1000 Family
ARM® Cortex®-M032-bit processor core
Edition 2017-10Published byInfineon Technologies AG81726 Munich, Germany© 2017 Infineon Technologies AGAll Rights Reserved.
Legal DisclaimerThe information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party.
InformationFor further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com).
WarningsDue to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office.Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Data SheetV2.0 2017-10
Microcontrol lers
XMC1300 AB-StepMicrocontroller Seriesfor Industrial Applications
XMC1000 Family
ARM® Cortex®-M032-bit processor core
XMC1300 AB-StepXMC1000 Family
Data Sheet V2.0, 2017-10
TrademarksC166™, TriCore™, XMC™ and DAVE™ are trademarks of Infineon Technologies AG.ARM®, ARM Powered® and AMBA® are registered trademarks of ARM, Limited.Cortex™, CoreSight™, ETM™, Embedded Trace Macrocell™ and Embedded TraceBuffer™ are trademarks of ARM, Limited.
XMC1300 Data Sheet
Revision History: V2.0 2017-10Previous Version: V1.9 2017-03Page SubjectsPage 10,Page 13
Add marking option for XMC1302-T28X0032, XMC1302-T28X0064, XMC1302-T28X0128, XMC1302-T28X0200.
We Listen to Your CommentsIs there any information in this document that you feel is wrong, unclear or missing?Your feedback will help us to continuously improve the quality of this document.Please send your proposal (including a reference to this document) to:[email protected]
XMC1300 AB-StepXMC1000 Family
Table of Contents
Data Sheet 5 V2.0, 2017-10
1 Summary of Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.2 Device Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101.3 Device Type Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121.4 Chip Identification Number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2 General Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.1 Logic Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162.2 Pin Configuration and Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182.2.1 Package Pin Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222.2.2 Port I/O Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252.2.3 Hardware Controlled I/O Function Description . . . . . . . . . . . . . . . . . . . 27
3 Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.1 General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.1.1 Parameter Interpretation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333.1.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343.1.3 Pin Reliability in Overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353.1.4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373.2 DC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.2.1 Input/Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383.2.2 Analog to Digital Converters (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 423.2.3 Out of Range Comparator (ORC) Characteristics . . . . . . . . . . . . . . . . . 463.2.4 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 483.2.5 Temperature Sensor Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 493.2.6 Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503.2.7 Flash Memory Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553.3 AC Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563.3.1 Testing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563.3.2 Power-Up and Supply Monitoring Characteristics . . . . . . . . . . . . . . . . 573.3.3 On-Chip Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593.3.4 Serial Wire Debug Port (SW-DP) Timing . . . . . . . . . . . . . . . . . . . . . . . 613.3.5 SPD Timing Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623.3.6 Peripheral Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633.3.6.1 Synchronous Serial Interface (USIC SSC) Timing . . . . . . . . . . . . . . 633.3.6.2 Inter-IC (IIC) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663.3.6.3 Inter-IC Sound (IIS) Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . 68
4 Package and Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704.1 Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704.1.1 Thermal Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704.2 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table of Contents
XMC1300 AB-StepXMC1000 Family
Table of Contents
Data Sheet 6 V2.0, 2017-10
5 Quality Declaration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
XMC1300 AB-StepXMC1000 Family
About this Document
Data Sheet 7 V2.0, 2017-10
About this DocumentThis Data Sheet is addressed to embedded hardware and software developers. Itprovides the reader with detailed descriptions about the ordering designations, availablefeatures, electrical and physical characteristics of the XMC1300 series devices.The document describes the characteristics of a superset of the XMC1300 seriesdevices. For simplicity, the various device types are referred to by the collective termXMC1300 throughout this document.
XMC1000 Family User DocumentationThe set of user documentation includes:• Reference Manual
– decribes the functionality of the superset of devices.• Data Sheets
– list the complete ordering designations, available features and electricalcharacteristics of derivative devices.
• Errata Sheets– list deviations from the specifications given in the related Reference Manual or
Data Sheets. Errata Sheets are provided for the superset of devices.Attention: Please consult all parts of the documentation set to attain consolidated
knowledge about your device.
Application related guidance is provided by Users Guides and Application Notes.Please refer to http://www.infineon.com/xmc1000 to get access to the latest versionsof those documents.
XMC1300 AB-StepXMC1000 Family
Summary of Features
Data Sheet 8 V2.0, 2017-10
1 Summary of FeaturesThe XMC1300 devices are members of the XMC1000 Family of microcontrollers basedon the ARM Cortex-M0 processor core. The XMC1300 series addresses the real-timecontrol needs of motor control, digital power conversion. It also features peripherals forLED Lighting applications.
Figure 1 System Block Diagram
CPU Subsystem• CPU Core
– High-performance 32-bit ARM Cortex-M0 CPU– Most 16-bit Thumb and subset of 32-bit Thumb2 instruction set– Single cycle 32-bit hardware multiplier – System timer (SysTick) for Operating System support
16k SRAM
200k + 0.5k1)
Flash
8k ROM
PRNG
Memories
Flash SFRs
1) 0.5kbytes of sector 0 (readable only).
AHB-Lite Bus
16-b
it AP
B B
us
AHB to APB Bridge
PAU
Cortex-M0 CPU
Debug system
SPD
SWD
NVICEVR
Temperature sensor
2 x DCO
Analog system
ANACTRL SFRs
SCU
WDT
MATH
PORTS
RTC
CCU40
USIC0
VADC
ERU0
ACMP & ORC
BCCU0
CCU80
POSIF0
XMC1300 AB-StepXMC1000 Family
Summary of Features
Data Sheet 9 V2.0, 2017-10
– Ultra low power consumption• Nested Vectored Interrupt Controller (NVIC)• Event Request Unit (ERU) for processing of external and internal service requests• MATH Co-processor (MATH)
– CORDIC unit for trigonometric calculation – division unit
On-Chip Memories• 8 kbytes on-chip ROM• 16 kbytes on-chip high-speed SRAM• up to 200 kbytes on-chip Flash program and data memory
Communication Peripherals• Two Universal Serial Interface Channels (USIC), usable as UART, double-SPI,
quad-SPI, IIC, IIS and LIN interfaces
Analog Frontend Peripherals• A/D Converters
– up to 12 analog input pins– 2 sample and hold stages with 8 analog input channels each– fast 12-bit analog to digital converter with adjustable gain
• Up to 8 channels of out of range comparators (ORC)• Up to 3 fast analog comparators (ACMP)• Temperature Sensor (TSE)
Industrial Control Peripherals• Capture/Compare Units 4 (CCU4) as general purpose timers • Capture/Compare Units 8 (CCU8) for motor control and power conversion• Position Interfaces (POSIF) for hall and quadrature encoders and motor positioning• Brightness and Colour Control Unit (BCCU), for LED color and dimming application
System Control• Window Watchdog Timer (WDT) for safety sensitive applications• Real Time Clock module with alarm support (RTC)• System Control Unit (SCU) for system configuration and control• Pseudo random number generator (PRNG) for fast random data generation
Input/Output Lines• Tri-stated in input mode• Push/pull or open drain output mode
XMC1300 AB-StepXMC1000 Family
Summary of Features
Data Sheet 10 V2.0, 2017-10
• Configurable pad hysteresis
On-Chip Debug Support• Support for debug features: 4 breakpoints, 2 watchpoints• Various interfaces: ARM serial wire debug (SWD), single pin debug (SPD)
1.1 Ordering InformationThe ordering code for an Infineon microcontroller provides an exact reference to aspecific product. The code “XMC1<DDD>-<Z><PPP><T><FFFF>” identifies:• <DDD> the derivatives function set• <Z> the package variant
– T: TSSOP– Q: VQFN
• <PPP> package pin count• <T> the temperature range:
– F: -40°C to 85°C– X: -40°C to 105°C
• <FFFF> the Flash memory size.For ordering codes for the XMC1300 please contact your sales representative or localdistributor.This document describes several derivatives of the XMC1300 series, some descriptionsmay not apply to a specific product. Please see Table 1.For simplicity the term XMC1300 is used for all derivatives throughout this document.
1.2 Device TypesThese device types are available and can be ordered through Infineon’s direct and/ordistribution channels.
Table 1 Synopsis of XMC1300 Device TypesDerivative Package Flash
KbytesSRAM Kbytes
XMC1301-T016F0008 PG-TSSOP-16-8 8 16XMC1301-T016F0016 PG-TSSOP-16-8 16 16XMC1301-T016F0032 PG-TSSOP-16-8 32 16XMC1301-T016X0008 PG-TSSOP-16-8 8 16XMC1301-T016X0016 PG-TSSOP-16-8 16 16XMC1302-T016X0008 PG-TSSOP-16-8 8 16
XMC1300 AB-StepXMC1000 Family
Summary of Features
Data Sheet 11 V2.0, 2017-10
XMC1302-T016X0016 PG-TSSOP-16-8 16 16XMC1302-T016X0032 PG-TSSOP-16-8 32 16XMC1302-T028X0016 PG-TSSOP-28-8 16 16XMC1302-T028X0032 PG-TSSOP-28-8 32 16XMC1302-T028X0064 PG-TSSOP-28-8 64 16XMC1302-T028X0128 PG-TSSOP-28-8 128 16XMC1302-T028X0200 PG-TSSOP-28-8 200 16XMC1301-T038F0008 PG-TSSOP-38-9 8 16XMC1301-T038F0016 PG-TSSOP-38-9 16 16XMC1301-T038F0032 PG-TSSOP-38-9 32 16XMC1301-T038X0032 PG-TSSOP-38-9 32 16XMC1301-T038F0064 PG-TSSOP-38-9 64 16XMC1302-T038X0016 PG-TSSOP-38-9 16 16XMC1302-T038X0032 PG-TSSOP-38-9 32 16XMC1302-T038X0064 PG-TSSOP-38-9 64 16XMC1302-T038X0128 PG-TSSOP-38-9 128 16XMC1302-T038X0200 PG-TSSOP-38-9 200 16XMC1301-Q024F0008 PG-VQFN-24-19 8 16XMC1301-Q024F0016 PG-VQFN-24-19 16 16XMC1302-Q024F0016 PG-VQFN-24-19 16 16XMC1302-Q024F0032 PG-VQFN-24-19 32 16XMC1302-Q024F0064 PG-VQFN-24-19 64 16XMC1302-Q024X0016 PG-VQFN-24-19 16 16XMC1302-Q024X0032 PG-VQFN-24-19 32 16XMC1302-Q024X0064 PG-VQFN-24-19 64 16XMC1301-Q040F0008 PG-VQFN-40-13 8 16XMC1301-Q040F0016 PG-VQFN-40-13 16 16XMC1301-Q040F0032 PG-VQFN-40-13 32 16XMC1302-Q040X0016 PG-VQFN-40-13 16 16XMC1302-Q040X0032 PG-VQFN-40-13 32 16
Table 1 Synopsis of XMC1300 Device Types (cont’d)
Derivative Package Flash Kbytes
SRAM Kbytes
XMC1300 AB-StepXMC1000 Family
Summary of Features
Data Sheet 12 V2.0, 2017-10
1.3 Device Type FeaturesThe following table lists the available features per device type.
XMC1302-Q040X0064 PG-VQFN-40-13 64 16XMC1302-Q040X0128 PG-VQFN-40-13 128 16XMC1302-Q040X0200 PG-VQFN-40-13 200 16
Table 2 Features of XMC1300 Device Types1)
1) Features that are not included in this table are available in all the derivatives
Derivative ADC channel ACMP BCCU MATHXMC1301-T016 11 2 - -XMC1302-T016 11 2 1 1XMC1302-T028 14 3 1 1XMC1301-T038 16 3 - -XMC1302-T038 16 3 1 1XMC1301-Q024 13 3 - -XMC1302-Q024 13 3 1 1XMC1301-Q040 16 3 - -XMC1302-Q040 16 3 1 1
Table 3 ADC Channels 1)
1) Some pins in a package may be connected to more than one channel. For the detailed mapping see the PortI/O Function table.
Package VADC0 G0 VADC0 G1PG-TSSOP-16 CH0..CH5 CH0..CH4PG-TSSOP-28 CH0..CH7 CH0 .. CH4, CH7PG-TSSOP-38 CH0..CH7 CH0..CH7PG-VQFN-24 CH0..CH7 CH0..CH4PG-VQFN-40 CH0..CH7 CH0..CH7
Table 1 Synopsis of XMC1300 Device Types (cont’d)
Derivative Package Flash Kbytes
SRAM Kbytes
XMC1300 AB-StepXMC1000 Family
Summary of Features
Data Sheet 13 V2.0, 2017-10
1.4 Chip Identification NumberThe Chip Identification Number allows software to identify the marking. It is a 8 wordsvalue with the most significant 7 words stored in Flash configuration sector 0 (CS0) ataddress location : 1000 0F00H (MSB) - 1000 0F1BH (LSB). The least significant word andmost significant word of the Chip Identification Number are the value of registersDBGROMID and IDCHIP, respectively.
Table 4 XMC1300 Chip Identification Number Derivative Value MarkingXMC1301-T016F0008 00013032 01CF00FF 00001FF7 0000100F
00000C00 00001000 00003000 201ED083H
AB
XMC1301-T016F0016 00013032 01CF00FF 00001FF7 0000100F 00000C00 00001000 00005000 201ED083H
AB
XMC1301-T016F0032 00013032 01CF00FF 00001FF7 0000100F 00000C00 00001000 00009000 201ED083H
AB
XMC1301-T016X0008 00013033 01CF00FF 00001FF7 0000100F 00000C00 00001000 00003000 201ED083H
AB
XMC1301-T016X0016 00013033 01CF00FF 00001FF7 0000100F 00000C00 00001000 00005000 201ED083H
AB
XMC1302-T016X0008 00013033 01FF00FF 00001FF7 0000900F 00000C00 00001000 00003000 201ED083H
AB
XMC1302-T016X0016 00013033 01FF00FF 00001FF7 0000900F 00000C00 00001000 00005000 201ED083H
AB
XMC1302-T016X0032 00013033 01FF00FF 00001FF7 0000900F 00000C00 00001000 00009000 201ED083H
AB
XMC1302-T028X0016 00013023 01FF00FF 00001FF7 0000900F 00000C00 00001000 00005000 201ED083H
AB
XMC1302-T028X0032 00013023 01FF00FF 00001FF7 0000900F 00000C00 00001000 00009000 201ED083H
AB
XMC1302-T028X0064 00013023 01FF00FF 00001FF7 0000900F 00000C00 00001000 00011000 201ED083H
AB
XMC1302-T028X0128 00013023 01FF00FF 00001FF7 0000900F 00000C00 00001000 00021000 201ED083H
AB
XMC1302-T028X0200 00013023 01FF00FF 00001FF7 0000900F 00000C00 00001000 00033000 201ED083H
AB
XMC1301-T038F0008 00013012 01CF00FF 00001FF7 0000100F 00000C00 00001000 00003000 201ED083H
AB
XMC1300 AB-StepXMC1000 Family
Summary of Features
Data Sheet 14 V2.0, 2017-10
XMC1301-T038F0016 00013012 01CF00FF 00001FF7 0000100F 00000C00 00001000 00005000 201ED083H
AB
XMC1301-T038F0032 00013012 01CF00FF 00001FF7 0000100F 00000C00 00001000 00009000 201ED083H
AB
XMC1301-T038X0032 00013013 01CF00FF 00001FF7 0000100F 00000C00 00001000 00009000 201ED083H
AB
XMC1301-T038F0064 00013012 01CF00FF 00001FF7 0000100F 00000C00 00001000 00011000 201ED083H
AB
XMC1302-T038X0016 00013013 01FF00FF 00001FF7 0000900F 00000C00 00001000 00005000 201ED083H
AB
XMC1302-T038X0032 00013013 01FF00FF 00001FF7 0000900F 00000C00 00001000 00009000 201ED083H
AB
XMC1302-T038X0064 00013013 01FF00FF 00001FF7 0000900F 00000C00 00001000 00011000 201ED083H
AB
XMC1302-T038X0128 00013013 01FF00FF 00001FF7 0000900F 00000C00 00001000 00021000 201ED083H
AB
XMC1302-T038X0200 00013013 01FF00FF 00001FF7 0000900F 00000C00 00001000 00033000 201ED083H
AB
XMC1301-Q024F0008 00013062 01CF00FF 00001FF7 0000100F 00000C00 00001000 00003000 201ED083H
AB
XMC1301-Q024F0016 00013062 01CF00FF 00001FF7 0000100F 00000C00 00001000 00005000 201ED083H
AB
XMC1302-Q024F0016 00013062 01FF00FF 00001FF7 0000900F 00000C00 00001000 00005000 201ED083H
AB
XMC1302-Q024F0032 00013062 01FF00FF 00001FF7 0000900F 00000C00 00001000 00009000 201ED083H
AB
XMC1302-Q024F0064 00013062 01FF00FF 00001FF7 0000900F 00000C00 00001000 00011000 201ED083H
AB
XMC1302-Q024X0016 00013063 01FF00FF 00001FF7 0000900F 00000C00 00001000 00005000 201ED083H
AB
XMC1302-Q024X0032 00013063 01FF00FF 00001FF7 0000900F 00000C00 00001000 00009000 201ED083H
AB
XMC1302-Q024X0064 00013063 01FF00FF 00001FF7 0000900F 00000C00 00001000 00011000 201ED083H
AB
Table 4 XMC1300 Chip Identification Number (cont’d)
Derivative Value Marking
XMC1300 AB-StepXMC1000 Family
Summary of Features
Data Sheet 15 V2.0, 2017-10
XMC1301-Q040F0008 00013042 01CF00FF 00001FF7 0000100F 00000C00 00001000 00003000 201ED083H
AB
XMC1301-Q040F0016 00013042 01CF00FF 00001FF7 0000100F 00000C00 00001000 00005000 201ED083H
AB
XMC1301-Q040F0032 00013042 01CF00FF 00001FF7 0000100F 00000C00 00001000 00009000 201ED083H
AB
XMC1302-Q040X0016 00013043 01FF00FF 00001FF7 0000900F 00000C00 00001000 00005000 201ED083H
AB
XMC1302-Q040X0032 00013043 01FF00FF 00001FF7 0000900F 00000C00 00001000 00009000 201ED083H
AB
XMC1302-Q040X0064 00013043 01FF00FF 00001FF7 0000900F 00000C00 00001000 00011000 201ED083H
AB
XMC1302-Q040X0128 00013043 01FF00FF 00001FF7 0000900F 00000C00 00001000 00021000 201ED083H
AB
XMC1302-Q040X0200 00013043 01FF00FF 00001FF7 0000900F 00000C00 00001000 00033000 201ED083H
AB
Table 4 XMC1300 Chip Identification Number (cont’d)
Derivative Value Marking
XMC1300 AB-StepXMC1000 Family
General Device Information
Data Sheet 16 V2.0, 2017-10
2 General Device InformationThis section summarizes the logic symbols and package pin configurations with adetailed list of the functional I/O mapping.
2.1 Logic Symbols
Figure 2 XMC1300 Logic Symbol for TSSOP-38, TSSOP-28 and TSSOP-16
XMC13XX
TSSOP-38
VDDP
(2)VSSP
(2)
Port 016 bit
Port 16 bit
Port 24 bit
XMC13XX
TSSOP-28
VDDP
(1)VSSP
(1)
XMC13XX
TSSOP-16
VDDP
(1)VSSP
(1)
Port 28 bit
Port 012 bit
Port 14 bit
Port 24 bit
Port 26 bit
Port 08 bit
Port 23 bit
Port 23 bit
XMC1300 AB-StepXMC1000 Family
General Device Information
Data Sheet 17 V2.0, 2017-10
Figure 3 XMC1300 Logic Symbol for VQFN-24 and VQFN-40
XMC1300
VQFN-40
VDD
(1)VSS
(1)
Port 016 bit
Port 17 bit
Port 24 bit
Port 28 bit
VDDP
(2)VSSP
(1)
XMC1300
VQFN-24
VDDP
(1)VSSP
(1)
Port 010 bit
Port 14 bit
Port 24 bit
Port 24 bit
XMC1300 AB-StepXMC1000 Family
General Device Information
Data Sheet 18 V2.0, 2017-10
2.2 Pin Configuration and DefinitionThe following figures summarize all pins, showing their locations on the differentpackages.
Figure 4 XMC1300 PG-TSSOP-38 Pin Configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
37
36
35
34
33
32
31
30
29
38
P2.5
P2.6
P2.7
P0.10
VSSP/VSS
VDDP/VDD
P0.13
P0.14
P2.1
P2.0
P2.2
P0.11
P0.12
P1.4 P0.8
P0.9
P2.10
P2.9
P2.3P2.4
P2.11
VDDPP1.3
P1.2 VSSP
15
16
17
18
19
24
23
22
21
20
P2.8
P1.5
P1.0
P0.0
P0.1
P1.1
P0.2
P0.6
P0.7
P0.4
P0.5
P0.3
P0.15
Top View
XMC1300 AB-StepXMC1000 Family
General Device Information
Data Sheet 19 V2.0, 2017-10
Figure 5 XMC1300 PG-TSSOP-28 Pin Configuration (top view)
Figure 6 XMC1300 PG-TSSOP-16 Pin Configuration (top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
18
17
16
15
27
26
25
24
23
22
21
20
19
28P2.6
P2.7
VSSP/VSS
VDDP/VDD
P2.10
P2.9
P2.11
P1.3
P1.2
P2.8
P1.0
P0.0
P1.1
P0.4
Top View
P0.10
P0.13
P0.14
P2.1
P2.0
P2.2
P0.12
P0.8
P0.9
P2.5
P0.6
P0.7
P0.5
P0.15
1
2
3
4
5
6
7
8
15
14
13
12
11
10
9
16P2.7/P2.8
VSSP/VSS
VDDP/VDD
P2.10
P2.9
P2.11
P0.5
P0.0
Top View
P0.14
P2.0
P0.8
P0.9
P2.6
P0.6
P0.7
P0.15
XMC1300 AB-StepXMC1000 Family
General Device Information
Data Sheet 20 V2.0, 2017-10
Figure 7 XMC1300 PG-VQFN-24 Pin Configuration (top view)
1 2 3 4 5 6
7
9
10
11
16 15 14 1312
24
23
22
21
20
1918 17
P2.0
VDDP
P1.2
P0.
5
P0.
6
P0.
0
P1.
1
P1.
0
P0.13
8
P2.1
P2.2
P2.6
P2.7/P2.8
P2.9
P2.10
P2.11
VSSP
P0.
7
P0.12
P0.9
P0.8
P1.3
P0.15
P0.14
/V DD
/V SS
XMC1300 AB-StepXMC1000 Family
General Device Information
Data Sheet 21 V2.0, 2017-10
Figure 8 XMC1300 PG-VQFN-40 Pin Configuration (top view)
1 2 3 4 5 6 7 8 9 10
11
13
14
15
24 23 22 2120
19
18
17
16
36
35
34
33
32
3130 29 28 27 26 25
37
38
39
40
P0.13
P0.12
P2.0
VDDP
VSSP
VDDP
P1.6
P1.5
P1.4
P0.
1
P0.
2
P0.
0
P1.
1
P1.
0
P0.11
12
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P2.8
P2.9
P2.10
P2.11
VSS
VDD
P1.3
P1.2P
0.6
P0.
7
P0.
5
P0.
3
P0.
4
P0.10
P0.9
P0.8
P0.15
P0.14
XMC1300 AB-StepXMC1000 Family
General Device Information
Data Sheet 22 V2.0, 2017-10
2.2.1 Package Pin SummaryThe following general building block is used to describe each pin:
The table is sorted by the “Function” column, starting with the regular Port pins (Px.y),followed by the supply pins.The following columns, titled with the supported package variants, lists the package pinnumber to which the respective function is mapped in that package.The “Pad Type” indicates the employed pad type:• STD_INOUT(standard bi-directional pads)• STD_INOUT/AN (standard bi-directional pads with analog input)• High Current (high current bi-directional pads)• STD_IN/AN (standard input pads with analog input)• Power (power supply)Details about the pad properties are defined in the Electrical Parameters.
Table 5 Package Pin Mapping DescriptionFunction Package A Package B ... Pad TypePx.y N N Pad Class
Table 6 Package Pin MappingFunction VQFN
40TSSOP 38
TSSOP 28
VQFN 24
TSSOP 16
Pad Type
Notes
P0.0 23 17 13 15 7 STD_INOUT
P0.1 24 18 - - - STD_INOUT
P0.2 25 19 - - - STD_INOUT
P0.3 26 20 - - - STD_INOUT
P0.4 27 21 14 - - STD_INOUT
P0.5 28 22 15 16 8 STD_INOUT
P0.6 29 23 16 17 9 STD_INOUT
XMC1300 AB-StepXMC1000 Family
General Device Information
Data Sheet 23 V2.0, 2017-10
P0.7 30 24 17 18 10 STD_INOUT
P0.8 33 27 18 19 11 STD_INOUT
P0.9 34 28 19 20 12 STD_INOUT
P0.10 35 29 20 - - STD_INOUT
P0.11 36 30 - - - STD_INOUT
P0.12 37 31 21 21 - STD_INOUT
P0.13 38 32 22 22 - STD_INOUT
P0.14 39 33 23 23 13 STD_INOUT
P0.15 40 34 24 24 14 STD_INOUT
P1.0 22 16 12 14 - High Current
P1.1 21 15 11 13 - High Current
P1.2 20 14 10 12 - High Current
P1.3 19 13 9 11 - High Current
P1.4 18 12 - - - High Current
P1.5 17 11 - - - High Current
P1.6 16 - - - - STD_INOUT
P2.0 1 35 25 1 15 STD_INOUT/AN
Table 6 Package Pin Mapping (cont’d)
Function VQFN 40
TSSOP 38
TSSOP 28
VQFN 24
TSSOP 16
Pad Type
Notes
XMC1300 AB-StepXMC1000 Family
General Device Information
Data Sheet 24 V2.0, 2017-10
P2.1 2 36 26 2 - STD_INOUT/AN
P2.2 3 37 27 3 - STD_IN/AN
P2.3 4 38 - - - STD_IN/AN
P2.4 5 1 - - - STD_IN/AN
P2.5 6 2 28 - - STD_IN/AN
P2.6 7 3 1 4 16 STD_IN/AN
P2.7 8 4 2 5 1 STD_IN/AN
P2.8 9 5 3 5 1 STD_IN/AN
P2.9 10 6 4 6 2 STD_IN/AN
P2.10 11 7 5 7 3 STD_INOUT/AN
P2.11 12 8 6 8 4 STD_INOUT/AN
VSS 13 9 7 9 5 Power Supply GND, ADC reference GND
VDD 14 10 8 10 6 Power Supply VDD, ADC reference voltage/ ORC reference voltage
VDDP 15 10 8 10 6 Power When VDD is supplied, VDDP has to be supplied with the same voltage.
Table 6 Package Pin Mapping (cont’d)
Function VQFN 40
TSSOP 38
TSSOP 28
VQFN 24
TSSOP 16
Pad Type
Notes
XMC1300 AB-StepXMC1000 Family
General Device Information
Data Sheet 25 V2.0, 2017-10
2.2.2 Port I/O Function DescriptionThe following general building block is used to describe the I/O functions of each PORTpin:
VSSP 31 25 - - - Power I/O port groundVDDP 32 26 - - - Power I/O port supplyVSSP Exp.
Pad- - Exp.
Pad- Power Exposed Die
PadThe exposed die pad is connected internally to VSSP. For proper operation, it is mandatory to connect the exposed pad to the board ground. For thermal aspects, please refer to the Package and Reliability chapter.
Table 7 Port I/O Function DescriptionFunction Outputs Inputs
ALT1 ALTn Input InputP0.0 MODA.OUT MODC.INAPn.y MODA.OUT MODA.INA MODC.INB
Table 6 Package Pin Mapping (cont’d)
Function VQFN 40
TSSOP 38
TSSOP 28
VQFN 24
TSSOP 16
Pad Type
Notes
XMC1300 AB-StepXMC1000 Family
General Device Information
Data Sheet 26 V2.0, 2017-10
Figure 9 Simplified Port Structure
Pn.y is the port pin name, defining the control and data bits/registers associated with it.As GPIO, the port is under software control. Its input value is read via Pn_IN.y, Pn_OUTdefines the output value. Up to seven alternate output functions (ALT1/2/3/4/5/6/7) can be mapped to a single portpin, selected by Pn_IOCR.PC. The output value is directly driven by the respectivemodule, with the pin characteristics controlled by the port registers (within the limits ofthe connected pad).The port pin input can be connected to multiple peripherals. Most peripherals have aninput multiplexer to select between different possible input sources. The input path is also active while the pin is configured as output. This allows to feedbackan output to on-chip resources without wasting an additional external pin.Please refer to the Port I/O Functions table for the complete Port I/O function mapping.
XMC1000
Pn.y
VDDP
GND
Pn.y
ALT1...ALTn
HWO0HWO1
SW
Control Logic
Input 0
Input n...
PAD
HWI0HWI1
MODB.OUT
MODBMODA
MODA.INA
XMC1300 AB-StepXMC1000 Family
General Device Information
Data Sheet 27 V2.0, 2017-10
2.2.3 Hardware Controlled I/O Function DescriptionThe following general building block is used to describe the hardware I/O and pull controlfunctions of each PORT pin:
By Pn_HWSEL, it is possible to select between different hardware “masters”(HWO0/HWI0, HWO1/HWI1). The selected peripheral can take control of the pin(s).Hardware control overrules settings in the respective port pin registers. Additionalhardware signals HW0_PD/HW1_PD and HW0_PU/HW1_PU controlled by theperipherals can be used to control the pull devices of the pin.Please refer to the Hardware Controlled I/O Functions table for the complete hardwareI/O and pull control function mapping.
Table 8 Hardware Controlled I/O Function DescriptionFunction Outputs Inputs Pull Control
HWO0 HWI0 HW0_PD HW0_PUP0.0 MODB.OUT MODB.INAPn.y MODC.OUT MODC.OUT
XMC1300 AB-StepXMC1000 Family
Data Sheet 2-28 V2.0, 2017-10Ports, V2.3
Tabl
e2-
1Po
rt I/
O F
unct
ions
Func
tion
Out
puts
Inpu
ts
ALT
1A
LT2
ALT
3A
LT4
ALT
5A
LT6
ALT
7In
put
Inpu
tIn
put
Inpu
tIn
put
Inpu
tIn
put
Inpu
tIn
put
Inpu
tP0
.0ER
U0.
PD
OU
T0E
RU
0.
GO
UT0
CC
U40
. O
UT0
CC
U80
. O
UT0
0U
SIC
0_C
H0.
SELO
0
US
IC0_
CH
1.S
ELO
0
BC
CU
0.
TRAP
INB
CC
U40
. IN
0CU
SIC
0_C
H0.
DX2
AU
SIC
0_C
H1.
DX
2A
P0.1
ERU
0.
PDO
UT1
ER
U0.
G
OU
T1C
CU
40.
OU
T1C
CU
80.
OU
T01
BC
CU
0.
OU
T8S
CU
. V
DR
OP
CC
U40
. IN
1C
P0.2
ERU
0.
PDO
UT2
ER
U0.
G
OU
T2C
CU
40.
OU
T2C
CU
80.
OU
T02
VAD
C0.
E
MU
X02
CC
U80
. O
UT1
0C
CU
40.
IN2C
P0.3
ERU
0.
PDO
UT3
ER
U0.
G
OU
T3C
CU
40.
OU
T3C
CU
80.
OU
T03
VAD
C0.
E
MU
X01
CC
U80
. O
UT1
1C
CU
40.
IN3C
P0.
4B
CC
U0.
O
UT0
CC
U40
. O
UT1
CC
U80
. O
UT1
3V
ADC
0.
EM
UX0
0W
WD
T.
SER
VIC
E_O
UT
CC
U80
. IN
0B
P0.
5B
CC
U0.
O
UT1
CC
U40
. O
UT0
CC
U80
. O
UT1
2A
CM
P2.
OU
TC
CU
80.
OU
T01
CC
U80
. IN
1B
P0.
6B
CC
U0.
O
UT2
CC
U40
. O
UT0
CC
U80
. O
UT1
1U
SIC
0_C
H1.
MC
LKO
UT
US
IC0_
CH
1.D
OU
T0
CC
U40
. IN
0BU
SIC
0_C
H1.
DX0
C
P0.
7B
CC
U0.
O
UT3
CC
U40
. O
UT1
CC
U80
. O
UT1
0U
SIC
0_C
H0.
SCLK
OU
T
US
IC0_
CH
1.D
OU
T0
CC
U40
. IN
1BU
SIC
0_C
H0.
DX1
CU
SIC
0_C
H1.
DX
0DU
SIC
0_C
H1.
DX1
C
P0.
8B
CC
U0.
O
UT4
CC
U40
. O
UT2
CC
U80
. O
UT2
0U
SIC
0_C
H0.
SCLK
OU
T
US
IC0_
CH
1.S
CLK
OU
T
CC
U40
. IN
2BU
SIC
0_C
H0.
DX1
BU
SIC
0_C
H1.
DX
1B
P0.
9B
CC
U0.
O
UT5
CC
U40
. O
UT3
CC
U80
. O
UT2
1U
SIC
0_C
H0.
SELO
0
US
IC0_
CH
1.S
ELO
0
CC
U40
. IN
3BU
SIC
0_C
H0.
DX2
BU
SIC
0_C
H1.
DX
2B
P0.
10BC
CU
0.
OU
T6A
CM
P0.
OU
TC
CU
80.
OU
T22
US
IC0_
CH
0.SE
LO1
US
IC0_
CH
1.S
ELO
1
CC
U80
. IN
2BU
SIC
0_C
H0.
DX2
CU
SIC
0_C
H1.
DX
2C
P0.
11BC
CU
0.
OU
T7U
SIC
0_C
H0.
MC
LKO
UT
CC
U80
. O
UT2
3U
SIC
0_C
H0.
SELO
2
US
IC0_
CH
1.S
ELO
2
US
IC0_
CH
0.D
X2D
US
IC0_
CH
1.D
X2D
P0.
12BC
CU
0.
OU
T6C
CU
80.
OU
T33
US
IC0_
CH
0.SE
LO3
CC
U80
. O
UT2
0B
CC
U0.
TR
APIN
AC
CU
40.
IN0A
CC
U40
. IN
1AC
CU
40.
IN2A
CC
U40
. IN
3AC
CU
80.
IN0A
CC
U80
. IN
1AC
CU
80.
IN2A
CC
U80
. IN
3AU
SIC
0_C
H0.
DX
2E
P0.1
3W
WD
T.
SER
VIC
E_O
UT
CC
U80
. O
UT3
2U
SIC
0_C
H0.
SELO
4
CC
U80
. O
UT2
1C
CU
80.
IN3B
PO
SIF
0.
IN0B
US
IC0_
CH
0.D
X2F
XMC1300 AB-StepXMC1000 Family
Data Sheet 2-29 V2.0, 2017-10Ports, V2.3
P0.
14BC
CU
0.
OU
T7C
CU
80.
OU
T31
US
IC0_
CH
0.D
OU
T0
US
IC0_
CH
0.S
CLK
OU
T
PO
SIF
0.
IN1B
US
IC0_
CH
0.D
X0A
US
IC0_
CH
0.D
X1A
P0.
15BC
CU
0.
OU
T8C
CU
80.
OU
T30
US
IC0_
CH
0.D
OU
T0
US
IC0_
CH
1.M
CLK
OU
T
PO
SIF
0.
IN2B
US
IC0_
CH
0.D
X0B
P1.
0B
CC
U0.
O
UT0
CC
U40
. O
UT0
CC
U80
. O
UT0
0A
CM
P1.
OU
TU
SIC
0_C
H0.
DO
UT
0
PO
SIF
0.
IN2A
US
IC0_
CH
0.D
X0C
P1.1
VAD
C0.
E
MU
X00
CC
U40
. O
UT1
CC
U80
. O
UT0
1U
SIC
0_C
H0.
DO
UT
0
US
IC0_
CH
1.S
ELO
0
PO
SIF
0.
IN1A
US
IC0_
CH
0.D
X0D
US
IC0_
CH
0.D
X1D
US
IC0_
CH
1.D
X2E
P1.2
VAD
C0.
E
MU
X01
CC
U40
. O
UT2
CC
U80
. O
UT1
0A
CM
P2.
OU
TU
SIC
0_C
H1.
DO
UT
0
PO
SIF
0.
IN0A
US
IC0_
CH
1.D
X0B
P1.3
VAD
C0.
E
MU
X02
CC
U40
. O
UT3
CC
U80
. O
UT1
1U
SIC
0_C
H1.
SCLK
OU
T
US
IC0_
CH
1.D
OU
T0
US
IC0_
CH
1.D
X0A
US
IC0_
CH
1.D
X1A
P1.4
VAD
C0.
E
MU
X10
US
IC0_
CH
1.SC
LKO
UT
CC
U80
. O
UT2
0U
SIC
0_C
H0.
SELO
0
US
IC0_
CH
1.S
ELO
1
US
IC0_
CH
0.D
X5E
US
IC0_
CH
1.D
X5E
P1.5
VAD
C0.
E
MU
X11
US
IC0_
CH
0.D
OU
T0
BC
CU
0.
OU
T1C
CU
80.
OU
T21
US
IC0_
CH
0.SE
LO1
US
IC0_
CH
1.S
ELO
2
US
IC0_
CH
1.D
X5F
P1.6
VAD
C0.
E
MU
X12
US
IC0_
CH
1.D
OU
T0
US
IC0_
CH
0.SC
LKO
UT
BC
CU
0.
OU
T2U
SIC
0_C
H0.
SELO
2
US
IC0_
CH
1.S
ELO
3
US
IC0_
CH
0.D
X5F
P2.0
ERU
0.
PDO
UT3
CC
U40
. O
UT0
ER
U0.
G
OU
T3C
CU
80.
OU
T20
US
IC0_
CH
0.D
OU
T0
US
IC0_
CH
0.S
CLK
OU
T
VAD
C0.
G
0CH
5E
RU
0.0B
0U
SIC
0_C
H0.
DX0
EU
SIC
0_C
H0.
DX
1EU
SIC
0_C
H1.
DX2
F
P2.1
ERU
0.
PDO
UT2
CC
U40
. O
UT1
ER
U0.
G
OU
T2C
CU
80.
OU
T21
US
IC0_
CH
0.D
OU
T0
US
IC0_
CH
1.S
CLK
OU
T
AC
MP2
.IN
PVA
DC
0.
G0C
H6
ER
U0.
1B0
US
IC0_
CH
0.D
X0F
US
IC0_
CH
1.D
X3A
US
IC0_
CH
1.D
X4A
P2.2
AC
MP2
.IN
NVA
DC
0.
G0C
H7
ER
U0.
0B1
US
IC0_
CH
0.D
X3A
US
IC0_
CH
0.D
X4A
US
IC0_
CH
1.D
X5A
OR
C0.
AI
N
P2.3
VAD
C0.
G
1CH
5E
RU
0.1B
1U
SIC
0_C
H0.
DX5
BU
SIC
0_C
H1.
DX
3CU
SIC
0_C
H1.
DX4
CO
RC
1.A
IN
P2.4
VAD
C0.
G
1CH
6E
RU
0.0A
1U
SIC
0_C
H0.
DX3
BU
SIC
0_C
H0.
DX
4BU
SIC
0_C
H1.
DX5
BO
RC
2.A
IN
Tabl
e2-
1Po
rt I/
O F
unct
ions
(con
t’d)
Func
tion
Out
puts
Inpu
ts
ALT
1A
LT2
ALT
3A
LT4
ALT
5A
LT6
ALT
7In
put
Inpu
tIn
put
Inpu
tIn
put
Inpu
tIn
put
Inpu
tIn
put
Inpu
t
XMC1300 AB-StepXMC1000 Family
Data Sheet 2-30 V2.0, 2017-10Ports, V2.3
P2.5
VAD
C0.
G
1CH
7E
RU
0.1A
1U
SIC
0_C
H0.
DX5
DU
SIC
0_C
H1.
DX
3EU
SIC
0_C
H1.
DX4
EO
RC
3.A
IN
P2.6
AC
MP1
.IN
NVA
DC
0.
G0C
H0
ER
U0.
2A1
US
IC0_
CH
0.D
X3E
US
IC0_
CH
0.D
X4E
US
IC0_
CH
1.D
X5D
OR
C4.
AI
N
P2.7
AC
MP1
.IN
PVA
DC
0.
G1C
H1
ER
U0.
3A1
US
IC0_
CH
0.D
X5C
US
IC0_
CH
1.D
X3D
US
IC0_
CH
1.D
X4D
OR
C5.
AI
N
P2.8
AC
MP0
.IN
NVA
DC
0.
G0C
H1
VAD
C0.
G
1CH
0E
RU
0.3B
1U
SIC
0_C
H0.
DX3
DU
SIC
0_C
H0.
DX
4DU
SIC
0_C
H1.
DX5
CO
RC
6.A
IN
P2.9
AC
MP0
.IN
PVA
DC
0.
G0C
H2
VAD
C0.
G
1CH
4E
RU
0.3B
0U
SIC
0_C
H0.
DX5
AU
SIC
0_C
H1.
DX
3BU
SIC
0_C
H1.
DX4
BO
RC
7.A
IN
P2.1
0ER
U0.
PD
OU
T1C
CU
40.
OU
T2E
RU
0.
GO
UT1
CC
U80
. O
UT3
0A
CM
P0.
OU
TU
SIC
0_C
H1.
DO
UT
0
VAD
C0.
G
0CH
3V
ADC
0.
G1C
H2
ER
U0.
2B0
US
IC0_
CH
0.D
X3C
US
IC0_
CH
0.D
X4C
US
IC0_
CH
1.D
X0F
P2.1
1ER
U0.
PD
OU
T0C
CU
40.
OU
T3E
RU
0.
GO
UT0
CC
U80
. O
UT3
1U
SIC
0_C
H1.
SCLK
OU
T
US
IC0_
CH
1.D
OU
T0
AC
MP.
RE
FVA
DC
0.
G0C
H4
VAD
C0.
G
1CH
3E
RU
0.2B
1U
SIC
0_C
H1.
DX0
EU
SIC
0_C
H1.
DX
1E
Tabl
e2-
1Po
rt I/
O F
unct
ions
(con
t’d)
Func
tion
Out
puts
Inpu
ts
ALT
1A
LT2
ALT
3A
LT4
ALT
5A
LT6
ALT
7In
put
Inpu
tIn
put
Inpu
tIn
put
Inpu
tIn
put
Inpu
tIn
put
Inpu
t
XMC1300 AB-StepXMC1000 Family
Data Sheet 2-31 V2.0, 2017-10Ports, V3.1
Tabl
e2-
2H
ardw
are
Con
trol
led
I/O F
unct
ions
Func
tion
Out
puts
Inpu
tsPu
ll C
ontr
ol
HW
O0
HW
O1
HW
I0H
WI1
HW
0_PD
HW
0_PU
HW
1_PD
HW
1_PU
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P0.8
P0.9
P0.1
0
P0.1
1
P0.1
2
P0.1
3
P0.1
4
P0.1
5
P1.
0U
SIC
0_C
H0.
DO
UT0
US
IC0_
CH
0.H
WIN
0B
CC
U0.
OU
T2B
CC
U0.
OU
T2
P1.
1U
SIC
0_C
H0.
DO
UT1
US
IC0_
CH
0.H
WIN
1B
CC
U0.
OU
T3B
CC
U0.
OU
T3
P1.
2U
SIC
0_C
H0.
DO
UT2
US
IC0_
CH
0.H
WIN
2B
CC
U0.
OU
T4B
CC
U0.
OU
T4
P1.
3U
SIC
0_C
H0.
DO
UT3
US
IC0_
CH
0.H
WIN
3B
CC
U0.
OU
T5B
CC
U0.
OU
T5
P1.4
BC
CU
0.O
UT6
BC
CU
0.O
UT6
P1.5
BC
CU
0.O
UT7
BC
CU
0.O
UT7
P1.6
BC
CU
0.O
UT8
BC
CU
0.O
UT8
P2.0
BC
CU
0.O
UT1
BC
CU
0.O
UT1
P2.1
BC
CU
0.O
UT6
BC
CU
0.O
UT6
P2.2
BC
CU
0.O
UT0
BC
CU
0.O
UT0
CC
U40
.OU
T3C
CU
40.O
UT3
P2.3
AC
MP
2.O
UT
AC
MP2
.OU
T
P2.4
BC
CU
0.O
UT8
BC
CU
0.O
UT8
XMC1300 AB-StepXMC1000 Family
Data Sheet 2-32 V2.0, 2017-10Ports, V3.1
P2.5
AC
MP
1.O
UT
AC
MP1
.OU
T
P2.6
BC
CU
0.O
UT2
BC
CU
0.O
UT2
CC
U40
.OU
T3C
CU
40.O
UT3
P2.7
BC
CU
0.O
UT8
BC
CU
0.O
UT8
CC
U40
.OU
T3C
CU
40.O
UT3
P2.8
BC
CU
0.O
UT1
BC
CU
0.O
UT1
CC
U40
.OU
T2C
CU
40.O
UT2
P2.9
BC
CU
0.O
UT7
BC
CU
0.O
UT7
CC
U40
.OU
T2C
CU
40.O
UT2
P2.1
0B
CC
U0.
OU
T4B
CC
U0.
OU
T4
P2.1
1B
CC
U0.
OU
T5B
CC
U0.
OU
T5
Tabl
e2-
2H
ardw
are
Con
trol
led
I/O F
unct
ions
(con
t’d)
Func
tion
Out
puts
Inpu
tsPu
ll C
ontr
ol
HW
O0
HW
O1
HW
I0H
WI1
HW
0_PD
HW
0_PU
HW
1_PD
HW
1_PU
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 33 V2.0, 2017-10
3 Electrical ParametersThis section provides the electrical parameters which are implementation-specific for theXMC1300.
3.1 General Parameters
3.1.1 Parameter InterpretationThe parameters listed in this section represent partly the characteristics of the XMC1300and partly its requirements on the system. To aid interpreting the parameters easilywhen evaluating them for a design, they are indicated by the abbreviations in the“Symbol” column:• CC
Such parameters indicate Controller Characteristics, which are distinctive feature ofthe XMC1300 and must be regarded for a system design.
• SRSuch parameters indicate System Requirements, which must be provided by theapplication system in which the XMC1300 is designed in.
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 34 V2.0, 2017-10
3.1.2 Absolute Maximum RatingsStresses above the values listed under “Absolute Maximum Ratings” may causepermanent damage to the device. This is a stress rating only and functional operation ofthe device at these or any other conditions above those indicated in the operationalsections of this specification is not implied. Exposure to absolute maximum ratingconditions may affect device reliability.
Table 9 Absolute Maximum Rating ParametersParameter Symbol Values Unit Note /
Test Condition
Min.
Typ. Max.
Junction temperature TJ SR -40 – 115 °C –Storage temperature TST SR -40 – 125 °C –Voltage on power supply pin with respect to VSSP
VDDP SR -0.3 – 6 V –
Voltage on digital pins with respect to VSSP
1)
1) Excluding port pins P2.[1,2,6,7,8,9,11].
VIN SR -0.5 – VDDP + 0.5 or max. 6
V whichever is lower
Voltage on P2 pins with respect to VSSP
2)
2) Applicable to port pins P2.[1,2,6,7,8,9,11].
VINP2 SR -0.3 – VDDP + 0.3 V –
Voltage on analog input pins with respect to VSSP
VAINVAREF SR
-0.5 – VDDP + 0.5 or max. 6
V whichever is lower
Input current on any pin during overload condition
IIN SR -10 – 10 mA –
Absolute maximum sum of all input currents during overload condition
ΣIIN SR -50 – +50 mA –
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 35 V2.0, 2017-10
3.1.3 Pin Reliability in OverloadWhen receiving signals from higher voltage devices, low-voltage devices experienceoverload currents and voltages that go beyond their own IO power supplies specification.Table 10 defines overload conditions that will not cause any negative reliability impact ifall the following conditions are met:• full operation life-time is not exceeded• Operating Conditions are met for
– pad supply levels (VDDP)– temperature
If a pin current is outside of the Operating Conditions but within the overloadconditions, then the parameters of this pin as stated in the Operating Conditions can nolonger be guaranteed. Operation is still possible in most cases but with relaxedparameters.Note: An overload condition on one or more pins does not require a reset.
Note: A series resistor at the pin to limit the current to the maximum permitted overloadcurrent is sufficient to handle failure situations like short to battery.
Figure 10 shows the path of the input currents during overload via the ESD protectionstructures. The diodes against VDDP and ground are a simplified representation of theseESD protection structures.
Table 10 Overload ParametersParameter Symbol Values Unit Note /
Test ConditionMin. Typ. Max.Input current on any port pin during overload condition
IOV SR -5 – 5 mA
Absolute sum of all input circuit currents during overload condition
IOVS SR – – 25 mA
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 36 V2.0, 2017-10
Figure 10 Input Overload Current via ESD structures
Table 11 and Table 12 list input voltages that can be reached under overload conditions.Note that the absolute maximum input voltages as defined in the Absolute MaximumRatings must not be exceeded during overload.
Table 11 PN-Junction Characterisitics for positive OverloadPad Type IOV = 5 mAStandard, High-current, AN/DIG_IN
VIN = VDDP + 0.5 VVAIN = VDDP + 0.5 VVAREF = VDDP + 0.5 V
P2.[1,2,6:9,11] VINP2 = VDDP + 0.3 V
Table 12 PN-Junction Characterisitics for negative OverloadPad Type IOV = 5 mAStandard, High-current, AN/DIG_IN
VIN = VSS - 0.5 VVAIN = VSS - 0.5 VVAREF = VSS - 0.5 V
P2.[1,2,6:9,11] VINP2 = VSS - 0.3 V
Pn.y IOVx
GNDESD Pad
GND
VDDPVDDP
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 37 V2.0, 2017-10
3.1.4 Operating ConditionsThe following operating conditions must not be exceeded in order to ensure correctoperation and reliability of the XMC1300. All parameters specified in the following tablesrefer to these operating conditions, unless noted otherwise.
Table 13 Operating Conditions ParametersParameter Symbol Values Unit Note /
Test ConditionMin. Typ. Max.Ambient Temperature TA SR -40 − 85 °C Temp. Range F
-40 − 105 °C Temp. Range XDigital supply voltage1)
1) See also the Supply Monitoring thresholds, Chapter 3.3.2.
VDDP SR 1.8 − 5.5 VMCLK Frequency fMCLK CC − − 33.2 MHz CPU clockPCLK Frequency fPCLK CC − − 66.4 MHz Peripherals
clockShort circuit current of digital outputs
ISC SR -5 − 5 mA
Absolute sum of short circuit currents of the device
ΣISC_D SR − − 25 mA
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 38 V2.0, 2017-10
3.2 DC Parameters
3.2.1 Input/Output CharacteristicsTable 14 provides the characteristics of the input/output pins of the XMC1300.Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Note: Unless otherwise stated, input DC and AC characteristics, including peripheraltimings, assume that the input pads operate with the standard hysteresis.
Table 14 Input/Output Characteristics (Operating Conditions apply)Parameter Symbol Limit Values Unit Test Conditions
Min. Max.Output low voltage on port pins(with standard pads)
VOLP CC – 1.0 V IOL = 11 mA (5 V)IOL = 7 mA (3.3 V)
– 0.4 V IOL = 5 mA (5 V)IOL = 3.5 mA (3.3 V)
Output low voltage on high current pads
VOLP1 CC – 1.0 V IOL = 50 mA (5 V)IOL = 25 mA (3.3 V)
– 0.32 V IOL = 10 mA (5 V)– 0.4 V IOL = 5 mA (3.3 V)
Output high voltage on port pins(with standard pads)
VOHP CC VDDP - 1.0
– V IOH = -10 mA (5 V)IOH = -7 mA (3.3 V)
VDDP - 0.4
– V IOH = -4.5 mA (5 V)IOH = -2.5 mA (3.3 V)
Output high voltage on high current pads
VOHP1 CC VDDP - 0.32
– V IOH = -6 mA (5 V)
VDDP - 1.0
– V IOH = -8 mA (3.3 V)
VDDP - 0.4
– V IOH = -4 mA (3.3 V)
Input low voltage on port pins (Standard Hysteresis)
VILPS SR – 0.19 × VDDP
V CMOS Mode (5 V, 3.3 V & 2.2 V)
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 39 V2.0, 2017-10
Input high voltage on port pins (Standard Hysteresis)
VIHPS SR 0.7 × VDDP
– V CMOS Mode(5 V, 3.3 V & 2.2 V)
Input low voltage on port pins (Large Hysteresis)
VILPL SR – 0.08 × VDDP
V CMOS Mode (5 V, 3.3 V & 2.2 V)18)
Input high voltage on port pins (Large Hysteresis)
VIHPL SR 0.85 × VDDP
– V CMOS Mode(5 V, 3.3 V & 2.2 V)18)
Rise time on High Current Pad1)
tHCPR CC – 9 ns 50 pF @ 5 V2)
– 12 ns 50 pF @ 3.3 V3)
– 25 ns 50 pF @ 1.8 V4)
Fall time on High Current Pad1)
tHCPF CC – 9 ns 50 pF @ 5 V2)
– 12 ns 50 pF @ 3.3 V3)
– 25 ns 50 pF @ 1.8 V4)
Rise time on Standard Pad1)
tR CC – 12 ns 50 pF @ 5 V5)
– 15 ns 50 pF @ 3.3 V6)
– 31 ns 50 pF @ 1.8 V7)
Fall time on Standard Pad1)
tF CC – 12 ns 50 pF @ 5 V5)
– 15 ns 50 pF @ 3.3 V6)
– 31 ns 50 pF @ 1.8 V7)
Table 14 Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter Symbol Limit Values Unit Test ConditionsMin. Max.
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 40 V2.0, 2017-10
Input Hysteresis8) HYS CC 0.08 × VDDP
– V CMOS Mode (5 V), Standard Hysteresis
0.03 × VDDP
– V CMOS Mode (3.3 V), Standard Hysteresis
0.02 × VDDP
– V CMOS Mode (2.2 V), Standard Hysteresis
0.5 × VDDP
0.75 × VDDP
V CMOS Mode(5 V),Large Hysteresis
0.4 × VDDP
0.75 × VDDP
V CMOS Mode(3.3 V),Large Hysteresis
0.2 × VDDP
0.65 × VDDP
V CMOS Mode(2.2 V),Large Hysteresis
Pin capacitance (digital inputs/outputs)
CIO CC – 10 pF
Pull-up resistor on port pins
RPUP CC 20 50 kohm VIN = VSSP
Pull-down resistor on port pins
RPDP CC 20 50 kohm VIN = VDDP
Input leakage current9) IOZP CC -1 1 μA 0 < VIN < VDDP,TA ≤ 105 °C
Voltage on any pin during VDDP power off
VPO SR – 0.3 V 10)
Maximum current per pin (excluding P1, VDDP and VSS)
IMP SR -10 11 mA –
Maximum current per high currrent pins
IMP1A SR -10 50 mA –
Maximum current into VDDP (TSSOP16, VQFN24)
IMVDD1 SR – 130 mA 18)
Maximum current into VDDP (TSSOP38, VQFN40)
IMVDD2 SR – 260 mA 18)
Table 14 Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter Symbol Limit Values Unit Test ConditionsMin. Max.
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 41 V2.0, 2017-10
Maximum current out of VSS (TSSOP16, VQFN24)
IMVSS1 SR – 130 mA 18)
Maximum current out of VSS (TSSOP38, VQFN40)
IMVSS2 SR – 260 mA 18)
1) Rise/Fall time parameters are taken with 10% - 90% of supply.2) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.150 ns/pF at 5 V supply voltage.3) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.205 ns/pF at 3.3 V supply voltage.4) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.445 ns/pF at 1.8 V supply voltage.5) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.225 ns/pF at 5 V supply voltage.6) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.288 ns/pF at 3.3 V supply voltage.7) Additional rise/fall time valid for CL = 50 pF - CL = 100 pF @ 0.588 ns/pF at 1.8 V supply voltage.8) Hysteresis is implemented to avoid meta stable states and switching due to internal ground bounce. It cannot
be guaranteed that it suppresses switching due to external system noise.9) An additional error current (IINJ) will flow if an overload current flows through an adjacent pin.10) However, for applications with strict low power-down current requirements, it is mandatory that no active
voltage source is supplied at any GPIO pin when VDDP is powered off.
Table 14 Input/Output Characteristics (Operating Conditions apply) (cont’d)
Parameter Symbol Limit Values Unit Test ConditionsMin. Max.
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 42 V2.0, 2017-10
3.2.2 Analog to Digital Converters (ADC) Table 15 shows the Analog to Digital Converter (ADC) characteristics.Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 15 ADC Characteristics (Operating Conditions apply)1)
Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.
Supply voltage range (internal reference)
VDD_int SR 2.0 – 3.0 V SHSCFG.AREF = 11BCALCTR.CALGNSTC = 0CH
3.0 – 5.5 V SHSCFG.AREF = 10B
Supply voltage range (external reference)
VDD_ext SR
3.0 – 5.5 V SHSCFG.AREF = 00B
Analog input voltage range
VAIN SR VSSP- 0.05
– VDDP+ 0.05
V
Auxiliary analog reference ground
VREFGND SR
VSSP- 0.05
– 1.0 V G0CH0
VSSP- 0.05
– 0.2 V G1CH0
Internal reference voltage (full scale value)
VREFINT CC
5 V
Switched capacitance of an analog input
CAINS CC – 1.2 2 pF GNCTRxz.GAINy = 00B (unity gain)
– 1.2 2 pF GNCTRxz.GAINy = 01B (gain g1)
– 4.5 6 pF GNCTRxz.GAINy = 10B (gain g2)
– 4.5 6 pF GNCTRxz.GAINy = 11B (gain g3)
Total capacitance of an analog input
CAINT CC – – 10 pF
Total capacitance of the reference input
CAREFT CC
– – 10 pF
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 43 V2.0, 2017-10
Gain settings GIN CC 1 – GNCTRxz.GAINy = 00B (unity gain)
3 – GNCTRxz.GAINy = 01B (gain g1)
6 – GNCTRxz.GAINy = 10B (gain g2)
12 – GNCTRxz.GAINy = 11B (gain g3)
Sample Time tsample CC 3 – – 1 / fADC
VDD = 5.0 V
3 – – 1 / fADC
VDD = 3.3 V
30 – – 1 / fADC
VDD = 2.0 V
Sigma delta loop hold time
tSD_hold CC
20 – – μs Residual charge stored in an active sigma delta loop remains available
Conversion timein fast compare mode
tCF CC 9 1 / fADC
2)
Conversion timein 12-bit mode
tC12 CC 20 1 / fADC
2)
Maximum sample rate in 12-bit mode 3)
fC12 CC – – fADC / 42.5
– 1 samplepending
– – fADC / 62.5
– 2 samplespending
Conversion timein 10-bit mode
tC10 CC 18 1 / fADC
2)
Maximum sample rate in 10-bit mode 3)
fC10 CC – – fADC / 40.5
– 1 samplepending
– – fADC / 58.5
– 2 samplespending
Conversion timein 8-bit mode
tC8 CC 16 1 / fADC
2)
Table 15 ADC Characteristics (Operating Conditions apply)1) (cont’d)
Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 44 V2.0, 2017-10
Maximum sample rate in 8-bit mode 3)
fC8 CC – – fADC / 38.5
– 1 samplepending
– – fADC / 54.5
– 2 samplespending
RMS noise 4) ENRMS CC
– 1.5 – LSB12
DC input, VDD = 5.0 V,VAIN = 2.5 V,25°C
DNL error EADNL CC – ±2.0 – LSB12
INL error EAINL CC – ±4.0 – LSB12
Gain error with external reference
EAGAIN CC
– ±0.5 – % SHSCFG.AREF = 00B (calibrated)
Gain error with internal reference 5)
EAGAIN CC
– ±3.6 – % SHSCFG.AREF = 1XB (calibrated),-40°C - 105°C
– ±2.0 – % SHSCFG.AREF = 1XB (calibrated),0°C - 85°C
Offset error EAOFF CC – ±8.0 – mV Calibrated,VDD = 5.0 V
1) The parameters are defined for ADC clock frequency fSH = 32MHz, SHSCFG.DIVS = 0000B. Usage of anyother frequencies may affect the ADC performance.
2) No pending samples assumed, excluding sampling time and calibration.3) Includes synchronization and calibration (average of gain and offset calibration).4) This parameter can also be defined as an SNR value: SNR[dB] = 20 × log(AMAXeff / NRMS).
With AMAXeff = 2N / 2, SNR[dB] = 20 × log ( 2048 / NRMS) [N = 12].NRMS = 1.5 LSB12, therefore, equals SNR = 20 × log (2048 / 1.5) = 62.7 dB.
5) Includes error from the reference voltage.
Table 15 ADC Characteristics (Operating Conditions apply)1) (cont’d)
Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 45 V2.0, 2017-10
Figure 11 ADC Voltage Supply
MC_VADC_AREFPATHS
AREF
:
VA
GN
D
SARConverter
VC
AL
VSS
VDDInternal
Reference
REFSEL
01
001X
VD
D
CH7..
CH0
VDDint/VDDext
VAIN
VREFGND VREFINT
CHNR
VAREF
VREF
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 46 V2.0, 2017-10
3.2.3 Out of Range Comparator (ORC) CharacteristicsThe Out-of-Range Comparator (ORC) triggers on analog input voltages (VAIN) above theVDDP on selected input pins (ORCx.AIN) and generates a service request trigger(ORCx.OUT).Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 12 ORCx.OUT Trigger Generation
Table 16 Out of Range Comparator (ORC) Characteristics (Operating Conditions apply; VDDP = 3.0 V - 5.5 V; CL = 0.25 pF)
Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.
DC Switching Level VODC CC 54 − 183 mV VAIN ≥ VDDP + VODC
Hysteresis VOHYS CC 15 − 54 mVAlways detected Overvoltage Pulse
tOPDD CC 103 − - ns VAIN ≥ VDDP + 150 mV88 − - ns VAIN ≥ VDDP + 350 mV
Never detected Overvoltage Pulse
tOPDN CC − − 21 ns VAIN ≥ VDDP + 150 mV− − 11 ns VAIN ≥ VDDP + 350 mV
Detection Delay of a persistent Overvoltage
tODD CC 39 − 132 ns VAIN ≥ VDDP + 150 mV31 − 121 ns VAIN ≥ VDDP + 350 mV
Release Delay tORD CC 44 − 240 ns VAIN ≤ VDDP; VDDP = 5 V57 − 340 ns VAIN ≤ VDDP; VDDP = 3.3 V
Enable Delay tOED CC − − 300 ns ORCCTRL.ENORCx = 1
VSS
VDDP
tORD
V OD
C
V OH
YS
tODD
ORCx.OUT
ORCx.AIN
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 47 V2.0, 2017-10
Figure 13 ORC Detection Ranges
VAIN (V)
VSSA
VDDP + 350 mV
VDDP + 150 mV
Overvoltage may be
detected(long enough,
level uncertain )
Never detected
Overvoltage Pulse
(Too short)
T < tOPDNtOPDN < T < tOPDD
Overvoltage may be
detected
T > tOPDD
Always detected Overvoltage Pulse
T < tOPDN
Never detected
Overvoltage Pulse
(Too short)
tOPDN < T < tOPDD T > tOPDD
Always detected Overvoltage Pulse
VDDP + 60 mV
Overvoltage may be
detected
T > tOPDD
Never detected
Overvoltage Pulse
(Too low)
VDDP
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 48 V2.0, 2017-10
3.2.4 Analog Comparator Characteristics Table 17 below shows the Analog Comparator characteristics.Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 17 Analog Comparator Characteristics (Operating Conditions apply)Parameter Symbol Limit Values Unit Notes/
Test ConditionsMin. Typ. Max.Input Voltage VCMP SR -0.05 – VDDP +
0.05V
Input Offset VCMPOFF CC – +/-3 – mV High power modeΔ VCMP < 200 mV
– +/-20 – mV Low power modeΔ VCMP < 200 mV
Propagation Delay1)
1) Total Analog Comparator Delay is the sum of Propagation Delay and Filter Delay.
tPDELAY CC – 25 – ns High power mode, Δ VCMP = 100 mV
– 80 – ns High power mode, Δ VCMP = 25 mV
– 250 – ns Low power mode, Δ VCMP = 100 mV
– 700 – ns Low power mode, Δ VCMP = 25 mV
Current Consumption
IACMP CC – 100 – μA First active ACMP in high power mode, ΔVCMP > 30 mV
– 66 – μA Each additional ACMP in high power mode, ΔVCMP > 30 mV
– 10 – μA First active ACMP in low power mode
– 6 – μA Each additional ACMP in low power mode
Input Hysteresis VHYS CC – +/-15 – mVFilter Delay1) tFDELAY CC – 5 – ns
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 49 V2.0, 2017-10
3.2.5 Temperature Sensor Characteristics Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 18 Temperature Sensor CharacteristicsParameter Symbol Values Unit Note /
Test ConditionMin. Typ. Max.Measurement time tM CC − − 10 msTemperature sensor range TSR SR -40 − 115 °CSensor Accuracy1)
1) The temperature sensor accuracy is independent of the supply voltage.
TTSAL CC -6 – 6 °C TJ > 20°C -10 – 10 °C 0°C ≤ TJ ≤ 20°C− -/+8 – °C TJ < 0°C
Start-up time after enabling tTSSTE SR − − 15 μs
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 50 V2.0, 2017-10
3.2.6 Power Supply Current The total power supply current defined below consists of a leakage and a switchingcomponent.Application relevant values are typically lower than those given in the following tables,and depend on the customer's system operating conditions (e.g. thermal connection orused application configurations).Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 19 Power Supply Parameters; VDDP = 5VParameter Symbol Values Unit Note /
Test ConditionMin.
Typ.1) Max.
Active mode currentPeripherals enabledfMCLK / fPCLK in MHz2)
IDDPAE CC − 9.2 12 mA 32 / 64 − 8.1 - mA 24 / 48− 6.6 - mA 16 / 32− 5.5 - mA 8 / 16− 4 - mA 1 / 1
Active mode currentPeripherals disabledfMCLK / fPCLK in MHz3)
IDDPAD CC − 4.8 - mA 32 / 64 − 4.1 - mA 24 / 48− 3.3 - mA 16 / 32− 2.7 - mA 8 / 16− 1.5 - mA 1 / 1
Active mode currentCode execution from RAMFlash is powered downfMCLK / fPCLK in MHz
IDDPAR CC − 7.3 - mA 32 / 64 − 6.3 - mA 24 / 48− 5.2 - mA 16 / 32− 4.2 - mA 8 / 16− 3.3 - mA 1 / 1
Sleep mode currentPeripherals clock enabledfMCLK / fPCLK in MHz4)
IDDPSE CC − 6.6 - mA 32 / 64 5.8 - mA 24 / 485.1 - mA 16 / 324.4 - mA 8 / 163.7 - mA 1 / 1
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 51 V2.0, 2017-10
Sleep mode currentPeripherals clock disabledFlash activefMCLK / fPCLK in MHz5)
IDDPSD CC − 1.8 - mA 32 / 64 1.7 - mA 24 / 481.6 - mA 16 / 321.5 - mA 8 / 161.4 - mA 1 / 1
Sleep mode currentPeripherals clock disabledFlash powered downfMCLK / fPCLK in MHz6)
IDDPSR CC − 1.2 - mA 32 / 64 1.1 - mA 24 / 481.0 - mA 16 / 320.8 - mA 8 / 160.7 - mA 1 / 1
Deep Sleep mode current7) IDDPDS CC − 0.24 - mAWake-up time from Sleep to Active mode8)
tSSA CC − 6 - cycles
Wake-up time from Deep Sleep to Active mode9)
tDSA CC − 280 - μsec
1) The typical values are measured at TA = + 25 °C and VDDP = 5 V.2) CPU and all peripherals clock enabled, Flash is in active mode.3) CPU enabled, all peripherals clock disabled, Flash is in active mode.4) CPU in sleep, all peripherals clock enabled and Flash is in active mode.5) CPU in sleep, Flash is in active mode.6) CPU in sleep, Flash is powered down and code executed from RAM after wake-up.7) CPU in sleep, peripherals clock disabled, Flash is powered down and code executed from RAM after wake-up.8) CPU in sleep, Flash is in active mode during sleep mode.9) CPU in sleep, Flash is in powered down mode during deep sleep mode.
Table 19 Power Supply Parameters; VDDP = 5VParameter Symbol Values Unit Note /
Test ConditionMin.
Typ.1) Max.
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 52 V2.0, 2017-10
Figure 14 shows typical graphs for active mode supply current for VDDP = 5V, VDDP =3.3V, VDDP = 1.8V across different clock frequencies.
Figure 14 Active mode, a) peripherals clocks enabled, b) peripherals clocks disabled: Supply current IDDPA over supply voltage VDDP for different clock
frequencies
0123456789
10
1/1 8/16 16/32 24/48 32/64
I (m A)
MCLK / PCLK (MHz)
IDDPA E 5V/3.3V
IDDPA E 1.8V
IDDPA D 5V/3.3V/1.8V
Condition:1. TA = +25° C
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 53 V2.0, 2017-10
Figure 15 shows typical graphs for sleep mode current for VDDP = 5V, VDDP = 3.3V, VDDP= 1.8V across different clock frequencies.
Figure 15 Sleep mode, peripherals clocks disabled, Flash powered down: Supply current IDDPSR over supply voltage VDDP for different clock frequencies
0
0 .2
0 .4
0 .6
0 .8
1
1 .2
1 .4
1 /1 8 /1 6 1 6 /32 2 4 /48 3 2 /64
I (m A )
M C L K / P C L K (M H z )
ID DP S R5 V /3 .3 V /1 .8 V
C o n d it io n :1 . T A = + 2 5 ° C
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 54 V2.0, 2017-10
Table 20 provides the active current consumption of some modules operating at 5 Vpower supply at 25° C. The typical values shown are used as a reference guide on thecurrent consumption when these modules are enabled.
Table 20 Typical Active Current ConsumptionActive Current Consumption
Symbol Limit Values
Unit Test Condition
Typ.Baseload current ICPUDDC 5.04 mA Modules including Core, SCU,
PORT, memories, ANATOP1)
1) Baseload current is measured with device running in user mode, MCLK=PCLK=32 MHz, with an endless loopin the flash memory. The clock to the modules stated in CGATSTAT0 are gated.
VADC and SHS IADCDDC 3.4 mA Set CGATCLR0.VADC to 12)
2) Active current is measured with: module enabled, MCLK=32 MHz, running in auto-scan conversion mode
USIC0 IUSIC0DDC 0.87 mA Set CGATCLR0.USIC0 to 13)
3) Active current is measured with: module enabled, alternating messages sent to PC at 57.6kbaud every 200ms
CCU40 ICCU40DDC 0.94 mA Set CGATCLR0.CCU40 to 14)
4) Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU4 slice for PWM switchingfrom 1500Hz and 1000Hz at regular intervals, 1 CCU4 slice in capture mode for reading period and duty cycle
CCU80 ICCU80DDC 0.42 mA Set CGATCLR0.CCU80 to 15)
5) Active current is measured with: module enabled, MCLK=PCLK=32 MHz, 1 CCU8 slice with PWM frequencyat 1500Hz and a period match interrupt used to toggle duty cycle between 10% and 90%
POSIF0 IPIF0DDC 0.26 mA Set CGATCLR0.POSIF0 to 16)
6) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, hall sensor mode
BCCU0 IBCCU0DDC 0.24 mA Set CGATCLR0.BCCU0 to 17)
7) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, FCLK=0.8MHz, Normalmode (BCCU Clk = FCLK/4), 3 BCCU Channels and 1 Dimming Engine, change color or dim every 1s
MATH IMATHDDC 0.35 mA Set CGATCLR0.MATH to 18)
8) Active current is measured with: module enabled, MCLK=32 MHz, PCLK=64MHz, tangent calculation in whileloop; CORDIC circular rotation, no keep, autostart; 32-by-32 bit signed DIV, autostart, DVS right shift by 11
WDT IWDTDDC 0.03 mA Set CGATCLR0.WDT to 19)
9) Active current is measured with: module enabled, MCLK=32 MHz, time-out mode; WLB = 0, WUB =0x00008000; WDT serviced every 1s
RTC IRTCDDC 0.01 mA Set CGATCLR0.RTC to 110)
10) Active current is measured with: module enabled, MCLK=32 MHz, Periodic interrupt enabled
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 55 V2.0, 2017-10
3.2.7 Flash Memory Parameters
Note: These parameters are not subject to production test, but verified by design and/orcharacterization.
Table 21 Flash Memory ParametersParameter Symbol Values Unit Note /
Test ConditionMin. Typ. Max.Erase Time per page / sector
tERASE CC 6.8 7.1 7.6 ms
Program time per block
tPSER CC 102 152 204 μs
Wake-Up time tWU CC − 32.2 − μsRead time per word ta CC − 50 − nsData Retention Time tRET CC 10 − − years Max. 100 erase /
program cyclesFlash Wait States 1)
1) Flash wait states are automatically inserted by the Flash module during memory read when needed. Typicalvalues are calculated from the execution of the Dhrystone benchmark program.
NWSFLASH CC 0 0 0 fMCLK = 8 MHz0 1 1 fMCLK = 16 MHz1 1.3 2 fMCLK = 32 MHz
Fixed Flash Wait States configured in bit NVM_NVMCONF.WS
NFWSFLASH SR
0 0 1 NVM_CONFIG1.FIXWS = 1B,fMCLK ≤ 16 MHz
1 1 1 NVM_CONFIG1.FIXWS = 1B,16 MHz < fMCLK ≤ 32 MHz
Erase Cycles NECYC CC − − 5*104 cycles Sum of page and sector erase cycles
Total Erase Cycles NTECYC CC − − 2*106 cycles
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 56 V2.0, 2017-10
3.3 AC Parameters
3.3.1 Testing Waveforms
Figure 16 Rise/Fall Time Parameters
Figure 17 Testing Waveform, Output Delay
Figure 18 Testing Waveform, Output High Impedance
10%
90%
VSS
VDDP
tR tF
10%
90%
VDDP / 2 VDDP / 2
VDDP
VSS
Test Points
VLOAD + 0.1V Timing Reference
PointsVLOAD - 0.1V
VOH - 0.1V
VOL + 0.1V
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 57 V2.0, 2017-10
3.3.2 Power-Up and Supply Monitoring Characteristics Table 22 provides the characteristics of the power-up and supply monitoring inXMC1300. The guard band between the lowest valid operating voltage and the brownout resetthreshold provides a margin for noise immunity and hysteresis. The electricalparameters may be violated while VDDP is outside its operating range. The brownout detection triggers a reset within the defined range. The prewarningdetection can be used to trigger an early warning and issue corrective and/or fail-safeactions in case of a critical supply voltage drop.Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Table 22 Power-Up and Supply Monitoring Parameters (Operating Conditions apply)
Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.
VDDP ramp-up time tRAMPUP SR VDDP/ SVDDPrise
− 107 μs
VDDP slew rate SVDDPOP SR 0 − 0.1 V/μs Slope during normal operation
SVDDP10 SR 0 − 10 V/μs Slope during fast transient within +/-10% of VDDP
SVDDPrise SR 0 − 10 V/μs Slope during power-on or restart after brownout event
SVDDPfall1) SR 0 − 0.25 V/μs Slope during
supply falling out of the +/-10% limits2)
VDDP prewarning voltage
VDDPPW CC 2.1 2.25 2.4 V ANAVDEL.VDEL_SELECT = 00B
2.85 3 3.15 V ANAVDEL.VDEL_SELECT = 01B
4.2 4.4 4.6 V ANAVDEL.VDEL_SELECT = 10B
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 58 V2.0, 2017-10
Figure 19 Supply Threshold Parameters
VDDP brownout reset voltage
VDDPBO CC 1.55 1.62 1.75 V calibrated, before user code starts running
VDDP voltage to ensure defined pad states
VDDPPA CC − 1.0 − V
Start-up time from power-on reset
tSSW SR − 320 – μs Time to the first user code instruction3)
BMI program time tBMI SR − 8.25 – ms Time taken from a user-triggered system reset after BMI installation is is requested
1) A capacitor of at least 100 nF has to be added between VDDP and VSSP to fulfill the requirement as statedfor this parameter.
2) Valid for a 100 nF buffer capacitor connected to supply pin where current from capacitor is forwarded only tothe chip. A larger capacitor value has to be chosen if the power source sink a current.
3) This values does not include the ramp-up time. During startup firmware execution, MCLK is running at 32 MHzand the clocks to peripheral as specified in register CGATSTAT0 are gated.
Table 22 Power-Up and Supply Monitoring Parameters (Operating Conditions apply) (cont’d)
Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.
VDDP}
5.0V
VDDPPW
VDDPBO
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 59 V2.0, 2017-10
3.3.3 On-Chip Oscillator Characteristics
Note: These parameters are not subject to production test, but verified by design and/orcharacterization.
Table 23 provides the characteristics of the 64 MHz clock output from the digitalcontrolled oscillator, DCO1 in XMC1300.
Table 23 64 MHz DCO1 Characteristics (Operating Conditions apply)Parameter Symbol Limit Values Unit Test Conditions
Min. Typ. Max.Nominal frequency fNOM CC – 64 – MHz under nominal
conditions1) after trimming
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 °C.
Accuracy2)
2) The accuracy can be further improved through alternative methods, refer to XMC1000 Oscillator HandlingApplication Note.
ΔfLT CC -1.7 – 3.4 % with respect to fNOM(typ), over temperature (TA = 0 °C to 85 °C)
-3.9 – 4.0 % with respect to fNOM(typ), over temperature (TA = -40 °C to 105 °C)
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 60 V2.0, 2017-10
Figure 20 shows the typical curves for the accuracy of DCO1, with and withoutcalibration based on temperature sensor, respectively.
Figure 20 Typical DCO1 accuracy over temperature
Table 24 provides the characteristics of the 32 kHz clock output from digital controlledoscillators, DCO2 in XMC1300.
Table 24 32 kHz DCO2 Characteristics (Operating Conditions apply)Parameter Symbol Limit Values Unit Test Conditions
Min. Typ. Max.Nominal frequency fNOM CC – 32.75 – kHz under nominal
conditions1) after trimming
1) The deviation is relative to the factory trimmed frequency at nominal VDDC and TA = + 25 °C.
Accuracy ΔfLT CC -1.7 – 3.4 % with respect to fNOM(typ), over temperature (0 °C to 85 °C)
-3.9 – 4.0 % with respect to fNOM(typ), over temperature (-40 °C to 105 °C)
-4.00
-3.00
-2.00
-1.00
0.00
1.00
2.00
3.00
4.00
-50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120
Acc
urac
y [%
]
Temperature [ C]
Without calibration based on temperature sensor
With calibration based on temperature sensor
°
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 61 V2.0, 2017-10
3.3.4 Serial Wire Debug Port (SW-DP) Timing The following parameters are applicable for communication through the SW-DPinterface.Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Figure 21 SWD Timing
Table 25 SWD Interface Timing Parameters(Operating Conditions apply)Parameter Symbol Values Unit Note /
Test ConditionMin. Typ. Max.SWDCLK high time t1 SR 50 – 500000 ns –SWDCLK low time t2 SR 50 – 500000 ns –SWDIO input setupto SWDCLK rising edge
t3 SR 10 – – ns –
SWDIO input holdafter SWDCLK rising edge
t4 SR 10 – – ns –
SWDIO output valid time after SWDCLK rising edge
t5 CC – – 68 ns CL = 50 pF– – 62 ns CL = 30 pF
SWDIO output hold time from SWDCLK rising edge
t6 CC 4 – – ns
SWDCLK
SWDIO(Output )
t1 t2
t6
t5
SWDIO(Input )
t3 t4
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 62 V2.0, 2017-10
3.3.5 SPD Timing Requirements The optimum SPD decision time between 0B and 1B is 0.75 µs. With this value thesystem has maximum robustness against frequency deviations of the sampling clock ontool and on device side. However it is not always possible to exactly match this valuewith the given constraints for the sample clock. For instance for a oversampling rate of4, the sample clock will be 8 MHz and in this case the closest possible effective decisiontime is 5.5 clock cycles (0.69 µs).
For a balanced distribution of the timing robustness of SPD between tool and device, thetiming requirements for the tool are:• Frequency deviation of the sample clock is +/- 5%• Effective decision time is between 0.69 µs and 0.75 µs (calculated with nominal
sample frequency)
Table 26 Optimum Number of Sample Clocks for SPDSample Freq.
Sampling Factor
Sample Clocks 0B
Sample Clocks 1B
Effective Decision Time1)
1) Nominal sample frequency period multiplied with 0.5 + (max. number of 0B sample clocks)
Remark
8 MHz 4 1 to 5 6 to 12 0.69 µs The other closest option (0.81 µs) for the effective decision time is less robust.
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 63 V2.0, 2017-10
3.3.6 Peripheral Timings Note: These parameters are not subject to production test, but verified by design and/or
characterization.
3.3.6.1 Synchronous Serial Interface (USIC SSC) Timing The following parameters are applicable for a USIC channel operated in SSC mode.Note: Operating Conditions apply.
Table 27 USIC SSC Master Mode TimingParameter Symbol Values Unit Note /
Test ConditionMin. Typ. Max.SCLKOUT master clock period
tCLK CC 62.5 − − ns
Slave select output SELO active to first SCLKOUT transmit edge
t1 CC 80 − − ns
Slave select output SELO inactive after last SCLKOUT receive edge
t2 CC 0 − − ns
Data output DOUT[3:0] valid time
t3 CC -10 − 10 ns
Receive data input DX0/DX[5:3] setup time to SCLKOUT receive edge
t4 SR 80 − − ns
Data input DX0/DX[5:3] hold time from SCLKOUT receive edge
t5 SR 0 − − ns
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 64 V2.0, 2017-10
Table 28 USIC SSC Slave Mode TimingParameter Symbol Values Unit Note /
Test ConditionMin. Typ. Max.DX1 slave clock period tCLK SR 125 − − nsSelect input DX2 setup to first clock input DX1 transmit edge1)
1) These input timings are valid for asynchronous input signal handling of slave select input, shift clock input, andreceive data input (bits DXnCR.DSEN = 0).
t10 SR 10 − − ns
Select input DX2 hold after last clock input DX1 receive edge1)
t11 SR 10 − − ns
Receive data input DX0/DX[5:3] setup time to shift clock receive edge1)
t12 SR 10 − − ns
Data input DX0/DX[5:3] hold time from clock input DX1 receive edge1)
t13 SR 10 − − ns
Data output DOUT[3:0] valid time
t14 CC - − 80 ns
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 65 V2.0, 2017-10
Figure 22 USIC - SSC Master/Slave Mode Timing
Note: This timing diagram shows a standard configuration, for which the slave selectsignal is low-active, and the serial clock signal is not shifted and not inverted.
t2t1
USIC_SSC_TMGX.VSD
Clock OutputSCLKOUT
Data OutputDOUT[3:0]
t3 t3
t5
Datavalid
t4
First Transmit Edge
Data InputDX0/DX[5:3]
Select OutputSELOx Active
Master Mode Timing
Slave Mode Timing
t11t10
Clock InputDX1
Data OutputDOUT[3:0]
t14 t14
Datavalid
Data InputDX0/DX[5:3]
Select InputDX2
Active
t13
t12
Transmit Edge: with this clock edge, transmit data is shifted to transmit data output.Receive Edge: with this clock edge, receive data at receive data input is latched.
Receive Edge
Last Receive Edge
InactiveInactive
Transmit Edge
InactiveInactive
First Transmit Edge
Receive Edge
Transmit Edge
Last Receive Edge
t5
Datavalid
t4
Datavalid
t12
t13
Drawn for BRGH.SCLKCFG = 00B. Also valid for for SCLKCFG = 01B with inverted SCLKOUT signal.
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 66 V2.0, 2017-10
3.3.6.2 Inter-IC (IIC) Interface Timing The following parameters are applicable for a USIC channel operated in IIC mode.Note: Operating Conditions apply.
Table 29 USIC IIC Standard Mode Timing1)
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal linesneed to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.
Fall time of both SDA and SCL
t1 CC/SR
- - 300 ns
Rise time of both SDA and SCL
t2 CC/SR
- - 1000 ns
Data hold time t3 CC/SR
0 - - µs
Data set-up time t4 CC/SR
250 - - ns
LOW period of SCL clock t5 CC/SR
4.7 - - µs
HIGH period of SCL clock t6 CC/SR
4.0 - - µs
Hold time for (repeated) START condition
t7 CC/SR
4.0 - - µs
Set-up time for repeated START condition
t8 CC/SR
4.7 - - µs
Set-up time for STOP condition
t9 CC/SR
4.0 - - µs
Bus free time between a STOP and START condition
t10 CC/SR
4.7 - - µs
Capacitive load for each bus line
Cb SR - - 400 pF
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 67 V2.0, 2017-10
Table 30 USIC IIC Fast Mode Timing1)
1) Due to the wired-AND configuration of an IIC bus system, the port drivers of the SCL and SDA signal linesneed to operate in open-drain mode. The high level on these lines must be held by an external pull-up device,approximalely 10 kOhm for operation at 100 kbit/s, approximately 2 kOhm for operation at 400 kbit/s.
Parameter Symbol Values Unit Note / Test ConditionMin. Typ. Max.
Fall time of both SDA and SCL
t1 CC/SR
20 + 0.1*Cb2)
2) Cb refers to the total capacitance of one bus line in pF.
- 300 ns
Rise time of both SDA and SCL
t2 CC/SR
20 + 0.1*Cb
- 300 ns
Data hold time t3 CC/SR
0 - - µs
Data set-up time t4 CC/SR
100 - - ns
LOW period of SCL clock t5 CC/SR
1.3 - - µs
HIGH period of SCL clock t6 CC/SR
0.6 - - µs
Hold time for (repeated) START condition
t7 CC/SR
0.6 - - µs
Set-up time for repeated START condition
t8 CC/SR
0.6 - - µs
Set-up time for STOP condition
t9 CC/SR
0.6 - - µs
Bus free time between a STOP and START condition
t10 CC/SR
1.3 - - µs
Capacitive load for each bus line
Cb SR - - 400 pF
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 68 V2.0, 2017-10
Figure 23 USIC IIC Stand and Fast Mode Timing
3.3.6.3 Inter-IC Sound (IIS) Interface Timing The following parameters are applicable for a USIC channel operated in IIS mode.Note: Operating Conditions apply.
Table 31 USIC IIS Master Transmitter TimingParameter Symbol Values Unit Note /
Test ConditionMin. Typ. Max.Clock period t1 CC 2/fMCLK - - ns VDDP ≥ 3 V
4/fMCLK - - ns VDDP < 3 VClock HIGH t2 CC 0.35 x
t1min
- - ns
Clock Low t3 CC 0.35 x t1min
- - ns
Hold time t4 CC 0 - - nsClock rise time t5 CC - - 0.15 x
t1min
ns
SCL
SDA
SCL
SDA
t1 t2
t1 t2
t10
t9t7t8
t7
t3
t4
t5
t6
P SSr
S
70%
30%
9th
clock
9th
clock
XMC1300 AB-StepXMC1000 Family
Electrical Parameters
Data Sheet 69 V2.0, 2017-10
Figure 24 USIC IIS Master Transmitter Timing
Figure 25 USIC IIS Slave Receiver Timing
Table 32 USIC IIS Slave Receiver TimingParameter Symbol Values Unit Note /
Test ConditionMin. Typ. Max.Clock period t6 SR 4/fMCLK - - nsClock HIGH t7 SR 0.35 x
t6min
- - ns
Clock Low t8 SR 0.35 x t6min
- - ns
Set-up time t9 SR 0.2 x t6min
- - ns
Hold time t10 SR 10 - - ns
SCK
WA/DOUT
t1
t5 t3
t2
t4
SCK
WA/DIN
t6
t10
t8
t7
t9
XMC1300 AB-StepXMC1000 Family
Package and Reliability
Data Sheet 70 V2.0, 2017-10
4 Package and ReliabilityThe XMC1300 is a member of the XMC1000 Family of microcontrollers. It is alsocompatible to a certain extent with members of similar families or subfamilies.Each package is optimized for the device it houses. Therefore, there may be slightdifferences between packages of the same pin-count but for different device types. Inparticular, the size of the exposed die pad may vary.If different device types are considered or planned for an application, it must be ensuredthat the board layout fits all packages under consideration.
4.1 Package ParametersTable 33 provides the thermal characteristics of the packages used in XMC1300.
Note: For electrical reasons, it is required to connect the exposed pad to the boardground VSSP, independent of EMC and thermal requirements.
4.1.1 Thermal ConsiderationsWhen operating the XMC1300 in a system, the total heat generated in the chip must bedissipated to the ambient environment to prevent overheating and the resulting thermaldamage.The maximum heat that can be dissipated depends on the package and its integrationinto the target board. The “Thermal resistance RΘJA” quantifies these parameters. Thepower dissipation must be limited so that the average junction temperature does notexceed 115 °C.
Table 33 Thermal Characteristics of the PackagesParameter Symbol Limit Values Unit Package Types
Min. Max.Exposed Die Pad Dimensions
Ex × EyCC
- 2.7 × 2.7 mm PG-VQFN-24-19- 3.7 × 3.7 mm PG-VQFN-40-13
Thermal resistance Junction-Ambient
RΘJA CC - 104.6 K/W PG-TSSOP-16-81)
1) Device mounted on a 4-layer JEDEC board (JESD 51-5); exposed pad soldered.
- 83.2 K/W PG-TSSOP-28-161)
- 70.3 K/W PG-TSSOP-38-91)
- 46.0 K/W PG-VQFN-24-191)
- 38.4 K/W PG-VQFN-40-131)
XMC1300 AB-StepXMC1000 Family
Package and Reliability
Data Sheet 71 V2.0, 2017-10
The difference between junction temperature and ambient temperature is determined byΔT = (PINT + PIOSTAT + PIODYN) × RΘJA
The internal power consumption is defined asPINT = VDDP × IDDP (switching current and leakage current).The static external power consumption caused by the output drivers is defined asPIOSTAT = Σ((VDDP-VOH) × IOH) + Σ(VOL × IOL)The dynamic external power consumption caused by the output drivers (PIODYN) dependson the capacitive load connected to the respective pins and their switching frequencies.If the total power dissipation for a given system configuration exceeds the defined limit,countermeasures must be taken to ensure proper system operation:• Reduce VDDP, if possible in the system• Reduce the system frequency• Reduce the number of output pins• Reduce the load on active output drivers
XMC1300 AB-StepXMC1000 Family
Package and Reliability
Data Sheet 72 V2.0, 2017-10
4.2 Package Outlines
Figure 26 PG-TSSOP-38-9
XMC1300 AB-StepXMC1000 Family
Package and Reliability
Data Sheet 73 V2.0, 2017-10
Figure 27 PG-TSSOP-28-16
XMC1300 AB-StepXMC1000 Family
Package and Reliability
Data Sheet 74 V2.0, 2017-10
Figure 28 PG-TSSOP-16-8
XMC1300 AB-StepXMC1000 Family
Package and Reliability
Data Sheet 75 V2.0, 2017-10
Figure 29 PG-VQFN-24-19
XMC1300 AB-StepXMC1000 Family
Package and Reliability
Data Sheet 76 V2.0, 2017-10
Figure 30 PG-VQFN-40-13
All dimensions in mm.
XMC1300 AB-StepXMC1000 Family
Quality Declaration
Data Sheet 77 V2.0, 2017-10
5 Quality DeclarationTable 34 shows the characteristics of the quality parameters in the XMC1300.
Table 34 Quality ParametersParameter Symbol Limit Values Unit Notes
Min. Max.ESD susceptibility according to Human Body Model (HBM)
VHBM SR
- 2000 V Conforming to EIA/JESD22-A114-B
ESD susceptibility according to Charged Device Model (CDM) pins
VCDM SR
- 500 V Conforming to JESD22-C101-C
Moisture sensitivity level MSL CC
- 3 - JEDECJ-STD-020D
Soldering temperature TSDR SR
- 260 °C Profile according to JEDECJ-STD-020D