xilinxworkshop_1

8/2/2019 XilinxWorkshop_1

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ECE 272 Xilinx Tutorial


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Workshop Goals Learn how to use Xilinx to:

Draw a schematic

Create a symbol

Generate a testbench

Simulate your circuit


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Getting Started Open Xilinx ISE (11)

Click File New Project Create a new project

directory titled Workshop

Name the project Project1

Select HDL as the top levelsource.


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Device Properties


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Create New Source In the Create New Source box, Click on New Source

Select Schematic from the box, and give it the filename Schematic1

Click next through the Create New Source window andthe Add Existing Source window, then click finish.


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Schematic Creation We will be drawing this circuit:

To get started, take a look at the Symbols box on theleft side of the Project Navigator window.


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Adding Logic Gates Under Categories select logic

Under symbols, select the appropriate logic symbol

Either AND2, XOR2, or OR2.

Click Add Symbol

Place each symbol in its proper place on the schematic.

Click AddWire, and connect these logic gates as shown below.


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Adding I/O Buffers Under Categories, select I/O

Under Symbols, select either IBUF or OBUF

IBUF is for inputs, OBUF is for outputs.

Place these symbols, and connect to the logic gates with wires.

Add extra hanging wires on each of the buffers.


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Defining Inputs and Outputs Click on Add Net Name, and appropriately name the

hanging wires A,B,C and Z.

To do this, look at the Options box on the lower left side of thewindow. Put the desired name in the Name box, then click on

the branch you want to name.

Click on Add I/O Marker, select the input marker choicefrom the Options box, and add them to A, B and C.

Click on Add I/O Marker, select the output marker choicefrom the Options box, and add it to Z.


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Final Schematic

Try writing up the truth table for this circuit. It will beuseful when we simulate it later!


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Creating a Circuit Symbol Often times simple circuits like this are small parts of a

larger, more complex circuit.

When building larger circuits, it is much easier to have

the smaller sections represented by their own symbols.

We will next represent our logic circuit as a symbol withthe same inputs and outputs.


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Symbol Creation Click on Tools Symbol Wizard Under Pin Name Source, select Using Schematic and make sure it is

referencing the proper schematic (Schematic1

ClickNext through the remaining boxes (all of the default values are fine).

If your symbol looks like the one below, click Finish.


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Symbol Creation To make sure our symbol can be accessed in future

designs, go to Project New Source Open a new schematic named Schematic2

Go to Categories in the symbols window and search for yourproject path (For example, mine was)

Select the Schematic1 symbol and click on AddSymbol. Does it appear correctly? If so, you are ready to incorporate

your logic circuit into a larger design!


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Circuit Testing Before using any circuit in a larger design, it is

important to make sure that it works correctly.

To test our circuit, we will create a file called a

testbench. This file will take our logic circuit and give it a series of

inputs.

We will then compare the outputs to the truth table for the

circuit, and see if it is working correctly.


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Generating Testbench Click on Project New Source Select Verilog Test Fixtureand name the file Test1

Select Schematic1 as the source to associate it withand click Next, then Finish.

Xilinx creates a Verilog Testbench file that we can useto test the circuit.


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Verilog Verilog is an HDL (Hardware Description Language).

It is used to describe circuits in terms of the behavior oftheir components, how the wires connect them, etc.

Circuits described in Verilog are called modules.

This testbench is taking the Schematic1 module andtreating it as the UUT (Unit Under Test).

The testebench is feeding the UUT inputs. Once wesimulate this file, we can observe the output!!


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Testbench Changes Remove the line ifdef auto_init

Change the line endif to only say end

The lines of code between initial begin and end shouldappear like this:


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Simulating Testbench Go to the Design window on the left side and change the

selection on the Sources for drop-down menu to BehavioralSimulation.

Be sure you have your testbench selected as your process.

Right click on Simulate Behavioral Model and select ProcessProperties.

Change the simulation time to 100ns, then press OK

Double click on Simulate Behavioral Model


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Simulation Results ISim should open up and display your simulation

results.

Does your waveform match mine?

Do the results of the simulation match what your logictable says should happen?


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Questions!?

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