xilinx xapp1103 simulation of the ieee 802.16 ctc encoder ... · noise (awgn) conditions using the...

XAPP1103 (v1.0) November 20, 2008 www.xilinx.com 1

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Summary This application note describes how to simulate the LogiCORE™ IP IEEE 802.16e CTC Encoder and IEEE 802.16e CTC Decoder together using either ModelSim® or Hardware-in-the-Loop using Xilinx® System Generator software.

Simulation using ModelSim gives users of the IP a chance to get an understanding of the operation of the IP and the various control signals. Hardware-in-the-loop provides bit-error rate (BER) performance measurements. Within the hardware design, a noisy channel model is used to test the encoder/decoder combination under a variety of Additive White Gaussian Noise (AWGN) conditions using the AWGN module. A combination of Simulink® blocks and MATLAB® scripts is used to control the hardware, and collect and display the results.

This application note does not deal with MATLAB simulation (which is covered in more detail in [Ref 1]).

Introduction The IEEE 802.16e CTC Encoder and Decoder cores (hereinafter referred to as encoder and decoder) perform duo binary turbo encoding and decoding of channel data as described in Section 8.4 of the IEEE Std 802.16e specification.

Running a simulation can help explain the operation of these cores and how they operate with each other. In addition, a simulation can detail any system-level implications.

The purpose of the application note is to:

• Outline a simulation methodology using Mentor Graphics® ModelSim® for the encoder and decoder.

• Provide information on hardware-in-the-loop simulations and creating a bit-error rate (BER) plot to assess the BER performance of the encoder/decoder.

Hardware-in-the-loop simulations are extremely useful and important. The ability to execute BER performance measurements within hardware can reduce many hours (perhaps even days) of software simulations to a few minutes of hardware execution. A significantly larger amount of data can be passed through the system with this approach to increase the accuracy of the final results.

Additional Reading

It is recommended that the reader be familiar with the data sheets for the Xilinx® CTC Encoder and Decoder cores [Ref 2] [Ref 3].

The data sheets can be obtained either through CORE Generator™ or the following product pages:

• CTC Encoder : www.xilinx.com/products/ipcenter/DO-DI-CTC-80216E-ENC.htm

• CTC Decoder : www.xilinx.com/products/ipcenter/DO-DI-CTC-80216E-DEC.htm

For the AWGN module [Ref 4], see:

• www.xilinx.com/products/ipcenter/DO-DI-AWGN.htm

Application Note: Virtex®-5 Family

XAPP1103 (v1.0) November 20, 2008

Simulation of the IEEE 802.16 CTC Encoder and DecoderAuthor: Michael Francis and Raied Mazahreh

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http://www.xilinx.com/products/ipcenter/DO-DI-CTC-80216E-ENC.htm

http://www.xilinx.com/products/ipcenter/DO-DI-CTC-80216E-DEC.htm

http://www.xilinx.com/products/ipcenter/DO-DI-AWGN.htm

http://www.xilinx.com

ModelSim Simulation


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A familiarity with System Generator and Xilinx® Tools is also assumed. For more information, see:

• www.xilinx.com/support/software_manuals.htm

• www.xilinx.com/ise/optional_prod/system_generator.htm

ModelSim Simulation

There are two simulation flows for simulating the CTC encoder and decoder:

• Standard simulation using a test bench comprising:

♦ UniSim® model of the CTC Encoder

♦ UniSim model of the CTC Decoder

• Advanced simulation using a test bench comprising:

♦ UniSim model of the CTC Encoder

♦ UniSim model of the Additive White Gaussian Noise (AWGN) module

♦ UniSim model of the CTC Decoder.

Standard ModelSim Simulation

Prior to running the simulation, the UniSim models for the encoder and decoder must be generated.

Generating the IEEE 802.16e CTC Encoder UniSim Model1. Create a new directory.

2. Open CORE Generator via Start => All Programs => Xilinx® ISE® Design Suite10.1 => ISE => Accessories => CORE Generator.

3. Create a new project through File => New Project and navigate to the created directory. Set the following:

♦ Family: Virtex-5

♦ Device: XC5VSX50T

♦ Package: FF1136

♦ Speed Grade: -1

This allows the netlists to be used with hardware-in-the-loop if required.

4. Go to Communications => Error Corrections => 802.16e CTC Encoder as shown in Figure 1. Select Customize.

5. For the CTC encoder GUI, set the following options, shown in Figure 2:

♦ Component Name: CTC_ENC

♦ Set Synchronous Clear (SCLR).

♦ Set Clock Enable (CE).

http://www.xilinx.com/support/software_manuals.htm

http://www.xilinx.com/ise/optional_prod/system_generator.htm


ModelSim Simulation


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.

6. Click Finish. This generates the simulation files ctc_enc.vhd and ctc_enc.ngc.

X-Ref Target - Figure 1

Figure 1: CORE Generator: 802.16e CTC Encoder Screen


Figure 2: CTC Encoder—Screen 1


ModelSim Simulation


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Generating the IEEE 802.16e CTC Decoder UniSim Model

Create the IEEE 802.16e CTC Decoder core as outlined in steps 1-3 above.

This produces the UniSim structural netlist and the NGC netlist.

1. Using CORE Generator, go to Communications => Error Corrections => 802.16e CTC Decoder and select Customize.

2. For the CTC Decoder GUI, set the following options, shown in Figure 3:

♦ Component Name: ctc_dec

♦ Maximum Block Size: 600

♦ SISO Decoders: 4

♦ Soft Input Data Bits: 6

♦ Extrinsic Data Bits: 6

Simulation

Use the following steps to create the simulation.

1. Unzip the xapp1103.zip in the directory. This extracts the following files:

♦ standard_sim_tb.zip

♦ advanced_sim_tb.zip

♦ hwitl_sim.zip

2. Unzip the standard_sim_tb.zip into a working directory for the simulation. This extracts the following files:

♦ ctc_sim_tb.vhd: Testbench for the decoder, includes CTC encoder component.

♦ ctc_enc.vhd: UniSim structural netlist of the CTC encoder.

♦ ctc_sim_tb.do: Simulation script file.

♦ wave_ ctc_sim_tb.do: Simulation signal script file.


Figure 3: CTC Decoder—Screen 1


ModelSim Simulation


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3. Create the CTC Encoder core as outlined in “Generating the IEEE 802.16e CTC Encoder UniSim Model.” Copy the UniSim VHD file for the encoder (corename.vhd) to the working directory.

4. Create the CTC Decoder core as outlined in “Generating the IEEE 802.16e CTC Decoder UniSim Model.” Copy the UniSim VHD file for the decoder (corename.vhd) to the working directory.

5. Open ModelSim and navigate to the working directory.

6. Create the work library if necessary.

7. Go to Tools => TCL => Execute Macro and select ctc_sim_tb.do. This runs the simulation and create the wave window shown in Figure 4.

In the waveform, look at the DEC ERROR signals to confirm the CTC Decoder is operating correctly. It compares the delayed version of the input data to the encoder with the decoder output.


Figure 4: Simulation Wave Window


Advanced ModelSim Simulation


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Modifying the Standard Simulation

If you need to use different parameters than the ones selected in the standard_sim_tb.zip files, make the following changes:

1. Create the CTC Encoder core as outlined in “Generating the IEEE 802.16e CTC Encoder UniSim Model,” but supply the required core name.

Copy the UniSim VHD file for the encoder to the working directory.

2. Create the CTC Decoder core as outlined in “Generating the IEEE 802.16e CTC Encoder UniSim Model,” but supply the required core name.

Copy the UniSim VHD file for the decoder to the working directory.

3. In the simulation script file ctc_sim_tb.do, change the CTC Decoder and CTC Encoder file name for the name of the new core names used in CORE Generator.

4. Open the ctc_sim_tb.vhd file.

5. Replace the component declarations and instantiations for the encoder and decoder in the test bench with the component statements from the vho file.

6. In the test bench file ctc_sim_tb.vhd, change the following lines to the values from the CORE Generator GUI, if required.

CONSTANT GHARQL5 : INTEGER := 1;CONSTANT widthd : INTEGER := 6;CONSTANT widthe : INTEGER := 6;

7. If Soft Input Data Width in CORE Generator is set to '8', set these values:

CONSTANT widthd : INTEGER := 8;

8. If Extrinsic Data Width in CORE Generator is set to '8', set these values:

CONSTANT widthe : INTEGER := 8;

9. If the Max Block Size in CORE Generator is set to ‘60’, set these values:

CONSTANT GHARQL5 : INTEGER := 0;

10. To change the early termination in ctc_sim_tb.vhd, change the following statement to what is required:

earlyterm <= "00";

11. To change the number of iterations in ctc_sim_tb.vhd, change the following statement:

NumIter <= "00000100";

12. Once the changes are done, open ModelSim, navigate to the directory, and execute the ctc_sim_tb.do macro.


This simulation uses a AWGN module to include noise as part of the simulation. Prior to running the simulation, the UniSim models for the encoder and decoder must be generated as well as the AWGN module.

Generating the AWGN UniSim Model

To generate the AWGN module and simulation, follow these steps:

1. Visit the product page for the Additive White Gaussian Noise module at www.xilinx.com/products/ipcenter/DO-DI-AWGN.htm.

2. Download the zip file to a temporary directory.

3. Unzip the file, ensuring that the existing folder path names will be replicated (select option "Use folder names" in WinZip).

4. There is a number of subdirectories, and the VHDL source code for the AWGN module is in the /src directory.


http://www.xilinx.com/products/ipcenter/DO-DI-AWGN.htm



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5. Open Project Navigator and navigate to the ISE project. There will be a message about updating the project. Click OK.

6. Click on the device in the sources window, right-click, and select Properties.

7. Modify the family and device as shown in Figure 5 and click OK.

8. With the ISE project open, remove wgn_wrapper.vhd and wgn_hwtb.vhd from the sources window. Select wgn.vhd as the top module.

9. For the following files, comment out the RLOC and BEL attributes:

♦ Wgn.vhd

♦ Snr_rom.vhd

♦ Snr_mult.vhd

♦ round.vhd

♦ Init_control.vhd

♦ Normal.vhd

♦ Bm1.vhd

♦ Fr_s_rom1.vhd

♦ G_s_rom.vhd

♦ Bm_mult.vhd

♦ Bm2.vhd

♦ Fr_s_rom2.vhd

♦ Bm3.vhd

♦ Fr_s_rom3.vhd

♦ Bm4.vhd

♦ Fr_s_rom4.vhd

♦ Bm_sum.vhd

♦ Bm_add.vhd

♦ Lfsr_17_3.vhd

♦ Lfsr_25_3.vhd

♦ Lfsr_29_2.vhd


Figure 5: Project Properties




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♦ Lfsr_31_3.vhd

♦ Lfsr_41_3.vhd

♦ Rom16x9.vhd

♦ Lfsr_47_5.vhd

♦ Up_counter.vhd

10. Under the Synthesis Properties and Xilinx Specific Options, ensure Add I/O Buffers is unchecked.

11. Under the Synthesize options, expand Generate the Post-Synthesis Simulation Model and double-click Post-Synthesis Simulation Report. The wgn_synthesis.vhd file is found in the \netgen\synthesis directory. This file will be needed for simulation.

Simulation1. Unzip the xapp1103.zip into a working directory. This extracts the following zip files.



♦ hwitl_sim.zip

2. Unzip advanced_sim_tb.zip.

3. Create the CTC Encoder core as outlined in “Generating the IEEE 802.16e CTC Encoder UniSim Model,” page 2, but supply the required core name.


4. Create the CTC Decoder core as outlined in “Generating the IEEE 802.16e CTC Decoder UniSim Model,” page 4, but supply the required core name.


5. Create the AWGN netlist as outlined in “Generating the AWGN UniSim Model,” page 6.

6. Copy the wgn_synthesis.vhd file for the AWGN to the directory where the standard_sim_tb.zip was unzipped. (UniSims model: Virtex-5 AWGN UniSim simulation netlist.)

7. Open ModelSim and navigate to the working directory.

8. To create the new library tccenc_lib, select File => New Library and name the library tccenc_lib.


Figure 6: Create New Library—tccenc




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Alternatively, do the following commands on the ModelSim command line:

vlib tccenc_libvmap tccenc_lib tccenc_lib

9. Compile the library by selecting Compile => ctc_enc.vhd and the library tccenc_lib.

10. Next, create a new library called awgn _lib. To do this, select File => New Library and name the library awgn _lib.


vlib awgn_libvmap awgn_lib awgn_lib

11. Compile the AWGN UniSim netlist (wgn_synthesis.vhd) into a library called awgn_lib.

12. Next, create a new library called tccdec_lib. To do this, select File => New Library and name the library tccdec_lib.


vlib tccdec _libvmap tccdec _lib tccdec _lib

13. Compile the CTC Decoder (ctc_dec.vhd) into the library called tccdec_lib.

14. Confirm in the library window in ModelSim that there are three libraries:

♦ tccenc_lib

♦ awgn_lib

♦ tccdec_lib

15. Create the work library if necessary.

16. From the menu, select Tools => TCL => Execute Macro and choose ctc_ber_sim_tb.do.

In the waveform, examine the TCCERROR signal to check that the CTC Decoder is operating correctly. It compares the delayed version of the input data to the encoder with the decoder output, as shown in Figure 8.


Figure 7: Create New Library—awgn




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Modifying the Advanced Simulation

If you need to use different parameters than the ones selected in the advanced_sim_tb.zip files, make the following changes:

1. Create the CTC Encoder core as outlined in “Generating the IEEE 802.16e CTC Encoder UniSim Model,” page 2, but supply the required core name.


2. Create the CTC Decoder core as outlined in '“Generating the IEEE 802.16e CTC Decoder UniSim Model,” page 4, but supply the required core name.


3. Open ctc_ber_sim_tb.vhd.


5. If Soft Input Data Width selected in CORE generator is set to '8', set these values:

widthd : integer := 8;;

6. If Extrinsic Data Width selected in CORE generator is set to '8', set these values:

widthe : integer := 8;;

7. If the Max Block Size selected in CORE generator is set to ‘60’, set these values:

Ncode => Ncode(7 downto 0),


Figure 8: Advanced Simulation Wave Window


Hardware-in-the-Loop Simulation in Virtex-5 FPGAs


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The concept of BER testing is quite simple: Create a random set of data using a simple linear feedback shift register (LFSR) and encode the data using the CTC Encoder. The next step is to add random errors to the data to simulate a noisy channel using the AWGN module and decode the data using the CTC Decoder.

The number of received errors is compared with the transmitted data to determine the number of bit errors.

There are two methods to analyze these kinds of systems: software simulation or hardware-in-the-loop (HWITL).

In the software simulation, simulation models of the various design blocks are simulated in software. This can be either through tools like ModelSim, using P files (see [Ref 4]), or System Generator software using black box.

The software simulation method allows the design functionality to be tested, but it does not provide the speed of operation required for this application.

With the HWITL method, the various blocks of the BER module are combined together using XST synthesis tool. This process is handled automatically by the System Generator software. The final output of this process is a hardware realization of the BER module for use on a Xilinx FPGA, or a development board like the ML506.

The ZIP file provided contains all the files to build the hardware model apart form any required netlist files. Follow these steps to create a HWITL simulation.

1. Create the CTC Encoder NGC netlist.

2. Create the AWGN NGC netlist for Virtex-5.

3. Create the CTC Decoder NGC netlist.

4. Unzip the xapp1103.zip into a working directory. This will extract the following zip files:



♦ hwitl_sim.zip

5. Unzip hwitl_sim.zip.

6. Open MATLAB and navigate to the working directory.

7. Open tcc16e_ber_test.mdl. This model has a black box and an associated configuration file ctc_ber_shell_config.m. This file allows System Generator to compile the following files necessary to build the hardware model:

♦ ctc_enc.ngc

♦ wgn.ngc

♦ ctc_dec_600.ngc

♦ rloc_package.vhd

♦ reset_counter.vhd

♦ clockgen.vhd

♦ enc_strobe.vhd

♦ RAMB16_S4096X4.vhd

♦ RAMB16_S8192X2.vhd

♦ RAMB16_S8192Xd.vhd

♦ partoser.vhd

♦ quantize.vhd

♦ sertopar.vhd

♦ puncture_gen.vhd




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♦ bit_counter.vhd

♦ err_counter.vhd

♦ clk_counter.vhd

♦ data_counter.vhd

♦ ctc_ber.vhd

♦ ctc_ber_shell.vhd

See “Reference Design Files,” page 17 for more details on the files. The design window should look like the one shown in Figure 9. X-Ref Target - Figure 9

Figure 9: Design Window




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8. Open Sysgen generator token and select ML506 (Point-to-point Ethernet) hardware-in-the-loop option.


Figure 10: System Generator Settings




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9. Click Generate and the design will create the HWCOSIM model shown in Figure 11. X-Ref Target - Figure 11

Figure 11: HWCOSIM Model




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10. Open tcc16e_ber_test_ml506.mdl and put the HWCOSIM model into the design by replacing the one that is already there. Set the configuration to free running. See Figure 12.

11. Save the file as tcc16e_ber_test_ml506.mdl and close the file.

12. Double-click on the HW cosim token and ensure it is set up for free running. Ensure the Ethernet HWITL is set up. Refer to the System Generator User Guide as necessary. Close the file.


Figure 12: tcc16e_ber_test_hw


http://lilyalice.smugmug.com/gallery/6053917_rbnie#P-1-20



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13. Run the TCC16eBerDemo.m file and the GUI shown in Figure 13 appears.

14. Through the GUI, set the conditions and click Start Plot. The BER plot is generated.

15. For each BER point, the HWITL simulation runs and plots the result.

If another configuration is required, click Clear Plot, select the parameters and click Start Plot again.

By using the GUI, the various code rates can be used to test the CTC Encoder and Decoder. The results are stored in a MATLAB file with the notation data_results_file_Ncode_NumIter_CodeRate.mat.


Figure 13: BER Demo GUI


Figure 14: BER Demo GUI with Graph


Reference Design Files


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Modifying the Hardware-in-the-Loop Simulation

Use these steps to change the simulation for a different core configuration.

1. Create the CTC Encoder core as outlined in “Generating the IEEE 802.16e CTC Encoder UniSim Model,” page 2. but supply the required core name.

Copy the NGC file for the encoder to the working directory.

2. Create the CTC Decoder core as outlined in “Generating the IEEE 802.16e CTC Decoder UniSim Model,” page 4, but supply the required core name. Copy the NGC file for the decoder to the working directory.

3. Open ctc_ber_shell.vhd.


5. If Soft Input Data Width in CORE generator is set to '8', set these values:

widthd : integer := 8;;

6. If Extrinsic Data Width in CORE generator is set to '8', set these values:

widthe : integer := 8;;

7. If Max Block Size in CORE generator is set to '60', set these values:

Ncode => Ncode(7 downto 0),


Included with this application note is a complete set of design files that allows the user to create and run the HWITL BER design for the CTC Encoder and Decoder. The files are described in Table 1.

Table 1: Reference Design Files

File Description

MATLAB Files

TCC16eBerDemo.m Script to start the simulation.

Bpsk.m BPSK channel is used as the channel example.

ctc_ber_shell_config.m

System Generator black box builds the hardware model with the following files:• ctc_enc.ngc• wgn.ngc• ctc_dec_600.ngc• rloc_package.vhd• reset_counter.vhd• clockgen.vhd• enc_strobe.vhd• RAMB16_S4096X4.vhd• RAMB16_S8192X2.vhd• RAMB16_S8192Xd.vhd• partoser.vhd• quantize.vhd• sertopar.vhd• puncture_gen.vhd• bit_counter.vhd• err_counter.vhd• clk_counter.vhd• data_counter.vhd• ctc_ber.vhd• ctc_ber_shell.vhd




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generate_ber.m Creates BER plot for uncoded BPSK as a reference.

generate_TCC16eBer.m Creates BER plot.

TCC16eBerDemo.fig MATLAB GUI file.

HDL Files

rloc_package.vhdThis package contains all the attributes needed to build an RPM code.

reset_counter.vhd Generates a delayed reset.

clockgen.vhd Clock buffers.

enc_strobe.vhd Enables strobe generator.

RAMB16_*.vhd Instantiation of block RAMS.

partoser.vhd TCC Encoder Output Parallel to Serial Converter.

quantize.vhd

This module multiplies the noise by 2 (6 dB increase in noise power), then adds it to the transmitted signal (txdata). The result is multiplied by 2^Nfrac_bits and rounded to the integer value. Finally, the result of the rounding operation is hard limited to widthd bits. The net result is widthd - Nfrac_bits integer bits and Nfrac_bits fractional bits. This module has three clock delays.

sertopar.vhd TCC Decoder Input Serial to Parallel Converter.

puncture_gen.vhdGenerates the puncture pattern for the WiMax CTC Decoder hardware test bench.

bit_counter.vhd Bit counter.

err_counter.vhd Logic counting the number of errors.

clk_counter.vhd

data_counter.vhd

ctc_ber.vhd This is the hardware test bench of the IEEE 802.16e CTC Decoder core. It measures the BER of the CTC decoder core in the AWGN channel. See Table 2 for more information.

ctc_ber_shell.vhd

Table 2: IO Description

Signal Description

TestMod

This signal determines the decoded data rate (throughput) that is running in the test bench. When 0, fixed mode is running and the throughput is fixed and equal to 0.25 of clock rate. When 1, maximum mode is running and the throughput is determined by the number of iterations.

Nfrac_bitsNumber of fractional bits. Since the total number of bits for this test bench is equal to six, then valid values for this signal are 0000, 0001, 0010, 0011, 0100 and 0101.

ex_scale Extrinsic scaling.

Table 1: Reference Design Files (Cont’d)

File Description




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SNR

Signal to noise ratio in dB. This is an eight-digit number. The four MSB bits are the integer part, and the four LSB bits are the fractional part. The output of the AWGN generator in this test bench is multiplied by 2 (for example, a 6 dB increase). Therefore, 6 dB and the code rate must be taken into account to set the right SNR value. For example, when using a 1/2 code rate, 6 dB + 10*log10(1/2) = 3 dB. Therefore, to find the BER at 0 dB, set the SNR value to 00110000.

BitselThis determines the bit count before the test bench stops running. The bit count is equal to 2^(8+bitsel). For example, if bitsel is equal to 00000, then bit count is equal to 2^8.

Earlyterm

Early termination enable signal.♦ When 00, early termination is not enabled.♦ When 01, early termination scheme one is enabled.♦ When 10, early termination scheme two is enabled.

Ncode Data block size in pairs.

NumIterNumber of iterations. This test bench can run up to seven iterations. If more iterations are necessary, then the file enc_strobe.vhd must be modified to allow more space between successive data blocks.

Code Rate

This 4-bit value indicates the code rate selected. ♦ When 0000, rate 1/3♦ When 0001, rate 2/5♦ When 0010, rate 3/7♦ When 0011, rate 4/9♦ When 0100, rate 5/11♦ When 0101, rate 6/13♦ When 0110, rate 7/15♦ When 0111, rate 8/17♦ When 1000, rate 1/2♦ When 1001, rate 2/3♦ When 1010, rate 3/4♦ When 1011, rate 4/5♦ When 1100, rate 5/6♦ When 1101, rate 6/7♦ When 1110, rate 7/8♦ When 1111, rate 8/9

Refclk System clock. This signal is not used in this test bench, instead the clock is generated internally.

DecDataCntDecoded data count. Number of decoded data bits in a period of 2^(16+bitsel) clocks. This signal is used to calculate the average decoded data rate of the core.

reset_n Active low synchronous reset used to reset the test bench to its initial state. This signal resets the random data generator and the AWGN.

enable_n Active low enable. This signal will first reset the remaining of the test bench, then run the test bench for a period determined by bitsel.

Tccoutput The CTC Decoder decoded output bits.

Tccdatain The random data generator output. When there is no noise, Tccoutput is equal to Tccdatain.

Tccerror High when Tccoutput is not equal to Tccdatain. An indication of a decoding error.

Table 2: IO Description (Cont’d)

Signal Description


References


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References The following Xilinx software and hardware were used to successfully execute and run these design files.

1. UG497, LogiCORE™ IP 802.16e CTC Decoder v3.0 Bit-Accurate MATLAB Model User Guide.

2. DS525, IEEE 802.16e CTC Encoder v2.1 Data Sheet.

3. DS634, IEEE 802.16e CTC Decoder v3.0 Data Sheet.

4. DS210, Additive White Gaussian Noise (AWGN) Module v1.0 Data Sheet.

Revision History

The following table shows the revision history for this document:

Notice of Disclaimer

Xilinx is disclosing this Application Note to you “AS-IS” with no warranty of any kind. This Application Note is one possible implementation of this feature, application, or standard, and is subject to change without further notice from Xilinx. You are responsible for obtaining any rights you may require in connection with your use or implementation of this Application Note. XILINX MAKES NO REPRESENTATIONS OR WARRANTIES, WHETHER EXPRESS OR IMPLIED, STATUTORY OR OTHERWISE, INCLUDING, WITHOUT LIMITATION, IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT, OR FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL XILINX BE LIABLE FOR ANY LOSS OF DATA, LOST PROFITS, OR FOR ANY SPECIAL, INCIDENTAL, CONSEQUENTIAL, OR INDIRECT DAMAGES ARISING FROM YOUR USE OF THIS APPLICATION NOTE.

Tccstart The CTC Decoder output start signal. It is high the first cycle of each of the decoder output data blocks.

Tccinfo The CTC Decoder output valid signal overflow. It is high when the number of errors is greater than 2^16 (the maximum value given by ErrCnt).

ErrCnt The number of decoded bit errors.

BLErrCnt The number of decoded block errors.

TestDone This signal goes high when the test is done (for example, after counting 2^(8+bitsel) bits).

Table 2: IO Description (Cont’d)

Signal Description

Date Version Description of Revisions

11/20/08 1.0 Initial Xilinx release.


http://www.xilinx.com/support/documentation/ip_documentation/tcc_enc_802_16e_ds525.pdf

http://www.xilinx.com/support/documentation/ip_documentation/awgn.pdf

http://www.xilinx.com/member/ieee802_16e_ctc_dec_eval/ctc_decoder_v3_0_bitacc_cmodel_ug497.pdf

http://www.xilinx.com/member/ieee802_16e_ctc_dec_eval/ctc_decoder_v3_0_bitacc_cmodel_ds634.pdf


http://www.xilinx.com/support/documentation/ip_documentation/tcc_enc_802_16e_ds525.pdf


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