xilinx confidential – internal netfpga10g michaela blott, september 2010 page 1
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Xilinx Confidential – Internal
NetFPGA10GMichaela Blott, September 2010
Page 1
Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 Xilinx
NetFPGA10G Team
Michaela Blott Adam Covington Jonathan Ellithorpe Paul Hartke John Lockwood Nick McKeown Sachidanandan Sambandan Kees Vissers Tatsuya Yabe James Zeng
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Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 XilinxPage 3
Motivation/ Objective
Leverage LATEST technology to create a networking reference platform
Enable researchers, students and customers to build working prototypes of hardware-accelerated networking systems
Upgrade interface speeds and components to facilitate faster and more complex prototypes
Successor to the highly successful networking research platform NetFPGA - used by over 500 universities worldwide
Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 XilinxPage 4
High-Level Specification
Xilinx Virtex5
XCV5TX240T-2
FG1759
1G or 10G Ethernet subsystem
PCIe x8, Gen1
interface
QDRII SRAM subsystem
High-speed serial expansion interface
RLDRAMII CIO DRAM subsystem • PCIe adapter full size card, dual slot with extra ATX power connector
• Standalone operation supported
1G or 10G Ethernet subsystem
1G or 10G Ethernet subsystem
1G or 10G Ethernet subsystem
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V2V2
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Memory Interface -SRAM Subsystem
– QDRII, 300MHz, CY7C1515JV18-300BZXC– overall density 216Mb– organized in 3 independent 36bit interfaces– 64.8Gbps raw access for read and 64.8Gbps for write @ 300MHz – sized to handle flow classification, routing table lookup, flow statistics,
and free and used lists
SRAM
adr, ctl din
dout
36bit36bit
SRAM
adr, ctl din
dout
36bit36bit
SRAM
adr, ctl din
dout
36bit36bit
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Memory Interface -DRAM Subsystem
RLDRAMIICIOadr, ctl dataadr, ctl data
RLDRAMIICIO
2*32=64bit
– RLDRAMII CIO, 250-300MHz, MT49H16M36HT-25:A– overall density 2.3Gb (57msec storage of 40Gbps traffic)– arranged as 2 independent 64bit interfaces (2 components per
interface)– 76.8Gbps shared raw access for read and write @ 300MHz – sized to handle packet buffering
2*32=64bit
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Network Interface Flavours
PHY: four single-port PHYs (NetLogic AEL2005) 10G interfaces or 1G interfaces via SFP+ cages Supported physical standards:
– 10G direct attach copper, and optical interfaces 10G LRM, 10G SR, 10G LR– 1000BaseT and 1000BaseX
SFP+ cage
SFP+ cage
SFP+ cage
SFP+ cage
10G PHYSFI
SFI
SFI
SFI
XAUI (4GTXs @3.125Gbps
FPGA
XAUI (4GTXs @3.125Gbps10G PHY
10G PHY XAUI (4GTXs @3.125Gbps
XAUI (4GTXs @3.125Gbps10G PHY
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Expansion Connector
purpose:– allow greater port density, – support different physical interface flavours– add daughter cards with
extra memory cards or NSEs/ KBPs 2 flavours:
– daughter card expansion– board to board with expansion cable
connector:– Two QTH Samtec connectors– Designed for XAUI, PCIe, SATA, Infiniband,
HyperTransport, etc. board to board cable:
– Twinax micro-ribbon cable– Available in different lengths:
for example 0.5m (100 Gbps);1m (50 Gbps) – recommended part number: HQDP-020-05.00-STL-SBR-2
10GTXs @6.25Gbps
FPGA
10GTXs @6.25Gbps
Samtec connector
Samtec connector
distance vs speed:
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NetFPGA 1G NetFPGA 10G
4 x 1Gbps Ethernet Ports 4 x 1Gbps or4 x 10Gbps Ethernet Ports
4.5 MB ZBT SRAM64 MB DDR2 SDRAM
27 MB QDRII-SRAM288 MB RLDRAM-II
PCI PCI Express x8
Virtex II-Pro 50 Virtex 5 TX240T
NetFPGA1G – 10G comparisonIn a nutshell...
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FPGA Designs
Stress-test design prove the board is functional under maximum load
(temperature, power, noise) Basic & full infrastructure designs
provides basic RTL infrastructure to all users in form of well-defined and abstracted interfaces
Planned reference designs PCIe-ICAP design (allows configuration of the FPGA via
PCIe) Stanford reference router design HLS platform and others...
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More information ...
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Alpha Program
Pricing is still being negotiated – heavily subsidized for academics as Micron, Cypress, NetLogic Microsystems and Xilinx are donating the parts
Board was built in collaboration with Hitech Global, who will also distribute the board: (for academic and commercial use) Visit HiTechGlobal’s website
– http://www.hitechglobal.com/Boards/PCIExpress_SFP+.htm
Status: Release to Manufacture in the next weeks
Visit NetFPGA website for the latest update– http://www.netfpga.org
If you haven’t already, sign up to netfpga-announce mailing list– https://mailman.stanford.edu/mailman/listinfo/netfpga-announce
Xilinx Confidential – Internal • Unpublished Work © Copyright 2009 XilinxPage 13
DemoStress-test Design
QDR memory testRLDRAM memory
test
PCIe testSFP+ test
UART report
PCIe Application & Driver
Hyperterminal
Host CPU
FPGA
Test computer
Config & Flash test
Clock & PWR test
Config & Flash test
CPLDNetFPGA10G board
Filler