xcell 20 newsletter (q1 96)pcb design until the pld design was completed and debugged. this...
TRANSCRIPT
Issue 20First Quarter 1996
GENERALFawcett: PLDs, Pins, PCBs ........................ 2Guest Editorial .......................................... 3Foundry Joint Venture .............................. 4Wim Roelandts New CEO ........................ 6Xilinx Ireland Earns ISO 9002 ...................6Customer Success Story ...........................7New Product Literature ............................ 8Financial Results .......................................8Upcoming Events .....................................9Xilinx Wins Awards in Japan .....................9Alliance Program Now On-Line ............ 10Training Information on Web ................ 10Introducing SmartSearch ....................... 11Component Availability Chart ........... 12-13Alliance Program Charts .................... 14-16Programming Support Charts ............ 17-19Development Systems Chart ................. 20
PRODUCTSIntroducing the XC4000E/EX ............. 21-23Low Voltage Line Expands ................ 24-25Designing with XC9500 CPLDs ......... 25-26XC4000E in Production ......................... 26DSP Design Contest .............................. 26XC5200 Family on Record Pace ............ 26
DEVELOPMENT SYSTEMSLogiCore Modules ............................. 27,32XABEL-CPLD on CD .............................. 28Series 8000 Adds Schematics ........... 28-29New XC7000 Core Software ................. 29PowerGuide ...................................... 30-31
HINTS & ISSUESSelecting a Product Family .................... 33JTAG Support for XC9500 Family ..... 34-35FIFO Buffer Design ............................ 36-38Laplacian Filters .................................38-40Retargeting in Design Architect ............ 41FPGA Audio Processing .................... 42-43Using Decoupling Capacitors ........... 42-43Questions & Answers ........................ 44-47Technical Support Resources ................ 47Fax Response Form ............................... 48
The ProgrammableLogic CompanySM
Inside This Issue:
T H E Q U A R T E R L Y J O U R N A L F O R X I L I N X P R O G R A M M A B L E L O G I C U S E R S
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XCELLPRODUCT INFORMATION
125K Gates:Introducing The
XC4000EX FPGA FamilyExtending FPGA capacities beyond
125,000 gates, Xilinx adds to its powerfulseries of XC4000-based architectures...
See Page 21
LogiCoreTM ModulesAccelerate Time-to-Market
DESIGN TIPS & HINTSFIFO Buffer Designin the XC4000E/EXUsing distributed RAM to build high
performance FIFO buffers...See Page 36
The LogiCore PCI Interface is the first in a series of pre-implemented andfully verified “drop-in modules” for FGPA designs created to accelerate thealready fast development process for FPGA devices...
See Page 27
Exploiting Rapid Reconfigurationin an Audio Processor
Metalithic Systems’ FPGA-based audio authoring system debuts...See Page 42
Enter the DSP Design Contest. See page 26 for details.
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FROM THE FAWCETT
PLDs, Pins and PCBsBy BRADLY FAWCETT ◆◆◆◆◆ Editor
R
XCELLPlease direct all inquiries,comments and submissions to:
Editor: Bradly Fawcett
Xilinx, Inc.2100 Logic DriveSan Jose, CA 95124Phone: 408-879-5097FAX: 408-879-4676E-Mail: [email protected]
©1996 Xilinx Inc.All rights reserved.
XCELL is published quarterly forcustomers of Xilinx, Inc. Xilinx, theXilinx logo and XACT are registeredtrademarks; all XC-designatedproducts, UIM, HardWire, XACTstepand XACT-Performance are trade-marks; and “The Programmable LogicCompany” is a service mark of Xilinx,Inc. All other trademarks are theproperty of their respective owners.
2
Continued on page 5
Change is inevitable. The best systemdesigners recognize this axiom and incor-porate tolerance for change into theirschedules, design methodologies, and
even the physical real-izations of their designs.
Changes can occurduring all stages of aproduct’s life cycle.Surveys suggest that asmuch as 50% of thetypical product’s devel-opment time is spent inthe debug/modify/re-implement cycle that
occurs after the first prototype is created.Even if the designer is skilled (and lucky)enough to create a working prototype onthe first try, the product specification canchange in the meantime in response tochanging market conditions. In somecases, products that already have beenproduced and sold formonths or even yearshave been modified toextend the product’s life(or, heaven forbid, tocorrect some previouslyundetected flaw).
Tolerance of changeis one of the primeattractions of program-mable logic devices. With PLDs, designchanges can be implemented quickly andeasily, especially as compared to customand semicustom IC technology. However,when it comes to tolerating changes,printed circuit boards (PCBs) are morelike custom ICs than PLDs. To modify aPCB, new drawings (masks) must becreated, and new prototypes must bemanufactured, with all the associatedexpenses and delays.
Thus, to garner the true benefits of theadaptability of programmable logic, pro-grammable logic device architecturesshould isolate the PCB design from logicchanges that occur within the device. As aresult, two concepts that should be ofprimary concern to PLD users are pin-locking and footprint compatibility.
Pin-locking refers to the ability to es-tablish a fixed pin location for all thesignals entering and leaving a PLD so thatthe PCB layout, in turn, can be fixed.Since PCB design and production is oftena critical path in product development,most designers would prefer to lock PLDpin locations early in the design cycle.However, with some PLDs, this can be arisky proposition; the chosen pinout mayprove to be less than optimal after theimplementation of the inevitable designchanges, leading to decreased perfor-mance, or, in the worse case, a design that
cannot be implementedat all due to routinglimitations within thePLD. Designers thatused the earliest gen-erations of CPLDs andFPGAs may recall thatPLD manufacturersroutinely warned theirusers not to begin their
PCB design until the PLD design wascompleted and debugged. This reputation,established in the early days of high-den-sity PLDs — that is, that design changescan be difficult or impossible to implementwithout changing the device pinout —lingers on today (and deservedly so, forsome of our competitors’ offerings!).
However, those days have long passedfor Xilinx FPGA and CPLD devices.
❝Tolerance ofchange is one of theprime attractions ofprogrammable logic
devices.❞
Part 1 of 2
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R
GUEST EDITORIAL
3
In-System Programming andFlash Technology for CPLDs
By NICK KUCHAREWSKI ◆◆◆◆◆ Vice President, EPLD Division
The latest wave of complex programmable logic devices (CPLDs) has beentargeted at an emerging applications area: In-System Programmability (ISP).In-system programmable CPLDs allow the user to mount an unprogrammeddevice on the PC board, then program the device as part of the manufacturingflow. This greatly eases the handling problems associated with fine pitch pack-ages such as the popular plastic quad flat pack (PQFP). But this is far from theonly advantage of ISP CPLDs.
Designers can use ISP devices to meet a wide range of needs — from facili-tating an integrated design, program, and test environment that allows easyprototyping and system debug, all the way to providing the ability to upgrade adesign in the field through CPLD reconfiguration. Of course, manufacturingsupport must be provided for integrated device programming and board-level test.We refer to supporting this range of user requirements as “supporting the total prod-uct life cycle” with in-system programmable CPLDs. As more and more users begin totake full advantage of ISP capabilities during all stages of a product’s life, the use ofISP CPLDs will continue to increase. In turn, CPLD manufacturers will need to offerdevice architectures and development tools that support this full range of user needsin order to remain competitive.
Introducing the FastFLASHTM XC9500TM FamilyThe XC9500 family is the first CPLD family specifically developed to meet all the
typical user requirements for in-system programmability. Xilinx used those require-ments to drive the XC9500 development process, including basic devicearchitecture decisions and process technology choices. Let’s take a closerlook at some of these requirements, and their impact on the CPLD.
As mentioned in Brad Fawcett’s editorial (see page 2), the flexibility ofISP is enhanced by the ability to fix the chip pinouts (“lock the pins”)while continuing to implement design changes. Obviously, thereconfiguration of CPLDs already in the field requires maintaining fixedpinouts to be successful. The approach we have taken to solving this chal-lenge is quite complex and involves several architectural innovations aswell as improvements to the optimization and fitter software. The result isthe industry’s best pin-locking CPLD.
Many users require complete support of industry-standard IEEE 1149.1JTAG boundary scan test capabilities. By including the in-system programming con-trol within the JTAG controller, both board test and device programming are accom-plished with a single interface, and in an integrated environment. This greatly simpli-fies the manufacturing engineering requirements. The XC9500 is the only CPLD toinclude support for JTAG instructions such as INTEST and USERCODE. The INTESTinstruction is used to test internal logic after device programming on the PC board,
Continued on the next page
❝The XC9500 familyis the first CPLD family
specifically developed to meetall the typical user
requirements for in-systemprogrammability.❞
4
GUEST EDITORIAL
Continued from the previous page
while the USERCODE function allowsthe user to “program in” information suchas version numbers, assembly locations,or dates as part of the manufacturingprocess.
Flash Process TechnologyAn easy-to-use, integrated design and
programming environment allows design-ers to implement multiple design iterationsper day. This can translate into a need tosupport hundreds, and perhaps thousands,of program-erase cycles. Flash processtechnology provides this capability, withmargin to spare. The Xilinx proprietaryFastFLASH Technology is the industry’sfirst 5-volt flash technology developedspecifically for CPLD applications. It isan extension of industry-standard flashmemory technology, and offers the provenreliability of 10,000 program-erase cycles— a factor of up to 100 times more thancompeting ISP CPLDs.
The benefits of flash technology extendbeyond program-erase endurance. Theflash memory cell provides the basic pro-grammable “switch” in the XC9500 CPLDs.The size of the flash memory cell is about1/3 that of other non-volatile technologies,allowing the implementation of manymore “switches” in the same chip area.These added resources lead to improvedroutability and pin-locking capability.
In-system programmability is anincreasingly important requirement forCPLDs. The needs of ISP CPLD usersextend beyond easier handling of PQFPpackages to more complete support of“the total product life cycle.” The architec-ture, process technology and developmenttools of the XC9500 FastFLASH familymeet these needs, allowing users to takefull advantage of the flexibility of ISPtechnology. ◆
In a joint venture with United Micro-electronics Corporation (UMC) and others,Xilinx has invested a 25% equity stake in asemiconductor manufacturing facility inHsin Chu City, Taiwan.
Xilinx is one of more than 100 semicon-ductor companies that use independentsilicon “foundries” rather than their ownwafer fabrication facilities. Being “fabless”allows the company to focus on whatXilinx does best — the design andmarketing of programmable logic devices.Xilinx transcends the scope of traditionalcustomer-supplier relationships by employ-ing its own process experts, who workclosely with our foundry partners in thedevelopment and implementation ofprocess technology improvements.
The Taiwan facility will ensure a steadyand reliable supply of product as thedemand for programmable logic devicescontinues to grow. Starting its two-yearramp up cycle in early 1996, the factory
will produce eight-inch wafers usingsubmicron CMOS processes. In the mean-time, UMC will provide Xilinx with interimcapacity at its other facilities in Taiwan.
Xilinx will maintain its existing foundrypartnerships with Seiko Epson, Yamaha,Taiwan Semiconductor ManufacturingCompany (TSMC) and IC Works. While theUMC investment marks the first time Xilinxhas taken an equity position in a foundry,it is not the first Xilinx investment involv-ing its foundry partners. For example, inearly 1994, Xilinx helped fund SeikoEpson’s expansion of an IC facility inSakata, Japan.
“This new venture ensures foundrycapacity of leading-edge process technolo-gies to meet the rising demand for FPGAs,”noted Xilinx CEO Bernie Vonderschmitt.“This agreement, combined with our otherfoundry partnerships, favorably positionsthe company to meet customer demandto the end of the decade.”◆
XilinxEnters Into
JointVenture for
FoundryCapacity
5
Pin-locking is not an issue with XilinxCPLDs. The XC7300 and XC9500 CPLDfamilies offer the ultimate in pin-lockingcapability, with 100% connectivity throughthe CPLD’s internal switch matrix. Thus,any I/O pin can be connected to anyfunction block input or output, regardlessof utilization levels. Design changes inter-nal to the CPLD will seldom force pinoutchanges.
While the Xilinx FPGA families cannotprovide the same guarantee of full con-nectivity offered by the Xilinx CPLDs, thelatest generations do provide a high de-gree of flexibility in their I/O connections.All recent Xilinx FPGA architectures, in-cluding the XC5200, XC4000E, XC4000EX,XC6200, and XC8100 families, embrace theVersaRingTM concept introduced in theXC5200 family. Simply put, these FPGAsinclude an extra layer of routing resourcesalong the perimeter of the logic array toincrease routing flexibility between theinternal array and the I/O blocks. Userfeedback is confirming that these devicesdeliver on the promise of allowing last-minute design changes without changes tothe I/O pin locations.
Actually, this capability also is presentto a large degree in the “older” XC4000series FPGAs. The popular XC4000 familywas the subject of the only independentresearch study (that I know of) that exam-ined pin-locking in FPGA architectures. Asreported at the 3rd Canadian Workshopon Field-Programmable Devices last May,researchers at the University of Torontoimplemented sixteen different designs inXC4000 devices. The designs were firstrouted with no placement constraints,then with “bad” pin constraints (whereinsignals that were assigned to adjacent pinsin the unconstrained design were nowassigned to opposite ends of the device),and, lastly, with a randomly-generated pin
placement. In every case, the designsrouted to completion, albeit with a slightperformance impact; the average signaldelay increase was less than 5% for the“bad” constraints and 3% for the randomconstraints. Significantly, the researchersconcluded that “Fixed pin assignment doesimpact routability significantly, because theamount of routing resources used wasincreased, but the Xilinx XC4000 seriesarchitecture provided sufficient resourcesto handle the increased demand”. Inciden-tally, a major competitor’sFPGA family — the onlyother device included inthe study — did not farenearly as well; severaldesigns were unroutablewith bad or random pinconstraints, and the re-searchers recommendedthat users of that FPGA“should leave about 20% ofthe logic elements and I/Opins free to avoidroutability problems due topin constraints.”
In conclusion, while“intelligent” placement ofI/O pins is still recom-mended, Xilinx FPGA andCPLD devices are quitetolerant of design changeswithout forcing the rede-sign of the PCB layout.This facilitates an earlyrelease of the PCB design and eases thedebugging process, thereby acceleratingtime-to-market, and accommodates theinevitable changes that occur throughout aproduct’s total life cycle.
In the next issue, part 2 of this articlewill examine the benefits of footprint com-patibility both within and across XilinxPLD product families. ◆
THE FAWCETT
Continued from page 2
❝These FPGAs include
an extra layer of routing
resources along the perimeter
of the logic array to increase
routing flexibility between the
internal array and the I/O
blocks. User feedback is
confirming that these devices
deliver on the promise of
allowing last-minute design
changes without changes to
the I/O pin locations.❞
6
Wim Roelandts New Xilinx CEOIn late January, Bernie Vonderschmitt
retired as Chief Executive Officer of Xilinx.His successor is Willem “Wim” Roelandts,a 28-year veteran of Hewlett-Packard.Vonderschmitt, 72, who co-founded Xilinxin 1984, remains with the company aschairman of the board of directors, andcontinues to be active in the businessaffairs of the company.
Roelandts joined HP in 1967 as a ser-vice engineer in his native Belgium andmost recently served as a senior vicepresident in Hewlett-Packard’s Computer
Xilinx Ireland, the new manufacturingfacility in Dublin, was awarded ISO 9002certification in November. The Xilinx manu-facturing facility in San Jose, California,obtained ISO 9002 certification last Octo-ber. The ISO quality standards were devel-oped by the International Organization forStandardization, a Geneva-based organiza-tion with representatives from 91 countries.
As noted by Derek Kernan, quality man-ager at Xilinx Ireland, “The ISO standard iswidely-recognized in Europe and is a verygood means of measuring the quality ofour processes and the extent to which thedevelopment of the company is keeping
pace with our overall strategy. AcquiringISO certification has made us look at allour processes and all our customers’ re-quirements and understand what we cando better. For us, it represented a goodexternal measure of the value and qualityof our systems.”
Xilinx Ireland, the company’s firstwholly-owned manufacturing facility out-side of the United States, produces anddistributes component products for Eu-rope and other international markets.More than one million FPGA devices wereshipped from Xilinx Ireland within the firstsix months of operation. The facility will
eventually replicateall the activities of thecompany headquar-ters in San Jose, withthe exception of fieldsales and marketing.
The first group ofXilinx Ireland’s soft-ware engineers hasreturned from trainingin California and hasbegun developmentwork in Ireland. Morethan 80 staff membersare now employedin Dublin. ◆
Systems Organization. He was respon-sible for all aspects of the computersystems business worldwide, includingresearch and development, manufactur-ing, marketing and sales.
“Wim Roelandts is a seasoned veteranwho possesses the right mix of leader-ship and management skills to guideXilinx through its next period ofgrowth,” Vonderschmitt stated. “Employ-ees, customers, and shareholders can beconfident he is the right man to take thehelm at Xilinx.” ◆
Xilinx IrelandEarns
ISO 9002Certification
The team of Xilinx Ireland
New Xilinx CEO Wim Roelandts
7
CUSTOMER SUCCESS STORY
Design engineers at SIXNET (Clifton Park,NY), a manufacturer of industrial control equip-ment, faced a daunting challenge: to build anew I/O module (from concept to installationat a customer’s site) within eight weeks.
The device, a digital counter board, wasrequired to provide position and/or velocityinformation for eight independent incomingsignals. The digital count signals can be usedsingly to provide total count or velocity infor-mation, or in pairs to provide quadrature-decoded position information. Typical applica-tions are flow metering (where a small turbinepulses at a rate proportional to the flow of aliquid) and position measurement (where aquadrature decoder tracks the motion of preci-sion machinery).
All previous designs at SIXNET had em-ployed 22V10 (or smaller) PLDs, using equa-tion-based design entry as the primary develop-ment tool. While time restrictions dictated theuse of programmable logic, severe space limita-tions drove the need for a more highly-inte-grated, single-chip solution. The SIXNET designteam quickly narrowed its choices to acompetitor’s SRAM-based FPGA or the XilinxXC8100 FPGA family.
The main elements of the design includeregisters to capture and synchronize incomingdata, state machines for quadrature decoding,and eight 16-bit counters and latches used forposition and velocity measurement. Theoutputs of the counters and state machinesare multiplexed and output on an 8-bit bus.The clock frequency is a modest 4 MHz.
SIXNET engineers quickly discovered thatit would be difficult to fit the design using therelatively large logic blocks of the SRAM-basedFPGA. The counter logic is register-intensive,requiring very little logic between flip-flops,resulting in substantial “wasted” logic in eachlogic block. Similarly, the wide multiplexerswere not a “good fit,” requiring the use ofmany blocks, but with relatively low utilizationof the logic in each block. (These problems
would have been even more prevalent in thecombinatorial-intensive architecture of aCPLD device.)
The same design was easily implementedin a less-expensive XC8103 FPGA. In theXC8100 FPGA architecture, each fine-grainedlogic cell can implement either combinatorialor sequential logic, allowing high utilizationregardless of the unequal mix of combinato-rial functions and flip-flops. The counterswere implemented as ripple counters, bothto minimize area and avoid switching noise;the flexible clocking structure of the XC8100architecture enabled this approach. An inter-nal quad latch with out-put enable — a primitivein the XC8100 library —was used to latch andmultiplex the eightcounters onto a com-mon bus, eliminatingthe multiplexinglogic needed withthe competitor’sproduct.
The designwas entered andimplemented on a PCusing a Viewlogic schematic editor and theXilinx XACT stepTM Series 8000 developmentsystem, respectively. “The transition fromequation entry to Viewlogic schematics waseasy, “ claims Dave Ellis, vice president ofEngineering at SIXNET. “It was just likedoing the schematic for a printed circuitboard. The XC8100 tools were very easy andintuitive to use. We were able to completethe design phase from concept to a workingboard in less than four weeks, includinglearning the Viewlogic and XC8100 designtools.” The controller fits on a compact3.3"x4.3" circuit board.
In conclusion, Mr. Ellis noted, “The XilinxXC8103 was by far the most cost-effectivesolution for our needs.”◆
30-Day Design Cycle With XC8100 FPGA Family
8
Learn about the newest Xilinx products and services through our extensive library ofproduct literature. The most recent pieces are listed below. To order or to obtain a com-plete list of all available literature, please contact your local Xilinx sales representative.◆
Revenue Grows by 58%Xilinx sales revenues achieved a record $144.1 million for the third quarter
of fiscal year 1996 (ended December 31, 1995). This is 58% larger than thesame quarter in fiscal year 1995. It shows a 2% increase from the second quar-ter of fiscal year 1996. This quarter’s performance was affected by a slowdownin bookings, particularly in the early portion of the quarter.
Growth was particularly strong for the new XC5200 FPGA family. Revenuesfrom this family have “ramped up” faster than any other new product family inXilinx history.
Sales revenues for the first nine months of fiscal 1996 totaled $411.1 million,an increase of 67% from the comparable period last year.
Looking ahead to the next quarter, CEO Bernie Vonderschmitt stated that,“We are encouraged by recent indications of a return to more normal bookings.Customer inventory corrections that we witnessed this past quarter appear tobe mostly completed. Most importantly, we are encouraged by the new prod-ucts that we have recently introduced, which will begin to contribute meaning-ful reveunes in calendar 1996.”
Founded in 1984, Xilinx is the world’s largest supplier of programmablelogic devices. Xilinx stock is traded on the NASDAQ exchange under stocksymbol XLNX. ◆
FINANCIAL RESULTS
New ProductLiterature
FPGAs
XC4000EX Overview Features & Benefits #0010284-01XC4000 Data Sheet Technical Data #0010278-01XC4000E Data Sheet Technical Data #0010274-01Xilinx XC5200 vs. Altera FLEX 8000A FPGAs White Paper Technical Data #0010270-01LogiCore PCI Target Interface for 4000E FPGA Data Sheet Technical Data #0010288-01XC3100L Data Sheet Technical Data #0010285-01Design Migration from XC3000/XC3000A to XC5200 Technical Data #0010275-01
EPLDs
XABEL-CPLD Overview Features & Benefits #0010277-01XABEL-CPLD Evaluation Software CD-ROM #500354XC9500 Data Sheet Technical Data #0010280-01XC9500 Applications Guide Technical Data #0010286-01
Development Systems
XACTstep Advanced Development System Overview Features & Benefits #0010271-01XACTstep 5.2 Overview Features & Benefits #0010289-01
TITLE DESCRIPTION NUMBER
Sales revenue up 58% oversame quarter in 1995!
Fast XC5200 FPGA familyproduction ramp up!
9
Xilinx and XC8100 ReceiveExcellence Awards in Japan
Hitachi, Ltd. bestowed the prestigious“Hitachi Award for Excellence” on Xilinxin December. Eiji Aoki, deputy generalmanager of Hitachi’s TelecommunicationsDivision, presented the award to represen-tatives of Xilinx KK in Japan.
The XC8100 FPGA was a finalist in the“ASIC of the Year” competition sponsored
by Sanyo Times Ltd., publisher of TheSemiconductor Industry News, a weeklyjournal. The prize is awarded for productsor technologies developed using EDA/ESDA technology. The XC8100 FPGAfamily was awarded third place in a fieldof more than 110 entries.◆
Advanced PLD & FPGA ConferenceMay 15London, UK
Canadian Workshop on Field Pro-grammable Devices
May 20-21Toronto, Canada
Design Automation Conference (DAC)June 3-7Las Vegas, Nevada
IntertronicJune 4-7Paris, France
Look for Xilinx technical papers and/or product exhibits at these upcoming industryforums. For further information about any of these conferences, please contact KathleenPizzo (Tel: 408-879-5377 FAX: 408-879-4676).◆
UPCOMING EVENTS
International IC ConferenceMar. 27-29Shanghai, China
PCI ‘96Apr. 14-18San Jose, California
DigitronicsApr. 17-18Birmingham, UK
IEEE Symposium on FPGAs for CustomComputing Machines (FCCM)
Apr. 17-19Napa, California
Custom IC Conference (CICC)May 5-8San Diego, California
10
The Xilinx Alliance has been goingstrong for six years, and 1996 promises tobe the most exciting year ever. In addition
to bringing you more world-classtools for your world-class products,we will provide easier and innova-tive ways to find out about thewide variety of high-quality, third-party design tools available throughthe Alliance.
One example is WebLINX, theXilinx site on the World Wide Web.In March, the Xilinx Alliance will goon-line. An initial listing of ourAlliance partners will allow you to
easily search our web pages (and ourpartners’ pages) for product and contactinformation. The Xilinx SmartSearch andSmartSearch Agents utilities (see relatedarticle at right) will allow you to quicklyfind the information you need — whetherit be product functionality, updates, orcompatibility data.
As of February, the Xilinx Allianceincludes more than 80 partners who havebeen selected for their contribution toXilinx development systems and theirability to provide the widest variety andhighest qualiity of design/programming
tools for Xilinx programmable logic. Thesevendors offer well over 100 products, in-cluding schematic editors, logic synthesistools, simulators, third party cores, recon-figurable computing products and deviceprogrammers. (See Alliance ProgramEDA tool vendor and product list onpages 14-16.)
The breadth and depth of the XilinxAlliance is not accidental. Today’s program-mable logic users are required to completeever more complex and dense designsmore quickly than ever before. Xilinx hasrecognized those needs by adopting anopen systems approach to enable engineersto select the best tools for the task at hand.
So come visit Xilinx and our Alliancepartners on the World Wide Web. E-mailyour comments to [email protected] us about what products you are build-ing, what tools you are using and whattools you need — we will continue to offeryou the best programmable logic develop-ment solution anywhere. The Xilinx Alli-ance is dedicated to your success by bring-ing together complete developmentsolutions for your needs. With Xilinx pro-grammable logic and the Xilinx Alliance,the possibilities are limitless.◆
Xilinx Alliance Goes On-Line
Wallace Westfeldt is themanager of the Xilinx Alli-
ance Program. He can bereached by telephone at 303-
413-3280 or by E-mail [email protected].
Xilinx is adding new training courses and schedulingadditional locations in 1996! To get the latest information onavailable classes, use the Xilinx site on the World Wide Web(http//www.xilinx.com). From the home page, select CustomerSupport and then Training Classes. You can even register forclasses on-line.
Both schematic-based and synthesis-based three-day intro-ductory classes are offered. In January, Xilinx began offering aseries of one-day update classes on XACTstepTM v6, targeted atcustomers familiar with XACT® 5.0. Watch the web site for newtraining class support as new products are introduced.◆
Alliance ProgramVendors and ContactsSee pages 14-16
Alliance Program E-Mail:[email protected]
LatestTrainingInformationon the Web
11From WebLINX, the Xilinx site on the
World Wide Web, you can now search andmonitor the Web like never before.WebLINX SmartSearch is the most effectiveweb search engine for finding informationrelated to programmable logic. WebLINXSmartSearch Agents will proactively informyou when new Web information becomesavailable that meets your specific interests.
SmartSearch provides:• Selective Multi-site Indexing
WebLINX SmartSearch spans multiplesites, not just the Xilinx site. You get“one-stop” searching of leading industrymagazines such as EE Times and Elec-tronic News, all the major EDA compa-nies, and programmable logic-relatedorganizations, universities and distribu-tors. Unlike generic search engines,WebLINX SmartSearch yields betterresults by only searching known con-tent-rich sites.
For example, if you enter “PCI” inthe search engine Lycos, you get pageson Berkeley UNIX pci structs and thePCI home page for geographic manage-ment software. With WebLINXSmartSearch, you’ll get more pertinentresults like Synopsys’ PCI Design Kit,NuHorizons’ Technical Forum, the PCISIG Group, and more.
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SmartSearch and SmartSearchAgents are the first web informationretrieval tools of their kind inany industry. Check them out byvisiting our home page athttp://www.xilinx.com andselecting the Search button.◆
Intr oducing WebLINXSmartSearch
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PIN
S
TYPE
CO
DE
XC
3020
AX
C30
30A
XC
3042
AX
C30
64A
XC
3090
AX
C30
20L
XC
3030
LX
C30
42L
XC
3064
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XC
4036
EX
XC
4044
EX
XC
4052
EX
XC
4062
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XC
4085
EX
XC
4012
5EX
PLASTIC LCC PC44PLASTIC QFP PQ44PLASTIC VQFP VQ44CERAMIC LCC WC44PLASTIC DIP PD48PLASTIC VQFP VQ64PLASTIC LCC PC68CERAMIC LCC WC68CERAMIC PGA PG68PLASTIC LCC PC84CERAMIC LCC WC84CERAMIC PGA PG84CERAMIC QFP CQ100PLASTIC PQFP PQ100PLASTIC TQFP TQ100PLASTIC VQFP VQ100TOP BRZ. CQFP CB100CERAMIC PGA PG120PLASTIC PGA PP132CERAMIC PGA PG132PLASTIC TQFP TQ144CERAMIC PGA PG144CERAMIC PGA PG156PLASTIC PQFP PQ160CERAMIC QFP CQ164TOP BRZ. CQFP CB164PLASTIC PGA PP175CERAMIC PGA PG175PLASTIC TQFP TQ176CERAMIC PGA PG184CERAMIC PGA PG191TOP BRZ. CQFP CB196PLASTIC PQFP PQ208METAL MQFP MQ208HI-PERF QFP HQ208CERAMIC PGA PG223PLASTIC BGA BG225WINDOWED BGA WB225TOP BRZ. CQFP CB228PLASTIC PQFP PQ240METAL MQFP MQ240HI-PERF QFP HQ240CERAMIC PGA PG299HI-PERF. QFP HQ304PLASTIC BGA BG352CERAMIC PGA PG411PLASTIC BGA BG432CERAMIC PGA PG499PLASTIC BGA BG596
12
COMPONENT AVAILABILITY CHART
44
4864
68
84
100
120
132
144
156160
164
175
176184191196
208
223
225
228
240
299304352411432499596
◆ = Product currently shipping or planned ❖ = New since last issue of XCELL
◆ ◆
◆
◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆
◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆◆ ◆
◆ ◆ ◆
◆ ❖◆ ❖ ❖
◆ ◆ ❖
◆ ◆ ❖
❖❖ ❖❖ ❖ ❖
❖ ❖ ❖❖ ❖ ❖ ❖
◆ ◆
◆ ◆ ◆◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆◆ ◆
◆ ◆ ◆ ◆ ◆ ◆◆ ◆ ◆ ◆
◆ ◆ ◆ ◆◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆
◆ ◆ ◆◆ ◆ ◆◆ ◆ ◆◆ ◆ ◆ ◆
◆ ◆ ◆
◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆
13
FEBRUARY 1996
PLASTIC LCC PC44PLASTIC QFP PQ44PLASTIC VQFP VQ44CERAMIC LCC WC44PLASTIC DIP PD48PLASTIC VQFP VQ64PLASTIC LCC PC68CERAMIC LCC WC68CERAMIC PGA PG68PLASTIC LCC PC84CERAMIC LCC WC84CERAMIC PGA PG84CERAMIC QFP CQ100PLASTIC PQFP PQ100PLASTIC TQFP TQ100PLASTIC VQFP VQ100TOP BRZ. CQFP CB100CERAMIC PGA PG120PLASTIC PGA PP132CERAMIC PGA PG132PLASTIC TQFP TQ144CERAMIC PGA PG144CERAMIC PGA PG156PLASTIC PQFP PQ160CERAMIC QFP CQ164TOP BRZ. CQFP CB164PLASTIC PGA PP175CERAMIC PGA PG175PLASTIC TQFP TQ176CERAMIC PGA PG184CERAMIC PGA PG191TOP BRZ. CQFP CB196PLASTIC PQFP PQ208METAL MQFP MQ208HI-PERF QFP HQ208CERAMIC PGA PG223PLASTIC BGA BG225WINDOWED BGA WB225TOP BRZ. CQFP CB228PLASTIC PQFP PQ240METAL MQFP MQ240HI-PERF QFP HQ240CERAMIC PGA PG299HI-PERF. QFP HQ304PLASTIC BGA BG352CERAMIC PGA PG411PLASTIC BGA BG432CERAMIC PGA PG499PLASTIC BGA BG596
PIN
S
TYPE
CO
DE
XC
4005
LX
C40
10L
XC
4013
LX
C52
02X
C52
04X
C52
06X
C52
10X
C52
15X
C72
36A
XC
7272
AX
C73
18X
C73
36X
C73
36Q
XC
7354
XC
7372
XC
7310
8X
C73
144
XC
8100
XC
8101
XC
8103
XC
8106
XC
8109
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9510
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C95
216
XC
9536
44
4864
68
84
100
120
132
144
156160
164
175
176184191196
208
223
225
228
240
299304352411432499596
◆ ◆ ◆ ◆ ◆ ❖ ❖◆ ◆ ◆
◆◆ ◆ ◆ ◆ ❖
◆ ◆ ◆
◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ❖ ◆◆ ◆ ◆
◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆ ◆❖
◆ ◆ ◆ ◆◆
◆ ◆◆ ◆ ◆ ◆ ◆ ◆ ❖
◆
◆
◆ ◆ ❖ ◆ ◆ ◆ ❖
◆❖ ◆ ◆ ◆ ❖
◆
◆◆
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◆ ❖
❖ ◆
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16
ALLIANCE PROGRAM - PLATFORMS & CONTACTS - FEBRUARY 1996COMPANY NAME CONTACT NAME CONTACT (TELEPHONE OR E-MAIL) PC SUN RS6000 HP7
ACEO Technology, Inc. Ray Wei 510-656-2189 ✓ ✓ ✓ ✓
Acugen Software, Inc. Nancy Hudson ✓ ✓ ✓
Aldec David Rinehart ✓
Aptix Corporation Robert Sarkaisian 408-428-6209
Aster Ingenierie S.A. Christopher Lotz 339-953-7171 ✓ ✓ ✓
Cadence Itzhak Shapira Jr. 408-428-5793 ✓ ✓ ✓
Capilano Computing Chris Dewhurst 604-522-6200 ✓
Chronology Corporation Mike McClure [email protected]
CINA - Computer IntegratedNetwork Analysis Brad Ashmore [email protected] ✓
Compass Design Automation Terry Strickland 408-434-7493 ✓ ✓
Escalade Mark Miller 408-481-1300 ✓ ✓
Exemplar Logic Mary Murphy 510-337-3700 ✓ ✓
Flynn Systems Mike Jingozian 603-598-4444 ✓
Fujitsu LSI Masato Tsuru +81-4-4812-8043 ✓
Harmonix Corporation Shigeaki Hakusui 617-935-8335 ✓ ✓
IBM - EDA George Doerre 914-433-9086 ✓
IK Technology Co. Tsutomu Someyu +81-3-3839-0606 ✓ ✓ ✓
IKOS Systems Larry Melling 408-255-4567 ✓ ✓
INCASES Engineering Christian Kerscher +49-89-839910 ✓
ISDATA Ralph Remme +49-721-751087 ✓ ✓ ✓
ITS Frank Meunier 508-897-0028 ✓ ✓
Logic Modeling Marnie McCollow 503-531-2412 ✓ ✓ ✓ ✓
Logical Devices David Mot 303-279-6868 ✓
Mentor Graphics Sam Picken 503-685-1298 ✓ ✓ ✓
MINC Kevin Bush 719-590-1155 ✓ ✓ ✓
Minelec Marketing Department +32-02-4603175 ✓
OrCAD Troy Scott 503-671-9500 ✓
Protel Technology Matthew Schwaiger 408-243-8143 ✓
Quad Design Technology Britta Sullivan 805-988-8250 ✓ ✓ ✓ ✓
SimuCad Richard Jones 510-487-9700 ✓
Sophia Sys & Tech Bobby Alvarez 408-232-4764 ✓ ✓ ✓
Summit Design Corporation Ed Sinclari 503-643-9281 ✓ ✓ ✓ ✓
Synario Design Automation Jacquelin Taylor 206-867-6257 ✓
Synopsys Lynn Fiance 415-694-4289 ✓ ✓ ✓
Synplicity Alisa Yaffa 415-961-4962 ✓ ✓
Teradyne Mike Jew 617-422—3753 ✓ ✓
The Rockland Group Rocky Awalt 916-622-7935 ✓ ✓ ✓ ✓
TopDown Design Solutions Art Pisani 603-888-8811 ✓ ✓ ✓
Trans EDA Limited James Douglas +44-1703-255118 ✓ ✓
VEDA Design Automation Kathie O’Toole 408-496-4515 ✓ ✓
VeriBest Will Wong 415-961-9680 ✓ ✓ ✓
Viewlogic Preet Virk 508-480-0881 ✓ ✓ ✓ ✓
Visual Software Solutions Andy Bloom 305-423-8448
Zuken Makato Ikeda +81-4-5942-7787 ✓ ✓ ✓
Zycad Mike Hannig 201-989-2900 ✓ ✓
Inquiries about the Xilinx Alliance Program can be E-mailed to [email protected].
17
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18
PROGRAMMER SUPPORT FOR XILINX XC7200 EPLDS — FEBRUARY 1996
WHITE=changed since last issue
MANUFACTURER MODEL 7236 7236A 7272 7272AADVANTECH PC-UPROG V2.4 V2.4 V2.4 V2.4
LabTool-48 V1.0 V1.0 V1.0 V1.0ADVIN SYSTEMS Pilot-U40 10.77E 10.77E
Pilot-U84 10.77E 10.77E 10.77E 10.77EB&C MICROSYSTEMS INC. Proteus V3.6j V3.6j V3.7h V3.7hBP MICROSYSTEMS BP-1200 3.12 3.12 3.12 3.12
BP-2100 3.12 3.12 3.12 3.12DATA I/O UniSite 4.9 4.9 V4.5 V4.5
2900 4.9 4.93900 4.9 4.9 V2.3 V2.3AutoSite 4.9 4.9 V2.3 V2.3
DEUS EX MACHINA ENGINEERING XPGM V1.40 V1.40 V1.40 V1.40ELECTRONIC ENGINEERING ALLMAX/ALLMAX+ V2.1 V2.1 V2.1 V2.1TOOLS PROMAX V2.34 V2.34 V2.5 V2.5ELAN DIGITAL SYSTEMS 6000 APS K2.04 K2.04 K2.06 K2.06HI-LO SYSTEMS RESEARCH All-03A V3.01 V3.01 V3.00 V3.00
All-07 V3.01 V3.01 V3.00 V3.00ICE TECHNOLOGY LTD Micromaster 1000/E VX1.00 VX1.00 VX1.00 VX1.00
Speedmaster 1000/E VX1.00 VX1.00 VX1.00 VX1.00Micromaster LV VX1.00 VX1.00 VX1.00 VX1.00Speedmaster LV VX1.00 VX1.00 VX1.00 VX1.00
LEAP ELECTRONICS LEAPER-10LEAP-SU1LEAP-U1
LOGICAL DEVICES ALLPRO-88 2.2 V2.4 2.2 V2.4ALLPRO-88XR 1.35 V2.4 1.35 V2.4XPRO-1 3.3 3.3 1.01 1.01
MICROPROSS ROM9000MQP ELECTRONICS SYSTEM 2000
PINMASTER 48NEEDHAM’S ELECTRONICS EMP20 V2.92 V2.92 V2.92 V2.92STAG Eclipse V5.7.3 V5.7.3 V5.7.3 V5.7.3SMS Expert A1/94 A1/94 A1/94 A1/94
Optima A1/94 A1/94 A1/94 A1/94Multisyte A1/94 A1/94 A1/94 A1/94
SUNRISE ELECTRONICS T-10 UDP V3.31 V3.31 V3.31 V3.31T-10 ULC V3.31 V3.31 V3.31 V3.31
SUNSHINE ELECTRONICS POWER-100 V8.16 V8.16EXPRO-60/80 V8.16 V8.16
SYSTEM GENERAL TURPRO-1/FX V2.12 V2.12 V2.12 V2.12MULTI-APRO V1.13E V1.13E V1.13E V1.13E
TRIBAL MICROSYSTEMS TUP-300 V3.0 V3.0 V3.0 V3.0TUP-400 V3.0 V3.0 V3.0 V3.0FLEX-700 V3.0 V3.0 V3.0 V3.0
XELTEK SUPERPRO 1.7C 2.2 2.1 2.1SUPERPRO II 1.7C 2.2 2.1 2.1
XILINX HW-120 2.02 2.02 2.02 2.02HW-130 1.14 1.14 1.04 1.04
19
PROGRAMMER SUPPORT FOR XILINX XC7300 EPLDS — FEBRUARY 1996
WHITE=changed since last issue
MANUFACTURER MODEL 7318 7336 7336Q 7354 7372 73108 73144ADVANTECH PC-UPROG V2.4 V2.6 V2.6 V2.4 NS NS
LABTOOL-48 V1.0 V2.6 V1.2 V1.0 V1.04 V1.04ADVIN SYSTEMS PILOT-U40 10.78N 10.78N 10.8 10.78N
PILOT-U84 10.78B 10.78B 10.8 10.78B 10.78B 10.79B&C MICROSYSTEMS Proteus 3.7k 3.7k 3.7k 3.71 3.7kBP MICROSYSTEMS BP-1200 V3.12 V3.12 V3.12 V3.12 V3.12 V3.13
BP-2100 V3.12 V3.12 V3.12 V3.12 V3.12 V3.13DATA I/O 2900 4.9 4.9 4.9 4.9
3900/AutoSite 4.9 4.9 4.9 4.9 4.9 4.9UniSite 4.9 4.9 4.9 4.9 4.9 4.9
DEUS EX MACHINA XPGM V1.40 V1.40 V1.40 V1.40 V1.40 V1.40ELECTRONIC ENGIN- ALLMAX/ALLMAX+ V2.1 V2.1 V2.1 V2.1EERING TOOLS PROMAX V2.34 V2.34 V2.88 V2.34 V2.57ELAN 6000 APS k2.13 k2.13 k2.13 k2.13 k2.13HI-LO SYSTEMS RESEARCH All-03A V3.04 V3.04 V3.08 V3.04 V3.05 V3.01
All-07 V3.02 V3.02 V3.08 V3.02 V3.01 V3.00ICE TECHNOLOGY LTD Micromaster 1000/E VX1.00 VX1.00 VX1.00 VX1.00 VX1.00
Speedmaster 1000/E VX1.00 VX1.00 VX1.00 VX1.00 VX1.00Micromaster LV VX1.00 VX1.00 V1.2 VX1.00 VX1.00 VX1.00Speedmaster LV VX1.00 VX1.00 V1.2 VX1.00 VX1.00 VX1.00
LOGICAL DEVICES ALLPRO-88 V2.5 V2.5 V2.5 V2.5 V2.5ALLPRO-88XR V2.5 V2.5 V2.5 V2.5 V2.5XPRO-1 3.3 3.3 1.01 1.01 1.01
MICROPROSS ROM9000MQP ELECTRONICS SYSTEM 2000
PINMASTER 48NEEDHAM’S ELECTRONICS EMP20 V2.92 V2.92 V2.92 V2.92 V2.92 V2.92SMS EXPERT C/94 C/94 C/94
OPTIMA C/94 C/94 C/94STAG ECLIPSE V4.10.31 V4.10.31 5.8.24 V4.10.31 V4.10.31 V4.10.31SUNRISE T-10 UDP V3.31 V3.31 V3.31 V3.31 V3.31
T-10 ULC V3.31 V3.31 V3.31 V3.31 V3.31SUNSHINE POWER-100 V8.18 V8.18 V8.18 V8.18 V8.18 V8.18
EXPRO-60/80SYSTEM GENERAL TURPRO-1/FX V2.2 V2.2 V2.22I V2.2 V2.2 V2.2
MULTI-APRO 1.13E 1.13E 1.13E 1.13E 1.13E 1.13ETRIBAL MICROSYSTEMS Flex-700 V3.02 V3.02 V3.08 V3.02 V3.01 V3.00
TUP-300 V3.03 V3.03 V3.08 V3.03 V3.03TUP-400 V3.03 V3.03 V3.08 V3.03 V3.03
XELTEK SUPERPRO 2.1 2.2A 2.1 2.2BSUPERPRO II 2.1 2.2A 2.1 2.2B
XILINX HW-120 3.13 3.13 1.00 3.00 1.01 3.01HW-130 1.15 1.15 1.06 1.16 1.05 1.07 1.02
20
XILINX INDIVIDUAL PRODUCTS XILINX PACKAGES
XIL
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3RD PARTY PRODUCTIONSOFTWARE VERSIONS
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PRODUCT INFORMATION — COMPONENTS
Introducingthe
The XC4000 series, including theoriginal XC4000, the XC4000E and nowthe XC4000EX family, is the ideal solutionfor high-density, high-performance FPGAneeds. First introduced in 1991, theXC4000 series has become the world’smost-popular FPGA family; in fact, if itwere a free-standing entity, the XC4000series would be the third largest program-mable logic company in the world.
The new XC4000EX family extends thedensity and performance leadership of theXC4000 series to new levels. With devicesup to 125,000 usable gates, the XC4000series density range will overlap with themajority of gate array design starts. Inaddition to increased density, theXC4000EX family features architecturalimprovements that increase design ease,utilization and performance.
125,000GATESXC4000EX FPGA FamilyXilinx Builds on the XC4000 Series to ExtendFPGAs up to a Quarter of a Million Gates.
The XC4000EX familyThe XC4000EX family will include
seven members ranging from 28,000 to125,000 logic gates. In a typical systemapplication using on-chipmemory, the maximum den-sity rises to 250,000 gates (seetable 1). These devices areavailable in a variety of pack-ages that are footprint com-patible with the other mem-bers of the XC4000EX andXC4000E families. TheXC4028EX is available now.The XC4036EX will be avail-able in the first half of thisyear, with the XC4044EX, XC4052EX andXC4062EX following in the second half.The two largest devices, the XC4085 andXC40125, will be offered in 1997.
Table 1 - The XC4000EX family4028EX 4036EX 4044EX 4052EX 4062EX 4085EX 40125EX
Typical Logic Gates 28,000 36,000 44,000 52,000 62,000 85,000 125,000Typical System Gates* 56K 72K 90K 110K 130K 175K 250K(Logic + Select-RAM)Available RAM bits 32,768 41,472 51,200 61,952 73,728 100,352 157,968
CLB Array 32x32 36x36 40x40 44x44 48x48 56x56 68x68CLBs 1,024 1,296 1,600 1,936 2,304 3,136 4,624
Flip-Flops 2,560 3,168 3,840 4,576 5,376 7,168 10,336I /O 256 288 320 352 384 448 544
Packages: HQ208HQ240PG299HQ304 HQ304BG352
BG432 BG432 BG432PG411 PG411 PG411 PG499 PG499
BG596 BG596 BG596 BG596
100% FootprintCompatible
Continued on thenext page
*30% of CLBsas RAM
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22
The XC4000E family is manufactured ona 0.6 micron (drawn) triple layer metal(TLM) process. The XC4000EX FPGAs arebased on an advanced 0.5µ (drawn) TLMprocess. This new process enables bothincreased density and increased perfor-mance. The two primary determinants ofsilicon speed are feature size and intercon-nect delay. The 0.5µ gate length speedstransistor performance, while the siliconsize decrease resulting from the smallergeometry dramatically reduces the size ofthe die, which, in turn, reduces intercon-nection delays.
The 0.5µ technology used for theXC4000EX devices will be replaced by amore advanced 0.35µ quad layer metaltechnology, planned for early 1997. Thisnew technology will allow the manufactureof the two largest members of theXC4000EX family — the XC4085EX andXC40125EX. In addition, all family mem-bers will be redesigned in 1997 to leveragethe 0.35µ technology, resulting in costreductions and speed improvements.
Additional Routing ResourcesProgrammable logic is successful be-
cause it allows designers to achieve a fastertime-to-volume than conventional ap-proaches. For high density FPGA designs,device routability is a key factor; better
routability enables faster design compila-tion times and boosts silicon utilization. Asdevice densities increase, both the numberof interconnections and the average lengthof interconnections increase. In order toeffectively route designs of more than100,000 gates, breakthroughs in intercon-nect topology were necessary.
The XC4000EX family features an en-hanced interconnect scheme. As shown inFigure 1, the number of interconnectresources has increased substantially com-pared to the XC4000E and XC4000 architec-tures. Twelve “quad lines” are added bothhorizontally and vertically. The quad linesare interconnected by a buffered switchmatrix that is spaced every four CLBs. Eachbuffered switch matrix contains both buff-ers and pass transistors. The place androute software will use the timing require-ments of the design to determine whetherit is optimal to use a buffer or pass transis-tor for each interconnect switch. Becauseof the buffered switch matrices, quad linesprovide the fastest means for routingheavily loaded signals over long distances.
In addition to the quad lines, the num-ber of vertical long lines has increasedfrom six to 10. Buffered programmablesplitters are added to these long lines atpositions 1/4, 1/2 and 3/4 of the wayacross the chip. Due to the buffering,XC4000EX long line performance does notdeteriorate with larger array sizes. If a longline is split, the resulting partial long linesare independent. The number of globallines also was doubled from four to eight,as described below.
The XC4000EX architecture also offersdirect connects that allow efficient and fastconnections between adjacent CLBs. Thesenets allow high-speed data flow from CLBto CLB. Signals routed on the direct con-nects exhibit minimum interconnect propa-gation delay and use no general routingresources. Direct connects are ideal forcreating sophisticated, high-speed macros.
The XC4000EX devices have additionalVersaRingTM routing around the perimeter
XC4000EXContinued from previous page
Figure 1 - XC4000EX Interconnect
23
of the CLB array. The VersaRing feature,first introduced with the XC5000 series,facilitates pin-swapping and redesign with-out affecting board layout. It avoids thetrade-off of high utilization versus pinassignment flexibility by allowing both.
Global Nets and BuffersGlobal nets and buffers are the primary
mechanism for distributing clocks and otherhigh fanout control signals throughout adevice. The buffers accept signals that aregenerated on-chip or externally and drivethem onto the global nets. The XC4000EXdevice has three types of global buffers.
• Global Low-Skew Buffers - similar tothose found on the XC4000, XC4000Eand many other devices. The buffers aredesigned to deliver a low-skew clocksignal to the entire chip, and are usedfor most internal clocking. They must beused when a single clock needs to drivethe entire chip. Each XC4000EX devicecontains eight Global Low-Skew Buffers.
• Global Early Buffers - pro-vide faster clock access thanGlobal Low-Skew Buffers, buthave a limited distributioncapability. Each buffer can onlysupply a clock signal to 1/4 ofthe CLBs and 1/4 or 3/8 of theIOBs. Each XC4000EX devicecontains eight Global EarlyBuffers.
• FastCLKTM Buffers - specifically de-signed to provide the fastest possibleI/O clocks. The only access they have toCLBs is through local interconnect.Using the FastCLK buffers enables near100 MHz chip-to-chip communication.Each XC4000EX device contains fourFastCLK Buffers.
Figure 2 shows the portion of a devicethat can be driven in a typical applicationby the three buffer types. Global Low-Skew and Global Early Buffers can drive
any of eight vertical long lines in eachcolumn. These long lines are separatefrom the vertical long lines used forstandard interconnect.
Development System SupportSoftware is the key enabling technology
for maximizing the power, flexibility, andperformance capabilities of the XC4000EX.Xilinx and its Alliance Partners are fully-prepared to support the XC4000EX with theindustry’s most powerful and versatile suiteof design tools. Support for HDL-based,ASIC-like design methodologies is a key partof this strategy.
The recent merger of Xilinx andNeoCad provided a unique opportunity tocombine the best software elements fromthe two companies. The merger tookplace during the development of theXC4000EX. A software tool, the FPGAArchitect, developed by NeoCad, wasused to evaluate design trade-offs and
maximize the ultimate performance androutability of the devices.
In summary, the new XC4000EX familyextends the capacity, performance andsystem-integration capabilities of thepopular XC4000 FPGA series to unprec-edented levels. Both advanced processingtechnology and architectural enhance-ments have contributed to these dramaticimprovements. The XC4000EX FPGA isthe ideal logic device for high-density,high-performance applications.◆
Figure 2 - XC4000EX Clockingoptions (shaded area indicatesreach of a typical single buffer)
24
LowVoltage
ProductLine
Expands
Xilinx Announces First 3 V PCI and CardBus Compliant Devicesarchitecturally and functionally identical to theXC3100A family. Family members include theXC3142L and XC3190L. The -2 speed grade of theXC3100L is the first 3 V PCI and CardBus compliantprogrammable logic device. The XC3100L family istargeted towards speed-sensitive, low-voltage applica-tions such as PC-Card modems and video peripherals.
The XC4000L family offers the broadest densityrange of any 3 V FPGA product family, ranging from5,000 gates to an industry-leading 13,000 gates. Fam-ily members include the XC4005L, XC4010L andXC4013L devices. The XC4000L FPGAs have all the
XC9500 CPLDs are the first in-systemprogrammable (ISP) devices based on 5 Vflash technology. The XC9500 architecturalfeatures enhance ISP by permitting designchanges without altering pin assignments.
The powerfulXC9500 archi-tecture supportsa wide varietyof design meth-odologies. Eachfunction blockand macrocell isidentical. Thisassists the de-signer whenusing HDLs,synthesis and/orschematic cap-ture tools by
allowing the software to fit and route thedesign quickly and efficiently.
The XC9500 family allows easy migra-tion across multiple density options in agiven package footprint. Designs initiallytargeted at a small part can be migratedinto a larger part. This capability helpsdesigns maintain their pin assignments ifadditional logic capacity is needed in a
socket already committed to a printed circuitboard.
The design software also incorporates anumber of strategies permitting future editswithout altering pinouts. The XC9500 Applica-tion Guide outlines many of these architecturalfeatures and software strategies.
MacrocellsUnderstanding the macrocell and intercon-
nect capability is key to designing with XC9500CPLDs. Detailed knowledge is not required,but general facts are helpful.
The XC9500 macrocell performs most logicfunctions at the bit level in a single macrocell.Counters, shifters, multiplexers and decodersrequire a single macrocell to perform one bit ofcorresponding function. Adding and subtract-ing functions generally require two macrocellsper bit. Parity can be calculated over four bitsin one macrocell. The design software auto-matically implements appropriate mapping andoptimization.
Product terms are automatically distributedamong macrocells. Any macrocell easily re-ceives up to 15 product terms with additionalproduct terms delivered from local neighboringmacrocells. There are few logic functions need-ing more than 25 product terms. However, upto 90 product terms can be assigned to a
Xilinx has significantly expanded itsproduct offerings for 3.3 V systems withthe introduction of the XC3100L andXC4000L FPGA families. These new prod-uct offerings include more than 30 combi-nations of device, speed, and package,tripling the size of the Xilinx 3 V FPGAproduct line. Engineering samples areavailable now, with full production sched-uled for the second quarter of this year.
XC3100L FPGAs, the highest-perfor-mance 3 V FPGAs available today, are
Designing with XC9500 CPLDs – First In-System
25
architectural features of the XC4000E family, includ-ing Select-RAMTM memory.
These low-voltage FPGA products are bitstreamcompatible with their 5 V counterparts; designers canuse the current XACTstep v6 and XACT 5.2 develop-ment systems to design with these new devices.
While in the past 3 V designs have been limitedmostly to laptop computer and cellular telephoneapplications, there now is a significant increase indesign activity in the mainstream telecommunica-tions, data communications and instrumentationmarkets The expansion of the 3 V FPGA product line
addresses this growing market. Please contact your local Xilinx represen-tative for the latest availability information.◆
SPEED ENG. LIMITED VOLUME PACKAGE
DEVICE GRADES SAMPLES PRODUCTION PRODUCTION AVAILABILITY
XC3142L -2/-3 Now March 2Q 96 PC84, VQ100, TQ144
XC3190L -2/-3 Now March 2Q 96 PC84, TQ144, TQ176
XC4005L -5/-6 Now March 2Q 96 PC84, PQ208
XC4010L -5/-6 Now March 2Q 96 PC84, TQ176, PQ208
XC4013L -5/-6 Now March 2Q 96 PQ208, PQ240, BG225
m Programmable Devices Based on 5-V Flash Technologymacrocell within a particular function block.The XACTstepTM design software handles thedetails of product term assignment.
In-System ProgrammingXC9500 devices are programmed in-system
via an IEEE 1149.1 standard 4-pin JTAG proto-col. Multiple XC9500 CPLDs as well as otherJTAG-compatible devices (such as XC4000Eand XC5200 FPGAs) can be linked together inthe same JTAG chain. In-system programmingoffers quick and efficient design iterations andeliminates package handling. Once designs arecompiled, their configuration patterns aredownloaded automatically using the EZTAGdownload software. Users need only providethe JTAG chain ordering sequence to thesoftware that targets the specific CPLD beingprogrammed.
All XC9500 CPLDs are in-system program-mable for at least 10,000 program/erase cycles.In addition, the JTAG downloading and pro-gramming circuitry is the most comprehensiveand advanced available today. Each XC9500device supports EXTEST, SAMPLE/PRELOAD,BYPASS, USERCODE, INTEST, IDCODE, andHIGHZ instructions. All in-system program-ming, erase and verify instructions fully com-ply with extensions of the IEEE 1149.1 bound-ary-scan.
The XC9500 family supports mixedvoltage systems combining both 3.3 V and5 V components. XC9500 CPLDs can imple-ment both logic and level shifting functionsin a single programmable device. Thiseliminates the need for discrete level trans-lation buffers.
The XC9500 family also includes UserProgrammable Ground for internalsignal management. User Program-mable Ground allows the device I/Opins to be configured as additionalground pins. Tying programmableground pins to the external groundconnection reduces system noise.
Superior PerformanceThese additional features enhance
the overall electrical capabilities ofthis new family, relieving designers of manycritical signal management responsibilities.
In summary, the XC9500 family offers asuperior high-performance, general-purposelogic integration solution. The powerfulCPLD architecture expands in-system pro-gramming capabilities with the industry’smost comprehensive JTAG support. Thearchitecture also permits design changeswithout altering pin assignments.◆
❝The XC9500family offers a superior
high-performance,general-purpose logicintegration solution.❞
26
XC5200 Family on Record PaceXC5200 FPGA family revenue for the
third fiscal quarter (ended December 30,1995) increased by more than 150% fromthe previous quarter — the fastest rampup of any new product in Xilinx history.The XC5200 family already is being usedin hundreds of high-volume applications,including communications, data process-ing, networking and industrial systems.
The XC5200 family’s unprecedentedsuccess results from a cost-optimized
design that takes full advantage of a0.6µ three-layer-metal SRAM processtechnology and architectural innova-tions such as the VersaRingTM I/O inter-face. The XC5200 family includes fivemembers, ranging from 2,000 to 18,000usable gates. The devices are offered in15 different packages, with more than100 different device/package/speedcombinations.◆
The XC4000E family has entered full-volume production. Xilinx is now ableto satisfy the rapidly growing demand forthe industry’s highest-performance, full-featured FPGA.
Production volumes of the -5, -4, and -3speed grades are available, and samplinghas begun for the fastest speed grade, the-2. The new -2 speed grade propels theXC4000E to a higher than 60 MHz typicalsystem speed and, like the -3 speed grade,is fully PCI compliant.
The XC4000E software began shippingin January. This XACT-DevelopmentTM
software update provides access to all theadvanced features of the XC4000E archi-tecture, including the Select-RAMTM
memory and the I/O clock enables. It willbe shipped free of charge to current in-warranty customers upon request. Contactyour local Xilinx sale representative or callCustomer Service at 408-559-7778.
XC4000E users can take full advantageof this advanced FPGA architecture toaccelerate their time-to-market through theuse of the new Xilinx LogiCoreTM modules.The inaugural LogiCore module is a fullyverified PCI interface based on theXC4000E architecture. (See page 27.)◆
XC4000E in Volume ProductionNew -2 Speed Grades Sampling! Software Shipping Today!
Would you like to see your namein print? Would you like to win a Xilinx XC4000E
t-shirt and either a CD-ROM drive with the lastest XilinxDevelopment Software Package, a multimedia board(and speakers) for your PC, or one of several otherprizes? Xilinx is looking for the five most innovativeXC4000E-based DSP designs using XC4000E/XC4000EXSelect-RAMTM memory. Xilinx will judge all entries re-ceived by May 30. The winning design ideas will befeatured in the 3Q96 edition of XCELL. So what’s the
catch? You must be willing to allow Xilinx toprint and share your design
idea with other designers, and promiseto wear your Xilinx t-shirt with pride.
If you need some ideas to get started, check outour DSP application notes on our World Wide Web site(http:/www.xilinx.com).
Send your schematic drawings, a diskette with yourXC4000E/EX design files, and any other relevant docu-mentation to: Xilinx DSP Designer Challenge, XilinxProduct Marketing, 2100 Logic Drive, San Jose, CA 95124 USAFor more information, email inquiries [email protected] or fax them to 408-879-4442,ATTN: DSP Design Challenge.◆
DSPApplication
DesignContest!
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27
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PRODUCT INFORMATION — DEVELOPMENT SYSTEMS
See LOGICORE, page 32
To date, integrating a PCI interfaceinto an FPGA or ASIC device has been adifficult challenge, often requiring monthsto learn the PCI specification and to opti-mize and verify the design. With LogiCoremodules, Xilinx is doing the tough workfor you (now for PCI, to be followed soonby several other applications).
The LogiCore program supplies pre-implemented “drop-in modules” for XilinxFPGA designs. As a result, users can slashdevelopment time, reduce design risk, andobtain optimal performance for their FPGAdesigns. Since LogiCore modules have pre-defined implementations and are alreadyfully-verified, designers can focus theirtime and energy on their unique systemfunctions.
The first LogiCore module is a fully-compliant, 32-bit PCI interface for theXC4000E FPGA family. It has pre-defined mapping, relative placementand timing specifications. Jointly developedby Xilinx and HighGate Design, the mod-ule has been verified using the PCI-compli-ant test bench from Virtual Chips. This testbench is approved by the PCI SpecialInterest Group (PCISIG) and simulates allpossible signaling on a PCI bus. Further-more, 30 designers have beta tested themodule, and 17 PCI board designs havebeen completed using the beta version.
“We chose Xilinx modules becausethey’re fully verified,” noted Brian Warren,senior design engineer at Delco Electron-ics. “The module we used worked the firsttime, saved us more than six months indevelopment time, and allowed us to focusour resources on our system design.” War-ren, one of the beta-site users of the mod-ule, has designed a Digital Audio Broadcast(DAB) transceiver that includes a RISC
processor and Xilinx XC6200 and XC4013FPGA devices.
As shown in the diagram, the LogiCorePCI module is partitioned into five majorblocks. In addition to the PCI interface,configuration and control logic, the mod-ule includes a FIFO buffer and a simple,general-purpose interface to the user’sback-end logic. The FIFO buffer uses theSelect-RAMTM memory feature of theXC4000E to support burst transfers at themaximum bus speed. The schematic-based module can be easily customized tomeet the user’s needs. When implementedin an XC4013E FPGA, more than 7,000
programmable gates remain free for inte-gration of the unique, back-end functionsof the application. This is a high-perfor-mance, one-chip solution.
The LogiCore PCI interface is availablewith target functionality today, and will beupdated with full initiator/target function-ality in March. (Contact your local Xilinxrepresentative for ordering information.)
Coming AttractionsThe LogiCore PCI interface is just the
first of a planned series of vertical solu-
LogiCore PCI moduleblock diagram
PCI Interface is First New
LogiCoreTM
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28
XC8100 Family Adds Schematic SupportProduction version 1.1 of XACTstep
Series 8000 is now available. This releaseadds support for the PC platform andthe use of Viewlogic’s ProCapture andMentor’s Design Architect schematiceditors for XC8100 FPGA design.
As a result, schematic-based de-signs can now access the advancedfeatures of the XC8100 FPGA family:• Extremely high design security• Near 100% utilization regardless of
logic type
XABEL-CPLD Software Available NOW!
• Abundant routing resources• Internal 3-state buffers• Pin-locking tolerance• Footprint compatibility with XC4000
and XC5200 FPGAs
XABEL-CPLD software is availablenow for immediate ordering and delivery!
XABEL-CPLD is the new Xilinx devel-opment system designed for PAL andCPLD users. With this completely self-contained system, PC-based customers canquickly and easily integrate their logic intoXilinx CPLDs using the industry-standardABEL hardware description language.
This new design software combines thewell-known, windows-based Data I/OABEL6 front-end with the new XilinxXACTstepTM v6 core software; the result isan extremely easy-to-use, industry-stan-dard user interface capable of targetingXilinx CPLDs.
Designed for the PC and priced at only$495, XABEL-CPLD is the perfect softwaresolution for users familiar with ABEL,PALASM, CUPL and MACHXL who designwith PALs and CPLDs.
Features• Familiar Data I/O ABEL, Windows-
based environment for design entry,simulation and fitting.
• Industry-standard ABEL-HDL supportsstate machines, high level logicdescriptions, truth tables andequation entry.
• Hierarchical design entry and JEDECfile conversion for integration ofexisting PALs into Xilinx CPLDs.
• Functional simulation with graphicalwaveform viewer and static timingreports
• Advanced XACTstep v6 fitter with fullyautomatic device selection, multiplepass optimization, partitioning andmapping, and timing-driven fitting.
• On-line tutorial and on-line helpreduces learning curve.◆
XABEL-CPLD Evaluation CD-ROM AvailableThe XABEL-CPLD software offers a truly accurate method for evaluatingthe performance, power, board real estate and cost savings gained byintegrating multiple PALs into a single Xilinx XC7000 CPLD device. Simplyenter the design and the evaluation software does the rest.
To obtain an evaluation CD, contact your local Xilinx salesrepresentative or distributor. You also can request a CD fromthe Xilinx WebLINX web page (www.xilinx.com).◆
29
New XC7000 Core Software in XACTstep v6tor Graphics, Exemplar and Synopsys. When com-bined with the appropriate library and interfacesoftware, XACTstep v6 provides a complete envi-ronment for the processing of Xilinx XC7000 CPLDdesigns
ABEL-HDL EntryXABEL owners can continue to embed macros
in their schematics or enter complete chip designsfor the XC7000 family and use XACTstep v6 tocomplete the design implementation. This coresoftware is included in the new Xilinx XABEL-CPLD package, a complete ABEL-HDL based tooldesigned specifically for PAL users who want touse Xilinx XC7000 CPLDs.
Embedded Third Party CompilersXilinx licenses its fitter technology to third-party
development tool vendors, giving you the flexibil-ity and versatility of industry-standard design soft-ware environments with the speed, density androutability of Xilinx CPLDs. The Xilinx CPLD fitteris fully integrated into the Data-I/O Synario, LogicalDevices CUPL and IsDATA LOGiC environments.For price and availability of the XACTstep v6 basedfitter, contact the development tool manufacturer.
Product Availability and PricingThe XC7000 XACTstep v6 core software is avail-
able on the PC for immediate delivery. The XACT5.2 core software is available for workstationplatforms. ◆
Part Number Version Platform Pricing AvailDS-550-PC1-C 6.0 PC $89.95 NowDS-550-SN2-C 5.2 Sun $995 NowDS-550-HP7-C 5.2 HP $995 Now
The table summarizes the sup-ported CAE interfaces. Many otherthird-party CAE vendors are work-ing on XC8100 solutions that willbe released in the first half of 1996.
Now Runs on PC — Version1.1 adds PC support (DS-8000-STD-PC1-C or DS-8000-EXT-PC1-C). It
runs under Windows 3.1,Windows 95 and WindowsNT. The CAE interfaces avail-able on the PC includeViewlogic and Exemplar.Workstation versions are avail-able for SunOS, Solaris, HPPA,and RS6000 platforms.◆
The Xilinx XC7000 core software delivered inXACTstep v6 contains new features and enhance-ments of existing features that address user pro-ductivity and design performance for Xilinx CPLDdesigns.
Productivity ImprovementsAutomatic Device Selection - The software auto-matically implements the design in the smallestdevice possible using device type, package typeand speed constraints entered by the designer
XACT-PerformanceTM - Timing-driven optimiza-tion collapses logic to meet user-specified criticaltiming requirements.
Static Timing Analyzer - Provides a completepin-to-pin timing report of the design, includingdetailed internal path analysis
Performance ImprovementsNew Design Optimization Algorithms - Newdesign optimization and partitioning algorithmsbetter utilize the XC7300 architecture without userintervention. Designs fit in smaller devices, takeabout 10% fewer macrocells and run about 10%faster than before.
Multiple-Pass Optimization, Partitioning andMapping - The software will try a different optimi-zation and partitioning strategy if necessary toachieve a first-time fit, without user intervention.
Schematic and VHDL Design EntryXilinx provides an open design environment
that allows designers to choose from a variety ofschematic entry, VHDL synthesizer and simulationtools, such as those from OrCAD, Viewlogic, Men-
CAE Tools Supporting XC8100 FPGA Design
Schematic Synthesis Simulation Timing Analysis
Viewlogic ProCapture Synopsys Design Compiler Synopsys VSS SynopsysMentor Design Architect Synopsys FPGA Compiler Cadence Verilog Motive
Viewlogic ViewSynthesis Viewlogic ViewSim Mentor QuickPathMentor Autologic I, II Mentor QuickSim Cadence VeritimeExemplar Mentor QuickVHDL
Model TechVITAL VHDL
30
Incremental design support (also known as “re-entrant design”) is a key feature oftoday’s FPGA implementation tools. Often, minor changes are required near the end of adesign cycle to fix last-minute bugs or respond to a change in specifications. The designof large, complex systems can be simplified by first implementing a small portion of the
design and then iteratively adding othermodules to it. Both these situations re-quire tools that support incrementaldesign techniques.
Incremental design techniques involveusing a previous implementation of adesign as a guide to the placement androuting of a new version of that design.Where the two designs match, the newer
design mimics the old one exactly, preserving its placement and routing, and, therefore,its timing characteristics. For example, suppose a large design has been successfullyimplemented and tested. A small change is then required. By using the “guide” option, themajority of the placement and routing will remain unchanged, so only the relatively small,altered portion of the design needs to be re-implemented and re-tested. With this tech-nique, minor changes can be implemented and verified in a matter of a few minutes. Thiscapability has been a valued feature of the XACTstep tools supporting the Xilinx FPGAfamilies.
The XACTstep Series 8000 development system for the XC8100 FPGA family furtheradvances the state-of-the-art for incremental design support. Conventional FPGA guidedplacement and routing algorithms match cells and nets using the cell instance and netnames. This approach breaks down when used with logic synthesis tools, as synthesistools assign instance and net names arbitrarily during the synthesis process. A smallchange in a design’s source code can result in different symbolic names for the majority ofcells and nets in the final design netlist. XACTstep Series 8000 PowerGuide feature is thefirst and only FPGA guide option that enables incremental and iterative design for HDL-based designs. PowerGuide accomplishes this by using a nameless correlation algorithm.
Instead of using instance and net names, PowerGuide uses the design’s topology toperform guide matching. Compare the two circuits above (Circuit A and Circuit B). Aconventional guide algorithm does not match any cells or nets between the two circuits,
since the instance and net names are different between the twocircuits. The PowerGuide algorithm matches all cells and netsbetween the two circuits, since the two circuits have identicaltopology.
For example, suppose a 3,000 gate VHDL design is synthe-sized with the Synopsys FPGA Compiler. All synthesis options areset to their default values. An area constraint of zero is applied tothe design. (This constraint produces minimum area in Synopsys.)A portion of the VHDL gate-level netlist is shown at the top ofthe next page, and the circuit is diagrammed in Figure 1, left.
Circuit BCircuit A
Figure 1
PowerGuide: Innovative Approachto Incremental Designfor the XC8100 Family
TM
31
U3053: BUFGP port map( O => n10123, I => OSC);
byteptr_reg: FDC port map( Q => byteptr, D => n10802, C =>n10123, CLR => n9602);
U3571 : M2_1B1B port map( O => n10802, D1 => byteptr, D0 =>n10651, S0 => n10251);
The VHDL design is then modified to add an inverter to aninput port named DACK7_N. The port is renamed DACK7 to showthe change in signal sense from active low to active high. Thismodified VHDL design is also synthesized with Synopsys FPGACompiler. The same options and constraints are used with thismodified design as was used with the original design. A portion ofthe new VHDL netlist is shown below; this netlist shows the samegates and nets as the previous code, but changes in the synthe-sized code are highlighted. The circuit is shown in Figure 2.
U3055: BUFGP port map( O => n10127 , I => OSC);
byteptr_reg: FDC port map( Q => byteptr, D => n10806 ,C => n10127 , CLR => n9606);
U3573: M2_1B1B port map( O => n10806 , D1 => byteptr,D0 => n10655 , S0 => n10255 );
The instance names for all combinational cells have changed from the guide netlistto the modified netlist. The names of all nets except the flip-flop output nets have alsochanged. If the guide algorithm relied on instance names and net names to match thesecells, then the guide algorithm would not match any of these cells.
Shown below is the PowerGuide correlation report for this modified design. Thisreport is generated when the guide design is read into the Series 8000 software. (Toread a guide design into XACT8000, select “Guide” from the Place/Route menu.)
Reading guide design from file “guide.xb”Comparing net-lists ...
: Nets CLCs Pads Misc----------------------------------------------------------------design : 861 1029 70 0guide : 861 1029 70 0----------------------------------------------------------------correlation : 861(100%) 1026(99%) 70(100%) 0
In the report above, all but three CLCs match. These three CLCs comprise a two-inputmultiplexer cell (1 CLC) and a six-input sum-of-products cell (2 CLCs). The inverter thatwas added to the DACK7 input pin in the modified VHDL source file is optimized to abubble on an input pin on both the multiplexer and the sum-of-products. All nets arecorrelated between the guide design and the modified design. All I/O pads are alsomatched between the guide design and the modified design, including the input pinwith the changed name (DACK7). Again, this result is obtained because the PowerGuidefeature does not use instance or net names for the guide matching.
In summary, Series 8000 PowerGuide uses the topology of the design to matchinstances and cells, enabling users to fully utilize incremental and iterative designmethodologies for HDL-based designs. The PowerGuide feature allows the user to makedesign changes without having to re-verify timing on the entire design, as well as provid-ing fast place and route times on successive iterations — features previously availableonly to schematic designers.◆
PowerGuideContinued from theprevious page
Figure 2
32
tions from Xilinx. Several LogiCore systemmodules are in development, including anISA bus plug and play interface, DSPbuilding blocks, and ATM modules. Inaddition to these high-complexity systemmodules, a collection of medium-sized,industry-standard building blocks will beavailable in the LogiCore base library.When released this spring, this library willinclude functions such as DMA controllers,UARTs, multipliers and FIFOs. All themodules are pre-defined, drop-in solutionsthat maximize utilization and performance,and accelerate time-to-market.
LogiCoreContinued from page 27
Along with the LogiCore productscreated and distributed by Xilinx, we willwork with third-party intellectual propertyproviders. In order to grow the number ofavailable modules rapidly, Xilinx has initi-ated the LogiCore Partners Program.This program will access existing industryexpertise to encourage the creation of awide range of high-quality FPGA buildingblocks from third-party vendors. Xilinxwill work closely with the LogiCore part-ners to verify the quality of LogiCoremodules. The table below lists the intialmembers of the program.
Xilinx is the first FPGA vendor to pro-vide pre-designed, fully-verified drop-inmodules. By allowing you to focus yourtime and effort on your system design,these modules can help you save monthsin development time for your high-perfor-mance, high-density systems.
For further information about theLogiCore PCI interface or other modulesin the program, please contact your localXilinx representative or visit the LogiCoresection of WebLINX, Xilinx’s World WideWeb site (http://www.xilinx.com).◆
Company Application areas of expertise3Soft Corporation (CA) Industry standard functionsComit Systems (CA) Communication, DSPCoreEl MicroSystems (CA) ATM, SonetLogic Innovations (CA) PCI Bus Models, Set Top Box TechnologiesRice Electronics (MO) Digital Signal Processing (DSP),
Image ProcessingSAND Electronics (CA) Bus Interfaces (PCI, ISA, PCMCIA, CardBus)Sierra Research and Technology (CA) ATM, 100MB Ethernet, CPU CoresToucan Technology (Ireland) Bus Interfaces including PCI, TelecomVAutomation (NH) Micro Processors, Embedded
Systems, CommunicationsVirtual Chips (CA) PCI, PCMCIA/CardBus, USB, ATM
LOGICORE PARTNERS
33
DESIGN HINTS AND ISSUES
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Programmable logic users enjoy a wealth of choices when selecting CPLD and FPGA de-vices from Xilinx. A quick guide to the broadest line of product offerings in the industry follows.
Type of Logic FunctionsAll Xilinx devices are general-purpose in nature. Any family can implement any type of logic. There
are, however, some features that make certain families more applicable than others for certain logic func-tions. These eight items should be interpreted as ‘soft’ suggestions, not as absolute, unequivocal choices.
• For shortest pin-to-pin delays and fastest flip-flops: Use XC7300, XC9500 or, if fan-in is sufficient,XC3100A, XC4000E/EX
• For fastest state machines: For encoded state machines, use XC7300, XC9500. For “one-hot” state ma-chines, use XC3100A, XC4000E/EX, XC5200, XC8100
• For fast counters/adders/subtractors/accumulators/comparators: Use XC4000E/EX, XC5200 or XC7300.Use XC3100A for very fast, but short or simple counters.
• For I/O -intensive applications with a high ratio of I/O to gates: Use XC5200
• For shortest design compilation time: Use XC7300, XC9500, or XC8100
• For lowest cost per gate, when on-chip RAM is not required: Use XC5200, XC3100A
• For pin-out compatibility within and between families, allowing easy migration to different device sizesin the same package (sometimes even between families), thus maintaining an existing pc-board layout:Use XC4000E/EX, XC5200, XC8100, XC9500
• For Digital Signal Processing (multiply-accumulate ) applications: Use XC4000E/EX
Specific Functions and CharacteristicsSpecific features/characteristics available only in the listed families. These are “hard” selection criteria.
1. For on-chip RAM: Use XC4000E, XC4000EX, or XC6200.
2. For on-chip bidirectional bussing: Use XC3000A, XC4000, XC5200, XC7300, XC9500, XC8100 (i.e. useany Xilinx family except XC2000). XC3000, XC4000 and XC5000 FPGA families have horizontal longlines that can be driven by internal 3-state drivers; XC8100 FPGAs use internal 3-state drivers on arbi-trarily defined interconnects; XC7300 and XC9500 CPLD devices implement busses indirectly using theirUniversal Interconnect MatrixTM.
3. For on-chip crystal oscillator circuitry: Use XC3000A, XC3100A.
4. For very fast or partial reconfiguration, and for a dedicated microprocessor interface: Use XC6200.
5. For non-volatile single-chip solutions: Use XC7300, XC9500, XC8100 or any HardWireTM device.
6. For lowest possible static power consumption at 5 V: Use XC3000A, XC8100 and, to a lesser extent,XC5200, XC4000E, XC4000EX.
7. For JTAG boundary scan test support: Use XC4000E, XC4000EX, XC5200, XC8100, XC9500 .
8. For rail-to-rail output voltage swing at 5 V VCC: Use XC3000A, XC3100A, XC4000E, XC4000EX, XC5200,XC6200, XC8100 (in XC4000E/EX, rail-to-rail is a user-option).
9. For 3.3-V operation: Use XC3000L, XC4000L, XC4000XL, XC8100.
10.For 5-V operation interfacing with 3.3 V devices: Use XC7300, XC9500 or XC4000E/EX. (Any XC4000E/EX ‘totem-pole’ output drives 3.3 V inputs safely, and the TTL-like input threshold can be driven from3.3 V logic.)
11.For in-system programmability: Use all Xilinx families except XC7300 and XC8100.
12.For PCI-compatibility: Use XC4000E/EX, XC3100A, XC3100L, XC7300, XC9500
13.For hi-rel, military or mil temperature-range applications: Use XC3100A, XC4003, XC4005, XC4010,XC4013.
14.For battery-operated applications requiring low stand-by current: Use XC3000A, XC4000E/EX, XC8100.
15.For best protection against illegal copying of a design (design security): Use XC8100, XC7300, XC9500with security bit activated. For powerdown battery-backed-up configuration: Use XC3000A, XC3000L.
Selectinga XilinxProductFamily
34
JTAG Support in the XC9500 CPLD FamilyThe new XC9500 family of CPLDs can
mitigate the effects of rapidly rising testingcosts for loaded PC boards by simplifyingthe manufacturing process. Caused by theincreasing complexity of IC’s and the useof packaging technologies that restrictaccess to interconnections, along with thehandling requirements of most complexprogrammable logic devices, increasedtesting costs have been a significant chal-lenge to manufacturers.
The XC9500 family allows you to auto-matically program and test multiple de-vices and PC boards in-system, using theindustry standard JTAG interface. Thisgreatly simplifies the production, test, andmaintenance of complex systems. With thiscapability you can even make engineeringchanges to CPLDs on your productionboards in the field, and those changes canbe fully verified.
The XC9500 CPLD family simplifiestesting because you can use software toverify the functionality of devices and their
interconnections; complex and expensivePC board test/probing systems areno longer required. Device handlingproblems are also minimized sinceXC9500 devices are programmed in-system, alleviating the lead integrityproblems associated with external pro-gramming methods. The XC9500 familyincludes seven devices that range from800 to 6,400 equivalent gates, withpin-to-pin delays as fast as 5 ns.
JTAG OverviewJTAG, also known as IEEE Standard
1149.1, uses a simple 4-wire interfaceknown as the Test Access Port (TAP) toaccess a boundary scan serial shift registerand control logic embedded within adevice. Each XC9500 I/O pin is connectedto one stage of the boundary scan shiftregister, allowing the pin to be stimulatedand sampled. Output sampling can evenoccur during normal device operation. Byshifting in a test stimulus and instructions,
Figure 1 - XC95000JTAG Architecture
35
and then shifting out the result, you caneffectively and automatically test devicesand their interconnections on a PC board.
Figure 1 shows the XC9500 JTAGarchitecture. JTAG allows multiple devicesto be daisy-chained and accessed via theTAP. This simplifies board layout, mini-mizes hardware overhead and reduces testsoftware requirements. Figure 2 illustratesa typical daisy-chain arrangement.
Xilinx has extended the TAP to includein-system programming capabilities. Justfour dedicated pins are needed for bothprogramming and testing any number ofdevices.
JTAG OperationsThe XC9500 devices support standard
and optional JTAG operations, including:• SAMPLE/PRELOAD - Allows output
sampling and input stimulus preloadingwhile the device is fully operational.
• EXTEST - Allows testing of deviceinterconnections, independent of inter-nal device operations.
• BYPASS - Bypasses a device by effec-tively connecting TDI to TDO.
• IDCODE - Used to identify the system,to verify that a system is “alive,” and toselect specific test sequences. It can beused for system debug, manufacturingtest, field diagnostics, and upgrades.
• USERCODE - Used to identify thecontents and version of a system. Thisis essential for on-line diagnostics, fieldupgrades and the specification of testsequences or programs to be used
during manufacturing. Also usedduring prototyping and manufacturingfor version control.
• INTEST - Facilitates functional verifi-cation, independent of system inter-connections. This is essential forprototyping and for low-cost manu-facturing test because it can immedi-ately identify functional errors in yourdesign.
• HIGHZ - Facilitates interconnect testin systems with busses. It allowsunique enabling and disabling ofdrivers on bussed lines and can alsobe used to isolate and diagnose inter-connect failures.These operations are fully-compatible
with the IEEE 1149.1 JTAG standard andall third party JTAG test systems.
Xilinx provides everything you needfor developing, programming and auto-matically testing XC9500 devices. Thissupport is available for SUN, HP 9000and IBM-compatible PC platforms.
In summary, the XC9500 CPLD familyis the first to feature full in-system pro-gramming and test capabilities. Thisfamily of high-speed, high-density de-vices will help you produce complexdesigns more efficiently, and those de-signs will be easier to program andverify. Circuit board manufacturing andmaintenance costs are reduced sinceproduction designs can be modified andtested without retooling or using expen-sive board testers.◆
XilinxXCheckerInterface
(test accessport)
Figure 2 - DaisyChain Operation
36
FIFO Buffer Designs in TheXC4000E/EX FPGA Families
Many XC4000 designs use the distrib-uted RAM feature to implement First-In-First-Out (FIFO) elastic buffers to form abridge between subsystems with differentclock rates and access requirements. How-ever, the non-synchronous nature of thesingle-port RAM in the original XC4000architecture leaves the designer with sev-eral challenges. Addresses must be multi-plexed, independent read and write clocksmust be synchronized, and access requestsmust be arbitrated.
The synchronous dual-port option RAMin the new XC4000E and XC4000EXFPGAs eliminates most of these problems.
Since the dual-port RAM in each CLB hasindependent write and read addresses,there is no need to multiplex addressesand arbitrate their selection. The synchro-nous write mechanism simplifies writetiming and contributes to much fasteroperation. The FIFO design effort cannow be concentrated on achieving highthroughput and low cost, and on solving
the fundamental timing problems createdby asynchronous read and write clocks.
Synchronous and AsynchronousFIFOs is an application note now availableon the Xilinx WebLINX World Wide Website (http://www.xilinx.com). This applica-tion note describes six complete designexamples of RAM-based FIFO designsusing the dual-port RAM feature of theXC4000E and XC4000EX FPGAs. Threesynchronous designs with a common read/write clock are described, as well as thecorresponding three asynchronous designswith independent read and write clocks.Emphasis is on the fast, efficient and reli-able generation of the handshake signalsFULL and EMPTY that determine designperformance.
The first design is a synchronous 16x16FIFO buffer, where the depth of the basicCLB-RAM is sufficient. This leads to a veryfast and efficient implementation that canrun at, or close to, the maximum writespeed of 70 MHz (-3 speed grade), evenfor simultaneous read and write operations.This is the simplest and fastest designbecause it avoids the more challengingissues of asynchronous clocking. The de-sign occupies 23 CLBs.
Figure 1 shows the basic block diagramof the 16x16 FIFO buffer. In the synchro-nous version of this design, read and writeclocks are identical. The 4-bit read counterand the 4-bit write counter (Figure 2) areimplemented as two cascaded 2-bit Greyor Johnson counters. In a fully synchro-nous design, this choice is not mandatory,but it has advantages in the non-synchro-nous implementation. It is, however, man-datory that the upper two bits always stayconstant for four consecutive counts.Therefore, Linear-Feedback-Shift-Register(LFSR) counters cannot be used.
The two 4-bit counters address the RAMin the conventional way. Seen as a “black
Figure 1 - 16x16 FIFOBlock Diagram
37
box,” the FIFO buffer behaves like anelastic shift register: input data is latchedby an active edge on the Write Clock, andoutput data is always available at the out-put port. FULL and EMPTY signals must beinterpreted by external logic to prevent aWrite operation during FULL, or a Readoperation during EMPTY.
Most of the design effort is spent on thecontrol logic (Figure 3) that detects theFULL and EMPTY conditions. Since theeasily decoded signal for these twoabnormal conditions is the same — readaddress is identical with write address —an additional signal must be created thatdistinguishes between the the two verydifferent conditions of FULL and EMPTY.For this purpose, an auxiliary signal, calledDIRECTION is created to indicate whetherthe Write counter is about to catch up withthe Read counter, or whether the Readcounter is about to catch up with the Writecounter. The two most significant bits ofboth counters are compared, since theyindicate in which quadrant of the 16-posi-tion circular address space the presentaddress resides. These two most significantbits of both address counters together areused to address two 4-input look-up tablesin parallel. The look-up tables ( LUTs )decode the relative quadrant position ofthe two counters.
The 4-bit LUT address describes one of16 possible conditions:• Four addresses describe the situation
where the write counter is in the quad-rant immediately behind the readcounter. This is decoded as a “possiblygoing full” condition, and sets the DI-RECTION latch or flip-flop.
• Another four addresses describe thesituation where the write counter is inthe quadrant immediately ahead of theread counter. This is decoded as a “pos-sibly going empty” condition, and itresets the DIRECTION latch or flip-flop.
• Four other addresses indicate that thetwo counters are in the same quadrant,and another four addresses indicate that
Figure 2 - Read Counteror Write Counter
the two counters are in opposite quad-rants. These eight addresses provideno useful information about the rela-tive address position, and thus do notaffect DIRECTION. Note that DIREC-
Figure 3 -16x16 FIFOSynchronousControl
Continued onthe next page
38
TION must start in the reset state whenthe FIFO is initiated with both countersat zero.DIRECTION is thus established well
before the actual FULL or EMPTY condi-tion can occur. There will be at least four,and usually many more, consecutive set orreset inputs to the DIRECTION latch orflip-flop before it is being used to dis-criminate between FULL or EMPTY.
FULL goes active as a result of thewrite clock edge that writes data into thelast available location. FULL goes inactiveas a result of the first read clock that readsone word out of the previously full FIFObuffer. EMPTY goes active as a result ofthe read clock edge that reads the lastavailable data from the FIFO buffer.EMPTY goes inactive as a result of the first
FIFO BufferContinued from previous page
write clock that writes one word into thepreviously empty FIFO buffer. In a syn-chronous design, FULL and EMPTY aresynchronous control signals, to be usedappropriately by the logic external to theFIFO buffer.
The application note goes on to de-scribe an asynchronous version of the16x16 FIFO buffer, and 32x8 and 64x8FIFO buffers with both synchronous andasynchronous read and write clocks. Thelarger FIFO buffer designs include inputand output data multiplexing betweenmultiple RAM banks. The asynchronous32x8 FIFO buffer requires 28 CLBs and the64x8 FIFO buffer needs 48 CLBs; both canperform simultaneous read and writeoperations at 40 MHz.◆
Distributed Arithmetic Laplacian FilterA common practice in image process-
ing involves convolving an image with aLaplacian operator. Figure 1 shows a
typical Laplacian operator thatmight be used for edge en-hancement. To convolve it withan image, the operator is movedover the image, and centeredover each pixel in turn. In eachposition, the 25 weights in thematrix are multiplied and accu-mulated with the 25 pixels thatthe matrix covers. This opera-tion yields one pixel in theresulting image.
This is an ideal application for “distrib-uted arithmetic” techniques that exploitthe lookup-table (LUT) architecture of theXC4000ETM FPGA family. Figure 2 showsthe basic approach. Four external linebuffers plus the incoming video dataprovide simultaneous access to five linesof the image. Inside the FPGA, each of thevideo streams is serialized and passed
through four 1-bit-wide shift registers,each of which delay the data by one pixel.This provides simultaneous bit-serial ac-cess to five adjacent pixels from five adja-cent lines — the region covered by theLaplacian filter. The shift registers can beimplemented very efficiently using theCLB RAM feature of the XC4000E FPGAarchitecture.
In the most basic distributed arithmeticapproach, the 25 signals address a 225-word LUT which, in turn, feeds a shiftingaccumulator. This is obviously impractical.A typical cost-reduction measure would beto partition the problem, segmenting theaddresses into multiple smaller LUTs. Theoutputs of these smaller LUTs would becombined in an adder tree to provide theinput to the accumulator.
In this particular case, however, theweighting values involved permit the useof more efficient techniques. Except forthe values 160 and -7, each of thecoefficients is used in four places.
Figure 1 - ExampleLaplacian operator foredge enhancement inan image processingsystem.
39
Consequently, serial adders can be used tocombine four serial bit streams into onebefore addressing the multiplying LUT(Figure 3). Effectively, this adds, and thenweights, data that would otherwise beweighted and added afterwards. A tree ofthree serial adders is needed in each case,and each serial adder can be implementedin a single CLB.
The value -7 is used eight times. Theeight inputs could be combined into one,but here it is only necessary to reducethem to two lines. The value 160 is usedonce, and the data only needs to be de-layed to match the delay introduced intothe other paths by the serial adders.
These modifications reduce the size ofthe LUT from 225 words to 27 words. Thisis a large reduction gained from a smallamount of logic, but the LUT still is solarge that it would have to be split. How-ever, further techniques can be applied.
The -13, -16 and the two -7 valuesneed to be combined into a LUT(Figure 4). The values 12 and 160,however, have no non-zero bit locationsin common. Consequently, all possiblesums of the two values can be achievedby simply wiring the input signals toappropriate bits of the adder.
All that remains is to handle the -1 value. This value uses the carry inputof the adder, but requires some trivialmodification to the LUT. Instead ofcontaining all of the possible sums of-13, -16, -7 and -7, it is loaded with allthe sums of 13, 16, 7 and 7. The minussigns are accommodated by subtractingin the “adder.”
The output of the LUT is inverted aspart of a conventional invert-and-add-one method of subtraction. The -1 valuecan then be accommodated by simplyomitting the “add-one” when necessary.
Continuedon next page
Figure 2 - Basic approachto implementing theLaplacian operator.
40 Figure 3 - Serial bitstreams can becombined beforeentering the LUT.
Figure 4 - (top) Finalimplementation of
Laplacian operator.
Figure 5 - (right)Sharing input shiftregisteres between
parallel MACs.
That means the inverted -1 input is usedas the carry input to the adder.
In this way, the 225-word LUT is re-duced to a 16-word LUT plus 18 serialadders and one 9-bit parallel adder.
Bit-serial arithmetic inherently involvesmultiple cycles per pixel. With the multi-plier-accumulator reduced to such a smallsize, however, two or more of them couldbe used in parallel to regain throughput.
Figure 5 shows how input shift registerscan be shared between two MACs.
For each MAC operation, two pixelsare brought in, and loaded simultaneouslyinto two parallel-to-serial converters. Thisrequires an additional register to tempo-rarily hold one of the pixels. Six serialoutputs are formed, and these are used astwo overlapping sets of five each.◆
LaplacianContinued from previous page
41
Retargeting Designs in MentorGraphics Design Architect
A new utility in Design Architect (DA) from Mentor Graphics can be used toretarget schematic-based designs between Xilinx FPGA families. Although the
Mentor Graphics Interface/Tutorial Guide recommends using the ChangeReferences utility in Mentor’s Design Manager to accomplish this, the latest
version of the Mentor interface (5.2) includes Convert Design, a more thoroughand robust utility for retargeting a Xilinx schematic.
◆ ◆ ◆
Invoke PLD_DA (it is not necessary to open the schematic). On DA’s desktop back-ground (that is, outside of any schematic or symbol windows), call up the session pop-upmenu with the mouse button on the right and select Convert Design. Of the fields in theresulting dialog box these are the most relevant:
Select a group of designs from a list file? Whether you answer “yes” or “no” to thisquestion affects the following field.
Enter Design name (List file = no). The name of the design to retarget. Convert Designdoes not traverse the hierarchy of a schematic.
Enter list file name (List file = yes). A file which lists designs, one per line, to retarget.This is useful if your design has many lower-level schematics.
TIP: You can easily create a list file with the following command:ls *.mgc_component.attr | sed s/.mgc_component.attr//g > listfile
The ls command lists all MGC components within a single directory; the sed com-mand strips off the .mgc_component.attr trailer. The result is redirected to listfile .
Schematic name. The name of the schematic model (the default is “schematic”).
Check & Save switch. Because all schematic sheets in Convert Design are literally re-drawn in Design Architect, you must apply Check & Save to each sheet. This switchcontrols whether to do this automatically. By default, this switch is set for manual check-ing because it allows you to spot Xilinx components that did not convert properly. Usethe manual setting until you are comfortable with how Convert Design works and youare certain that all Xilinx components will convert properly.
From Technology. The device family from which you are converting (e.g., XC3000,XC4000, XC4000E, XC5200, etc.). This and the next field are case insensitive.
To Technology. The device family to which you are converting.
After filling out the fields in the dialog box and selecting “OK,” you will see ConvertDesign doing its job directly in Design Architect.◆
Note: The first few times youuse Convert Design, you maywant to make a copy of theschematic(s) you wish toretarget, to make sure youhave a feel for what this util-ity does before modifying yourdesign permanently.
42
UsingDecouplingCapacitors
As CMOS devices have become fasterand as the number of outputs increases,good decoupling is vital to reliable circuitoperation. Current pulses with a 1 ns riseor fall-time must be treated like GHz sig-nals. In fact, digital printed circuit boarddesigners could learn something fromlooking inside a UHF-TV tuner.
The standard “rule of thumb” fordecoupling-modern CMOS ICs is to mountone low-inductance, decoupling capacitorof 0.01 to 0.1 µF very close to each VCC
pin. This provides the fast changing dy-namic supply current, especially whencapacitively-loaded outputs are switching.
The big power-supply capacitor, and eventhe 100 µF board-decoupling capacitor, cannotperform this function. First, big capacitors havean unavoidable internal series-inductance thatmakes them incapable of supplying fast-chang-ing current pulses with nanosecond rise andfall-times. Second, those capacitors are typi-cally positioned too far away from the devicesthat need access to an instant current reservoir.Even a good power/ground distribution net-work has unacceptable inductance over dis-tances of several inches.
For example, assume a device has 40 out-puts switching simultaneously (or within a fewnanoseconds of each other), with each output
The Xilinx Reconfigurable ComputingDeveloper’s Program is promoting thecommercial use of FPGAs in RapidReconfiguration (RR, also known asreconfigurable computing) applications.These systems add significant value bydynamically changing FPGA designs, inreal-time, while the system is operating.Applications that can exploit the benefits
of the RR concept include graph-ics and image
processing, audio process-ing and data communications.
In recognition of the unique achieve-ments of Metalithic System Inc. (Sausalito,California), Xilinx presented the companywith its inaugural “RR Company of theQuarter” award. Metalithic Systems (MSI)was one of the first companies to realizethe potential of RR, and has released a
Metalithic Systems Exploits Real-Timecommercial product that has RR benefitswhich vastly improve the music industry’sstate-of-the-art.
MSI’s Digital Wings audio processingsystem uses FPGAs in one of its first mass-market commercial applications. DigitalWings is a complete audio authoring sys-tem that operates in the Windows environ-ment on a PC. It delivers 128 tracks, al-lowing a random access edit environmentwith a programmable algorithmic synthe-sizer that supports pan, level, fade, para-metric EQ, echo, chorus, reverb and ste-reo effects.
The Digital Wings for Audio product —a system consisting of a single add-inboard for the PC and related software —was announced and demonstrated at theNAMM (National Association of MusicMarketers) convention in Anaheim thisJanuary. (NAMM is the “COMDEX” of themusic industry.) Their closest competitorwas displaying a 48-track, 9-board systemcosting more than 50 times as much. En-thusiastic editorial interest in MSI andDigital Wings has resulted in feature ar-ticles planned for upcoming editions of
43
Reconfigurability for Audio Processing
Pro Sound News, EQ, Electronic Musicianand Mix. MSI left the convention withcommitments for tens of thousands ofsystems. Digital Wings will be distributedthrough retail stores later this spring.
MSI’s proprietary “nanoprocessor tech-nology” uses Xilinx XC3090 and XC4005FPGAs to reconfigure the system’s hard-ware on-the-fly. Hardware changes withthe needs of the system. In one instant ithandles a specific communication func-tion, in the next it is configured as a
driving a 100 pF load. With an output swing of4 V and all outputs switching in the samedirection, each such transition consumes 0.016µCoulomb. If four decoupling capacitors of0.01 µF have to supply this charge, they willdrop their voltage by 0.016/0.04 = 0.4 V. Thatis barely acceptable. Four 0.1 µF decouplingcapacitors would be preferred, since theyreduce this drop by an order of magnitude.Capacitors larger than 0.1µF tend to have moreseries-inductance, and are actually inferior forthis application.
Another way to look at dynamic currentrequirements is to start with power dissipation.A 3-watt device clocked at 40 MHz does not
consume a steady 600 mA, but mightconsume 3 A for 5 ns, and very little forthe rest of the time. As explained above,to provide the 0.015 µCoulombs (3 A x5 ns) requires at least four 0.01 µFdecoupling capacitors, and 0.1µF wouldbe better.
The need for VCC decoupling varieswith the amount of internal logic, thenumber of outputs that switch simulta-neously and their capacitive load. Therule of one low-inductance 0.01 to 0.1 µFcapacitor at each VCC pin is still a goodguideline. ◆
multi-processor to do complex patternrecognition, and in the next it’s amicrocontroller handling a specializedperipheral. Reconfigurable FPGAs performall these functions, significantly reducingsystem cost while accelerating systemperformance.
Congratulations are due to the wholeMSI development team. For more informa-tion on the Digital Wings product, contactMetalithic Systems at 415-332-2690.◆
The staff ofMetalithicSystems.
For more on theXilinx Developer’s
Program and our RRefforts, please see
our web site athttp://www.xilinx.comor call John Watson
at 408-879-6584.
44
QCan I use XACTstep v6 with Windows 95?Windows 95 is not officially supported by the XACTstep v6 release, but many users havebeen successfully working with this combination. You will, however, run into this problem:
when exiting the Design Manager, the error message “This program has performed an illegal opera-tion and will be shut down.” will appear. Simply choose Close; this message is benign.
The Viewlogic PROseries tools are not supported in Windows 95. Windows NT is not supportedby XACTstep or PROseries.
QHow can I find out more information about my Windows Configuration?There are two Windows utilities on the XACTstep CD-ROM (the following instructions assumethat C:\ is the hard drive and D:\ is the CD drive). Choose File➡Run from the Program Man-
ager and select D:\XBBS\UTILS\XINFO\XINFO.EXE to run XINFO. XINFO will analyze the currentconfiguration of your PC, and report DOS and Windows environment settings, amount of memoryavailable, and a list of hints and recommendations. The other program, XMEM, is run by selectingD:\XBBS\UTILS\XMEM\XMEM.EXE from File➡Run. This dynamic program will keep you updatedwith the status of RAM, memory below 1 Meg, and USER and GDI percentages. These tools aredesigned to help you debug memory or configuration issues you may come across.
QI followed the instructions from the article “Executing from the XACTstepCD-ROM” from the last issue of XCELL (#19, 4Q95) but I still get errors. Whatam I doing wrong?
The article assumed that the XACTstep SETUP program had been previously run. In other words, itassumed that some Windows environment settings had already been configured. Here’s what you’llneed to do:1. Install the correct version of Win32s, which is 1.25.142.0. You can verify this by looking at the
file: C:\WINDOWS\SYSTEM\WIN32S.INI or by checking XMEM or XINFO. If you do not havethis version, exit Windows and run the batch file from the XACTstep CD-ROM:D:\XBBS\UTILS\RMWIN32S.BAT. Then re-enter Windows and chooseFile ➡Run and select D:\WIN32S\DISK1\SETUP.EXE to install the proper version of Win32s.
2. Install the necessary Windows drivers. If you are only using the XACTstep tools, do the following:copy D:\XACT\WINDOWS\SYSTEM\*.* C:\WINDOWS\SYSTEM
mkdir C:\WINDOWS\ASYM
mkdir C:\WINDOWS\ASYM\RUNTIME
copy D:\XACT\WINDOWS\ASYM\RUNTIME\*.*
C:\WINDOWS\ASYM\RUNTIME
If you are using the PROseries tools, you will also need
to do the following:
copy D:\PROSER\WINDOWS\*.* C:\WINDOWS
copy D:\PROSER\WINDOWS\SYSTEM\*.* C:\WINDOWS\SYSTEM
3. Install the DAIKON.386 device driver. You have already copied this driver in Step 2, but nowyou need to edit the C:\WINDOWS\SYSTEM.INI file. Open this file and add the line:
DEVICE=DAIKON.386
after the [386Enh] header. After you quit and re-enter Windows, you’ll be all set.
TECHNICAL QUESTIONS AND ANSWERS
INSTALL
DesignManager/Flow
Engine
QWhen using Viewlogic schematics, what can I do to avoid problems in thetranslation phase of the Design Manager?There are several problems that can stop the design from translating. The .WIR files must be
present for the translation process to complete. If they are missing, the design can be brought up todate by running check -p <design>from a DOS prompt or selecting Tools ➡check ➡project fromPROcapture. The parttype must be specified either in the design or in the Translate Options dialogbox; WIR2XNF requires a parttype to be specified. The path to the design must not contain a pe-riod, other than in the name of the design file.
Continued on the next page
45
QHow do I change options that aren’t listed in the Options dialogs?Select Utilities ➡ Template Manager from the Design Manager’s menu. Select the desiredtemplate and click on the Customize... button. In the Custom Template Dialog, type in the
program name and the desired option. For example, to force XNFPREP to ignore xnf locations inthe interior of the chip, the following line would be used:
xnfprep ignore_xnf_locs=true
When any custom options are used, an asterisk will appear next to that template.
QI am running the Flow Engine from the Design Manager and it hangs.My PC is still working (I can move my mouse), but the Flow Engineseems to have stopped. What has happened?
The problem is that the DOS process underneath the Windows application has become discon-nected. The Flow Engine is still running in Windows, but there is nothing running in DOS to tell itwhen it is done. Try the following suggestions one at a time:1. Disable 32-bit File Access and reduce the cache size by using the
Control Panel ➡386Enhanced ➡Virtual Memory ➡Change. (Windows 3.1.1 only)2. Disable SmartDrive write caching by using the /X option.3. Disable 32-bit Disk Access, also found in the Virtual Memory settings.If these changes do not fix the problem, call the Technical Support Hotline at 800-255-7778.
QSelecting Design ➡➡➡➡➡Implement seems to give one Flow Engine while theTools ➡➡➡➡➡Flow Engine gives a different one. What’s the difference?The one under Design ➡Implement is an automatic version of the Tools ➡Flow Engine. Use
the first to perform automatic runs; use the latter to set advanced options or stop the flow at acertain point.
QThe Flow Engine appeared to hang in bitstream phase.How do I get it to finish?This is a problem we have traced to 32-bit file access in Windows for Workgroups v3.1.1. In the
Windows control panel under Enhanced ➡ Virtual Memory... ➡ Change>>there is a “Use 32 Bit FileAccess” checkbox. Turn this off, restart Windows, and the Flow Engine should complete successfully.
QWhat’s the difference between the report browser and browse revision?The report browser is a graphic interface that allows access to the most commonly neededreport files, such as I/O pin locations, trimming report, etc. Design ➡ Browse Revision allows
access to all the files in a selected revision through a listing of the files. (See figures.)
DesignManager/FlowEngine (con’t)
Report Browser
Revision Browser
Technical Questions and Answerscontinued on the next page
46
TECHNICAL QUESTIONS AND ANSWERS (CONTINUED)
QI have several external signals connected to PAD symbols that I merge into orbus-rip out of a single bus connected to a bussed I/O buffer symbol (e.g., IBUF8,OBUF8, etc.). I have done this so that I can place LOC properties on the individual
PAD symbols (since they cannot be placed on IPAD8s, OPAD8s, etc.). However, when Icompile the design, I discover that the LOC constraints have not been followed, and nowarning has been issued by any programs. In fact, these LOC properties do not exist inany of the XNF files output by Men2XNF8! What’s happening?The Mentor translation process involves two programs, ENWrite and EDIF2XNF. ENWrite (a Mentor program)generates an EDIF netlist which EDIF2XNF translates to a set of XNF files. When signals are bussed in aMentor schematic, ENWrite creates a construct called a “net bundle” in the EDIF file. Although all the informa-tion about the associated LOC properties is included as part of the net bundle, EDIF2XNF expects to see aseparate, independent construct for each of these nets when it looks for associated properties. Therefore,when EDIF2XNF translates these net bundles from the EDIF file, it leaves off the pin-location constraints thatwere placed on the input and output signals. This problem is solved by simply bus-ripping the signal pathinternally (i.e., after the IBUFs or before the OBUFs).
QSome LOC properties on the pads in my design are not passed to subsequentstages in the design compilation. I’ve noticed that these LOC properties aredisplayed as purple text in Design Architect, instead of the normal gold color.
What does this mean?A purple property in Design Architect means that the property is attached to the pin on the PAD symbol,whereas a gold property means that it is attached to the net attached to the pin. Because the PAD symbols inthe Mentor libraries are defined as ports, any properties attached to these symbols (i.e., shown in purple) willnot be passed to the EDIF file during Men2XNF8, and thus will not be passed to subsequent stages of thecompilation.
Usually, LOC properties on Xilinx PAD symbols will transfer to the attached net and will therefore appeargold; however, sometimes the property gets stuck on the PAD pin. The workaround is to select the net vertexconnected to the offending pin, then add the LOC property to the net vertex. This new property should showup in gold, and thus will be passed to the compilation tools. In any case, beware of purple LOC properties!
QWhen running the Check function in Design Architect, I get these warnings:Warning: Unable to evaluate property “model” on I$30
Unable to resolve expression symbol lca_technologyWarning: Unable to evaluate property “__qp_prim” on I$30
Bad Triplet CASE Control ExpressionUnable to resolve expression symbol lca_technology
What do these warnings mean and how can I fix them?All Xilinx simulation models in Mentor have a variable associated with them called “lca_technology.” Nor-mally, this parameter is set whenever a library component is instantiated, but a number of situations cancause Design Architect to lose this parameter. If this happens, Check will not be able to evaluate any proper-ties that use this parameter; however, the lca_technology parameter does not need to be set until the design issimulated or translated to an XNF netlist, at which point the lca_technology parameter is filled in appropri-ately. Therefore, these warnings can be safely ignored.
You can recover the value of lca_technology and unclutter the Check report of these warnings by selectingCheck ➔ Parameters ➔ Set. In the dialog box, enter lca_technology as the parameter name, and set thevalue to the appropriate device family (e.g., xc3000 or xc4000). After doing this, re-execute Check Sheet.
MentorGraphics
Synopsys QCan Input and Output flip-flops be inferred in XC4000E designs?Synopsys can infer input and output flip flops in an XC4000E design. However, if a flip flop has itsclock enable (or reset pin) connected, then Synopsys cannot infer it as an IOB flip-flop, and it will be
implemented as an XC4000E CLB flip-flop. For a flip-flop to be inferred as an IOB flip flop by Synopsys, itsclock enable (and reset pin) must not be connected to anything. You must, therefore, instantiate IOB flip-flops that have their clock enable pin connected.
NOTE: A more elegantsolution was in develop-
ment at press time.For further information,
send an e-mail [email protected]
with “send 692” asthe subject line.
47
QCan Synopsys infer an input flip-flop with the “NODELAY” attribute?The Synopsys (XSI) For FPGAs manual states on page B-9 and B-10 that input latches andflip flops with the NODELAY attribute may be inferred. This is not true. All Input flip flops
and input latches with a NODELAY attribute must be instantiated.Input Flip-Flops:
For the XC4000/A/H/D family, the “fast” input flip-flops are IFD_F and IFDI_FFor the XC4000E family, the “fast” input flip-flops are IFDX_F, IFDXI_F, and IFDXI_U
Input Latches:For the XC4000/A/H/D family, the “fast” input latches are ILD_1F and ILDI_1FFor the XC4000E family, the “fast” input latches are ILDX_1F and ILDXI_1F
QDo I require any additional settings for XC3000 or XC5200 designs inSynopsys?There is one additional setting that you should include into your .synopsys_dc.setup file, if
you are using the FPGA Compiler to synthesize XC3000 or XC5200 designs. Include the followingline in your .synopsys_dc.setup file:
fpga_improved_delay_mapping = 1 ◆
Synopsys (con’t)
Technical Support ResourcesIn addition to field application engineers (FAEs) and technical support engi-
neers (TSEs) located all over the world to provide direct support, Xilinx hasseveral automated services to provide answers to your queries: an e-mail server,an automated FAX system, a bulletin board system, and special interest e-mailgroups.
The XDOCS e-mail system provides 24-hour-a-day, 7-day-a-week access tothe same database that the TSEs use. It is updated daily with bugs, workarounds,and helpful hints. Via e-mail, users can search for a specific record, or use key-words to trigger a search of the database; XDOCS will send the requested infor-mation by return e-mail. Users can receive periodic updates regarding new addi-tions to the system.
To subscribe to XDOCS, send an e-mail to [email protected] with “help” asthe only word in the subject header.
The XFACTS automated FAX system (408-879-4400) provides the same infor-mation as XDOCS, but uses a phone/FAX interface instead of e-mail. Using atouch-tone telephone, users can request documents that are sent to their FAXmachine.
The technical support group also has an e-mail alias: [email protected],and a bulletin board that is updated with utilities such as new package files asthey become available.
Due to the growth in interest in specific application areas, Xilinx has estab-lished a set of e-mail addresses to provide support for questions relatedto these topics (see margin at right).
If you have any questions or comments regarding these systems, or if thereare other support methods that you would like to see implemented, give us acall or send a FAX; the numbers are given in the margin at right.◆
HOTLINE SUPPORTUnited States
Customer Support Hotline:800-255-7778
Hrs: 8:00 a.m.-5:00 p.m. PacificCustomer Support Fax Number:
408-879-4442Avail: 24 hrs/day-7 days/week
E-mail Address:[email protected]
Electronic Tech. Bulletin Board:408-559-9327
Avail: 24 hrs/day-7 days/weekCustomer Service*:
408-559-7778ask for customer service
*Call for software updates, authorizationcodes, documentation updates, etc.
EuropeUK , London Office
telephone: (44) 1932 349402fax: (44) 1932 333530BBS: (44) 1932 333540
e-mail: [email protected], Paris Office
telephone: (33) 1 3463 0100fax: (33) 1 3463 0109
e-mail: [email protected], Munich Office
telephone: (49) 89 99 15 49 30fax: (49) 89 904 4748
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