www.hyivs.tnc.edu.tw shen ching yang no. 2-1 cpld-vhdl 國立新營高工沈慶陽

www.hyivs.tnc.edu.tw

Shen Ching Yang No. 2-1

CPLD-VHDL國立新營高工

WWW.HYIVS.TNC.EDU.TW

沈慶陽



VHDL 範例真值表 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.all;

ENTITY true IS

Port (a,b,c:in STD_Logic;

y:out STD_Logic);

End true;

ARCHITECTURE a OF true IS

Begin

Y<=((not a) and b and (not c))

or (a and b and (not c));

End a;

輸入輸出

a b y

0 0 0

1

0

11

1

1

1

1

0

真值表

c

0

1

0

0

00

0 1

1

0

1

1

1

1

0

0

0

0

0

0



VHDL 範例解碼器 (2 對4) LIBRARY IEEE;


ENTITY decoder2_4 IS

Port (s1,s0:in STD_Logic;

m0,m1,m2,m3:out STD_Logic);

End decoder2_4;

ARCHITECTURE a OF decoder2_4 IS

Begin

m0<=(not s0) and (not s1);

m1<= s0 and (not s1);

m2<= (not s0) and s1;

m3<= s0 and s1;

End a;

m0

m1

m2

m3

S0S1 m0 m1 m2 m3

00 1 0 0 0

0 1 0 1

1

1

0 0

00

00

0

0

1 0

1 1

2 4對解碼器真值表與邏輯電路

s0

s1



VHDL 範例 4 對 1 多工器 LIBRARY IEEE;


ENTITY mux4_1 IS

Port(s1,s0,d0,d1,d2,d3:in STD_Logic;

Y:out STD_Logic);

End mux4_1;

ARCHITECTURE a OF mux4_1 IS

Begin

Y<=((not s0) and (not s1) and d0)

or (s0 and (not s1) and d1)

or ((not s0) and s1 and d2)

or (s0 and s1 and d3);

End a;

S0S1

S0S1 Y

00 d0

0 1

1 0

1 1

4 1對多工器真值表與邏輯電路

2 4對解碼器

d1

d0

d2

d3

Y

d1

d2

d3



VHDL 範例 1 對 4 解多工器 LIBRARY IEEE;


ENTITY demux1_4 IS

Port(d,s1,s0:in STD_Logic;

d0,d1,d2,d3:out STD_Logic);

End demux1_4;

ARCHITECTURE a OF demux1_4 IS

Begin

d0<= d and (not s0) and (not s1);

d1<= d and s0 and (not s1);

d2<= d and (not s0) and s1;

D3<= d and s0 and s1;

End a;

d0

d1

d2

d3

S0S1 d0 d1 d2 d3

00 d 0 0 0

0 1 0 d

d

d

0 0

00

00

0

0

1 0

1 1

1 4對解多工器真值表與邏輯電路

d

d

d

d

d

2 4對解碼器

d

s1s0



VHDL 行為性描述—並行敘述式指令條件式的訊號設定敘述 :When – Else

訊號 Y<= 訊號 A When ( 條件 1) Else

訊號 B When ( 條件 2) Else

訊號 C;

選擇式的訊號設定敘述 :With – Select – When

With 選擇訊號 X Select

訊號 Y<= 訊號 A When 選擇訊號 X 為 m,

訊號 B When 選擇訊號 X 為 n,

:

訊號 Z When Others;



範例 : 真值表使用並行敘述 When-Else LIBRARY IEEE;


ENTITY true_table IS

Port (x:in STD_Logic_Vector(2 downto 0);

y:out STD_Logic);

End true_table;

ARCHITECTURE a OF true_table IS

Begin

Y<= ‘1’ When x=“010” Else

‘1’ when x=“110” Else

‘0’;

End a;

輸入輸出

x2 x1 y

0 0 0

1

0

11

1

1

1

1

0

真值表

x0

0

1

0

0

00

0 1

1

0

1

1

1

1

0

0

0

0

0

0



VHDL 範例解碼器 (2 對 4)When-Else LIBRARY IEEE;


ENTITY decoder2_4w IS

Port (s:in Std_Logic_Vector(1 downto 0);

m0,m1,m2,m3:out Std_Logic);

End decoder2_4w;

ARCHITECTURE a OF decoder2_4w IS

Begin

m0<=‘1’ when s=“00” Else ‘0’;

m1<=‘1’ when s=“01” Else ‘0’;

m2<= ‘1’ when s=“10” Else ‘0’;

m3<= ‘1’ when s=“11”Else ‘0’;

End a;

m0

m1

m2

m3

S0S1 m0 m1 m2 m3

00 1 0 0 0

0 1 0 1

1

1

0 0

00

00

0

0

1 0

1 1


s0

s1



範例具有 EN 的解碼器 (2 對 4)When-Else LIBRARY IEEE;


ENTITY decoder2_4w IS


en:in std_logic;

y:out Std_Logic_vector(3 downto 0));

End decoder2_4w;

ARCHITECTURE a OF decoder2_4w IS

Begin

y<="1000" when en= '1' and s="00" else

"0100" when en= '1' and s="01" else



"0000" ;

End a;

y0

y1

y2

y3

S0S1 y0 y1 y2 y3

00 1 0 0 0

0 1 0 1

1

1

0 0

00

00

0

0

1 0

1 1

EN 2 4具有的對解碼器真值表與邏輯電路

EN

1

1

1

1

EN

s0

s1



VHDL 範例 4 對 1 多工器 When-Else LIBRARY IEEE;


ENTITY mux4_1w IS


d0,d1,d2,d3:in STD_Logic;

Y:out STD_Logic);

End mux4_1w;

ARCHITECTURE a OF mux4_1w IS

Begin

Y<= d0 When s=“00” Else

d1 When s=“01” Else

d2 When s=“10” Else

d3;

End a;

S0S1

S0S1 Y

00 d0

0 1

1 0

1 1

4 1對多工器真值表與邏輯電路

2 4對解碼器

d1

d0

d2

d3

Y

d1

d2

d3



VHDL 範例優先權電路 When-Else LIBRARY IEEE;

use IEEE.STD_Logic_1164.all;

ENTITY priority is

port (d0,d1,d2,d3:in std_logic;

y:out std_logic_vector(1 downto 0));

end priority;

ARCHITECTURE a of priority IS

BEGIN

y <= "11" when (d3='1)' else-- 高優先 --

"10" when (d2='1‘) else

"01" when (d1='1‘) else

"00" ; --low priority

END a;

d2d3 d1 d0 y1 y0

0 01 0

0 1 0

1

1

0

00

0

0

0

10

低優先

高優先

0

0 0 0

1

1

1



VHDL 範例優先權電路 When-Else LIBRARY IEEE;


ENTITY priority is

port (d:in std_logic_vector(3 downto 0);


end priority;

ARCHITECTURE a of priority IS

BEGIN

y <= "11" when d(3)='1' else-- 高優先 --

"10" when d(2)='1' else

"01" when d(1)='1' else

"00" ; --low priority

END a;

d2d3 d1 d0 y1 y0

0 01 0

0 1 0

1

1

0

00

0

0

0

10

低優先

高優先

0

0 0 0

1

1

1



範例 : 真值表並行敘述 With-Select-When

LIBRARY IEEE;


ENTITY true_table IS

Port (x:in STD_Logic_Vector(2 downto 0);

y:out STD_Logic);

End true_table;

ARCHITECTURE a OF true_table IS

Begin

With x Select

Y<= ‘1’ When “010”,

‘1’ When “110”,

‘0’ When Others;

End a;

輸入輸出

x2 x1 y

0 0 0

1

0

11

1

1

1

1

0

真值表

x0

0

1

0

0

00

0 1

1

0

1

1

1

1

0

0

0

0

0

0



VHDL 範例解碼器 (2 對 4)With-Select-When LIBRARY IEEE;


ENTITY decoder2_4ws IS


m:out Std_Logic_Vector(3 downto 0));

End decoder2_4ws;

ARCHITECTURE a OF decoder2_4ws IS

Begin

With s Select

m<=“0001” when “00” ,

“0010” when “01” ,

“0100” when “10”,

“1000” when “11”,

“0000” when others;

End a;

m0

m1

m2

m3

S0S1 m0 m1 m2 m3

00 1 0 0 0

0 1 0 1

1

1

0 0

00

00

0

0

1 0

1 1


s0

s1

嘗試依此例作3 對 8 及 4 對 16

之解碼器



VHDL 範例編碼器 (4 對 2)With-Select-When LIBRARY IEEE;


ENTITY encoder4_2 IS

Port (d:in Std_Logic_Vector(3 downto 0);

y:out Std_Logic_Vector(1 downto 0));

End encoder4_2;

ARCHITECTURE a OF encoder4_2 IS

Begin

With d Select

y<=“00” when “0001” ,

“01” when “0010” ,

“10” when “0100”,

“11” when “1000”,


End a;

d2d3 d1 d0 y1 y0

0 0 10

0 10

1

0

0

0

0

1 0

0

00

4 2對編碼器

0

0 1

1 0

1 1

輸入輸出

(ENCODER)編碼器的邏輯功能.與解碼器的功用相反且輸入端

. ,最多有一個被激發換句話說在眾多的輸入線中只允許其中一

.條有輸入信號

4->2編碼器Encoder

d0

d1

d2

d3

y0

y1

嘗試依此例作8 對 3 及 16 對 4

之編碼器



VHDL 範例七段顯示器解碼電路 With-Select-When y:out Std_Logic_Vector(6 downto 0));

End sev_seg;

ARCHITECTURE a OF sev_seg IS

Begin

With d Select

y<=“1111110” when “0000” ,

“0110000” when “0001” ,

“1101101” when “0011”,

“1111001” when “0011”,

“0110011” when “0100”,

“1011011” when “0101”,

“1011111” when “0110”,

“1110000” when “0111”,

“1111111” when “1000”,

“1111011” when “1001”,

“1110111” when “1010”,

“0011111” when “1011”,

“1001110” when “1100”,

“0111101” when “1101”,

“1001111” when “1110”,

“1000111” when “1111”,


End a;

d2d3 d1 d0y1b

y0a

0 0

1

顯示

y2c

y3d

y4e

y5f

y6g

000

1000

2 0 0 1 0

3 0 0 1 1

4 0 1 0 0

5 0 1 10

6 0 1 1 0

7 0 1 1 1

8 1 0 0 0

9 1 0 0 1

b

1 0 1 0a

1 0 1 1

c

d

f

f

1 1 0 0

1 1 0 1

1 1

1

0

1 1

1

1

1 1 1 1 1 1 0

110 0 0 0 0

1 0 11 1 0 1

00 11111

1 1 11000

1 0 1 1

0

1 1

01 1 1 1 1 1

1 1 1 0 0 0

1 1 1 1 1 1 1

0 1 11111

0 1 1 1111

0 0 1 1 1 1 1

0 01 011

10 0 111 1

1 1 1 100

1 0 0 0

1

1 1 1

七段顯示器真值表

1

LIBRARY IEEE;


ENTITY sev_seg IS

Port (d:in Std_Logic_Vector(3 downto 0);

a

b

c

d

e

f g



範例 : 簡易 ALU 設計 With-Select-When LIBRARY IEEE;


use IEEE.STD_Logic_unsigned.all;

use IEEE.STD_LOGIC_arith.all;

ENTITY alu is

port (a,b:in std_logic_vector(3 downto 0);

s:in std_logic_vector(2 downto 0);


end alu;

ARCHITECTURE a of alu IS

BEGIN

With s Select

y<= (a+b) when "000",

(a-b) when "001",

(a and b) when "010",

(a or b) when "011",

not (a) when "100",

(a xor b) when "101",

a When Others;

END a;

s2 s1 s0

0 0

1

1

0

0

0

10

0

0

選擇操作

0

110

1 0 0

1 0 1

Others( )其他

y<=A+B

y<=A-B

y<=A-B

y<=A and B

y<=A or B

y<=not A

y<=A xor B

y<=A

ALU( )簡易算數邏輯運算設計



並行敘述 When-Else 練習 Library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity logic4 is

port( d0,d1,d2,d3 :IN Std_Logic;

s:IN Std_Logic_Vector(1 downto 0);

y:OUT Std_Logic);

end logic4;

architecture a of logic4 is

begin

y <= d0 when S="00" ELSE

d1 when S="01" ELSE

'1' when S="10" ELSE

(d2 AND d3);

end a;

s1,s0

y

d0

d1

1d2d3

組合邏輯電路s1,s0=00 , y<=d0當時則s1,s0=01 , y<=d1當時則s1,s0=10 , y<=1當時則s1,s0=11 , y<=d2 and d3當時則



並行敘述 When-Else 練習 library IEEE;

use IEEE.std_logic_1164.all;

entity logic5 is

port (a,b,c: in std_logic;

s: in std_logic_vector (1 downto 0);

y0,y1: out std_logic);

end logic5;

architecture a of logic5 is

begin

y0 <= (a or b) and (not c);

y1 <=(a xor b) when s= "11" else

C when s="10" else

(b and c);

end a;

s1,s0

y1

MUX4->1

y0abc

www.hyivs.tnc.edu.tw shen ching yang no. 2-1 cpld-vhdl 國立新營高工 沈慶陽

Documents

www.hyivs.tnc.edu.tw shen ching yang no. 2-1 cpld-vhdl 國立新營高工沈慶陽