writing basic software applications using axi - dc.uba.ar · pdf filelab workbook writing...

Lab Workbook Writing Basic Software Applications Using AXI

www.xilinx.com/university Nexys3 4-1 [email protected] © Copyright 2012 Xilinx

Writing Basic Software Applications Using AXI

Introduction

This lab guides you through the process of writing a basic software application. The software will write to the LEDs on the Nexys3 Board. You will add an XPS BRAM controller and modify the linker script to place the text section in the BRAM. Finally, you will verify that the design operates as expected in hardware.

Objectives

After completing this lab, you will be able to:

• Add an internal Block RAM memory controller • Write a basic application to access an IP peripheral in SDK

• Develop a linker script

• Partition the executable sections onto both the LMB and AXI memory spaces

• Generate a bit file • Download the bit file and verify on the Nexys3 Board

Procedure

This lab is separated into steps that consist of general overview statements that provide information on the detailed instructions that follow. Follow these detailed instructions to progress through the lab.

This lab comprises 4 primary steps: You will add an internal BRAM, invoke SDK and create a software project, analyze assembled object files, and, finally, verify the design in hardware.

Design Description

Extend the processor system created in lab3 by adding a memory controller (see Figure 1) and the writing a basic software application to access the LEDs on the Nexys3 Board.

Figure 1. Design Updated from Previous Lab

Writing Basic Software Applications Using AXI Lab Workbook

Nexys3 4-2 www.xilinx.com/university [email protected] © Copyright 2012 Xilinx

General Flow for this Lab

Add an Internal BRAM Step 1

1-1. Create a lab4 folder and copy the contents of the lab3 folder into the lab4 folder, or copy the content of the labsolution\lab3 folder into the lab4 folder. Launch Xilinx Platform Studio (XPS) and open the project file.

1-1-1. Create a lab4 folder in the C:\xup\embedded\labs directory and copy the contents from lab3 to lab4, or copy the content of the labsolution\lab3folder into the lab4 folder

1-1-2. Open XPS by selecting Start > All Programs > Xilinx Design Tools > ISE Design Suite 14.2 > EDK > Xilinx Platform Studio.

1-1-3. Browse to the lab4 directory and open the project system.xmp.

1-2. Add a BRAM controller and BRAM to the design.

1-2-1. From the IP catalog, add AXI BRAM Controller from the Memory and Memory Controller sub-folder, and click Yes to add the IP.

1-2-2. Expand AXI field in the configuration form.

Note that the default protocol is AXI4. However, we want to use AXI4Lite interface.

1-2-3. Change the AXI4 protocol to AXI4Lite. Click OK twice to add the controller.

Note that adding the controller also adds the BRAM memory and makes PORTA and PORTB connections between the controller and the memory. The BRAM controller is connected to axi4lite_0 instance.

Step 1:

Add an internal BRAM

Step 2: Invoke SDK and create a

software project

Step 3: Analyze

assembled object files

Step 4: Verify the design in hardware



Figure 2. Add internal AXI memory controller

1-2-4. Select the Addresses tab

1-2-5. Select the size of 8K for the AXI4 BRAM controller.

Figure 3. Specify size of AXI4 BRAM Memory Controller

1-2-6. Generate hardware bitstream by clicking Hardware > Generate Bitstream.

Invoke SDK and Create Application Project Step 2

2-1. Start SDK from XPS. Remove lab2.c file from the TestApp. Import lab4.c file from the c:\xup\embedded\sources directory.

2-1-1. Start SDK by clicking Project > Export Hardware Design to SDK … in XPS.

2-1-2. Click on Export & Launch SDK button with default settings.

2-1-3. In Select a Workspace window, locate c:\xup\embedded\labs\lab4\SDK\SDK_Export and click OK

2-1-4. Click Yes to load the updated hardware platform.



2-1-5. Expand TestApp project in the project view.

2-1-6. Select lab2.c, right-click and select Delete.

2-1-7. Click OK to remove it from the file system.

2-1-8. Select TestApp in the project view, right-click, and select Import.

2-1-9. Expand General category and double-click on File System.

2-1-10. Browse to c:\xup\embedded\sources folder.

2-1-11. Select lab4.c and click Finish.

2-1-12. Select the system.mss tab.

2-1-13. Click on Documentation link corresponding to dip peripheral under the Peripheral Drivers section to open the documentation in a default browser window

Figure 4. Accessing device driver documentation



2-1-14. View the various C and Header files associated with the GPIO by selecting File List at the top.

2-1-15. Click the header file xgpio.h and review the list of available function calls for the GPIO.

The following steps must be performed in the software application to enable reading from the GPIO: 1) Initialize the GPIO, 2) Set data direction, and 3) Read the data

Find the descriptions for the following functions by clicking links:

XGpio_Initialize (XGpio *InstancePtr, u16 DeviceId)

InstancePtr is a pointer to an XGpio instance. The memory the pointer references must be pre-allocated by the caller. Further calls to manipulate the component through the XGpio API must be made with this pointer.

DeviceId is the unique id of the device controlled by this XGpio component. Passing in a device id associates the generic XGpio instance to a specific device, as chosen by the caller or application developer.

XGpio_SetDataDirection (XGpio * InstancePtr, unsigned Channel, u32 DirectionMask)

InstancePtr is a pointer to the XGpio instance to be worked on.

Channel contains the channel of the GPIO (1 or 2) to operate on.

DirectionMask is a bitmask specifying which discretes are input and which are output. Bits set to 0 are output and bits set to 1 are input.

XGpio_DiscreteRead(XGpio *InstancePtr, unsigned channel)

InstancePtr is a pointer to the XGpio instance to be worked on.

Channel contains the channel of the GPIO (1 or 2) to operate on

2-1-16. Double-click on lab4.c in the Project Explorer view to open the file. This will populate the Outline tab. Open the header file xparameters.h by double-clicking on xparameters.h in the Outline tab

Figure 5. Double-Click the generated header file

In the xparameters.h file, find the following #define used to identify the dip peripheral:

#define XPAR_DIP_DEVICE_ID 0

Note: The dip matches the instance name assigned in the MHS file for this peripheral.

This #define can be used in the XGpio_Intialize function call.

Note: The number might be different



2-1-17. Your C code should read the dip switch settings and output it to the led_ip.

Figure 6. Imported source file

2-2. Assign the led_ip driver from the c:\xup\embedded\labs\lab4\drivers directory to the led_ip instance.

2-2-1. Click File > Open File…, browse to c:\xup\embedded\labs\lab4\drivers\led_ip_v1_00_a\src and select led_ip_selftest.c, and click Open.

2-2-2. Add the code (to define the number of user registers available in the IP) under the Constant Definitions, then save and close the file.

Note: if the definition is missing, the board support package won’t compile successfully.



Figure 7. Adding definition so the BSP compiles

2-2-3. Select Xilinx Tools > Repositories.

2-2-4. Click on New button of Local Repositories, browse to c:\xup\embedded\labs\lab4, and click OK.

2-2-5. Select standalone_bsp_0 in the project view, right-click, and select Board Support Package Settings.

2-2-6. Select Drivers panel in left, click on Driver column for led_ip_0 and select led_ip driver and click OK.

Figure 8. Assign led_ip driver

2-2-7. Modify your C code (you can find modified code lab4_sol.c from sources folder) to echo the dip switch settings on the LEDs and save the application.



Figure 9. The completed C file

2-2-8. Save the file and the program will be compiled again.



Analyze Assembled Object Files Step 3

3-1. Generate linker script targeting all sections to microblaze_0_i_bram_ctrl_ microblaze_0_d_bram_ctrl and setting heap and stack sizes to 400 each. Compile the application, and analyze the assembled object files using the objdump utility.

3-1-1. Select TestApp, right-click, and select Generate Linker Script.

3-1-2. Make sure that the memory used is microblaze_0_i_bram_ctrl_microblaze_0_d_bram_ctrl as the targets for code, data, and heap and stack segments. Change Heap and Stack sizes to 400 each (to fit the program into single memory) followed by clicking Generate.

Figure 10. Assigning various sections, and setting heap and stack sizes

3-1-3. Click Yes to overwrite the linker script if asked. The program will be compiled again.

3-1-4. Launch the shell by selecting Xilinx Tools > Launch Shell.

3-1-5. Change the directory to TestApp/Debug using the cd command in the shell.

You can determine your directory path by using the pwd command.

3-1-6. Type mb-objdump –h TestApp.elf at the prompt in the shell window to list various sections of the program, along with the starting address and size of each section

You should see results similar to that below:



Figure 11. Object dump results - .text in the ILMB space

3-2. Change the location of the .Data and .Stack sections so that they reside in the axi_bram_ctrl_0_S_AXI_BASEADDR memory. Set heap and stack sizes to 1024 each. Generate the linker script. Recompile the code, re-execute the objdump command, and analyze the output.

3-2-1. Select TestApp, right-click, and select Generate Linker Script.

3-2-2. Select the stack and heap sections to target in to axi_bram_ctrl_0_S_AXI_BASEADDR.

3-2-3. Set Heap and Stack size to 1024 each, click Generate, and Yes to overwrite.

Figure 12. Target .text Section to XPS BRAM



3-2-4. Execute the mb-objdump –h TestApp.elf command in the shell.

Figure 13. Object Dump Results - .heap and .stack sections in AXI4 BRAM space

Verify in Hardware Step 4

4-1. Connect and power up the board. Set the Terminal tab to communicate at 115200 baud using correct COM port. Select TestApp.elf as the application to intialize the BRAM with and program the FPGA from SDK.

4-1-1. Connect and power up the board.

4-1-2. Select the tab. If it is not visible then select Window > Show view > Terminal.

4-1-3. Click on and select appropriate COM port (depends on your computer), and configure it with 115200 baud rate.

4-1-4. Select Xilinx Tools > Program FPGA.

4-1-5. Set the Bitstream and BMM File paths to c:\xup\embedded\labs\lab4\lab1_hw_platform_0\system.bit and c:\xup\embedded\labs\lab4\lab1_hw_platform_0\system_bd.bmm

4-1-6. Click on drop-down button and select TestApp.elf file.

4-1-7. Click the Program button to program the FPGA.

Flip the DIP switches and verify that the LEDs light according to the switch settings. Verify that you see the results of the DIP switch and Push button settings in SDK Terminal.



Figure 14. DIP switch and Push button settings displayed in SDK terminal

Note: Setting the DIP switches and push buttons will change the results displayed.

4-1-8. Close SDK and XPS

Conclusion

Use SDK to define, develop, and integrate the software components of the embedded system. You can define a device driver interface for each of the peripherals and the processor. SDK imports xml file, creates a corresponding MSS file and let you update the settings so you can develop the software side of the processor system. You can then develop and compile peripheral-specific functional software and generate the executable file from the compiled object codes and libraries. If needed, you can also use a linker script to target various segments in various memories.



Completed MHS File # ############################################################################## # Created by Base System Builder Wizard for Xilinx EDK 14.2 Build EDK_P.28xd # Wed Sep 19 09:57:18 2012 # Target Board: digilent nexys3 Rev B # Family: spartan6 # Device: xc6slx16 # Package: csg324 # Speed Grade: -3 # ############################################################################## PARAMETER VERSION = 2.1.0 PORT RS232_Uart_1_sout = RS232_Uart_1_sout, DIR = O PORT RS232_Uart_1_sin = RS232_Uart_1_sin, DIR = I PORT RESET = RESET, DIR = I, SIGIS = RST, RST_POLARITY = 1 PORT GCLK = GCLK, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000 PORT dip_GPIO_IO_I_pin = dip_GPIO_IO_I, DIR = I, VEC = [7:0] PORT push_GPIO_IO_I_pin = push_GPIO_IO_I, DIR = I, VEC = [3:0] PORT led_ip_0_LED_pin = led_ip_0_LED, DIR = O, VEC = [7:0] BEGIN proc_sys_reset PARAMETER INSTANCE = proc_sys_reset_0 PARAMETER HW_VER = 3.00.a PARAMETER C_EXT_RESET_HIGH = 1 PORT MB_Debug_Sys_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst PORT Dcm_locked = proc_sys_reset_0_Dcm_locked PORT MB_Reset = proc_sys_reset_0_MB_Reset PORT Slowest_sync_clk = clk_100_0000MHz PORT Interconnect_aresetn = proc_sys_reset_0_Interconnect_aresetn PORT Ext_Reset_In = RESET PORT BUS_STRUCT_RESET = proc_sys_reset_0_BUS_STRUCT_RESET END BEGIN lmb_v10 PARAMETER INSTANCE = microblaze_0_ilmb PARAMETER HW_VER = 2.00.b PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET PORT LMB_CLK = clk_100_0000MHz END BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_i_bram_ctrl PARAMETER HW_VER = 3.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00003fff BUS_INTERFACE SLMB = microblaze_0_ilmb BUS_INTERFACE BRAM_PORT = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block END BEGIN lmb_v10 PARAMETER INSTANCE = microblaze_0_dlmb PARAMETER HW_VER = 2.00.b PORT SYS_RST = proc_sys_reset_0_BUS_STRUCT_RESET PORT LMB_CLK = clk_100_0000MHz END



BEGIN lmb_bram_if_cntlr PARAMETER INSTANCE = microblaze_0_d_bram_ctrl PARAMETER HW_VER = 3.10.a PARAMETER C_BASEADDR = 0x00000000 PARAMETER C_HIGHADDR = 0x00003fff BUS_INTERFACE SLMB = microblaze_0_dlmb BUS_INTERFACE BRAM_PORT = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block END BEGIN bram_block PARAMETER INSTANCE = microblaze_0_bram_block PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = microblaze_0_i_bram_ctrl_2_microblaze_0_bram_block BUS_INTERFACE PORTB = microblaze_0_d_bram_ctrl_2_microblaze_0_bram_block END BEGIN microblaze PARAMETER INSTANCE = microblaze_0 PARAMETER HW_VER = 8.40.a PARAMETER C_INTERCONNECT = 2 PARAMETER C_USE_BARREL = 1 PARAMETER C_USE_FPU = 0 PARAMETER C_DEBUG_ENABLED = 1 PARAMETER C_ICACHE_BASEADDR = 0X00000000 PARAMETER C_ICACHE_HIGHADDR = 0X3FFFFFFF PARAMETER C_USE_ICACHE = 0 PARAMETER C_ICACHE_ALWAYS_USED = 0 PARAMETER C_DCACHE_BASEADDR = 0X00000000 PARAMETER C_DCACHE_HIGHADDR = 0X3FFFFFFF PARAMETER C_USE_DCACHE = 0 PARAMETER C_DCACHE_ALWAYS_USED = 0 BUS_INTERFACE ILMB = microblaze_0_ilmb BUS_INTERFACE DLMB = microblaze_0_dlmb BUS_INTERFACE M_AXI_DP = axi4lite_0 BUS_INTERFACE DEBUG = microblaze_0_debug PORT MB_RESET = proc_sys_reset_0_MB_Reset PORT CLK = clk_100_0000MHz END BEGIN mdm PARAMETER INSTANCE = debug_module PARAMETER HW_VER = 2.10.a PARAMETER C_INTERCONNECT = 2 PARAMETER C_USE_UART = 1 PARAMETER C_BASEADDR = 0x41400000 PARAMETER C_HIGHADDR = 0x4140ffff BUS_INTERFACE S_AXI = axi4lite_0 BUS_INTERFACE MBDEBUG_0 = microblaze_0_debug PORT Debug_SYS_Rst = proc_sys_reset_0_MB_Debug_Sys_Rst PORT S_AXI_ACLK = clk_100_0000MHz END BEGIN clock_generator PARAMETER INSTANCE = clock_generator_0 PARAMETER HW_VER = 4.03.a PARAMETER C_CLKIN_FREQ = 100000000 PARAMETER C_CLKOUT0_FREQ = 100000000



PARAMETER C_CLKOUT0_GROUP = NONE PORT LOCKED = proc_sys_reset_0_Dcm_locked PORT CLKOUT0 = clk_100_0000MHz PORT RST = RESET PORT CLKIN = GCLK END BEGIN axi_interconnect PARAMETER INSTANCE = axi4lite_0 PARAMETER HW_VER = 1.06.a PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0 PORT interconnect_aclk = clk_100_0000MHz PORT INTERCONNECT_ARESETN = proc_sys_reset_0_Interconnect_aresetn END BEGIN axi_uartlite PARAMETER INSTANCE = RS232_Uart_1 PARAMETER HW_VER = 1.02.a PARAMETER C_BAUDRATE = 115200 PARAMETER C_DATA_BITS = 8 PARAMETER C_USE_PARITY = 0 PARAMETER C_ODD_PARITY = 1 PARAMETER C_BASEADDR = 0x40600000 PARAMETER C_HIGHADDR = 0x4060ffff BUS_INTERFACE S_AXI = axi4lite_0 PORT S_AXI_ACLK = clk_100_0000MHz PORT TX = RS232_Uart_1_sout PORT RX = RS232_Uart_1_sin END BEGIN axi_gpio PARAMETER INSTANCE = dip PARAMETER HW_VER = 1.01.b PARAMETER C_GPIO_WIDTH = 8 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_BASEADDR = 0x40000000 PARAMETER C_HIGHADDR = 0x4000ffff BUS_INTERFACE S_AXI = axi4lite_0 PORT S_AXI_ACLK = clk_100_0000MHz PORT GPIO_IO_I = dip_GPIO_IO_I END BEGIN axi_gpio PARAMETER INSTANCE = push PARAMETER HW_VER = 1.01.b PARAMETER C_GPIO_WIDTH = 4 PARAMETER C_ALL_INPUTS = 1 PARAMETER C_BASEADDR = 0x40040000 PARAMETER C_HIGHADDR = 0x4004ffff BUS_INTERFACE S_AXI = axi4lite_0 PORT S_AXI_ACLK = clk_100_0000MHz PORT GPIO_IO_I = push_GPIO_IO_I END BEGIN led_ip PARAMETER INSTANCE = led_ip_0 PARAMETER HW_VER = 1.00.a PARAMETER C_BASEADDR = 0x7f400000



PARAMETER C_HIGHADDR = 0x7f40ffff BUS_INTERFACE S_AXI = axi4lite_0 PORT S_AXI_ACLK = clk_100_0000MHz PORT LED = led_ip_0_LED END BEGIN axi_bram_ctrl PARAMETER INSTANCE = axi_bram_ctrl_0 PARAMETER HW_VER = 1.03.a PARAMETER C_S_AXI_PROTOCOL = AXI4LITE PARAMETER C_S_AXI_BASEADDR = 0x40050000 PARAMETER C_S_AXI_HIGHADDR = 0x40051FFF BUS_INTERFACE S_AXI = axi4lite_0 BUS_INTERFACE BRAM_PORTA = axi_bram_ctrl_0_BRAM_PORTA BUS_INTERFACE BRAM_PORTB = axi_bram_ctrl_0_BRAM_PORTB PORT S_AXI_ACLK = clk_100_0000MHz END BEGIN bram_block PARAMETER INSTANCE = axi_bram_ctrl_0_bram_block_1 PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = axi_bram_ctrl_0_BRAM_PORTA BUS_INTERFACE PORTB = axi_bram_ctrl_0_BRAM_PORTB END

writing basic software applications using axi - dc.uba.ar · pdf filelab workbook writing...

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