wlan ahb bus specification

SoC for car application Specification for WLAN API Bridge

SOC FOR CAR APPLICATION

WLAN AHB-bus Bridge

Awais Qadir

Roll# 23563

DOCUMENT CHANGE HISTORY

Version Number Date Description

1.0 4/6/13 Draft

1.1 6/6/13 Modified first version

1.2 15/6/2013

June 2013

SOC FOR CAR APPLICATIONWLAN AHB-bus Bridge

Version 1.1

[Insert approval date of document]

SoC for car media application Specification for WLAN AHB Bridge

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TABLE OF CONTENTS

SOC FOR CAR APPLICATION................................................................................................................................I1. INTRODUCTION...................................................................................................................................................1

1..1 Identification......................................................................................................................................11..2 System Overview................................................................................................................................11..3 Document Overview...........................................................................................................................2

REFERENCE DOCUMENTS...........................................................................................................................................22. PROJECT DESCRIPTION....................................................................................................................................3

PROJECT PERSPECTIVE................................................................................................................................................3PROJECT FUNCTIONS..................................................................................................................................................3USER CHARACTERISTICS............................................................................................................................................3CONSTRAINTS.............................................................................................................................................................3

2..1 What is the Actual Speed of an 802.11b Wi-Fi Network?.................................................................32..2 Practical system compliance.............................................................................................................42..3 Additional constraints, programming language and tools being employed......................................4

ASSUMPTIONS AND DEPENDENCIES............................................................................................................................43. REQUIREMENTS..................................................................................................................................................5

INTERFACES................................................................................................................................................................53..1 User Interface....................................................................................................................................53..2 Other allowed external peripherals...................................................................................................5

SYSTEM DESIGN OVERVIEW........................................................................................................................................53..1 AMBA Bus protocol...........................................................................................................................53..2 AHB BUS...........................................................................................................................................63..3 WLAN baseband processor................................................................................................................6

FIFO IMPLEMENTATION.............................................................................................................................................74. SYSTEM ARCHITECTURE.................................................................................................................................9

BRIDGE DESIGN...........................................................................................................................................................9DESIGN IMPLEMENTATION..........................................................................................................................................9BRIDGE AS AN AHB SLAVE.......................................................................................................................................11

4..1 Signals..............................................................................................................................................124..2 Registers..........................................................................................................................................13

5. COMPONENTS....................................................................................................................................................14WLAN......................................................................................................................................................................14BRIDGE......................................................................................................................................................................15

6. SIGN OFF..............................................................................................................................................................16LIST OF FIGURES.......................................................................................................................................................16

7. REFERENCES......................................................................................................................................................17APPENDIX A – GLOSSARY....................................................................................................................................18

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1. INTRODUCTION

This Specification Document captures the requirements for the Design concept and describes the design decisions, architectural design and the detailed design needed to implement an AHB WLAN bridge based SoC for car Media System. It provides the acquirer visibility into the design and provides information needed for hardware support.

The purpose of the specification is to review the design calculation and architecture for the implementation of the system according to the AMBA bus architecture.

The initial goal (goal of this version) is to develop the sub-system to the point in the analytical workflow where system can be assessed and implemented as a part of the SoC . The estimations and calculation represented in this specification are made on the basis of manual calculation through different software and is not tested or experimented on a hardware. Goals of the specification are:

1. Allow the recording of all necessary, and desired, data pertaining to analyses.

2. Allow interoperability with parallel Soc systems.

3. Remain AMBA Architecture compliant.

4. Bridging AHB bus with the AMBA AHB bus .

1.1 Identification

This is an initial version of the specification for the Design of WLAN AHB Bridge in compliance to AMBA Bus Architecture for the SoC for Car Media System application.

1.2 System Overview

The SoC for car Media System comprises of the following sub systems.

1. Graphic / Hmi

2. USB interface

3. Memory system

4. Debug interface

5. Speed / RPM calculation

6. Battery status

7. Climate control

8. Mobile phone , hands free implementation

9. An ARM926 operating @ 1Ghz

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1.3 Document Overview

There are no additional or specific security or privacy considerations associated with this document. All the references and the citations are marked. The document is being developed transparently and as open source. Questions, comments and requests may be submitted directly.

The remaining Specification sections are organized as follows:

Section 2. Project Description: Describes the general factors that affect the SoC.

Section 3. Requirements: Describes all the Design requirements to a level of detail sufficient to enable designers to design a system to satisfy those requirements.

Section 4. System architecture: Describes architectural aspects of the system as a whole.

Section 5. Components: Describes functional and architectural aspects of the system components.

Appendix A. Acronym List: Defines the abbreviations used on the project.

REFERENCE DOCUMENTS

For additional project, and requirement specific information, refer to the following documents:

AMBA Design Kit Technical Reference Manual Cortex-M™ System Design Kit Technical Reference Manual http://infocenter.arm.com

Space reserved for the specification addresses of the other Subsystems on SoC.

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2. PROJECT DESCRIPTION

The Specifications for The WLAN AHB Bridge provides information for interfacing the WLAN baseband processor to the AHB bus in compliance with the AMBA bus architecture. The System is a part of Car media system. The main areas which would be looked upon are

Cross clock bridging

General design overview , with Tx, Rx FIFO

Interfaces that WLAN will provide

PROJECT PERSPECTIVE

The system is being developed as a course work for the Masters level program. It is a part of SoC in compliance with AMBA bus architecture which provides design & calculations for the construction of a Car media system.

PROJECT FUNCTIONS

The complete project would provide new and innovative interfaces to communicate and control the car media system. The subsystem of the project, ‘the WLAN AHB Bridge ‘would be used to communicate between the other peripherals and the CPU using the AHB bus.

USER CHARACTERISTICS

Anticipated end-users of ‘the car media system’ and ‘the WLAN AHB bridge’ are users researching on SoC in compliance with AMBA architecture or, more specifically, dedicated engineering facilities. In addition, researchers who are not performing the analyses themselves, but have proper permissions to access the system and specific data subset(s), may also act as end users.

CONSTRAINTS

2.1 What is the Actual Speed of an 802.11b Wi-Fi Network?

The theoretical peak bandwidth of an 802.11b wireless connection is 11 Mbps. This is a performance number advertised on 802.11b Wi-Fi equipment, that many people equate with the expected "speed" of a network. However, this level of performance is never achieved in practice due to network overhead and other factors. The typical peak throughput (sustained data rate) of an 802.11b wireless connection under ideal conditions for end user data is roughly 4-5 Mbps. This level of performance assumes a wireless client in very close proximity (within a few meters) of the base station or other communication endpoint. Due to the distance-sensitive nature of Wi-Fi signaling, 802.11b throughput numbers will decrease the client moves further away from the base station. [1]

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2.2 Practical system compliance

The system is just in design phase and is not tested on any platform or experimented with. The design is just a system overview and some values are estimations or might be fictitious, although where estimations are taken it would be mentioned clearly.

2.3 Additional constraints, programming language and tools being employed

Excel sheet is used for the calculation for the cross bridge clocking at different instants.

ASSUMPTIONS AND DEPENDENCIES

The perceived "speed" of a network is determined not only by available bandwidth but also by network latency. The typical peak throughput (sustained data rate) of an 802.11b wireless connection under ideal conditions for end user data is roughly 4-5 Mbps. This level of performance assumes a wireless client in very close proximity (within a few meters) of the base station or other communication endpoint. Due to the distance-sensitive nature of Wi-Fi signaling, 802.11b throughput numbers will decrease the client moves further away from the base station. [1]

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3. REQUIREMENTS

INTERFACES

3.1 User Interface

WLAN would be able to connect to different devices complaint with the IEEE 802.11 standards . for the specific project IEEE 802.11b would be used for the calculations.

3.2 Other allowed external peripherals

Figure 1 OBD Wifi WLAN ELM327 shows a WLAN OBD, which is used to diagnose and benchmarking tool for car systems. It can be used as an external peripheral hooked up with the WLAN.

Figure 1 OBD Wifi WLAN ELM327

Another very useful external device connected to the WLAN network can be a dashboard camera, especially useful for commercial commuters. The network can send all the data remotely to any server, using high speed 3g wireless internet connections.

SYSTEM DESIGN OVERVIEW

3.1 AMBA Bus protocol

The AMBA-based microcontroller system consists of a high-performance backbone bus, Advanced High-performance bus (AHB), able to sustain the external memory bandwidth, on which the CPU, on-chip memory and other direct memory access (DMA) devices reside. Also located on the high-performance bus is a bridge to lower bandwidth APB, where most of peripheral devices in the system are located. (2)

AHB supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces with low-power peripheral macro-cell functions. AHB is also specified to ensure ease of use in an efficient design flow using synthesis and automated test techniques.

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https://en.wikipedia.org/wiki/IEEE_802.11


AHB Bus supports to burst mode data transfer and split transaction. instances of classes represented by a domain model.

Figure 2 AHB acting as a backbone bus

3.2 AHB BUS

AHB slaves can be considered passive elements in the bus structure because they do not initiate transactions on the bus. As the AHB protocol states, there is an address phase and data phase for every AHB transaction, therefore one way to construct the slave is to build a state machine that has a state for each phase in the transactions. [3]

3.3 WLAN baseband processor

The wireless LAN base-band processor is separated in two main blocks, such as base-band transceiver and hardwired MAC. The transceiver consists of a data scrambler, header generator, modulator, pulse shape filter, interpolator, matched filter, equalizer, rake receiver, demodulator and descrambler.

The standard specifies a data rate ranging from 1 to 11Mbps. Depending on the desired data rate, the adopted modulation scheme could be binary phase shift keying (BPSK) at 1Mbps, quaternary phase shift keying (QPSK) at 2Mbps, or complementary code keying (CCK) at 5.5Mbps and 11Mbps [3] . Figure 3 Comparison of WLAN standards , shows how the WLAN standards evoved. For the calcutions we will be using IEEE 802.11b standard, which has a throughput ranging 1-11Mbps . more number of connections to the WLAN mean more bandwidth shared among the peers , so the number of devices that can connect are finite due to bandwidth limitations.

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Figure 3 Comparison of WLAN standards

FIFO IMPLEMENTATION

The bridge between the WLAN and the AHB bus (the secondary AHB), would need to cater the clocking difference between the main bus clock (including overheads) and the clock needed to transfer data from WLAN. The Bridge consists of 2 FIFO (for receive and transmit). The FIFO depth can be adjusted by the designer in accordance with the speed & overhead requirement. Figure 4 FIFO implementation shows the overview of how the FIFO can handle the data transmit and receive to and from the WLAN. The clock crossing would be explained in the more detail in the ‘system Architecture’ heading.

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Figure 4 FIFO implementation

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4. SYSTEM ARCHITECTURE

BRIDGE DESIGN

Figure 5 FIFO interface

The (Figure 5 FIFO interface) shows the blocks being used to implement the clock crossing in the bridge. The bridge is a Slave on the AHB bus and master on the WLAN interface. When transmitting the data is stored in the Tx FIFO until it is fetched by the WLAN. For receiving, the data is stored in Rx FIFO and correspondingly fetched by the AHB bus. The Timing and detailed working of the bridge is explained in following headings.

DESIGN IMPLEMENTATION

Suppose AHB2 or the AHB at a lower speed for the peripherals can give 1/4 th of the time to the AHB Bridge, and subtracting all the overhead the bridge get 200 MHz as the Slave clk. On the Master interface of the bridge the WLAN decides the clock required according to the A/D sampled data. The max data rate varies according to the WLAN standards and the distance from the router. The WLANclk or the master clk can be calculated by the following formula

f =WLAN Data rate (throughput)

Data buswidth

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e.g in (Figure 6 TX and Rx FIFO example) when receiving data, frecuency needed at WLANclk to store the A/D sampled data through the 32 bit wide data bus into the Rx FIFO @1Mbps

WLAN throughput . f =1000000 bit /s32 bit

=¿31250 Hz

Figure 6 TX and Rx FIFO example

For transmission that means @ 1Mbps connection when transmitting we receive data @ 200 MHz and store it in FIFIO until overflow interrupt is sent upon reaching overflow limit. The WLAN baseband processor fetches data @ 62500Hz.

For receiving data @1Mbps connection, the data is stored in FIFO @62500Hz. The data is sent at AHB bus @200 MHz so as the stack hits the underflow limit, an interrupt is sent to stop fetching data accordingly. That means that the clock dead time is (slaveclk /Master). So 200 MHz/62500Hz = 32 dead cycles.

The FIFO size from transmission theoretically would be about 6400Mb (data from 32 bit data bus from CPU per sec) – 1Mb (Min WLAN speed per sec), which is too much. So a greater then128 Mb FIFO can be estimated to be used compromising either storage or speed. For Receive FIFO it can be as low as 5mb because the data rate for feeding FIFO is much lower than the data rate from FIFO to AHB.

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WLAN connection

speed (Mbps)

A/D sampled

Data rate in bps

Data bus width Clock speed required for master (WLANclk) in Hz

for data bus 8 / 16 / 32 bit 1 1000000 8 16 32 125000 62500 312502 2000000 8 16 32 250000 125000 625006 6000000 8 16 32 750000 375000 1875009 9000000 8 16 32 1125000 562500 281250

12 12000000 8 16 32 1500000 750000 37500018 18000000 8 16 32 2250000 1125000 56250024 24000000 8 16 32 3000000 1500000 75000036 36000000 8 16 32 4500000 2250000 112500048 48000000 8 16 32 6000000 3000000 150000054 54000000 8 16 32 6750000 3375000 1687500

Figure 7 speed calculation for the WLANclk

In (Figure 7 speed calculation for the WLANclk) the standard WLAN data rates are used to calculate the required Master clock (WLANclk) speed. The data rate depends on the IEEE standard for WLAN used and on the proximity from the router. Although the practical speed is a bit lower than advertised, please look in the topic “Assumptions and Dependencies” for further information.

BRIDGE AS AN AHB SLAVE

The AHB WLAN Bridge is a slave on the AHB Bridge so the (Figure 8 AHB slave example), demonstrates the implementation of a simple AHB slave, and consists of the ahb_eg_slave_interface.v and the ahb_eg_slave_reg.v.[4] It shows all the registers & buses used for the interface. The buses and the signals can be searched in the glossary for more detail. The detailed information about AHB slave is explained on topic 3.1 Cortex-M™ System Design Kit Revision: r0p0 Technical Reference Manual.

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Figure 8 AHB slave example

4.1 Signals

The following table gives the function of the signals that are used in the process.

Signal Description

HCLK This clock times all bus transfers

HRESETn The bus reset signal is active LOW. It resets the system and the bus.

HSEL Each AHB slave has its own slave select signal and this signal indicates that the current transfer is intended for the selected slave. This signal is simply a combinatorial decode of the address bus.

HADDR[31:0] The 32-bit system address bus.

HTRANS[1:0] This indicates the type of the current transfer. This can be NONSEQUENTIAL, SEQUENTIAL, IDLE, or BUSY.

HSIZE[2:0] These signals indicate the size of the transfer, typically byte (8-bit), halfword (16-bit), or word (32-bit). The protocol permits larger transfer sizes up to a maximum of 1024 bits.

HWRITE When HIGH, this signal indicates a write transfer, and when LOW, a read

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transfer.

HREADY When HIGH, the HREADY signal indicates that a transfer has finished on the bus. You can drive this signal LOW to extend a transfer.

HWDATA[31:0] or

HWDATA[63:0]

The write data bus transfers data from the master to the bus slaves during write operations. ARM recommends a minimum data bus width of 32 bits. However, you can easily extend this to enable higher bandwidth operation.

HREADYOUT When HIGH, the HREADY signal indicates that a transfer has finished on the bus. You can drive this signal LOW to extend a transfer.

HRESP[1:0] The transfer response provides additional information on the status of a transfer. Four different responses are provided, OKAY, ERROR, RETRY, and SPLIT.

HRDATA[31:0] or

HRDATA[63:0]

The read data bus transfers data from bus slaves to the bus master during read operations. ARM recommends a minimum data bus width of 32 bits. However, you can easily extend this to enable higher bandwidth operation.

ECOREVNUM The ECOREVNUM input signal is connected to the ECO .

4.2 Registers

Fstat [0:3] 0 error in the data received in the FIFO

1 Overflow interrupt signal to the interrupt generator

2 Underflow interrupt signal to the interrupt generator

4 data transmit error

FFlush Flush all data in the FIFO

FEnablerec Enable data receive

FEnabletran Enable data transmit

Fretry Request data resend

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5. COMPONENTS

WLAN

Purpose High speed Wireless data transceiver peripheral

Function Providing the car media system a wireless interface to connect devices complaint to IEEE 802.11 standards.

Dependencies The WLAN operation and data speed depends on the IEEE 802.11 standard supported on the devices.

Interfaces The WLAN provide the media system a wireless interface to connect devices and exchange data between the Car media system and the devices.

Uses The WLAN can be used by the system to make a network of devices connected to it and share data such as music/video files, data that can be displayed on the screen interface. The WLAN can also be used to acquire data about the car through diagnostic interfaces such as mentioned in 3.2 Otherallowed external peripherals and display it on the screen. It can also be used to connect cameras e.g in commuters and send it to the system which can then send the data to a server through a wireless internet connection.

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BRIDGE

Purpose Bridges two buses or a peripheral and Bus having a different frequency clock.

Function In this system the AHB WLAN bridge interfaces the bus and the WLAN module both working at a different frequency.

Subordinate Implements a FIFO to cater the difference in the data transfer rate due to clock difference.

Dependencies FIFO size can be adjusted by the designer of the system considering that a larger FIFO means higher latency but lower depth FIFO can run out of memory and create bottleneck situation. The Bridge uses an interrupt generator to generate interrupts according FIFO status, and send them to the DMA interface.

Interfaces The bridge is a slave on the AHB bus and a master on the WLAN.

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6. SIGN OFF

LIST OF FIGURES

FIGURE 1 OBD WIFI WLAN ELM327 5FIGURE 2 AHB ACTING AS A BACKBONE BUS 6FIGURE 3 COMPARISON OF WLAN STANDARDS 7FIGURE 4 FIFO IMPLEMENTATION 8FIGURE 5 FIFO INTERFACE 9FIGURE 6 TX AND RX FIFO EXAMPLE 10FIGURE 7 SPEED CALCULATION FOR THE WLANCLK 11FIGURE 8 AHB SLAVE EXAMPLE 12

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7. REFERENCES

1. compnetworking.about.com/od/wirelessfaqs/f/maxspeed80211b . [Online]

2. ARM. AMBA specification (rev 2.0), ARM, May 1999.

3. Choi, Yong-Mu Jeong Seung-Eun Lee Won-Seok Oh and Jong-Chan. flexible AMBA bridge for RISC based SoC. s.l. : SoC Research Center, Korea Electronics Technology Institute, KyoungGi-Do, Korea.

4. Cortex-M™ System Design Kit.

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APPENDIX A – GLOSSARY

Term/Abbreviation

Description

AMBA AHB

The AMBA Advanced High-performance Bus system connects embedded processors such as an ARM core to high-performance peripherals, DMA controllers, on-chip memory, and interfaces. It is a high-speed, high-bandwidth bus that supports multi-master bus management to maximize system performance.

AMBA AMBA is the ARM open standard for multi-master on-chip buses, capable of running with multiple masters and slaves. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC). It aids in the development of embedded processors with one or more CPUs or signal processors and multiple peripherals. AMBA complements a reusable design methodology by defining a common backbone for SoC modules. AHB conforms to this standard.

Architecture The organization of hardware and/or software that characterizes a processor and its attached components, and enables devices with similar characteristics to be grouped together when describing their behavior, for example, Harvard architecture, instruction set architecture, ARMv6 architecture.

BURST A group of transfers to consecutive addresses. Because the addresses are consecutive, there is no requirement to supply an address for any of the transfers after the first one. This increases the speed at which the group of transfers can occur. Bursts over AHB buses are controlled using the HBURST signals to specify if transfers are single, four-beat, eight-beat, or 16-beat bursts, and to specify how the addresses are incremented.

A block of on-chip or off-chip fast access memory locations, situated between the processor and main memory, used for storing and retrieving copies of often used instructions and/or data. This is done to increase the average speed of memory accesses and therefore to increase processor performance.

Cache A block of on-chip or off-chip fast access memory locations, situated between the processor and main memory, used for storing and retrieving copies of often used instructions and/or data. This is done to increase the average speed of memory accesses and therefore to increase processor performance.

CPU The part of a processor that contains the ALU, the registers, and the instruction decode logic and control circuitry. Also commonly known as the processor core.

processor A contraction of microprocessor. A processor includes the CPU or core, plus additional components such as memory, and interfaces. These are combined as a single macro cell that can be fabricated on an integrated circuit.

Region A partition of instruction or data memory space.

Register A temporary storage location used to hold binary data until it is ready to be used.

Write buffer

A block of high-speed memory, arranged as a FIFO buffer, between the Data Cache and main memory, whose purpose is to optimize stores to main memory. Each entry in the write buffer can contain the address of a data item to be stored to main memory, the data for that item, and a sequential bit that indicates if the next store is sequential or not.

FIFOfirst in–first out. First in–first out is an abstraction in ways of organizing andmanipulation of data relative to time and prioritization.

RISC Reduced instruction set computer. Reduced instruction set computer represents a CPU design strategy emphasizing the insight that simplified instructions which can be executed very quickly to provide higher performance.

SoC System-on-chip. System-on-chip refers to integrating all components of a Computer or other electronic system into a single integrated circuit (chip).

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