Wireless Terminal and PC Interface Using VLSI

EE452 - Senior Project

Members: Chris Brophy

Matt Olinger

Advisor: Dr. V. Prasad5/2/02

• Uses ISA (Industry Standard Architecture) interface and off-the-shelf wireless RF module

• Design and testing accomplished with Logic Works, Emac 8051 Development Board, Renoir, ModelSim, Xilinx CPLD, and L-EDIT

• Provides alternative to costly internet providers – low cost, short range transmissions

Abstract

Outline• Design Overview

• Pin Count

• Block Diagram

• Testing

• Logic Works, Renoir, CPLD (Complex Programmable Logic Device), Emac

• Implementation / Problems

• Future Improvements

• Schedule

• References

Design Overview

• Two interfaces are required:

• ISA bus (from computer)

• Proprietary bus interface (RF device)

• A method of buffering is also necessary, since the data rates of both interfaces are unequal.

• A status register is also necessary to provide feedback to the computer when to send and receive.

• Timing is critical!

Pin Count26 / 34 pins used

• ISA interface

• Data D0-D7

• Address A0-A9

• IOW, IOR, INT, BCLK

• RF module (Linx Tech)

• RX enable, TX enable

• Serial Data (RX and TX)

Typical MOSIS Pad

Block Diagram

Hardware Flowchart

Testing• Logic Works

• Component level simulation

• Emac 8051 Development Board - Keil

• Test RF module

• Communication protocol

• Xilinx CPLD – Renoir / ModelSim

• ISA bus timing tester

• Component level design

Address Decoding – Logic Works

Address Decoder - Renoir

Address Decoder - VLSI

Shift Register – Logic Works

Shift Register - Renoir

Shift Register – VLSI

9 Bit Counter – Logic Works

9 Bit Counter – Renoir

Shift Counter – Logic Works

Shift Counter – Renoir

Combination – Renoir

ISA bus timing simulation – ModelSim

Computer ISA development board and Xilinx CPLD

Linx RF transceiver

VHDL Testing

EMAC Testing

• Serial Transmission Testing

• Assembly code emulates serial transmission to and from the RF module

Implementation / Problems• EMAC

• Transmitter and Receiver Code

• Renoir / FPGA

• Large learning curve using Renoir

• Xilinx XC4200 cannot implement flip flops with both asynchronous set and reset

• CPLD implementation

• Software deficiencies, Address line loading, grounding

Future Improvements• Newer bus

• PCI (Peripheral Component Interconnect) or USB (Universal Serial Bus)

• ISA bus is obsolete

• Plug and Play allows easy configuration

• Hardware Error Detection / Correction

• Take software responsibility from CPU

• Larger Buffer / Shift Register

• Send information as packets

• Less time wasted during TX/RX transitions

Proposed Schedule• Dec – Jan (Break)

• More “preliminary” design work (Begin Logic Gates)

• Feb

• Finish Logic Design

• Begin Simulation

• March

• Finish Simulation / Begin drawing in LEDIT

• Implement design on FPGA / CPLD

• April

• Finish drawing gates in LEDIT / Present at Expo

Solari, Edward. ISA and EISA Theory and Operation. Annabooks, 1994.

Mazidi, Muhammad Ali. The 80x86 IBM PC and Compatible Computers Third Ed. Prentice-Hall Inc., 2000.

www.xilinx.com

Renoir Architecture Tutorial (http://cegt201.bradley.edu/tutorial/)

References

QUESTIONS?

Visit http://cegt201.bradley.edu/projects/proj2002/asdf