wings to your thoughts… a high performance … high performance bus invert encoding and...keywords...

webpage: www.ijaret.org Volume 2 Issue VII July 2014 ISSN 2320-6802

INTERNATIONAL JOURNAL FOR ADVANCE RESEARCH IN

ENGINEERING AND TECHNOLOGY WINGS TO YOUR THOUGHTS…

A High Performance Bus Invert Encoding and Decoding

Technique Using Reversible Logic

Kumari Khushboo1, Ghanshyam Jangid

2

1 Research Scholar, Suresh Gyan Vihar University, Jagatpura, Jaipur

[email protected] 2 Corresponding Author (Assistant Professor), Suresh Gyan Vihar University, Jagatpura, Jaipur)

[email protected]

Abstract: - Low power VLSI circuit design is one of the most important issues in present day technology. One of the ways of

reducing power is to reduce the number of transitions on the bus. The main focus here is to present a method for reducing the

power consumption of compressed-code systems by inverting the bits that are transmitted on the bus . Compression will

generally increase bit-toggling, as it removes redundancies from the code transmitted on the bus. Arithmetic coding

technique is used for compression /decompression and bit-toggling reduction is done by using shift invert coding technique.

Therefore, there is also an additional challenge, to find the right balance between compression ratio and the bit-toggling

reduction .This paper presents a bus invert coding on reversible logic using Feynman, Feynman double gate, BJN and SCG

gates .We thus reduced the area and speed of the system. We proposed a high performance bus encoder techniques using a

new gate named as “KK Gate”. We have found remarkable changes in speed, area, garbage output, constant input and gate

count.

Keywords – Reversible Logic, Circuit Design using Reversible Gates, Reversible Logic Gates, and Bus invert coding, Xilinx

Isim simulator, Xilinx Vertex 5 FPGA platform.

1. INTRODUCTION Landauer proposed that, in a single bit of information

loss, kTln2 joules of energy dissipates, where K is the

Boltzmann’s constant and T is the absolute temperature at

which the bit loss operation has been performed. Thus,

the amount of energy lost has direct relationship to the

number of bits erased during computation involving

conventional logic gates. Bennett [1] showed that circuits

built using reversible logic gates dissipate no energy as

they have zero internal power. According to Gordon

Moore, enactment of integrated circuit continues to

improve at an exponential rate and doubles in every 18

months, hence generates a lot of heat and reduces the life

of the circuit. The classical computer consists of

conventional logic gates for processing large amount of

data. In conventional gates only the NOT gate is

reversible gate, i.e. in which input and output are uniquely

retrievable from each other.

Bus-Invert method is the one used to coding and decoding

the I/O which lowers the bus activity and thus decreases

the I/O peak power dissipation by 50% and the I/O

average power dissipation by up to 25%. This is fortunate

because buses are indeed most likely to have very large

capacitances associated with them, thus systems with

conventional logic gates causes’ power dissipation and

energy loss in the system [2] in order to overcome these

we have to use reversible logic with reversible logic gates.

We have shown this concept in sections. Each and every

section describes some specific points about the topic.

Section I shows the introduction, section II shows some

details about reversible logic gates. Section III gives

information about bus invert encoding section IV shows

my proposed work. Section V shows results and

computation and section VI gives details of conclusion

and future work.

2. REVERSIBLE LOGIC GATES For a reversible logic gate will be having a × function

and it is said to be reversible if and only if m = n i.e. equal

number of inputs and equal number of outputs. IV = (I1, I2,

I3......Im) and OV = (O1, O2, O3.....On), where IV and OV are

the input and output vectors respectively where m = number of inputs, and n = number of output. A Reversible

Gate will be having following requirements:

the input vector can be uniquely determined by

the output vector.

there is a one-to-one correspondence between the

input and the output assignments.

there should not be a fan-out of more than one.

Feedback is not allowed in reversible logic

circuits.

There exist several reversible gates in the literature we

will discuss few preferable gates required for our design:

Feynman Gate:

Feynman gate [3] is a 2*2 gate and is also called as

Controlled NOT and it is widely used for fan-out

purposes. It has Quantum cost one. The Feynman gate is

shown in Fig. 1.

Figure 1: 2*2 Feynman Gate




Feynman Double Gate (F2G):

Feynman double Gate (F2G) [4] is a 3*3 gate. Quantum

cost is equal to 2.The Feynman double gate is shown in

Fig. 2.

Figure 2: 3*3 Feynman Double Gate (F2G)

BJN Gate:

BJN Gate [5] is a 3*3 gate with inputs (A, B, C) and

outputs P=A, Q=B and R= (A+B) C. Quantum cost is

equal to 1. The BJN gate is shown in Fig. 3

Figure 3: 3*3 BJN gate

Six-correction logic Gate (SCL):

SCL [5] is a 4*4 reversible gate. The input (A, B, C, D)

and outputs P=A, Q=B, R=C and S=A(B+C) D.

Quantum cost is equal to 1.The SCL gate is shown in

Fig. 4 .

Figure 4: 4*4 SCL Gate

3. BUS INVERT CODING Bus-Invert method is used to coding and decoding the I/O

which lowers the bus activity and thus decreases the I/O

peak power dissipation by 50% and the I/O average

power dissipation by up to 25% [1]. This happens because

buses most have very large capacitances associated with

them and consequently dissipate a lot of power. Let’s

denote as the data value (Pd) the piece of information that

has to be transmitted over the bus in a given time-slot.

Then the bus value (Din) the coded value (the actual value

on the bus). The Bus- Invert method proposed here uses

one extra control bit called invert. By convention then

invert = 0 the bus value will equal the data value. When

invert = 1 the bus value will be the inverted data value.

The peak power dissipation can then be decreased by half

by coding the I/O as follows (Bus-Invert method):

i. Compute the Hamming distance (the number of

bits in which they differ) between the present bus

value (also counting the present invert line) and

the next data value by using the majority voter

logic circuit.

ii. If the Hamming distance is larger than n/2, set

invert = 1 and make the next bus value equal to

the inverted next data value.

iii. Otherwise let invert = 0 and let the next bus value

equal to the next data value.

iv. At the receiver side the contents of the bus must

be conditionally inverted according to the invert

line, unless the data is not stored encoded as it is.

4. PROPOSED WORK In this paper we have worked on the area and speed

basically. We remarkably reduced the speed and area.

Also we have reduced the constant input and garbage

output both by 5 which is the most important factor for

speed and more functioning of bus. The more the number

of times the bus will function more the peak power

dissipation and average power dissipation will occur.

We have proposed new gate, i.e, KK Gate [7]. It is 3*3

reversible gate. The input (A, B, C) and outputs (P, Q, R)

where P=A, Q=A. B C and R= (A B) (C A B).

MHNG gate [7] is replaced by this gate. MHNG Gate 4*4

reversible gate in which there is one constant output and

one garbage input. Thus, we have invented new gate

called KK gate in fig. 5

Figure 5: 3*3 KK gate

The Fig. 6, Fig. 7 and Fig.8 shows the Bus invert encoder

and decoder and majority voter logic circuits using

Reversible logic gates.




Figure 6: Bus Invert Encoder using Reversible

Logic Gate

The bus invert encoder has F2G gate .Q pin of F2G gives

the result after comparing the previous data and new data.

The new data is transmitted to the majority voter for

comparison and to the D flip flop. Majority voter analyses

after that and gives the result by dividing the data.

Figure 7: Bus Invert Decoder using Reversible

Logic Gate

Bus invert decoder takes the input from encoder and

decodes according to the data input(bus width). Means if

input of encoder is inverted then decoder output is

inverted also, otherwise not.

Figure 8: Majority Voter logic circuit using

Reversible Logic Gates

Majority voter circuit compares the 2 parts of the divided

input. If hamming distance data is greater than half of the

bus width, it output become high. Otherwise it would

remain low.

5. RESULTS AND COMPUTATION The new gate that we have designed i.e. K. K. logic gate,

its quantum cost is 4. The entire architecture is

programmed using Verilog. The coding is done on Xilinx

ISE 9.2 on Vertex 5 FPGA. Simulation can be done using

Xilinx ISim simulator. For the design of Reversible Bus

Invert Encoder and Decoder we must use reversible gates

such as F Gate, F2 Gate, BJN Gate and SCL gate and KK

gate. Fig. 9, Fig.10, shows the RTL schematic diagram

and output waveform of bus invert encoder and decoder

circuit respectively. Some remarkable changes has been

noticed during comparison has been noticed in area,

performance, gate count, constant input, garbage output

etc. Table 1.

Previous work Proposed work

Gate count 7 7

Garbage output 23 17

Constant input 8 4

Speed 2.536 ns 2.528 ns

Area

(no. of slices)

20 15

Table 1: Difference between pervious bus

invert encoder and proposed bus invert

encoder




Figure 9: RTL schematic of encoder and decoder

Figure 10: Output waveform of encoder and

decoder

6. CONLUSION AND FUTURE

WORK Here in this paper we have tried to attain bus invert coding

circuit by using some of the basic reversible gates.

Although the Bus Invert method was explained in the

particular setting of dynamic I/O power dissipation the

same methods can be applied in any case where large

capacitances are involved. Furthermore it is likely that the

method will also reduce the total I/O overlap current. We

can also this algorithm and technique for on high bus

width like 16, 32, 64. We also plan to further study the

theory of limited weight codes and in particular their

relationship to error correcting codes. In the end we

would like to say that our work is more efficient than

previous work. It is interesting to mention that the bus

invert method decreases the total power dissipation

although both the total number of transition and the total

capacitance.

REFERENCES [1] C.H. Bennett, “Logical Reversibility of

Computation”, IBM J. Research and Development,

pp. 525-532, November 1973.

[2] R. Landauer, “Irreversibility and Heat

Generation in the Computational Process”, IBM

Journal of Research and Development, pp. 183-191,

1961.

[3] Feynman R., 1985. Quantum mechanical

computers, Optics News, 11: 11-20.

[4] B. Parhami , “Fault tolerant reversible circuits”, in

Proceedings of 40th Asimolar Conf. Signals, Systems,

and Computers, Pacific Grove, CA, pp. 1726-1729,

October 2006.

[5] Raghava Garipelly, P.Madhu Kiran, A.Santhosh

Kumar “A Review on Reversible Logic Gates and

their Implementation” International Journal of

Emerging Technology and Advanced Engineering

Volume 3, Issue 3, March 2013

[6] Mircea R.Stan,Wayne P.Burleson “Bus Invert

Coding For Low Power I/O” IEEE Transactions on

VLSI Systems,Vol.3,No.1,March 1995

[7] Naveena Pai G., “Design and Synthesis of Bus

Invert Encoding and Decoding Technique Using

Reversible Logic”,International Journal of

Engineering Research and Application IJERA, Vol. 3,

Issue 4, Jul- Aug 2013, pp. 143-146.

[8] Md. Belayet Ali , Hosna Ara Rahman and Md.

Mizanur Rahman “ Design of a High Performance

Reversible Multiplier” IJCSI International Journal of

Computer Science Issues, Vol. 8, Issue 6, No 1,

November 2011

[9] Raghava Garipelly, P.Madhu Kiran, A.Santhosh

Kumar “A Review on Reversible Logic Gates and

their Implementation” International Journal of

Emerging Technology and Advanced Engineering

Volume 3, Issue 3, March 2013

wings to your thoughts… a high performance … high performance bus invert encoding and...keywords...

Documents