Why did we want AFE12 in the first place?

We want dual range for both trigger and digitized signals

For the digitized signals, we need a large dynamic range:

• Want ~ 60-80 MIPs to avoid saturation of shower signals

**• Want PS information to correct calorimeter energy for energy loss in magnet, lead **• Want to calibrate on MIP signals in single strips. Would like ~10 cts/MIP **

Solutions exist to give all requirements with AFE12 with sensible charge splitting capacitors; waiting for final design to fix the splits.

Could/should DØ run with AFE8 only?

Apr. 5, 2001

FPS test beam data and Simulations

PS use for Cal EM calibration

Need CPS energy to regain CCEM resolution, particularly at high At want CPS energy deposit calibration to < 10%

Need for FPS calibration not as severe, but still needed

MIP Calibration

Get sample in 1 hr with event rate of 10 Hz (moderate ET jet triggers)

For 80 hits per strip, rms < 3%. No special selection other than requiring that neighbor strip be < 0.1 MeV

Want 10 counts/MIP (in high gain channel)

Select strips with neighbors < 10%

10 counts/MIP

For trigger, want two thresholds available

• Want threshold in range 2 – 5 MIPs to allow low energy electron, di-electrons, tri-lepton triggers (J/, , b e X, chargino/neutralino trileptons … )

• For W/Z, top, Higgs triggers, want higher threshold to help control rates at high luminosity. (Will perhaps not use preshower elements in W/Z triggers until it is absolutely necessary for rate control, since we want the most efficient and least biassed triggers possible.)

CPS axial and stereo signals are mixed with CFT stereo on AFE12 boards. 64 CPS signals per VLPC/cassette module split on MCM board to the dual MCM daughterboards from modules 3,4,5,6.

**

n.b. Although VLPC’s for a given detector are chosen to have ~equal gain, this does not mean that they have the same bias voltage!

1

2

3

4

5

6

7

8

2

5

1

2

1

3

4

4

3

8

5

6

6

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7

8

Warm fiber/VLPC modules. 64(E) and 64(W) waveguides /module

MCM daughter boards (SIFT+SVX) 64 channels used

Backplane Backplane

Boa

rd to

p Board top

Right hand bd Left hand bd8 MCM Cassette (2 Analog Front End Bd) CFT

64

North (front)

South (back)

64

64

64

64

64

64

64 64

64

64

64

64

64

64

64

VLPC chips -- 8 pixels/chip

1

2

3

4

5

6

7

8

2

1

2

112

11

11

12Backplane Backplane

Boa

rd to

p Board top

Right hand bd Left hand bd12 MCM Cassette (2 AFE Bd) CPS/CFT stereo

64

64

64

64

34

56

78

9103

4

56

78

910

64

64

64

64

64

64

64

64 64

64

64

64

North (front)

South (back)

CFT stereo

CFT stereo

CFT stereo

CFT stereo

CFT stereo

CFT stereo

CFT stereo

CFT stereo

CPS low

CPS low

CPS low

CPS low

CPS low

CPS low

CPS low

CPS low

high

high

high

high

high

high

high

high

C1

C2Cd

MCM daughter boards (SIFT+SVX) 64 channels used

Warm fiber/ VLPC modules 64(E)& 64(W) waveguides /module

VLPC

FPS is more complicated since there are 103 MIP layer strips (103 < 128 !) 144 SHWR layer strips (144 = 128 + 16 !) divert 16 SHWR strips to modules 2 & 7 together with MIP strips

**16 strip crossovers in u and in v

Crossover strips now are at low eta (in shadow of solenoid; no lead preceding). It is thought that recabling FPS could make the high eta (small angle) strips be the crossovers.

North

C1

C2Cd

Warm fiber VLPC modules -- 64E (+64W) waveguides /module

2

1

11

12Backplane

34hi

FPS MIP

FPS MIP

FPS MIP

FPS MIP

FPS Sh lo

AFE right -- v strips

1E

55

55

48

48

16

64

64

64

64

16

MIP sect j v strips North

MIP sect j v strips South

SHWR sect j v strips South

SHWR sect j v strips North

55

48

72

72

72

72

48

55

VLPC chips 8 pixel/chip

FPS from detector to MCM - only shown for 12 MCM AFE right (v)

clear waveguide cables - 16 channels/cable

FPS (v) detector strips

Flex cable

(12 MCM AFE left (u strips) is mirror image, through West ports )

5hi

FPS Sh lo

7hi

FPS Sh lo

9hi

FPS Sh lo

6

8

10

72

72

24

24 48

48

48

48

192

192

10355

48

24

24

72

72 192

55

48

103

U strips

U strips

LVDS DFE / daughter bds

DB j North

DB j South

DFEF

2E

3E

4E

5E

6E

7E

8E

96

96

u

u

u

u

East

Down

West

Up

South FPS (from IP)

West

Down

East

Up

North FPS (from IP)

12

3

4

5

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789

10

11

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1516

1098

7

6

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4

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21

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1516

East

Cassettes for FPS-- from East end

1E

2E

3E

4E

5E

6E

7E

8E

9E

10E

11E

12E

13E

14E

15E

16E

FPS N 8 FPS S 8

FPS N 7 FPS S 7

FPS N 6 FPS S 6

FPS N 5 FPS S 5

FPS N 4 FPS S 4

FPS N 3 FPS S 6

FPS N 2 FPS S 2

FPS N 1 FPS S 1

Spare

CFT Stereo

CFT Stereo

CFT Stereo

CFT Stereo

CFT Stereo

CFT Stereo

CFT Stereo

West

East

36W

37W

38W

39W

40W

41W

42W

43W

44W

45W

46W

47W

48W

49W

50W

51W

FPS N 16 FPS S 16

FPS N 15 FPS S 15

FPS N 14 FPS S 14

FPS N 13 FPS S 13

FPS N 12 FPS S 12

FPS N 11 FPS S 11

FPS N 10 FPS S 10

FPS N 9 FPS S 9

CFT Stereo

CFT Stereo

CFT Stereo

CFT Stereo

CFT Stereo

CFT Stereo

CFT Stereo

Spare

Cassettes for FPS-- from West end

12 MCM

12 MCM

12 MCM

12 MCM

12 MCM

12 MCM

12 MCM

12 MCM

12 MCM

12 MCM

12 MCM

12 MCM

12 MCM

12 MCM

12 MCM

12 MCM

8 MCM

8 MCM

8 MCM

8 MCM

8 MCM

8 MCM

8 MCM

8 MCM

8 MCM

8 MCM

8 MCM

8 MCM

8 MCM

8 MCM

Different VLPC classes for MIP and SHWR; modules 2 & 7 have both types. Special modification to cassettes to provide bias voltage appropriate for specific VLPC chips.

Different bias voltages needed

showershowerMIP

MCM 1

MCM 2

MCM 3,4

MCM 5,6

Why would we think of abandoning AFE12 now ?*** Without CFT (axial and stereo) tracking, *** *** DØ is not an experiment. ***

Much (1/3) of CFT stereo readout is on AFE12 (mingled with CPS axial/stereo)

Guess at optimistic AFE12 schedule: 6 wks toM’bd prototype; 4 more wks to D’ bd proto; 4 wks test prototype; 2 wks bid/procure; 4 wks bare bd production; 4 + 4 wks bd assembly; 4 wks prod. bd test; ready to install Xmas (2001). later if use the AFE8 experience! (n.b. others have guessed AFE12 by September)

These considerations had led to plan for spare (throwaway) AFE8 bds; use for the remaining CFT stereo channels until AFE12’s ready. Requires extra 30 AFE8 bds; if only populate the CFTst, need 120+spares MCM’s to be removed and put on AFE12 later. Estimates vary on efficiency of removal of MCM’s (75% -- 25%)

quote (Sanmina) for 28 extra AFE8 bds = $37K. DØ finances not up to this (or even $10K). Do not exercise quote.

There are several people spending time now on AFE12 design/layout; this manpower could be useful for AFE8 debug/test/commission.

Why would we think of abandoning AFE12 now ?

Consider permanent replacement of AFE boards for CFT stereo/CPS with AFE8’s. Stop all design work on AFE12 boards (FPS) for now. FPS in the end could be done with AFE12 or with modified AFE8’s (modification is change in bias voltage feed to accommodate the crossover channels in FPS cassettes as built and threshold references.)

Pro’s: fastest way to full CFT and CPSreduce costs -- expect AFE8 to be roughly

half of AFE12 cost (no ‘spare’ AFE8 now)Can redirect some manpower to AFE8 production

Con’s: FPS is still late (either AFE12 or AFE8’ (end of year??)loss of functionality for CPS trigger/offline

And: Still need some redesign for FPS even if done in AFE8’

Schedule for extra AFE8: 3 months to procure and test??

Options

1. Do nothing -- just complete AFE8 and get full CFT/PS when the AFE12 comes of age (2002??)

2. Buy the insurance of 28 extra AFE8 boards to tide us over AFE12, then scrap when we get AFE12

3. Buy 28 extra AFE8 boards now and leave on CFTstereo/CPS for Run IIa. Start on AFE12 or AFE8’ for FPS when we can.

4. Buy extra AFE boards for CPS/CFTst AND for FPS now (48 boards). Scrap plans for AFE12

Option 1 is uglyOptions 2 and 3 may differ down the line, but have the same next step -- order the 28 AFE8 boards identical to those now being made. These schemes become different when we restart design of AFE12 of AFE8’, or when we decide whether to populate new AFE8 with 4 or 8 MCM’sOption 4 differs only in number of AFE8 extras to buy

Can we operate CPS (FPS) with AFE8 successfully?

Will certainly lose the dual range trigger. This means either losing the capability for J/etc. triggers or not using CPS in W/Z triggers. My guess is that we would not want to put CPS into W/Z triggers until it is absolutely needed for rate control -- why add extra inefficiency, trigger corrections etc.? J/studies are mainly for early low luminosity running? But Susy trilepton searches will continue through the run.

Preshowers used to regain good CAL energy resolution; this requires that we not saturate below ~60-80 MIPs. We must be able to calibrate preshower strips relatively. We had planned to use single MIPs for this. So we are fighting for dynamic range.

Standard AFE8 parameters (VLPC gain, SIFT gain etc.) give saturation for preshowers. That’s why we had charge splits on Preshower inputs. Are there appropriate working conditions for CPS/FPS? (remember that CPS strips see roughly 3 times signal at ends of strips as at 90o )

QE Gain

Noise Charge

Varying bias voltage can change QE, Gain, Noise, Charge = QE x Gain. Can ‘tune’ charge downwards by factor 3 or so before QE falls off; upward tune dependent on where the noise rate is too high, but probably not more than 30% increase from nominal.

Input Constants value units (bold=input numbers)1 fC 6250 e/ fCVLPC gain; CPS 26500 e/peVLPC gain; FPS shwr 29500 e/peVLPC gain; FPS MIP 39000 e/peVLPC chrg out/ CPS 4.2 fC/ peVLPC chrg out/ FPS shwr 4.7 fC/ peVLPC chrg out/ FPS mip 6.2 fC/ peSIFT input noise 2.7 fClayer MIP CPS 90 deg 9 pe/MIPlayer MIP -- CPS 90 deg 38.16 fC/MIPlayer MIP -- CPS 45 deg 18 pe/MIPlayer MIP -- CPS 45 deg 76.32 fC/MIPlayer MIP FPS 90 deg 9 pe/MIPlayer MIP -- FPS shwr 45 deg 13 pe/MIPlayer MIP -- FPS shwr 45 deg 60 fC/MIPlayer MIP -- FPSmip 45 deg 13 pe/MIPlayer MIP -- FPSmip 45 deg 79 fC/MIPSIFT max threshhold 160 fCSIFT min threshhold 20 fCSVX ramp full range 150 fCSVX full scale cnts 256 counts

Caps value units Jan. 20, 2001(bold=input numbers)

C cable 30 pF input cable capacitanceC drain 15 pF cap to ground to drain some chargeC1 shr CPS 50 pF input to higher gain channel for dual MCM CPSC2 shr CPS 25 pF input to lower gain channel for dual MCM CPSC1 shr FPS 40 pF input to higher gain channel for dual MCM FPSC2 shr FPS 20 pF input to lower gain channel for dual MCM FPSCin MIP 100 pF input to single MIP FPS layer channel(Ctot) CPS 120 pF total capacitance CPS(Ctot) FPS 105 pF total capacitance FPS

Input constants for PS (for AFE12)

CPS settings

FPS settings

for central value Caps CPS center CPS 45 deg Units Gain = High Low High LowNominal Charge fraction 41.7% 20.8% 41.7% 20.8% Drain charge ---> 37.5% ---> 37.5% 31.0%one pe 1.77 0.88 1.77 0.88 fC lowest SIFT thrsh 0.63 1.26 0.31 0.63 MIP highest SIFT thrsh 10.06 20.13 5.03 10.06 MIP Lower desired thresh 2.0 5.0 1.0 2.5 MIP Higher desired thresh 5.0 10.0 3.2 5.0 MIP Input charge low thrsh 31.8 39.8 31.8 39.8 fC Input charge high thrsh 79.5 79.5 79.5 79.5 fCSIFT output gain 0.388 0.194 0.388 0.194SVX ramp full scale 150 150 150 150 fCSVX full scale 24.3 97.3 12.2 48.6 MIP SVX resolution (cnt / MIP) 10.5 2.6 21.1 5.3 ct / MIPSVX resolution (cnt / pe) 1.17 0.29 1.17 0.29 ct / pe

for central value Caps FPS Dnstrm FPS Units Gain = High Low UpstrmNominal Charge fraction 38.1% 19.0% 69.0% Drain charge ---> 37.5% ---> 31.0%one pe 1.80 0.81 4.30 fC lowest SIFT thrsh 0.44 0.87 0.18 MIP highest SIFT thrsh 6.99 13.98 2.92 MIP Lower desired thresh 2.0 5.0 0.2 MIP Higher desired thresh 5.0 10.0 0.5 MIP Input charge low thrsh 45.8 57.2 11.0 fC Input charge high thrsh 114.4 114.4 27.4 fCSIFT output gain 0.388 0.194 0.388SVX ramp full scale 150 150 150 fCSVX full scale 16.9 67.6 7.1 MIP SVX resolution (cnt / MIP) 15.2 3.8 36.3 ct / MIPSVX resolution (cnt / pe) 1.19 0.30 2.85 ct / pe

85%

13.633.8

Settings with AFE12

Current plan for AFE12 prototype is to omit the ‘virtual SVX’ – reads out the SIFT discriminator bits for the preshowers to Level 3. (heat dissipation on close-spaced daughter boards, total power to AFE, space for CPLD chips)

Loss is that we do not have a record of discriminator bits set at L3 for debugging the operation of the digital L1 trigger algorithm.

The bits of course go directly to the DFEA, DFEF, DFES boards. The Glink outputs for disc. bits to L3 could be installed for CPS stereo and FPS, not CPS axial. We are investigating sending CPSax bits to CTOC boards for L3 during special operation. 640 bits per CTOC to L3; may be OK.

If we operate preshowers with AFE8 as is

• There is only one gain/trigger threshold. We thus lose dynamic range. With the standard VLPC gains, unsplit signals saturate at only a few MIPs, so we cannot see SHWR signals – cannot correct the Calorimeter energy and thus lose EM resolution.• We may lose at least the 24 FPS crossover strips in both trigger and digitized data streams; their VLPCs not biassed appropriately. Can’t set desired high thresholds SVX saturates ; can’t see shower deposits

for central value Caps CPS CPS FPS FPS Units 90 deg 45 deg Dnstrm Upstrm

Fract. Charge input 76.9% 76.9% 76.9% 87.0%one pe 3.26 3.26 3.63 5.43 fC lowest SIFT thrsh 0.68 0.34 0.43 0.29 MIP highest SIFT thrsh 6.82 3.41 4.33 2.89 MIP Lower desired thresh 3.0 1.5 5.0 0.2 MIP Higher desired thresh 10.0 5.0 10.0 0.5 MIP Input charge low thrsh 88.0 88.0 231.0 13.8 fC Input charge high thrsh 293.5 293.5 462.0 34.5 fCSIFT output gain 0.194 0.194 0.194 0.388SVX ramp full scale 150 150 150 150 fCSVX full scale 26.3 13.2 16.7 5.6 MIP SVX resolution (cnt / MIP) 9.7 19.4 15.3 45.8 ct / MIPSVX resolution (cnt / pe) 1.08 1.08 1.20 3.59 ct / pe

If we can reduce charge input to SIFTs, have a much better situation. If keep 25% - 35% of charge and standard SIFT/SVX transfer gains:

For 10 - 15 pF input CPS CPS FPS FPS Units std. Xfer gain center 45 deg Dnstrm UpstrmFract. Charge input 35.0% 35.0% 25.0% 80.0%one pe 1.48 1.48 1.18 4.99 fC lowest SIFT thrsh 1.50 0.75 1.33 0.31 MIP highest SIFT thrsh 14.97 7.49 13.32 3.15 MIP Lower desired thresh 3.0 1.5 5.0 0.2 MIP Higher desired thresh 10.0 5.0 10.0 0.5 MIP Input charge low thrsh 40.1 40.1 75.1 12.7 fC Input charge high thrsh 133.6 133.6 150.2 31.8 fCSIFT output gain 0.194 0.194 0.194 0.388SVX ramp full scale 150 150 150 150 fCSVX full scale 57.9 28.9 51.5 6.1 MIP SVX resolution (cnt / MIP) 4.4 8.8 5.0 42.1 ct / MIPSVX resolution (cnt / pe) 0.49 0.49 0.39 3.31 ct / pe

X

Can probably live with the dynamic range in this case … some truncation for very large ET electron/photons but not all PS layers will saturate (only one needed for CAL correction).5 counts/MIP is marginal for MIP relative calibration.

These calculations need independent confirmation !

To reduce the charge presented to SHWR layer SIFT:• Can reduce bias to lower QE and gain, but must avoid too small QE where probability of 0 pe becomes large. Perhaps reduce charge to ~50%

• Can lower input capacitor value to SIFT (from 100 pF to 10pF) and get as low as 25% input charge transfer. Simple component change on board. Charge split = CIN / (CIN + CCABLE ) = CIN / (CIN +30 pF) Combination of the above two changes should give enough flexibility to solve Shwr layer range

Would prefer not to modify the AFE boards that take CFT stereo/CPS since we need these first. Modification to AFE8 for FPS needed anyway to allow crossover channel bias control.

Charge

Calibration is an issue. Correction of calorimeter energy for early shower contribution requires < 10% relative calibration of preshower strips (absolute calibration unneeded – fit the sampling fractions for best resolution). Monte Carlo study showed that MIP calibration was rather unstable when the digitization is as coarse as 3 counts/MIP, but it may still be possible ?? Could have special calibration run with high (0.4 - 0.5) SIFT to SVX transfer gain; gives ~10 ct/MIP. Requires that AFE operation is stable over long enough times to avoid frequent calibrations.Could think of relative calibration of CPS using symmetry of shower deposits. Such relative calibration for FPS is difficult, as the strips are at different eta (different energy particles), and with variable material in front.

Running preshowers with AFE8 would regain the virtual SVX readout, hence better ability to debug. (a minor bright spot !)

Effect of differential nonlinearity on AFE8 preshower operation. (not so different for AFE12 !)

Operating conditions suggested above have 4-8 counts/MIP. DNL peaks at 8 counts would then be roughly at 1 -2 MIP intervals. The mean deposit in the preshower for 40 GeV electrons is about 45 MIPs (**) Thus might expect a jitter of +/- 0.5 - 1 MIP due to DNL would be a few % shift from true to observed energy. Our spec is to have calibration of preshower scale to 10%, so it seems that the DNL does not strongly affect ability to correct the Calorimeter energy at the W/Z.

Calibration of the Preshower was expected to use single MIP traversals. DNL at level of +/- 0.5 MIP will clearly render this method unusable. Recourse would be to use azimuthal symmetry for high energy electrons from standard data stream. No study of this. For forward preshower this won’t work.

Summary:We can imagine operating preshowers with AFE8:Losses: cannot trigger on both high and low energy e/Someone’s physics suffers dynamic range suffers (would compromise MIP calibration ability at best; at worst, would saturate Shower layer strips for trigger and SVX digitization)

Possible loss of the 24 cross-over channels because VLPC bias not appropriate

Problems to be solved: How to reduce the charge seen at input to SIFT?

modify VLPC bias voltage (changes to AFE8 cassettes for preshower signals). Believed possible for x2 reduction modify AFE8 board input cap. to give

effective charge division? Seems possible to give x 3-4 reduction.. Time to to develop vendor and produce extra AFE8s for CFT stereo/CPS use ~ 3 months?? Another 3-4 months for FPS AFE8 or AFE12 ??

Added manpower needed to develop new order