What’s New in OrCAD/Allegro 16.6

QIR4

OrCAD Capture

What’s New in QIR4

• Mechanical Parts in Capture – Allegro

• Enhancements in Display Properties dialog

• Enhancement in Comment Text

• Capture Viewer

• Capture - Sigrity SI flow license

• Miscellaneous Enhancements

– Accelerator Support

– Double quotes support in part references of variant.lst

– Enhancements in Capture INI Manager

Mech Parts in Capture-Allegro Flow

• include a zero pin

mechanical part

– bar codes

– mechanical holes

– Fiducials

• CLASS=MECHANICAL

Display Property Enhancements

• New Display format called Value if Value Exists

• Displays value only if value exists

• can be used for those properties where the name

should not be visible

– Tolerance

– Power

– …

Enhancement in Comment Text

• Comment text in Capture can be netlisted to Pspice

• Add @PSpice at the start of the comment

• The comment directive(s) should only be used on

the top level page of the design

• Only for those parameters, which are not added

using PSpice Setup

Capture Viewer

• View Capture design files as read-only

• Enter capture.exe -viewer on the command prompt

• Capture Viewer does not checkout any license

• Capture Viewer is different from OrCAD Lite as it

does not limit the size of the design being viewed

• No CIS data is viewable

• Capture needs to be

closed before

Capture - Sigrity SI flow license

• Invoke Signal Explorer from Explore Signal menu in

Capture to run Sigrity SI using PA7500 license

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OrCAD Capture

• Capture Viewer

• Mechanical Parts in Capture

PSpice

What’s New in QIR4

• Expression support in .TRAN, .OPTIONS, and

.FOUR commands

• Parameter support in .PROBE command

• New Convergence options in .OPTIONS command

• TCL Functions support in circuit file

• Ignore DML check in IBIS2Spice

• Global Parasitic Support

• Enhancements in Learning Pspice

• Frequency Response Analysis

• Documentation Enhancements

Expression support

Expression support is provided for the following

commands:

• .TRAN - for TSTART, TSTEP, and TSTOP

• .FOUR - for fundamental frequency

• .OPTIONS - for MINSIMPTS

– MINSIMPTS option specifies the minimum number of

points per section in simulation output. It helps in

improving the output resolution

PARAMETERS:

FREQ = 100

@PSpice:

.TRAN 0 {5/Freq+.1m} 0.1m

.STEP OCT PARAM FREQ 0.1 1MEG 3

.PROBE64 P(FREQ)

.options MINSIMPTS = 1000

Parameter support

• Define parameter using .PARAM command

• Add Parameter to .PROBE command

• .PROBE64 P(FREQ)

.TRAN 0 {5/Freq+.1m} 0.1m

.STEP OCT PARAM FREQ 0.1 1MEG 3

.PROBE64 P(FREQ)

.options MINSIMPTS = 1000

New Convergence options

• PREORDERMODE option

• MINSIMPTS option

• RMIN option

• BPPseudoTran option

• TRANCONV1 option

PREORDERMODE option

• PSpice SOLVER = 1 uses PREORDER only once in

the simulation, that is, at the start of the simulation

• But now by enabling PREORDERMODE option,

PREORDER gets executed in every simulation

iteration

• Using PREORDERMODE option improves accuracy

and convergence properties of the simulation server

• Note: This is may be added as PSpice Directive in

Capture Schematic using comment text

MINSIMPTS option

• Using MINSIMPTS you can override default 50 time points for any given TSTOP value

• This option allows user to control minimum points that must be executed in a simulation run

• For example, setting MINSIMPTS=1000 ensures that at least 1000 points are generated at equal timestep (The simulator may take a shorter timestep for accuracy reasons)

• MINSIMPTS option is useful if expression is used for TSTOP and if transient analysis data is required for post-processing of algorithms, such as Fourier Analysis

RMIN option

• PSpice implements an internal minimum timestep (delta)

value, which if reached can result in convergence failure

• Now RMIN allows user to override the minimum timestep

value

• When used with other transient convergence options, a

higher RMIN value can improve performance depending

upon the circuit

• The higher RMIN value forces the simulator to move to

different convergence continuation methods rather than

going to lower Delta value

• A lower RMIN value may resolve some convergence

issues as well

BPPseudoTran option

• A Biaspoint convergence may be slow due to

absence of capacitors and indictors from the circuit,

such as circuits using behavioral elements

• BPPseudoTran option forces PSpice simulator to

use PseudoTran algorithm instead of regular

biaspoint algorithm

• Note: This is may be added as PSpice Directive in

Capture Schematic using comment text.

TRANCONV1 option

• This option enables an internal continuation method

• fix convergence failure during transient analysis

TCL Functions support in circuit file

• PSpice allows execution of TCL script from PSpice

Engine.

• .TCLPOSTRUN command

• This command is called after simulation

• Any operation can be performed after simulation

– post-processing of the DAT file

• .TCLPOSTRUN postrun.tcl.

• Note: .TCLPOSTRUN command may be added as

PSpice Directive in Capture Schematic using

comment text

Ignore DML check in IBIS2Spice

• For orPSpiceParsers, a new parameter has been

added to ignore DML

• -skipDMLCheck

• check errors while generating output file from IBIS

file

Enhancements in Learning PSpice

• A new book called Power

Electronics Design Examples is

available in Learning PSpice.

• Explains Single Switch Forward

Converter using a design example,

which can be simulated using

PSpice and taken to PCB layout

• Note: You can access Learning

PSpice in Capture - PSpice flow only

• To access Learning PSpice, choose

Help- Learning PSpice in Capture

Global Parasitic Support

• New parameters have been added in .OPTIONS command to support parasitic globally for devices: – Junction Gate Field-Effect Transistor Capacitance (JFETCJ)

• gate-to-source capacitance (Cgs)

• gate-to-drain capacitance (Cgd)

– Metal–Oxide–Semiconductor Field-Effect Transistor Capacitance (MOSCJ) • gate-to-source overlap capacitance (Cgso)

• gate-to-drain overlap capacitance (Cgdo)

• zero-bias bulk-to drain junction capacitance (Cbd)

• zero-bias bulk-to-source junction capacitance (Cbs)

• zero-bias bulk junction bottom capacitance (Cj)

• zero-bias bulk junction sidewall capacitance (Cjsw)

• Also, Bipolar Junction Transistor Capacitance (BJTCJ) has been enhanced with zero-bias collector substrate capacitance (Cjs)

• For more information, see PSpice Reference Guide

Frequency Response Analysis

• You can now perform frequency response analysis to get frequency response of the non-linear switching circuits having varying operating point

• RA is an open-source application and TCL program in FRA is provided to: – Develop HTML5 GUI with PSpice

– Access transient analysis data from DAT file

– Use TCL interpolate functions to get equidistant points from transient analysis data

– Perform fourier analysis in TCL

– Create a PSpice DAT file for frequency response using TCL, to view in Probe

• Note: To enable Frequency Response Analysis, choose Tools - FRA in PSpice.

Documentation Enhancements

• New Tutorial: Simulating an SMPS Design using Capture-PSpice Flow – new tutorial walks you through OrCAD Capture - PSpice

flow using an Switched Mode Power Supply (SMPS) design

– configure the design for simulation, simulate the design using Pspice

– use Advanced Analysis to verify stability and yield of the design

• Reorganization of Content: Co-Simulation using PSpice SLPS Interface – Content has been reorganized to create a tutorial that

walks you through the various steps to perform co-simulation using the PSpice SLPS Interface using the example of an electronic cruise system

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PSpice

• Netlisting Comment Text

• Expression Support

• Frequency Response Analysis

Allegro Design Entry HDL

What’s New in QIR4

• Hierarchical Split Symbols

• Page Setup Options in Design Publisher

Hierarchical Split Symbols

• provides a solution to manage large hierarchical

block symbols by splitting them into multiple split

symbols

• split the ports of a hierarchical block across multiple

symbols

• reduces the size of the block symbol

Page Setup Options in Design

Publisher

• Support for specifying page setup options

– measurement unit

– page size

– Orientation

– Margins

– scaling factor

• Available from the UI

as well as the

command line

PCB Editor

What’s New in QIR4

• Allegro STEP Model Mapping Enhancements

• Allegro Timing Environment

• IPC2581 Enhancements

• Productivity Enhancements

Allegro STEP Model Mapping

Enhancements • Primary and Secondary STEP model

mapping feature – Map a high resolution STEP model as

primary, a low resolution model as secondary. Low resolution has a smaller file size STEP model.

– Map STEP models with alternate mounting type

– STEP export can export low resolution STEP model to create a smaller exported board STEP model.

• Mapping Graphics Enhancements – Enhanced performance.

– Center mouse button/wheel zoom control feature in graphics window.

– Right Mouse button pan feature in graphics window.

Allegro STEP Model Mapping

Enhancements

Updated Mapping Controls

• Left mouse button used to drag STEP model for proper alignment

• Incremental value used with arrow buttons to move STEP model in

drawing units

Allegro Export as STEP

Enhancements • Export Secondary STEP

models

– New Option to export STEP models assigned as Secondary STEP models

• Export by Highlight

– Exports only those highlighted in the Allegro drawing

– Board, mechanical holes, and Assembles may also be exported with highlighted symbols

Allegro Timing Environment

• High Speed Product Option

• Introduced over the last several QIRs as

unsupported prototypes, the ATE suite of features

are now available

IPC2581 Enhancements

• Shorted Nets:

Nets shorted by the

NET_SHORT property

will be exported

• BOM populate support: If the property BOM_IGNORE is

set to a component instance, Allegro PCB Editor will

export <RefDes name = "***" populate = "FALSE"/>

under <BomItem> in the IPC2581 output file

Productivity Enhancements

• Voids in Keepout Shapes

• Artwork Control Form update

• Allegro PDF Publisher

• Relative Snapping

• Ref-Des Layer Visibility Control

• Dynamic Shapes

• Testprep – Add Scan and Highlight update

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PCB Editor

• STEP Mapping

• STEP Export

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