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1 March 8, 2013

A DAY IN THE LIFE OF A MEMORY ARCHITECT

Hany Fahmy Master High-Speed-Digital App. Expert Agilent Technologies Charles Jackson & Charlie Shu & Chen Wang Sr. Managers-SIEMC, Nvidia Corporation Amolak Badesha Sr. R & D Manager, Avago Technologies Ahmed M. Attiya Associate Prof. , King Saud University Romi Mayder Sr. Signal Integrity Engineer, Xilinx Inc. Davy Pissoort Prof. FMEC-KHBO, K.U. Leuven Hermann Ruckerbauer CEO EyeKnowHow Consultants

WORKSHOP EMEA

Romi Attiya Davy

Introduction

Hany is WW-Business-Development Manager & Master Application Expert for HSD.

Before joining Agilent, Hany was the director of SIE/EMC System Design and Manufacturing at NVIDIA, dealing with the design and analysis of high-speed digital and analog interconnecting systems (DDR3, GDDR3/5, LVDS, HDMI/DP & PCIe) for GPU boards and the Tegra-1/2 Smartphone systems.

Before joining NVIDIA, he worked at Intel for 10-years heading the Memory Architecture Group (MAG) designing system memory (PC100/133, Rambus & DDR1/2/3) for desktop, notebook and workstations based on Intel chipsets and microprocessors. Hany also worked at Micron and TI.

He has a Ph.D. in Computational Electromagnetics of MMIC from the University of Toronto and an M.Sc. and a B.Sc. from Cairo University in Egypt.

2

AGENDA A Typical HSD system

Why do we need RF-tools for HSD? GHz Age for HSD

Common SI/PI/EMI Problems for a Memory-Channel Design

Workflow Optimization for Best Channel Performance

MOM best modeling technique for Packages & PCBs

Return-Path-Discontinuity in Memory Controller Packages

“Slow Dancing” PDN & Noise x-talk

State of the Art EMI Workflow for:

Trace-Emission from Packages: Memory Data-bus

3

WORKSHOP EMEA

4

Dramatic increase in HSD Gigabit Rates THANKS “STEVE JOBS” FOR APPLE-INNOVATIONS

2011

USB 3.0 5.0 Gb/s

HDMI 1.4 3.4 Gb/s

DVI 4.95 Gb/s

DP 5.4 Gb/s

PCIe-gen3 8 Gb/s

SATA 6 Gb/s

DDR3 0.8-2.133 Gb/s

Increased Density

High-speed everywhere

Pressure to Reduce cost

A look at Apple Macbook pro

+GPU

Components of DDR3 System Memory Channel for

Mobile applications (Notebook, Netbooks & Tablets)

EMEA 2011 5

Memory-Controller-Hub

PKG

MB for 2-

SODIMMs/channel

in a Daisy-Chain

topology

SODIMM R/C-F SODIMM R/C-F

Where do we find Memory Channel?

PCs & Workstations UDIMMs

Copyright © 2012 Agilent Technologies

6

UDIMM vs. SODIMM vs RDIMM Memory Modules


7

Real PCB + Antenna Performance

13x GPU Speedup: 9-mins (4-GPUs) vs. 120-mins

for 8-cores CPUs

Antenna Mounted on Real-PCB Insertion-Loss of ANT+REAL-

PCB


8

What about x-talk of memory to RF-Antennas!!!!!


9

X-talk from Memory Data-nets Switching to

GSM/GPRS/EDGE Antenna


10

GDDR5 running at 7GB/s

Fermi GPU talking w GDDR5 memory device

March 8, 2013

Confidentiality Label

11

SiP Memory System

Controller Talking to 8-SDRAM Dies

March 8, 2013


12

How the wave travels on Data Nets in SiP?

3D Packages: Vertical Interconnects for A/D

applications

March 8, 2013


14

Are we in the GHz Age? Not ICE-AGE!!! THANKS “XILINX INC.”

March 8, 2013 15

For DDR3-1333-2133Mb/s Models up to 15/20GHz

On Controller-PKG: Break-out to Main TL

Impedance Discontinuity & Tight-Coupling

March 8, 2013 16

On MB: Vias & Via-Stub Discontinuity

March 8, 2013 17

On MB: Surpentine for length-matching of byte-

lanes on MB: Real X-talk vs. pre-layout x-talk

March 8, 2013 18

Why Memory Channel is a Challenge compared to

SERDES?

• Single Ended bi-directional DQ bus running at 7GB/s on FR4

material for GDDR5 apps

• X-talk and Return-Path-Discontinuity is a BIG ENEMY

• No Equalization

• Very limited pre-/de-emphasis techniques

• Very Wide Interface: Almost 150-signals routing

• SDRAM is a very Cheap Commodity device: SDRAM eats

45% of the eye & Controller eats another 30% Leaving ONLY

25% for the FR4 channel

March 8, 2013


19


20

PCB ROUTING GUIDELINE OF A

DDR3 MEMORY CHANNEL FOR A

WORKSTATION


21

22

Channel A Data Byte Group [7:0] Signals

Layer 2

Channel ACh A DIMMs

MCH Pkg

1.0” max

0.3” min

Layer 1

6.5 on 124 on 9 6.5 on 18.54 on 60.7” max 0.6” max 5.0” max 0.5” max

Layer 5

Region A Region DRegion CRegion B

Layer 6

Main T-Line

SE 6.5 mils = 40 Ω ± 15%

• Channel A Bytes 0 - 7

• Signal Layer: 1 or 6 (micro-strip)

• Max Via per Signal = 1

• Signal Referencing = Ground

• DQS/DQS# differential trace spacing 5mils

• DQS/DQS# isolation spacing = 17.5mils and serpentine spacing = 18.5 mils.

23

ChA Byte 8 and ChB Byte [8:0] Data Group Signals

Ch B DIMMs

Layer 2

Region B Region D Region E Region F

Channel BCh A DIMMs

Region CRegion AMCH Pkg

1.0” max

0.3” min

Layer 4

Layer 3

Layer 5

10 on 25 10 on 255 on 10 10 on 510 on 255 on 50.45” max 0.2” max 4.5” max 1.0” max 1.2” max 0.5” max

Main T-Line

SE 10 mils = 35 W ± 10%

• Channel A Byte 8(ECC) and Channel B Bytes 0 - 8

• Signal Layer: 3 or 4 (strip-line)

• Max Via per Signal = 1

• Signal Referencing = Ground

• DQS/DQS# differential trace spacing 5mils

• DQS/DQS# isolation spacing = 25mils and serpentine spacing = 15 mils.

AGILENT = RF

Even FOR DDR1!!!!! SUCCESS STORY FROM

INTEL (1999-2007)


24

What is the benefit of FD

Analysis? FD Analysis:

1. Selects the Optimum Topology

2. Alleviates any channel Resonance

3. Reduce TD Matrix through Sensitivity Analysis

TD Analysis:

Obtain the actual

noise/timing margins per

worst-corners defined

from FD Analysis

FD Optimization Procedure in

Pre-Layout Simulation

Topology Optimization in Frequency Domain

TD Statistical Simulation or FD Sensitivity Analysis

Time-Domain Simulation

Reduce TD Matrix

Grounding, Referencing and Power Distribution

Buffer/Package/Conn/ Stackup Model Generation Based on Previous

Layout Design

For Optimum SQ

Sensitivity

Analysis

Optimization

in FD

Uncontrolled

Parameters

Optimized ?

Controlled

Parameters

Satisfied ?

Uncontrolled

/Controlled

Parameters

Sensitivity Analysis: Gaussian Distribution

Nominal Values: Optimized Values

Std Dev.: 5 or 10%

END

START

Yes

Yes

No

No

DQ/DQS Schematic for FD Topology Optimization

using Multi-layer Library Models DIMMA

DIMMB

P1:DQ

P2:DQS

MCH

GND

P3:DQ

Vtt

P4:DQS

P6:DQS P5:DQ

GND

P7:DQ P8:DQS

P10:DQS P9:DQ

1 3

5


28

3/8/2013

Goals for FD Optimization

Max/min Swing

Slew Rate Max/min

3/8/2013

Simulation Parameters for Optimization

Controllable Parameters

Added Uncontrollable Parameters

Between DIMMs Rtt Stub

Break-in

Examples with some Details:

IBIS Corner Case Simulation

Source: Hermann Ruckerbauer (EKH)

08.03.2013

EKH - EyeKnowHow

31


Routing variations

Source: Hermann Ruckerbauer (EKH) Sweep of dimensions: Length, width, spacing

08.03.2013

EKH - EyeKnowHow

32

Example here: just enable/disable variables.

Better solution: Function to sweeps or batch simulations automatically


Timing budget

Source: Hermann Ruckerbauer (EKH) Selecting Speed adjust tS/H and output timings

08.03.2013

EKH - EyeKnowHow

33

Insert Simulation results

Calculate De-Rating automatically

Margin based on DQS placement

Considered:

Board length matching

Vref noise

Package double count

Original

After Optimization

Z11 [

ohm

]

Z13 [

ohm

]

Before and After Optimization

2 4 6 8 10 12 14 16 180 20

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

0.0

2.0

time, nsec

RYU_

DQ_D

QS_D

DR26

6_33

3_8D

S_8D

S_Rc

h20_

REW

R_TD

_22O

CT01

..VDI

MM

2_DQ

_up,

VRY

U_DQ

_DQS

_DDR

266_

333_

8DS_

8DS_

Rch2

0_RE

WR_

TD_2

2OCT

01..V

DIM

M2_

DQS_

up, V

DQ_D

QS_D

DR26

6_33

3_8D

S_8D

S_Oc

tobe

r_5t

h_20

01_T

D..V

DIM

M2_

DQ_u

p, V

DQ_D

QS_D

DR26

6_33

3_8D

S_8D

S_Oc

tobe

r_5t

h_20

01_T

D..V

DIM

M2_

DQS_

up, V

Original After Optimization

DQ

DQS

Eye Diagrams - WRITE x8DS x8DS

0.0 0.5 1.0 1.5 2.0 2.5-0.5 3.0

0.5

1.0

1.5

2.0

0.0

2.5

time, nsec

eye_D

QS

_4p7nH

eye_D

Q1_4p7nH

0.0 0.5 1.0 1.5 2.0 2.5-0.5 3.0

0.5

1.0

1.5

2.0

0.0

2.5

time, nsec

eye_D

QS

_10nH

eye_D

Q1_10nH

0.0 0.5 1.0 1.5 2.0 2.5-0.5 3.0

0.5

1.0

1.5

2.0

0.0

2.5

time, nsec

eye_D

QS

_15nH

eye_D

Q1_15nH

Original DIMMs

Matched DIMMs

0.0 0.5 1.0 1.5 2.0 2.5-0.5 3.0

0.5

1.0

1.5

2.0

0.0

2.5

time, nsec

eye_D

QS

_22ohm

eye_D

Q1_22ohm

Lab Correlation: Matched vs. Original

x8DS x8DS Topology Matched DIMM Original DIMM

Odd Fall

Even Fall

tDS=

+400ps

tDH=

-400ps

+150mV

-150mV

March 8, 2013 37

WHAT’S NEXT FOR DDR4?

DDR1 TO DDR4

TRANSFORMATION

March 8, 2013


38

Agilent DDR4 Data Valid

Window Measurements

Item 1794.26

1st Showing

September 11, 2012

39

DDR 4 Eye Mask Position and Margins

March 8, 2013 40

Eye mask is centered on DQS crossing and Vcent.

Voltage and timing margin can be measured from each corner of the eye mask.

Impact of Measurement Procedure on DDR4 Spec

The exact meaning of DDR4 AC Parameters is defined by the

precise procedure used to measure them.

Agreement on this is important in replacing TBD values with

realistic numbers.

March 8, 2013 41

DDR 4 TdiVW Timing Margin to Mask (up to 2133).

March 8, 2013 42

TdiVW = minimum time from mask corner to eye.

DDR 4 TdiVW Margin to Mask Detail (up to 2133).

March 8, 2013 43

125ps

62.5ps 62.5ps

% Margin is then (Actual-Spec)/Spec*100% or

(118.8ps-62.5ps)/62.5ps * 100% = 90%

DDR 4 Eye Voltage Margin to Mask (up to 2133).

March 8, 2013 44

VdiVW = minimum voltage from mask corner to eye.

DDR 4 VdiVW Margin to Mask (up to 2133).

March 8, 2013 45

136mV

68mV

68mV

Voltage margin is measured analogously to timing margin:

Margin is then (139mv-68mv)/68mV * 100% =104%

DDR 4 Eye Margin to Mask 2400 and greater.

March 8, 2013 46

BER contour 1E-12

At DDR4/2400 and above the extrapolated BER contour is used.

Since direct measurement beyond 1e-7 is extremely slow a standard dual Dirac

model is used to compute the contour from actual measured waveforms.

DDR 4 Eye Margin to Mask 2400 and greater.

March 8, 2013 47

Margin is really calculated the

same, to BER contour rather

than direct measurement.

TdiVW margin = min time from

mask corner

VdiVW margin = min voltage

from mask corner

Margin = (Actual-Spec)/Spec

*100%

Additional consideration for VdiVW

March 8, 2013 48

Ringback could cause the

meaurement using the mask

corners to be incorrect.

VdiVW – voltage must stay

above/below VdiVW for

TdiVW time.

Margin should really be the

min voltage in the entire

TdiVW range.

Requires additional study to

determine if this method

should be recommended over

mask corner measurements.

HOW CAN WE MODEL MULTI-

LAYER PCB & PACKAGES

DC UP TO 20-GHZ?

BUILDING CONFIDENCE LEVEL

March 8, 2013 49

Numerical Techniques: MoM

Method of Moments (Momentum):

• Boundary Discretization

• 3D: Layered

• Polygonal Mesh

• J,M-based

50

Triangles/Quadrilaterals

Do MOM correlate to VNA measurements? THANKS “NVIDIA CORP. & GIGATEST LABS”

March 8, 2013 51 51

Courtesy of Gigatest

S-parameter modeling of PCB & package interconnects

N1930B Physical Layer

Test System (PLTS) WORKSHOP EMEA

Correlation…Correlation…Correlation


52


53

WHY MOM and not Others like HFSS?

Model Comparison between HFSS and Sigrity-3D FEM Sigrity 3D FEM HFSS with Lumped Port

Elapsed Simulation Time Comparison

Ansoft HFSS Version 12.0.0, Build: 2009-09-02 10:18:38

Location: /home/tools/ansoft/hfss_12.0/hfss12/hfss.exe

Batch Solve/Save:

/home/scratch.chihweit_t40/t35/t35_hfss_study/90degree/t35_dsc_90d_DQ_1R_44line_alan_0715_run2.hf

ss

Starting Batch Run: 7/14/11, 7:02:05 PM

Stopping Batch Run: 8/3/11, 3:22:09 AM

Sigrity 3D FEM-----------Start Engine------------------Mon Jul 09 12:44:04 2012

Wave3D Engine Version: 12.0.b1.06193, built on Jun 21 2012, 13:02:30

Available memory: 138066 MB

Available hard disk space: 1395615MB

Pipe name: HRJVTWXWUZAVKNW

Command line: wave3d_engine E:\Nvidia_Jack_default_2cnv\ nvidia_pk_mod_cut2 r 0.040000 1

---------------End Engine--------------------Tue Jul 10 09:42:27 2012

Elapsed time for engine process (final run): 55105 seconds

Available hard disk space: 1380823MB

Peak temporary disk usage by solver (Temp): 0MB

Peak memory usage: 97794MB

Total elapsed time for the simulation process: 7.59e+004 seconds =21.1hrs

Total elapsed time is around 464 hrs

larger than 19 days

Total elapsed time is around 20 hrs

but needs 97GB of memory

PACKAGE MODELING

FOR DATA-NETS CAPTURING:

RETURN-PATH-DISCONTINUITY { RPD=

REFERENCE-PLANE TRANSITIONS,

SIGNAL/GND-PTH & ROUTING OVER VOIDS}

BREAK-OUT/IN, SERPENTINE, VIA-STUBS,

IMPEDANCE DISCONTINUITY & X-TALK

March 8, 2013 56

What is Return-Path-Discontinuity?

March 8, 2013 57

Overcoming the RPD with Stitching vias:

How many? How far from Signal-vias?

Changing Reference-Planes

Is that all of Return-Path-Discontinuity?

March 8, 2013 58

Traces passing by Slots or Splits

DDR3 Package Modeling using MOM DC to 20GHz

DQ nets major referencing to GND: VIDEO

March 8, 2013 59

Routing of DQ signals from Bumps-Top to Layer-3

running as Symmetric-SL sandwiched between

GND on Layers 2 & 4

March 8, 2013 60

DQ signals @ Die-Bumps DQ signals on Layer-3 as Symmetric-SL

Moving from Layer-3 to Layer-6 through Signal-PTH

to pickup the Balls

March 8, 2013 61

DQ signals on Layer-3

DQ signals on Layer-6 routed

between GND on layers 5

Impact of GND-PTH stitching: Proximity & #

Original-Package: PKG1 with 15-GND-PTH

EMEA

2011

62


New Proposal-Package:PKG2 with ONLY 3-GND-

PTH

March 8, 2013 63


Test-case Package: PKG3 with 0-GND-PTH

March 8, 2013 64

Do we have traces crossing slots in the GND-plane?

March 8, 2013 65

March 8, 2013 66

Eric Bogatin’s Blog:

“When two adjacent signal lines transition from one

signal layer, through a pair of planes, to another signal

layer, the return current flows between the cavity formed

by the planes. The impact of the return path discontinuity

is strongest on which S-parameter term?”

P1

P3

P4

P2

S11

S21

S31

Impact of GND-PTH stitching on Insertion-Loss

0.5 dB delta @ 3GHz

March 8, 2013 67

PKG1: 15-GND-PTH

PKG2: 3-GND-PTH

PKG3: 0-GND-PTH

Impact of GND-PTH stitching on Return-Loss

0-dB delta @ 3GHz

March 8, 2013 68

PKG1: 15-GND-PTH

PKG2: 3-GND-PTH

PKG3: 0-GND-PTH

FEXT with 20dB delta for 0-GND-PTH and 10dB for

3-GND-PTH @ 3GHz

March 8, 2013 69

PKG1: 15-GND-PTH

PKG2: 3-GND-PTH

PKG3: 0-GND-PTH

NEXT with 30dB delta for 0-GND-PTH and 10dB for

3-GND-PTH @ 3GHz

March 8, 2013 70

PKG1: 15-GND-PTH

PKG2: 3-GND-PTH

PKG3: 0-GND-PTH

Comparison of Return-current on GND-L2

March 8, 2013 71

Original-PKG: 15-GND-PTH PKG3: 0-GND-PTH

Comparison of Return-current on GND-L3 & L4

March 8, 2013 72



March 8, 2013 73




March 8, 2013 74

Return-Current for Original Package: PKG1

with 15-GND-PTH @ 3GHz: VIDEO

March 8, 2013 75

Return-Current for Test-Package: PKG3

with 0-GND-PTH @ 3GHz: VIDEO

GND-Return-Current

PTH-Return-Current

March 8, 2013 76

WHAT IS THE IMPACT OF THE MCH-PKG

FOR DDR3 TWO-SODIMMS/CHANNEL

March 8, 2013 77

MB PCB MOM Modeling to capture layer

transitions and via-stub-discontinuity: VIDEO

March 8, 2013 78

SODIMM-R/C-F PCB MOM Modeling to capture

layer changes and via-stub-discontinuity: VIDEO

March 8, 2013 79

SODIMM SURFACE-MOUNT CONNECTOR S-

parameter measurements AND/OR EMpro modeling

March 8, 2013 80

• 86100C DCA-J/TDR

EMPro Modeling of a USB Connector

Numerical Techniques: FEM

FEM: EMDSG2, Agilent FEM

• Volume Discretization

• Full 3D

• Tetrahedral Mesh

• E-based

• Frequency Domain

81

Schematic Capture of Die-2-Die Modeling using

either Linear-driver AC analysis or Channel-Sim

BER or IBIS-PRBS or BSIM4-PRBS Transistor

March 8, 2013 82

What is the eye-mask for DDR3 SDRAM device?

March 8, 2013 83


84

Comparison of Original-PKG (15-GND-PTH) with

Test-PKG (0-GND-PTH) @ 1.33GB/s

March 8, 2013 85

15-GND-PTH 0-GND-PTH

Setup/Hold DDR3-1.33GB/s margins

EMEA

2011

86

15-GND-PTH

Worst-case Setup-Margin is 95ps

0-GND-PTH

FAIL-FAIL-FAIL-FAIL

Lack of GND-PTH on test-PKG FORCES Down-bining

R/C-F_F Configuration down to 1.067GB/s operation Medium-2-High-Risk @ 1.067GB/s as worst Margin is -30ps

March 8, 2013 87

Cost-Reduced Package of 3-GND-PTH enables

operation @ 1.33GB/s

worst-case Setup-Margin is +55ps (loss of 40ps

compared to Original Package)

March 8, 2013 88

‘SLOW-DANCING’ PDN

March 8, 2013


89

Conceptual Origin of Simultaneous Switching

Output (SSO) Noise

March 8, 2013 90

On Chip

V SS

V CC

GND

15836

© 1991 Integrated Circuit Engineering Corporation

L Bonding

L Bonding Power

common lead

inductance

Icharge

Idischarge

Quiet loop

What influences SSO Noise:

Mutual inductance between the loops

Number of SSOs

dI/dt

Resonance of PDN

Switching lines

Quiet data line

Active loop

Co-SI/PI Modeling OF Multi-Giga-bit EMI effects

91

• Signal layer transitions: L1-2-L3 is it same like L1-2-L5?

• Open-stubs of Vias

• Stitching vias impact (# & Locality)

Optimizing on-PKG

decaps for Minimum

coupling of Power-Noise

to Data-Signals

Routing of DQ signals from Bumps-Top to Layer-3

running as Symmetric-SL sandwiched between

GND on Layers 2 & 4

March 8, 2013 92

DQ signals @ Die-Bumps DQ signals on Layer-3 as Symmetric-SL

Optimizing on-PKG

decaps for Minimum

Power-Noise to Signal-

Coupling

FD Risk Assessment of VddQ-Noise coupling to

Data-Signals

March 8, 2013


93

ON-PKG DECAPS

PACKAGE MOM S-MODEL

PORTS DIE-BUMP & DECAPS & BALLS

& 8-DATA SIGNALS + DQS/DQS# + DQM

AC NOISE-SOURCE

SWEEPING

AMPLITUDE @ VDDQ-

BUMP

MB LOADING

MODEL

NOISE-COUPLING TO TOGGELLING DATA-SIGNALS

0V noise @ VddQ-Bump Cpkg

March 8, 2013


94

15 GND-PTH

NOISE-COUPLING TO TOGGELLING DATA-SIGNALS

300mV noise @ VddQ-Bump

Cdie 50pF per I/O

Cpkg is 4.7uF

March 8, 2013


95

1 GND-PTH

20mV LESS noise coupling at 2.57GHz for 1-

GND-PTH than 15-GND-PTH

BUT 200mV wide-band coupling around 4.7GHz

What did we learn?

• Accurate modeling of Data-signals along with VddQ & VssQ

is important to capture VddQ-Noise Coupling to Data-Signals

• MOM is well suited to Model Data-Signals + VddQ + VssQ

including Return-Path-Discontinuity

• PDN Decoupling & GND-Stitching (Return-path-discontinuity)

impacts the Amount of VddQ-Noise coupling as well as the

Coupling-Frequency & Bandwidth of noise-coupling

March 8, 2013


96

TRACE EMISSION DUE TO RPD

ON PACKAGE

March 8, 2013 97

PKG-Antenna-Parameters Comparison of PKG1

(15-GND-PTH) vs. PKG3 (3-GND-PTH)

March 8, 2013 98

Radiated Power: 37-uwatts vs. 220-uwatts (6X)

Maximum Intensity: 5u-watts/Steradian vs. 42-uwatts/Steradian (8X)

Angle of U-max: 165-degrees vs. 140-degrees

Antenna-Gain of -19dB vs. -11dB (8dB difference)

Conclusion

Return-Path-Discontinuity caused 40ps loss of eye-margin @ 1.33GB/s

Also caused increased x-talk between Power to Signals and Wide-band noise coupling around 5GHz range

Also caused +8dB extra Radiated Emission

Therefore, Cost-reduction On-PKG by reducing # of layers or GND-stitching On-Die Cost adder of PLLs for Spread-Spectrum Enabling to pass FCC EMI Certification Requirements.

March 8, 2013


99

WORKFLOW PROPOSAL FOR

NEXT GENERATION MEMORY

TECHNOLOGY

March 8, 2013


100

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Documents

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signal layer

memory datanets

channel b bytes

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mils dqsdqs

agilent technologies6