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Nanotechnology

Nanotechnology 31 (2020) 465303 (6pp) https://doi.org/10.1088/1361-6528/abac31

Wafer-scale carbon nanotube networktransistors

Yongwoo Lee1, Jinsu Yoon1, Hyo-Jin Kim1, Geon-Hwi Park1, Ju Won Jeon1,Dae Hwan Kim1, Dong Myong Kim1, Min-Ho Kang2,3 and Sung-Jin Choi1,3

1 School of Electrical Engineering, Kookmin University, Seoul 02707, Korea2 Department of Nano-process, National Nanofab Center (NNFC), Daejeon 34141, Korea

E-mail: sjchoiee@kookmin.ac.kr and kmh@nnfc.re.kr

Received 11 June 2020, revised 22 July 2020Accepted for publication 4 August 2020Published 28 August 2020

AbstractHighly purified, preseparated semiconducting carbon nanotubes (CNTs) hold great potential forhigh-performance CNT network transistors due to their high electrical conductivity, highmechanical strength, and room-temperature processing compatibility. In this paper, we reportour recent progress on CNT network transistors integrated on an 8-inch wafer. We observe thatthe key device performance parameters of CNT network transistors at various locations on an8-inch wafer are highly uniform and that the device yield is impressive. Therefore, this workvalidates a promising path toward mass production and will make a significant contribution tothe future field of wafer-scale CNT electronics.

Keywords: carbon nanotube, network, transistor, uniform, wafer-scale

(Some figures may appear in colour only in the online journal)

1. Introduction

Low-dimensional material-based semiconductors have attrac-ted enormous attention in both industry and academia and havebeen widely researched over the last few years [1–3]. Carbonnanotubes (CNTs), one-dimensional materials, are promisingcandidates for high-performance field-effect thin-film transist-ors (TFTs) because of their high electrical conductivity, highmechanical strength, and solution-based processing [4–7]. Inparticular, there have been efforts in solution processes to sep-arate semiconducting and metallic CNTs. Research on high-performance CNT transistor fabrication using preseparatedsemiconducting CNTs has also been actively carried out [8–11]. Of the many methods developed, the density gradientultracentrifugation method enables rapid and inexpensive sep-aration of high-purity semiconducting CNTs [12, 13]. Highlypreseparated semiconducting CNT-percolated network thinfilms exhibit the merits of high transparency and high scalab-ility and can be applied to electronic skin, skin-like sensors,and large-scale integration processes [14, 15].

3 Authors to whom any correspondence should be addressed.

Recently, considerable progress in CNT network transistorshas been achieved [16–18]. For practical applications, furtherdevelopments of CNT electronics should rely on large-scalefabrication based on highly preseparated semiconductingCNTs in wafer-scale units. Previously reported CNT networktransistors and their ICs have been mostly demonstrated onlyon diced or 2- to 4-inch wafers at the present stage; hence,these demonstrations are not strictly large-scale processes.Indeed, for mass-production commercialization studies, theelectrical performance of CNT network transistors manufac-tured on wafers with a size of at least 8 inches should be eval-uated. Of course, CNT-based transistors fabricated on 8-inchwafers have been reported previously [19–21], but the stabil-ity and uniformity issues associated with 8-inch wafer-scaleprocesses have remained challenging.

Herein, we demonstrate the preparation of CNT networktransistors on an 8-inch wafer constructed from solution-processed 99% semiconducting CNTs for mass productionverification; these high-purity semiconducting CNTs providea high device yield. We form wafer-scale high-density anduniform semiconducting CNT networks and establish keytechnologies for 8-inch wafer-scale processing. In addi-tion, our proposed CNT network transistors exhibit excellent

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Nanotechnology 31 (2020) 465303 Y Lee et al

Figure 1. (a) Preparation of an 8-inch wafer covered with a SiO2 layer with a thickness of 300 nm. (b) Evaporation of a Ti/Pd bottom gateelectrode. (c) Formation of an Al2O3/SiO2 gate dielectric via ALD/PECVD. (d) Formation of solution-processed 99% semiconductingseparated CNT networks. (e) Evaporation of Ti/Pd S/D electrodes for ohmic contact formation with CNT network channels. (f) CNTchannel definition using oxygen plasma.

electrical performances and highly uniform key performanceparameters at various locations on the 8-inch wafer. Our CNTnetwork transistor results are expected to make a significantcontribution to the field of CNT electronics as a first steptoward mass production.

2. Results and discussion

Figure 1 illustrates the detailed manufacturing processes usedto prepare CNT network transistors on an 8-inch wafer basedon 99% semiconducting separated CNTs. For CNT networktransistor fabrication, highly purified 99% semiconductingseparated CNTs were used to form well-percolated networks;these CNTs provide wafer-scale processing, a uniform CNTnetwork density, and high-yield CNT device fabrication. Fab-rication of the CNT network transistors started on a p-type8-inch wafer with a thermally grown Si dioxide (SiO2) layerwith a thickness of 300 nm. Then, an i-line stepper photo-lithography (NSR-2205i11D, Nikkon) process was employedto form a local bottom gate pattern. To provide a local bot-tom gate structure, titanium/palladium (Ti/Pd) layers with athickness of 5/30 nm were sequentially deposited using ane-beam evaporation system (KVET-C500200, Korea VacuumTech). Here, Ti was applied in extremely thin adhesion lay-ers to enhance the adhesion between the substrate and thePd electrode. A 30-nm-thick aluminum oxide (Al2O3) filmwas then grown via an atomic layer deposition (ALD) sys-tem (Nano-ALD2000, IPS) at 350 C, followed by the depos-ition of a SiO2 layer with a thickness of 10 nm using plasma-enhanced chemical vapor deposition (PECVD) (TELIA200,TES) at 400 C. Thereafter, the substrate was cleaned with

radio frequency (RF) oxygen plasma treatment to make thesubstrate hydrophilic and then treated with a poly-L-lysinesolution (0.1% wv−1 in water; Sigma Aldrich) on the cleanedwafer surface to form an amine-terminated monolayer, whichacted as an effective adhesion layer for the deposition of theCNT percolated network. Then, to form semiconducting CNTnetworks, 200 ml of a 0.01 mg ml−1 99% semiconductor-enriched, preseparated CNT solution (IsoNanotubes-STM, pur-chased from NanoIntegris, Inc.) was prepared in a glass petridish, and the substrate functionalized with amine groups wasimmersed in the solution for 20 min, followed by thoroughrinsing with DI water and isopropanol. Subsequently, Ti andpalladium (Pd) layers (2 nm and 30 nm, respectively) weredeposited as a source and drain (S/D) electrode using e-beamevaporation. Then, the CNT channel region was defined bya photolithography process and RF oxygen plasma-etchingstep. The photoresist (PR) was then thoroughly stripped witha sequence of acetone, isopropanol, and flowing nitrogen.Finally, after coating with negative PR and patterning by pho-tolithography to open the gate electrode contact pad, the gatedielectric (Al2O3/SiO2) was wet-etched by immersing the sub-strate in diluted HF solution (HF: H2O = 1: 4), followed byremoval of the PR with acetone.

A photograph of an 8-inch wafer with fully manufacturedCNT network transistors is shown in figure 2(a), and magni-fied top-view opticalmicroscope images of the fabricatedCNTnetwork transistors are presented in figures 2(b) and (c). Field-emission scanning electron microscopy (FE-SEM) images ofCNT network transistors and a deposited 99% semiconductingCNT percolated network channel are also presented in figures2(d) and (e). From the SEM image of the percolated CNT net-work in the channel region, it is observed that the density of the

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Figure 2. (a) Photograph and (b), (c) magnified top-view optical microscope images of an 8-inch wafer with fully fabricated CNT networktransistors. (d) Top-view SEM image showing a single CNT network transistor and (e) a CNT percolated network in a channel.

Figure 3. (a) AFM images of the CNT network channel consisting of a 99% semiconducting separated CNT solution for various locations(TL, T, TR, L, C, R, BL, B, and BR) on an 8-inch wafer. (b) Schematic illustration of our 8-inch wafer where the density of the CNTnetwork is observed. (c) Manually calculated average CNT network density for the TL, T, TR, L, C, R, BL, B, and BR locations.

CNT network was highly uniform. In addition, all electrodepatterns were correctly formed on the 8-inch wafer, and thegate contact pads were clearly opened.

To verify that the CNTs were uniformly deposited on theentire 8-inch wafer, we observed the density of the 99% semi-conducting CNT networks through atomic force microscopy(AFM) images of the top left (TL), top (T), top right (TR),left (L), center (C), right (R), bottom left (BL), bottom (B),and bottom right (BR) locations, as shown in figure 3(a).

Figure 3(b) is a schematic diagram of the 8-inchwafer showingthe abovementioned nine different locations where the densityof the CNT networks was observed, and the CNT networkdensities manually calculated for each location are summar-ized in figure 3(c). Importantly, the AFM images showed ahighly similar and uniform CNT network density across the8-inch wafer. This distribution would be expected to prod uceCNT network transistors with highly uniform electrical per-formance.

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Figure 4. (a) Transfer curves (IDS—VGS) of CNT network transistors fabricated on an 8-inch wafer at a VDS of—0.5 V. (b) Output curves(IDS—VDS) of the CNT network transistor with L equal to 3 µm and W equal to 10 µm for different values of VGS varying from—10 V to0 V in 1 V steps. (c) Summarized key performance parameters (ION × L/W, IOFF × L/W, log (ION/IOFF), VT, gm × L/W, SS, µ, Rc × W, anddevice yield) of our CNT network transistors.

The transfer curves (i.e. IDS vs. VGS; drain current vs.gate voltage) of the CNT network transistors fabricated atthe abovementioned nine locations on the 8-inch wafer weremeasured at a drain voltage (VDS) of −0.5 V, as shown infigure 4(a). The defined CNT network channel widths (W) andlengths (L) of the CNT network transistors ranged from 2 µmto 10 µm and from 2 µm to 10 µm, respectively, with a totalof 216 devices measured at each location. Figure 4(b) showsthe output curves (i.e. IDS vs. VDS) of CNT network transistorswith L equal to 3 µm andW equal to 10 µm at various VGS val-ues varying from −10 V to 0 V, showing well-formed ohmiccontact at low VDS and obvious IDS saturation behavior at highVDS.

The key performance parameters of the devices, such asthe normalized on-state current with respect to L and W(ION × L/W) defined at a VGS of −10 V and a VDS of −0.5 V,off-state current with respect to L and W (IOFF × L/W)defined at a VGS of 10 V and a VDS of −0.5 V, on/off ratio(log(ION/IOFF)), threshold voltage (VT), normalized transcon-ductance with respect to L and W (gm × L/W), subthresholdslope (SS), carrier mobility (µ) at a VDS of −0.5 V, nor-malized contact resistance of the S/D electrodes with respectto W (Rc × W), and device yield, are summarized in figure

4(c). Overall, the extracted electrical parameters are fairly uni-form at different locations, but a slight difference in electricalparameters occurred because the channels of themanufacturedCNT network transistors are not 100% semiconducting CNTs(i.e. containing 1% metallic components) and the formedpercolation network paths are slightly different from eachother. If CNT transistors are fabricated based on solution-processed CNTs with a semiconducting purity above 99%,the device-to-device variation is expected to be sufficientlyimproved. The average ION × L/W, log(ION/IOFF), VT, andgm × L/W of all devices measured on the 8-inch wafer are1.44 µA ± 0.26 µA, 4.59 ± 0.29, −5.67 V ± 0.33 V, and0.34 µS ± 0.06 µS, respectively. The µ of the device was cal-culated by the following equation:

µ=L

VDSCgW∂IDS∂VGS

=L

VDSCg

gmW

(1)

where Cg is defined as the gate capacitance per unitarea and was computed by using a sophisticated cyl-indrical model6. Under a VDS of −0.5 V, the extrac-ted value of µ of the CNT network transistors was17.1 cm2 V−1 sec−1 ± 2.6 cm2 V−1 sec−1. In addition, wecompared the contact configurations by extracting Rc using

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Nanotechnology 31 (2020) 465303 Y Lee et al

the transfer length method (TLM) for CNT network transistorswith different L values ranging from 2 µm to 10 µm. Thetotal resistance (Rtotal) of CNT network transistors was plot-ted as a function of L for various overdrive voltage (VOV)values of −3 V, −3.5 V, and −4 V. We confirmed that theRc values corresponding to different values of VOV matched.Rtotal for the CNT devices can be expressed by the followingequation:

Rtotal =VDSIDS

= Rc+Rch = Rc+L× rch (2)

where Rch is the channel resistance and rch is a VGS-dependentchannel resistivity. Therefore, Rc between CNTs and S/D elec-trodes could be extracted from the intercept of the linear fir tothe TLM plot. As a result, for the abovementioned 9 positions,the value of Rc × W for the CNT network transistors with Wequal to 10 µm was 41.02 kΩ µm ± 4.15 kΩ µm. That is,since the CNT network density under the S/D electrodes washigh and uniform, the value of Rc did not differ significantlyat different locations on the 8-inch wafer.

Although this study evaluated the electrical performanceand reliability at the device level on an 8-inch wafer, webelieve that we can further achieve reliable, high-performanceintegrated circuits and applications based on the developed 8-inch wafer-scale processing technology.

3. Conclusion

We demonstrated CNT network transistors on an 8-inch waferto advance the next step toward mass production. CNT net-work transistors were fabricated based on solution-processed99% semiconducting CNTs, which provide high operationalstability and high-yield fabrication. First, we observed thedensity of the percolated CNT network deposited at variouslocations on an 8-inch wafer, which showed highly similar anduniform results. In addition, the key electrical performanceparameters of CNT network transistors with a uniform CNTnetwork density on an 8-inch wafer exhibited fairly similarvalues. Our research represents a significant advance towardthe challenging task of preparing wafer-scale CNT networktransistors and their complex circuits and will be an importantstep for commercialization.

Acknowledgments

This work was supported by the National Research Found-ation (NRF) of Korea under grants 2016R1A5A1012966and 2019R1A2B5B01069988 and by the Future Semicon-ductor Device Technology Development Program (Grant10067739) funded by MOTIE (Ministry of Trade, Industry& Energy) and KSRC (Korea Semiconductor ResearchConsortium).

ORCID iDs

Yongwoo Lee https://orcid.org/0000-0003-3224-1960

Sung-Jin Choi https://orcid.org/0000-0003-1301-2847

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