vl$t and verification - wordpress.com...why vlsi testing? discuss in detail about testing...
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Time: 3 hrs.
VL$t TestEurg and Verification
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What is path sensitization? Explain with example. (0S &{arks}Give D-aigorithm using cubical algorithrn for autornatic test pattern generator. (10 Marks)Using PODEM algorithnt derive tests for the circuits girren in Fig.Q2(c).
r lg.'\21(c) (05 iViarks)
Explain with circuit diagrarn, hor.r, clouble-latch and single-iatch LSSD techniques toimprove testability. (tS Marks)Expiain boundary scan method aiong with test access pat (TAP) architecture. (10 Marks)
a. Explain in detaii about syndrome driver counter and LFSR./SR methods for pseudoexaustivepattern generator. (10 Marks)
b. Explain with ciiagrarn syncirorne checking and signature analysis compression techniquesused in a BIST environment. (tr8 M*rks)
Note: Answev any FtrVE fwll questions.
a. Why VLSI testing? Discuss in detail about testing philosophy.b. Explain how lauits are rtrocleled in digital circuits.c. What are ternporary laults'? Also expiain horv they are detected.
a. Give comparison betrveen testing and verification.b. Give three different approaches for functional verification.c. Differentiate between equivalence checking and model checking.
a. What is sintulators'/ Also cxplain cycle based sirnulation and co-simulators.b. Explain path coverage and expression coverage tools.c. Explain with diagrarn verification tool wavefbnn viewer.
a. Explain with clear reason how noise in signal integrity plays importantsubmicron technologies.
b. What are the limitations of static tiniing analysis (STAXc. What are design checks'? E,xplain electrical and layout rule checks.
Write notes on the following:a. AS IC verificationb. Partiai scan technique f,or testability '
c. BILBO based BIST architectured. Cross talk glitch analysis
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