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Instructor-in-Charge (Section -1)

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Outline

oore s aw

Power dissipation issues

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v f

thestudent

an

introduction to

the

pertainingtothedesignofintegratedcircuits.

digitalintegratedcircuits.Theimportanceof

acknowledgedandstressedupon.

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PrimereferenceBooks(R1))

Kang.

S.M

and

Leblebici

Y.,

CMOS

Digital

Integrated

Circuits:AnalysisandDesign, McGrawHillInternational

Editions3rd Edition2003.

TextBook :

(T1)JanM.Rabaey;AnanthaChandrakasan;BorivojeNikolic,DigitalIntegratedCircuits ADesignPerspective,(Second

. (T2)BehzadRazavi,DesignofAnalogCMOSintegrated

circuits,McGrawHillInternational Edition.2001.

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Neil

H.E.

Weste,

Kamran

Eshraghian,

"Principles

of

CMOS

VLSI

Design,AddisonWesley PublishingCompany.

PucknellD.A.,EshraghianK.,"BasicVLSIdesign,systemsand

circuits",Third

edition,

Prentice

Hall

of

India

Pvt.

Ltd.

a r c us . ., ntro uct onto es gn , c rawinternationaleditions.

Gre orian R. Temes G.C. "Analo Mos inte rated circuits forsignal

processing",

Wiley

interscience

publication.

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Sze

S.M.,"VLSI

Technology",

Second

edition,

McGraw

Hill

International

Edition.

RandallAGeiger,PhillipsE.allen,NoelRStrader,"VLSIDesigntechniquesfor" ' , .

BhaskharJayram,"AVHDLPRIMER",PrenticeHall.

IEEEJournals

of

solid

state

circuits,

VLSI

system.

. , , , .

Johns.DavidA.andMartinK,AnalogIntegratedCircuitDesign,JohnWily&Sons.Inc.2002.

Referencesfordesignassignments

Michael. L.Bushnell,andVishwani.D.Agrawal,EssentialsOfElectronicTestingForDi ital Memor AndMixedSi nalVLSICircuits.KluwerAcademicPublishers

ThirdEdition,2004

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v f

,

layouttool

based

laboratory

is

included.

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followingtopics

Basic

circuit

theory

and

design,

BJTan MOSt eory an un amenta so ogic

design.

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, ,VLSICircuitsandSystems,PHI2005.

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Reference books

PrenticeHallIndia,2000

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No ofLec.

Topic To be Covered Learning Objectives Ref. to Text Book

Common Topics-

2

3

.Methodogies

2. Scaling

3. CMOS Technology, Design Rules,

MOS Capacitances

Technology Generation transition and its effects

on performance

Introduction to layouts and industry design flow

for analog and digital integrated circuits

,

Chapter-3,3,

(T1), R1), (RJ)

Chapter 2,1 (T1),RJ)

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No ofLec.


5 Digital Design Basic building block for most digital sub-systems Chapter 5 ,6

4

5

. nverter- tat c an sw tc ng

characteristics, Combinational MOS

logic circuits static logic

2. Synchronous system and Sequentialcircuits design

3. Memory Circuits Design

4. Desi n verification & test

an pee o g a sys ems

Study and design of various CMOS logic gate

families

Synchronous design, timing metrics, Design of flip-flops

Design of SRAM, DRAM, decoders, senseam lifiers

,Chapter7, (R1),(T1)

Chapter 8,9 (R1) ,(T1)

Chapter 10 (R1) ,(T1)

Reference bookRm

& internet resources

Verification of functionality, manufacturing defects

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No of

Lec.


6Analog Design

1. Advanced Current Sources & sinks; Building temperature independent voltage and Chapter 6, (RJ), (T2)

4urrent e erence c rcu t,

Operational amplifiers Architectures,

feed back

2. Noise

current re erences, as c u ng oc or mostanalog subsystems

Quantification of various types of noise in analog

circuits

apter ,

Chapter 7 (RJ), (T2)

Chapter 7 (T2)

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No of

Lec.


2

2

3

Common Topics

1. Introduction to VLSI Design

Methodogies

2. Scaling

3. CMOS Technology, DesignRules, MOS Capacitances

Introduction to the semiconductor industry

Technology Generation transition and itseffects on performance

Introduction to layouts and industry design

flow for analog and digital integrated

Chapter-I ((T1),

R1)

Chapter-3,3,

(T1), R1), (RJ)

Chapter 2,1

c rcu ts ,

6

8

4

5

5

Analog Design

1. Advanced Current Sources &

sinks; Current Reference

circuit, Operational amplifiers

Architectures, feed back

2. Noise

Building temperature independent voltage

and current references, Basic buildingblock for most analog subsystems

Quantification of various types of noise inanalo circuits

Chapter 6, (RJ),

(T2)

Chapter 6 (RJ),

(T2)

4

5Digital Design

1. MOS inverter- Static and

switching characteristics,

Combinational MOS logiccircuits static logic

2. Synchronous system and

Basic building block for most digital sub-

systems and Speed of digital systems

Study and design of various CMOS logic

gate families

Synchronous design, timing metrics,

Design of flip-flops

,

(T2)

Chapter 7 (T2)

Chapter 5 ,6

(R1) , (T1)

Chapter7,

(R1),(T1)

Sequential circuits design

3. Memory Circuits Design

4. Design verification & test

Design of SRAM, DRAM, decoders,

sense amplifiers

Verification of functionality,manufacturing defects

Chapter 8,9 (R1)

,(T1)

Chapter 10 (R1)

,(T1)

Reference

bookRm

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resources

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Component Duration Marks Date & Time Venue Remarks

Test I 60 Mts. 50 25/9 & 8.00 -- 9.00 AM

Test II 60 Mts 50 6/11 & 8.00 -- 9.00 AM

Surprise Test/Assignments

20 Spread across semester

Comp. Exam 3 Hours 80 14/12 AN

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ingenuine cases.

In

all

cases

prior

intimation

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theEEE/ECE Notice

board

and

EDUCAN only

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Introduction:Issuesindigitaldesign

The

CMOS

inverter Layout Combinationallogicstructures Sequentiallogicgates

Interconnect:R,LandC Timin

Arithmeticbuilding

blocks

Memoriesandarraystructures

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Introduction

y s es gn ng g a

ICsdifferent

today

than

was e ore

Willit

change

in

future?

21

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The First Com uter

The BabbageDifference Engine

25,000 parts

cost: 17,470

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ENIAC - The first electronic computer

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The Transistor Revolution

PNP BIPOLARTRANSISTOR

First transistor

Bell Labs, 1948

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The First Inte rated Circuits

Bipolar logic

1960s

ECL 3-input Gate

Motorola 1966

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Intel 4004 Micro-Processor

1971

1000 transistors1 MHz operation

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Intel Pentium (IV) microprocessor

Intel 2005

125,000,000

transistors

3.8Ghz operation

90nm Technology

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Circuitsize(transistorcount)

Circuittechnology(BJT,BiCMOS,NMOS,CMOS)

Designstyle

s an ar ce

gatearray

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Size

classification

(historical)

500,000 ULSI 1990

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Transistor Counts1 Billion1 Billion

1,000,000

100,000

10,000

1,000 PentiumPentiumPro

PentiumIIPentiumIII

10080286

i3864

1

1975 1980 1985 1990 1995 2000 2005 2010

Source: IntelSource: Intel

31

ProjectedProjected

Courtesy, Intel8/28/2012

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zIn 1965, Gordon Moore noted that thenumber of transistors on a chi doublesevery 18 to 24 months.

zHe made a prediction thatsemiconductor technolo will double its

effectiveness every 18 months

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15

141312

OFDFUNCT

ION

1098

7FTHENUMBE

ER

INTEGRAT

5

4321

LOG2O

MPONENTSP

0

1959

1960

1961

1962

1963

1964

1965

1966

1967

1968

1969

1970

1971

1972

1973

1974

1975

C

33

Electronics, April 19, 1965.

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Moores law in Microprocessors

1000

100

(MT)

2X growth in 1.96 years!

386

486Pentium proc

P6

1

nsistors

80088080

8085 80860.01

.Tr

Transistors on Lead Microprocessors double every 2 years

0.0011970 1980 1990 2000 2010

Year

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Moores Law, Intel Processors

Source: Intel web page (www.intel.com)

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Fre uenc10000

Doubles every

P6100

1000

y(Mh

z) years

486

38628680868085

10

Frequen

80084004

0.1

Year

Lead Microprocessors frequency doubles every 2 years


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Power Dissi ation

P6

100

Pentium proc

486286

10

(Watt

s)

3868085

8080

8008

1Power

0.1

Year

Lead Microprocessors power continues to increase


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Power will be a major problem

5KW18KW

10000

100000

.

500WPentium proc

1000

(Watts)

80088080

80858086

286

386486

10Powe

4004

0.1

1971 1974 1978 1985 1992 2000 2004 2008

Year

Power delivery and dissipation will be prohibitive


i

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PowerDensity10000

2)

Rocket

Nozzle1000

ty(W/cm

NuclearReactor

808610e

rDens

Hot Plate8008

8080

8085286

386486

Pentium proc

1

Po

1970 1980 1990 2000 2010Year

Courtesy, Intel

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State-of-the Art: Lead Microprocessors

EE 534 Summer 2004 University of South Alabama

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Why Scaling?

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Why Scaling?

Technology shrinks by ~0.7 per generation

every genera on can n egra e x more unc ons on

a chip; chip cost does not increase significantly

But

z Design engineering population does not double every two years

,

z Exploit different levels of abstraction


Design Abstraction Levels

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Behavior description

(Verilog, HDL, etc.)Silicon compilation

Physical description(layout, circuit, etc.)

+

MODULE

Simulation for systemspecification

CIRCUIT

S

G

D

DEVICE


n+n+

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Challen es in Di ital Desi n

Macrosco ic Issues

Ultra-high speed design

Interconnect

Noise, Crosstalk

Time-to-Market Millions of Gates

High-Level Abstractions

e a y, anu ac ura y Power Dissipation Clock distribution.

Predictability etc.

Everything Looks a Little Different and Theres a Lot of Them!

?

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SYSTEM

MODULE

GATE

CIRCUIT

n+n+

SG D

518/28/2012

Design flow

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Designflow

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VLSI D i St

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VLSIDesignStages

LogicDesign/Simulation

Partitionarchitectureintocycles latches

Verify

against

architecture

specification CircuitDesign/Simulation

Transistorsizing

Performanceverification

StaticTimingAnalysis

er ymarg nrequ rements

PhysicalDesign

Drawmasksforlayout,followingdesignrules

acementan rout ng

Parasiticextraction

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Synthesis

Architectural,Logic,Physical

StaticAnalysis

Desi nrulecheckin DRC

Circuitextraction

Designverification

Test

eneration

DynamicAnalysis

Logicsimulation

Circuitsimulation

(SPICE)

VLSI Design Stages

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VLSIDesignStages Logic

Design/Simulation

Partitionarchitectureintocycles/latches

Verifyagainstarchitecturespecification

CircuitDesign/Simulation

Transistorsizing

Performanceverification

StaticTimingAnalysis

Verifymarginrequirements

Physical

Design Drawmasksforlayout,followingdesignrules

Placementandrouting

Parasiticextraction

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Impl

er er

Anytime, brake

Spec

Here is acounterexample

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Everyoneknows

debugging

is

twice

ashardaswritingaprograminthefirst

lace

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Verification in Verilog

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VerificationinVerilog

DUT

DUT: Design Under Test

628/28/2012

Verification of 1Bit Full Adder

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Verificationof1 BitFullAdder

DUT: Design Under Test orDUV: Design Under Verification

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Synthesis

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Sy t es s

Logic Synthesis is the automated process of converting

- .

TechnologyLibraryConstraints

DESIGN(RTL code)

Synthesis Engine

64

Synthesis Report Technology Net list

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WHY SYNTHESIS IS REQUIRED

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WHYSYNTHESISIS REQUIRED

Benefits of synthesis :

Highlevel

design

entry

Increaseddesignerproductivity

Reductionofla outdesi nex ertise

requirement

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mprove qua y

Technologyindependence

Facilitatesdesign

re

use

and

sharing

668/28/2012


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mprove qua y

Technologyindependence

Facilitatesdesign

re

use

and

sharing

678/28/2012

Modern Desi n Methodolo

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ModernDesi nMethodolo

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Analysisand

Design

byKang

and

Leblebici

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