vlsi systems design - bfh · vlsi systems design ... (fsmd models in tabular forms)...

MicroLab, VLSI-21 (1/95)

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VLSI Systems DesignVLSI Systems DesignVLSI Systems DesignVLSI Systems DesignTopTopTopTop----down Design and down Design and down Design and down Design and HDLsHDLsHDLsHDLs

OverviewOverviewOverviewOverview�Top down designTop down designTop down designTop down design----flow, flow, flow, flow, VHDL VHDL VHDL VHDL hardware description hardware description hardware description hardware description language, testlanguage, testlanguage, testlanguage, test----bench methodologybench methodologybench methodologybench methodology

Goal: Goal: Goal: Goal: You are able to design circuits with the VHDL You are able to design circuits with the VHDL You are able to design circuits with the VHDL You are able to design circuits with the VHDL language with behavioral, dataflow and structural language with behavioral, dataflow and structural language with behavioral, dataflow and structural language with behavioral, dataflow and structural modeling. You are familiar with the top down design flow modeling. You are familiar with the top down design flow modeling. You are familiar with the top down design flow modeling. You are familiar with the top down design flow and the testand the testand the testand the test----bench methodology. bench methodology. bench methodology. bench methodology.

It seems I It seems I It seems I It seems I have tohave tohave tohave tohurry up!hurry up!hurry up!hurry up!


JMM v1.5

The Need for The Need for The Need for The Need for HDLsHDLsHDLsHDLsA A A A specificationspecificationspecificationspecification is an engineering contract that lists all the is an engineering contract that lists all the is an engineering contract that lists all the is an engineering contract that lists all the goals for a project:goals for a project:goals for a project:goals for a project:

�� goals include area, power, throughput, latency, goals include area, power, throughput, latency, goals include area, power, throughput, latency, goals include area, power, throughput, latency, functionality, test coverage, costs (functionality, test coverage, costs (functionality, test coverage, costs (functionality, test coverage, costs (NREsNREsNREsNREs and piece costs). and piece costs). and piece costs). and piece costs). Helps you figure out when you’re done and how to make Helps you figure out when you’re done and how to make Helps you figure out when you’re done and how to make Helps you figure out when you’re done and how to make engineering tradeoffs. Later on goals help remind everyone engineering tradeoffs. Later on goals help remind everyone engineering tradeoffs. Later on goals help remind everyone engineering tradeoffs. Later on goals help remind everyone (especially management) what was agreed to!(especially management) what was agreed to!(especially management) what was agreed to!(especially management) what was agreed to!

�� partition the project into modules with wellpartition the project into modules with wellpartition the project into modules with wellpartition the project into modules with well----defined defined defined defined interfaces so that each module can be worked on by a interfaces so that each module can be worked on by a interfaces so that each module can be worked on by a interfaces so that each module can be worked on by a separate team. Gives the SW types a head start too! separate team. Gives the SW types a head start too! separate team. Gives the SW types a head start too! separate team. Gives the SW types a head start too! ((((Hardware/software Hardware/software Hardware/software Hardware/software codesigncodesigncodesigncodesign))))

�� A A A A behavioral modelbehavioral modelbehavioral modelbehavioral model serves as an executable specification serves as an executable specification serves as an executable specification serves as an executable specification that documents the exact behavior of all the individual that documents the exact behavior of all the individual that documents the exact behavior of all the individual that documents the exact behavior of all the individual modules and their interfaces. Since one can run tests, this modules and their interfaces. Since one can run tests, this modules and their interfaces. Since one can run tests, this modules and their interfaces. Since one can run tests, this model can be refined and finally verified through model can be refined and finally verified through model can be refined and finally verified through model can be refined and finally verified through simulation.simulation.simulation.simulation.

We need a way to talk about what hardware should do We need a way to talk about what hardware should do We need a way to talk about what hardware should do We need a way to talk about what hardware should do without actually designing the hardware itself, i.e., need to without actually designing the hardware itself, i.e., need to without actually designing the hardware itself, i.e., need to without actually designing the hardware itself, i.e., need to separate functionality from implementation. We need aseparate functionality from implementation. We need aseparate functionality from implementation. We need aseparate functionality from implementation. We need a

HHHHardware ardware ardware ardware DDDDescription escription escription escription LLLLanguageanguageanguageanguage

chapter chapter chapter chapter 1111


JMM v1.5

The Need for The Need for The Need for The Need for HDLsHDLsHDLsHDLs cont.cont.cont.cont.

� easier to explore ideas in easier to explore ideas in easier to explore ideas in easier to explore ideas in HDLsHDLsHDLsHDLs than in logic gatesthan in logic gatesthan in logic gatesthan in logic gates� stepwise refinement: stepwise refinement: stepwise refinement: stepwise refinement: HDLsHDLsHDLsHDLs allow to describe allow to describe allow to describe allow to describe

designs at various levels of abstractiondesigns at various levels of abstractiondesigns at various levels of abstractiondesigns at various levels of abstraction� HDLsHDLsHDLsHDLs sustain descriptionsustain descriptionsustain descriptionsustain description----synthesis methodsynthesis methodsynthesis methodsynthesis method� pitfalls:pitfalls:pitfalls:pitfalls: abstract models are not preciseabstract models are not preciseabstract models are not preciseabstract models are not precise

� first first first first HDLsHDLsHDLsHDLs were introduced in late 70swere introduced in late 70swere introduced in late 70swere introduced in late 70s� difficulties to develop general purpose HDL for difficulties to develop general purpose HDL for difficulties to develop general purpose HDL for difficulties to develop general purpose HDL for

signalsignalsignalsignal----processing and realprocessing and realprocessing and realprocessing and real----time applications and ...time applications and ...time applications and ...time applications and ...� portability needs lead to standardizations (Institute portability needs lead to standardizations (Institute portability needs lead to standardizations (Institute portability needs lead to standardizations (Institute

of electrical and electronics engineering, IEEE)of electrical and electronics engineering, IEEE)of electrical and electronics engineering, IEEE)of electrical and electronics engineering, IEEE)


JMM v1.5

Hardware Description LangHardware Description LangHardware Description LangHardware Description Languagesuagesuagesuages

� textual textual textual textual HDLsHDLsHDLsHDLsVHDL, VHDL, VHDL, VHDL, VerilogVerilogVerilogVerilog----HDL, HDL, HDL, HDL, HardwareCHardwareCHardwareCHardwareC, , , , SystemCSystemCSystemCSystemC, UML, etc., UML, etc., UML, etc., UML, etc.

� graphic graphic graphic graphic HDLsHDLsHDLsHDLsSpecdChartSpecdChartSpecdChartSpecdChart, etc. (control & dataflow graphs) , etc. (control & dataflow graphs) , etc. (control & dataflow graphs) , etc. (control & dataflow graphs)

� tabular tabular tabular tabular HDLsHDLsHDLsHDLsBIF, etc. (FSMD models in tabular forms)BIF, etc. (FSMD models in tabular forms)BIF, etc. (FSMD models in tabular forms)BIF, etc. (FSMD models in tabular forms)

� timetimetimetime----diagram diagram diagram diagram HDLsHDLsHDLsHDLsWaves, etc.Waves, etc.Waves, etc.Waves, etc.

� StandardizationStandardizationStandardizationStandardization� VHDL: IEEE Std 1067VHDL: IEEE Std 1067VHDL: IEEE Std 1067VHDL: IEEE Std 1067----1987 & 19931987 & 19931987 & 19931987 & 1993� std_logic package IEEE Std 1164std_logic package IEEE Std 1164std_logic package IEEE Std 1164std_logic package IEEE Std 1164----1993199319931993� VerilogVerilogVerilogVerilog----HDL: IEEE Std 1997HDL: IEEE Std 1997HDL: IEEE Std 1997HDL: IEEE Std 1997


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A Tale of Two A Tale of Two A Tale of Two A Tale of Two HDLsHDLsHDLsHDLsVHDLVHDLVHDLVHDL VerilogVerilogVerilogVerilog----HDLHDLHDLHDL

VHSIC HDL, Very High Speed VHSIC HDL, Very High Speed VHSIC HDL, Very High Speed VHSIC HDL, Very High Speed Integrated Circuits. ADAIntegrated Circuits. ADAIntegrated Circuits. ADAIntegrated Circuits. ADA----like like like like verbose syntax, lots of redundancyverbose syntax, lots of redundancyverbose syntax, lots of redundancyverbose syntax, lots of redundancy

CCCC----like concise syntaxlike concise syntaxlike concise syntaxlike concise syntax

Extensible types andExtensible types andExtensible types andExtensible types andsimulation engine. Logicsimulation engine. Logicsimulation engine. Logicsimulation engine. Logicrepresentations are notrepresentations are notrepresentations are notrepresentations are notbuilt in and have evolvedbuilt in and have evolvedbuilt in and have evolvedbuilt in and have evolvedwith time (IEEEwith time (IEEEwith time (IEEEwith time (IEEE----1164).1164).1164).1164).

BuiltBuiltBuiltBuilt----in types and logicin types and logicin types and logicin types and logicrepresentations. Oddly,representations. Oddly,representations. Oddly,representations. Oddly,this has led to slightlythis has led to slightlythis has led to slightlythis has led to slightlyincompatible simulatorsincompatible simulatorsincompatible simulatorsincompatible simulatorsfrom different vendors.from different vendors.from different vendors.from different vendors.

Design is composed ofDesign is composed ofDesign is composed ofDesign is composed ofentitiesentitiesentitiesentities each of which can have each of which can have each of which can have each of which can have multiple multiple multiple multiple architecturesarchitecturesarchitecturesarchitectures. A . A . A . A configurationconfigurationconfigurationconfiguration chooses what chooses what chooses what chooses what architecture is used for a given architecture is used for a given architecture is used for a given architecture is used for a given instance of an entity.instance of an entity.instance of an entity.instance of an entity.

Design is composed ofDesign is composed ofDesign is composed ofDesign is composed ofmodulesmodulesmodulesmodules. . . .

Behavioral, structural,Behavioral, structural,Behavioral, structural,Behavioral, structural,logiclogiclogiclogic----level modelinglevel modelinglevel modelinglevel modeling

Behavioral, structural,Behavioral, structural,Behavioral, structural,Behavioral, structural,logiclogiclogiclogic----level modelinglevel modelinglevel modelinglevel modeling

Synthesizable subset...Synthesizable subset...Synthesizable subset...Synthesizable subset... Synthesizable subset...Synthesizable subset...Synthesizable subset...Synthesizable subset...

Harder to learn and use,Harder to learn and use,Harder to learn and use,Harder to learn and use,not technologynot technologynot technologynot technology----specific,specific,specific,specific,DoDDoDDoDDoD mandate.mandate.mandate.mandate.

Easy to learn and use,Easy to learn and use,Easy to learn and use,Easy to learn and use,fast simulation, good forfast simulation, good forfast simulation, good forfast simulation, good forlogic. Gateway Design logic. Gateway Design logic. Gateway Design logic. Gateway Design AutomationAutomationAutomationAutomation


JMM v1.5

Introduction to Introduction to Introduction to Introduction to VHDL & VHDL & VHDL & VHDL & VerilogVerilogVerilogVerilog

� rich & powerful rich & powerful rich & powerful rich & powerful languagelanguagelanguagelanguage

� data type driven data type driven data type driven data type driven languagelanguagelanguagelanguage

� goal: documentation of goal: documentation of goal: documentation of goal: documentation of large complex systemslarge complex systemslarge complex systemslarge complex systems

language structureslanguage structureslanguage structureslanguage structures� entity (hierarchy entity (hierarchy entity (hierarchy entity (hierarchy

interface)interface)interface)interface)� architecture (behavior architecture (behavior architecture (behavior architecture (behavior

of system)of system)of system)of system)� configuration (binding configuration (binding configuration (binding configuration (binding

of entity and of entity and of entity and of entity and architecture)architecture)architecture)architecture)

� package (library of package (library of package (library of package (library of global types or global types or global types or global types or blocks)blocks)blocks)blocks)

� simple & efficient simple & efficient simple & efficient simple & efficient languagelanguagelanguagelanguage

� hardware driven hardware driven hardware driven hardware driven languagelanguagelanguagelanguage

� goal: automatic goal: automatic goal: automatic goal: automatic synthesissynthesissynthesissynthesis

language structureslanguage structureslanguage structureslanguage structures� module (blocks or submodule (blocks or submodule (blocks or submodule (blocks or sub----

blocks)blocks)blocks)blocks)� #include (file #include (file #include (file #include (file

structuring)structuring)structuring)structuring)

VHDLVHDLVHDLVHDL VerilogVerilogVerilogVerilog----HDLHDLHDLHDL


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Introduction to VHDL & Introduction to VHDL & Introduction to VHDL & Introduction to VHDL & VerilogVerilogVerilogVerilog cont.cont.cont.cont.

language featureslanguage featureslanguage featureslanguage features� signal data types (in, out, signal data types (in, out, signal data types (in, out, signal data types (in, out, bidirbidirbidirbidir, signal, signal, signal, signal----strength ...)strength ...)strength ...)strength ...)� hardware structures (memory, registerhardware structures (memory, registerhardware structures (memory, registerhardware structures (memory, register----files, ...)files, ...)files, ...)files, ...)� logic operators (shift, rotation, masking, ...)logic operators (shift, rotation, masking, ...)logic operators (shift, rotation, masking, ...)logic operators (shift, rotation, masking, ...)� asynchronous structures (set, reset of memories)asynchronous structures (set, reset of memories)asynchronous structures (set, reset of memories)asynchronous structures (set, reset of memories)� parallel or synchronous structuresparallel or synchronous structuresparallel or synchronous structuresparallel or synchronous structures� constraints (pin, technology, area, delays, ...)constraints (pin, technology, area, delays, ...)constraints (pin, technology, area, delays, ...)constraints (pin, technology, area, delays, ...)

VHDLVHDLVHDLVHDL


JMM v1.5

Signals, DelaSignals, DelaSignals, DelaSignals, Delays, Events, Concurrency ys, Events, Concurrency ys, Events, Concurrency ys, Events, Concurrency

� digital systems in contrast to software systems are digital systems in contrast to software systems are digital systems in contrast to software systems are digital systems in contrast to software systems are fundamentally about fundamentally about fundamentally about fundamentally about signalssignalssignalssignals

� signals in contrast to variables do have signals in contrast to variables do have signals in contrast to variables do have signals in contrast to variables do have delays delays delays delays which which which which leads to signal leads to signal leads to signal leads to signal waveformswaveformswaveformswaveforms

� digital systems are comprised of digital systems are comprised of digital systems are comprised of digital systems are comprised of componentscomponentscomponentscomponents� digital systems do have digital systems do have digital systems do have digital systems do have concurrencyconcurrencyconcurrencyconcurrency of operationof operationof operationof operation� eventseventseventsevents on signals lead to computations that may on signals lead to computations that may on signals lead to computations that may on signals lead to computations that may

generate events on other signalsgenerate events on other signalsgenerate events on other signalsgenerate events on other signals

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sumsumsumsum

carrycarrycarrycarry

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time (ns)time (ns)time (ns)time (ns)

eventeventeventevent

chapter 2 (starter)chapter 2 (starter)chapter 2 (starter)chapter 2 (starter)


JMM v1.5

Signal ValuesSignal ValuesSignal ValuesSignal Values

� signal values are physically associated to wiressignal values are physically associated to wiressignal values are physically associated to wiressignal values are physically associated to wires� VHDL language supports signal type: VHDL language supports signal type: VHDL language supports signal type: VHDL language supports signal type:

� typetypetypetype: bit, : bit, : bit, : bit, valuesvaluesvaluesvalues: ‘0’, ‘1’: ‘0’, ‘1’: ‘0’, ‘1’: ‘0’, ‘1’� typetypetypetype: bit_vector, : bit_vector, : bit_vector, : bit_vector, valuesvaluesvaluesvalues: “0001”, etc: “0001”, etc: “0001”, etc: “0001”, etc

� VHDL package IEEE 11VHDL package IEEE 11VHDL package IEEE 11VHDL package IEEE 1164 supports signal type:64 supports signal type:64 supports signal type:64 supports signal type:� typetypetypetype: : : : std_ulogicstd_ulogicstd_ulogicstd_ulogic and vector and vector and vector and vector std_ulogic_vectorstd_ulogic_vectorstd_ulogic_vectorstd_ulogic_vector� std_ulogicstd_ulogicstd_ulogicstd_ulogic is a 9 value logicis a 9 value logicis a 9 value logicis a 9 value logic

valuevaluevaluevalue interpretationinterpretationinterpretationinterpretation

UUUU unununun----initializedinitializedinitializedinitializedXXXX forcing unknownforcing unknownforcing unknownforcing unknown0000 forcing 0forcing 0forcing 0forcing 01111 forcing 1forcing 1forcing 1forcing 1ZZZZ high impedancehigh impedancehigh impedancehigh impedanceWWWW weak unknownweak unknownweak unknownweak unknownLLLL weak 0weak 0weak 0weak 0HHHH weak 1weak 1weak 1weak 1---- don’t caredon’t caredon’t caredon’t care


JMM v1.5

Resolved SignalsResolved SignalsResolved SignalsResolved Signals

� it is common for components in a digital system to it is common for components in a digital system to it is common for components in a digital system to it is common for components in a digital system to have have have have multiple sourcesmultiple sourcesmultiple sourcesmultiple sources for the value of an input for the value of an input for the value of an input for the value of an input signalsignalsignalsignal

� many designs use many designs use many designs use many designs use busesbusesbusesbuses: a group of signals that can : a group of signals that can : a group of signals that can : a group of signals that can be shared among multiple sourcesbe shared among multiple sourcesbe shared among multiple sourcesbe shared among multiple sources

� the values on shared signals will be determined the values on shared signals will be determined the values on shared signals will be determined the values on shared signals will be determined upon the type of interconnection, like wired logicupon the type of interconnection, like wired logicupon the type of interconnection, like wired logicupon the type of interconnection, like wired logic

� the signal values depend on its implementationthe signal values depend on its implementationthe signal values depend on its implementationthe signal values depend on its implementation�the VHDL simulator has to the VHDL simulator has to the VHDL simulator has to the VHDL simulator has to resolveresolveresolveresolve the signals valuethe signals valuethe signals valuethe signals value�The IEEE 1164 package offers The IEEE 1164 package offers The IEEE 1164 package offers The IEEE 1164 package offers std_logicstd_logicstd_logicstd_logic and and and and

std_logic_vectorstd_logic_vectorstd_logic_vectorstd_logic_vector signal types for resolved version signal types for resolved version signal types for resolved version signal types for resolved version of the signal of the signal of the signal of the signal std_ulogicstd_ulogicstd_ulogicstd_ulogic and and and and std_ulogic_vectorstd_ulogic_vectorstd_ulogic_vectorstd_ulogic_vector

resolved signal necessaryresolved signal necessaryresolved signal necessaryresolved signal necessary

unresolved signalunresolved signalunresolved signalunresolved signal

wiredwiredwiredwired----or logicor logicor logicor logic


JMM v1.5

EntityEntityEntityEntity

� the design the design the design the design entityentityentityentity is a primary programming is a primary programming is a primary programming is a primary programming abstraction in VHDLabstraction in VHDLabstraction in VHDLabstraction in VHDL

� entityentityentityentity defines the interface of a component, without defines the interface of a component, without defines the interface of a component, without defines the interface of a component, without giving any information about the component giving any information about the component giving any information about the component giving any information about the component behaviorbehaviorbehaviorbehavior

+

entityentityentityentity HalfAdder isisisisportportportport (a,b : inininin bitbitbitbit;

sum,carry : outoutoutout bitbitbitbit);endendendend HalfAdder;

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sumsumsumsum


library IEEE;library IEEE;library IEEE;library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;entityentityentityentity HalfAdder isisisis

portportportport (a,b : inininin std_ulogic; sum,carry : out out out out std_ulogic);

endendendend HalfAdder;



JMM v1.5

Exercises ExExercises ExExercises ExExercises Ex401: Entity401: Entity401: Entity401: Entity

� Ex401 (difficulty: easy): Ex401 (difficulty: easy): Ex401 (difficulty: easy): Ex401 (difficulty: easy): Define the entities of the Define the entities of the Define the entities of the Define the entities of the following digital components. Use the unresolved 9 following digital components. Use the unresolved 9 following digital components. Use the unresolved 9 following digital components. Use the unresolved 9 value logic of the IEEE 1164 package. Each value logic of the IEEE 1164 package. Each value logic of the IEEE 1164 package. Each value logic of the IEEE 1164 package. Each component has to be edited in a separate file with component has to be edited in a separate file with component has to be edited in a separate file with component has to be edited in a separate file with the components name plus extension “.the components name plus extension “.the components name plus extension “.the components name plus extension “.vhdvhdvhdvhd” . The ” . The ” . The ” . The files have to be analyzed by the files have to be analyzed by the files have to be analyzed by the files have to be analyzed by the SynopsysSynopsysSynopsysSynopsys command: command: command: command: vhdlanvhdlanvhdlanvhdlan

Mux4to1i0i0i0i0

i1i1i1i1

selselselsel

zzzzi2i2i2i2i3i3i3i3

D_ffdddd

rNotrNotrNotrNot

qqqq

clkclkclkclk

sNotsNotsNotsNot

qNotqNotqNotqNot

aaaa

bbbbcccc

opopopop

n z n z n z n z

8 bit data8 bit data8 bit data8 bit data

32 bit data32 bit data32 bit data32 bit data6 bit op6 bit op6 bit op6 bit op----codecodecodecode

Alu32Alu32Alu32Alu32

use first letter ofuse first letter ofuse first letter ofuse first letter ofcomponent name in capital,component name in capital,component name in capital,component name in capital,and first letter of signaland first letter of signaland first letter of signaland first letter of signalname in small capname in small capname in small capname in small cap


JMM v1.5

ArchitectureArchitectureArchitectureArchitecture

� the design the design the design the design architecturearchitecturearchitecturearchitecture is a primary programming is a primary programming is a primary programming is a primary programming abstraction in VHDLabstraction in VHDLabstraction in VHDLabstraction in VHDL

� architecturearchitecturearchitecturearchitecture describes the internal behavior of a describes the internal behavior of a describes the internal behavior of a describes the internal behavior of a component, without giving any information about component, without giving any information about component, without giving any information about component, without giving any information about the component the component the component the component IO’sIO’sIO’sIO’s

� The behavioral description can take many forms. The behavioral description can take many forms. The behavioral description can take many forms. The behavioral description can take many forms. These forms differ in the levels of abstraction and These forms differ in the levels of abstraction and These forms differ in the levels of abstraction and These forms differ in the levels of abstraction and detail.detail.detail.detail.

architecturearchitecturearchitecturearchitecture behavior ofofofof HalfAdder isisisis-- comment: declaration of variablesbeginbeginbeginbegin...

endendendend behavior;

functional descriptionof the system


JMM v1.5

EntityEntityEntityEntity----Architecture: HierarchyArchitecture: HierarchyArchitecture: HierarchyArchitecture: Hierarchy(VHD(VHD(VHD(VHDL vs. L vs. L vs. L vs. VerilogVerilogVerilogVerilog))))

library library library library IEEE;;;;useuseuseuse IEEE.std_logic_1164.all;entityentityentityentity FullAdder isisisis

portportportport (a,b,ci: inininin std_logic; co,s:outoutoutout std_logic);endendendend FullAdder;

architecturearchitecturearchitecturearchitecture behavior ofofofof FullAdder isisisis-- comment: declaration of variablesbeginbeginbeginbegin



+

module module module module FullAdder (a,b,ci,co,s);inputinputinputinput a,b,ci;outputoutputoutputoutput co,s;

/* comment: declarations of variables */...

endmoduleendmoduleendmoduleendmodule


VHDLVHDLVHDLVHDL

VerilogVerilogVerilogVerilog----HDLHDLHDLHDL


JMM v1.5

ConcurrencyConcurrencyConcurrencyConcurrency

� The operation of digital systems is inherently The operation of digital systems is inherently The operation of digital systems is inherently The operation of digital systems is inherently concurrentconcurrentconcurrentconcurrent

� Within VHDL signals are assigned values using Within VHDL signals are assigned values using Within VHDL signals are assigned values using Within VHDL signals are assigned values using signal assignmentsignal assignmentsignal assignmentsignal assignment statements statements statements statements <=<=<=<=

� Multiple signal assignment statements are executed Multiple signal assignment statements are executed Multiple signal assignment statements are executed Multiple signal assignment statements are executed concurrentlyconcurrentlyconcurrentlyconcurrently

architecturearchitecturearchitecturearchitecture concurrent_behavior ofofofof HalfAdder isisisisbeginbeginbeginbeginsum <= (a xorxorxorxor b) afterafterafterafter 5 nsnsnsns;carry <= (a andandandand b) afterafterafterafter 5 nsnsnsns;

endendendend concurrent_behavior;

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bbbb

sumsumsumsum


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concurrentconcurrentconcurrentconcurrentsignal assignmentsignal assignmentsignal assignmentsignal assignment


JMM v1.5

Dataflow Dataflow Dataflow Dataflow Model Model Model Model ####1 1 1 1

library library library library IEEE;;;;useuseuseuse IEEE.std_logic_1164.all;

entityentityentityentity HalfAdder isisisisportportportport (a,b: inininin std_logic;

carry,sum:outoutoutout std_logic);endendendend HalfAdder;

architecturearchitecturearchitecturearchitecture dataflow ofofofof HalfAdder isisisisbeginbeginbeginbeginsum <= (a xorxorxorxor b) afterafterafterafter 5 nsnsnsns;carry <= (a andandandand b) afterafterafterafter 5 nsnsnsns;

endendendend dataflow;

+


JMM v1.5

Dataflow Model Dataflow Model Dataflow Model Dataflow Model ####2222


entityentityentityentity FullAdder isisisisportportportport (a,b,cIn: inininin std_logic;

cOut,sum: outoutoutout std_logic);endendendend FullAdder;

architecturearchitecturearchitecturearchitecture dataflow ofofofof FullAdder isisisissignal signal signal signal s1,s2,s3 : std_logic;constantconstantconstantconstant gate_delay: Time:=5 nsnsnsns;beginbeginbeginbeginL1: s1 <= (a xorxorxorxor b) afterafterafterafter gate_delay;L2: s2 <= (cIn andandandand s1) afterafterafterafter gate_delay;L3: s3 <= (a andandandand b) afterafterafterafter gate_delay;L4: sum <= (s1 xorxorxorxor cIn) afterafterafterafter gate_delay;L5: cOut <= (s2 orororor s3) afterafterafterafter gate_delay;


architecturearchitecturearchitecturearchitecturedeclarativedeclarativedeclarativedeclarativesegmentsegmentsegmentsegment

architecturearchitecturearchitecturearchitecturebodybodybodybody

+

s1s1s1s1

s2s2s2s2

s3s3s3s3

L1L1L1L1L4L4L4L4

L3L3L3L3L2L2L2L2

L5L5L5L5


JMM v1.5

Signal Assignments Signal Assignments Signal Assignments Signal Assignments ####1111

� simple signal assignmentssimple signal assignmentssimple signal assignmentssimple signal assignments

sum<=(a xor b) after 5 ns, (a or b) after 10 ns, (not a) after 15 ns;

sig <= ‘0’, ‘1’ after 10 ns, ‘0’ after 20 ns, ‘1’ after 40 ns;

clock <= ‘0’, not(clock) after 5 ns;

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a <= “00000000_00000000”, to_stdlogicvector(x”abcd”) after 5 ns;

Type conversion from Type conversion from Type conversion from Type conversion from hexadecimalhexadecimalhexadecimalhexadecimalto to to to std_logic_vectorstd_logic_vectorstd_logic_vectorstd_logic_vector is defined in is defined in is defined in is defined in package std_logic_1164package std_logic_1164package std_logic_1164package std_logic_1164

goto UNIX directory, where packages are placed:goto UNIX directory, where packages are placed:goto UNIX directory, where packages are placed:goto UNIX directory, where packages are placed:cd $SYNOPSYS/packages/IEEE/src


JMM v1.5

Conditional Signal Assignment Conditional Signal Assignment Conditional Signal Assignment Conditional Signal Assignment ####2222

� The right hand value is computed immediately and The right hand value is computed immediately and The right hand value is computed immediately and The right hand value is computed immediately and assigned at some point in the future using the assigned at some point in the future using the assigned at some point in the future using the assigned at some point in the future using the afterafterafterafterclauseclauseclauseclause


entityentityentityentity Mux4to1 isisisisportportportport (i0,i1,i2,i3: inininin std_logic_vector(7 downtodowntodowntodownto 0);

sel : inininin std_logic_vector(1 downtodowntodowntodownto 0);z : outoutoutout std_logic_vector(7 downtodowntodowntodownto 0));

endendendend Mux4to1;

architecturearchitecturearchitecturearchitecture dataflow ofofofof Mux4to1 isisisisbeginbeginbeginbeginz <= i0 afterafterafterafter 5 ns whenns whenns whenns when sel=“00” elseelseelseelse

i1 afterafterafterafter 5 ns whenns whenns whenns when sel=“01” elseelseelseelsei2 afterafterafterafter 5 ns whenns whenns whenns when sel=“10” elseelseelseelsei3 afterafterafterafter 5 ns whenns whenns whenns when sel=“11” elseelseelseelse“00000000” afterafterafterafter 5 nsnsnsns;


one singleone singleone singleone singlesignalsignalsignalsignalassignmentassignmentassignmentassignment


JMM v1.5

Exercises Ex4Exercises Ex4Exercises Ex4Exercises Ex402: Conditional Signal 02: Conditional Signal 02: Conditional Signal 02: Conditional Signal AssignmentAssignmentAssignmentAssignment

� Ex402 (difficulty: easy): Ex402 (difficulty: easy): Ex402 (difficulty: easy): Ex402 (difficulty: easy): Define the VHDL code of Define the VHDL code of Define the VHDL code of Define the VHDL code of a 1bit a 1bit a 1bit a 1bit ALU with the operations: AND, OR, ALU with the operations: AND, OR, ALU with the operations: AND, OR, ALU with the operations: AND, OR, FullAdderFullAdderFullAdderFullAdder. Use the resolved 9 value logic of the . Use the resolved 9 value logic of the . Use the resolved 9 value logic of the . Use the resolved 9 value logic of the IEEE 1164 package. The IEEE 1164 package. The IEEE 1164 package. The IEEE 1164 package. The Simple1bitALU.vhdSimple1bitALU.vhdSimple1bitALU.vhdSimple1bitALU.vhd file has file has file has file has to be analyzed and simulated by the to be analyzed and simulated by the to be analyzed and simulated by the to be analyzed and simulated by the SynopsysSynopsysSynopsysSynopsyscommands: commands: commands: commands: vhdlanvhdlanvhdlanvhdlan & & & &

aaaa

bbbbresultresultresultresult

opcodeopcodeopcodeopcode

carry carry carry carry

ALUALUALUALUcarryIncarryIncarryIncarryIn


JMM v1.5

Delays: Delta Delay Delays: Delta Delay Delays: Delta Delay Delays: Delta Delay ModelModelModelModel� The VHDL language distinguished between tree The VHDL language distinguished between tree The VHDL language distinguished between tree The VHDL language distinguished between tree

delay models:delay models:delay models:delay models:� Delta delay modelDelta delay modelDelta delay modelDelta delay model� Inertial delay model (default)Inertial delay model (default)Inertial delay model (default)Inertial delay model (default)� Transport delay modelTransport delay modelTransport delay modelTransport delay model

�Delta delay modelDelta delay modelDelta delay modelDelta delay model� If no delay is specified, a delta delay is assumed. A delta If no delay is specified, a delta delay is assumed. A delta If no delay is specified, a delta delay is assumed. A delta If no delay is specified, a delta delay is assumed. A delta

delay is as small as zero delay. It is used by the delay is as small as zero delay. It is used by the delay is as small as zero delay. It is used by the delay is as small as zero delay. It is used by the simulator which sums delta delays to zero.simulator which sums delta delays to zero.simulator which sums delta delays to zero.simulator which sums delta delays to zero.

in1in1in1in1in2in2in2in2zzzzs1s1s1s1s2s2s2s2s3s3s3s3s4s4s4s4

0000 10101010 20202020 30303030 40404040 50505050 60606060 70707070

10101010 ∆∆∆∆ 2222∆∆∆∆ 3333∆∆∆∆

in2in2in2in2s2s2s2s2s3s3s3s3zzzz

architecture architecture architecture architecture delta_delay of of of of Comb isisisissignal signal signal signal s1,s2,s3,s4: std_logic:=0;beginbeginbeginbegin

s1 <=not(in1);s1 <=not(in1);s1 <=not(in1);s1 <=not(in1);s2 <=not(in2);s2 <=not(in2);s2 <=not(in2);s2 <=not(in2);s3 <=not(s1 and in2);s3 <=not(s1 and in2);s3 <=not(s1 and in2);s3 <=not(s1 and in2);s4 <=not(s2 and in1);s4 <=not(s2 and in1);s4 <=not(s2 and in1);s4 <=not(s2 and in1);z <=not(s3 and s4);z <=not(s3 and s4);z <=not(s3 and s4);z <=not(s3 and s4);

end end end end delta_delay;;;;


JMM v1.5

Delays: Inertial Delay ModelDelays: Inertial Delay ModelDelays: Inertial Delay ModelDelays: Inertial Delay Model

� Digital circuits have a certain amount of inertia. Digital circuits have a certain amount of inertia. Digital circuits have a certain amount of inertia. Digital circuits have a certain amount of inertia. For example it takes a finite amount of time and a For example it takes a finite amount of time and a For example it takes a finite amount of time and a For example it takes a finite amount of time and a certain amount of energy for the output of a gate to certain amount of energy for the output of a gate to certain amount of energy for the output of a gate to certain amount of energy for the output of a gate to respond to a change on the inputrespond to a change on the inputrespond to a change on the inputrespond to a change on the input

�Inertial delay model (default)Inertial delay model (default)Inertial delay model (default)Inertial delay model (default)� a pulse shorter than the propagation delay will not a pulse shorter than the propagation delay will not a pulse shorter than the propagation delay will not a pulse shorter than the propagation delay will not

propagate to the outputpropagate to the outputpropagate to the outputpropagate to the output

inputinputinputinput

out1out1out1out1

out2out2out2out2

5555 10101010 15151515 20202020 25252525 30303030 35353535 40404040


2 ns2 ns2 ns2 ns

8 ns8 ns8 ns8 nsoutput for delay: 8 nsoutput for delay: 8 nsoutput for delay: 8 nsoutput for delay: 8 ns

output for delay: 2 nsoutput for delay: 2 nsoutput for delay: 2 nsoutput for delay: 2 ns

inputinputinputinputoutoutoutout

out1 <= (a out1 <= (a out1 <= (a out1 <= (a xorxorxorxor b) after 8 ns;b) after 8 ns;b) after 8 ns;b) after 8 ns;out2 <= (a out2 <= (a out2 <= (a out2 <= (a xorxorxorxor b) after 2 ns;b) after 2 ns;b) after 2 ns;b) after 2 ns;

VHDL’93!VHDL’93!VHDL’93!VHDL’93!sum <=resum <=resum <=resum <=reject 2 ns inertial (a ject 2 ns inertial (a ject 2 ns inertial (a ject 2 ns inertial (a xorxorxorxor b) after 5 ns;b) after 5 ns;b) after 5 ns;b) after 5 ns;


JMM v1.5

Delays: Transport Delay ModelDelays: Transport Delay ModelDelays: Transport Delay ModelDelays: Transport Delay Model

� Unlike switching devices, wires have a Unlike switching devices, wires have a Unlike switching devices, wires have a Unlike switching devices, wires have a comparatively less inertia, As a result, wires will comparatively less inertia, As a result, wires will comparatively less inertia, As a result, wires will comparatively less inertia, As a result, wires will propagate signals with very small pulse width.propagate signals with very small pulse width.propagate signals with very small pulse width.propagate signals with very small pulse width.

� In modern technologies with increasingly small In modern technologies with increasingly small In modern technologies with increasingly small In modern technologies with increasingly small feature sizes the wire delays dominate.feature sizes the wire delays dominate.feature sizes the wire delays dominate.feature sizes the wire delays dominate.

�Transport delay modelTransport delay modelTransport delay modelTransport delay model� any pulse will propagate to the output, independent of any pulse will propagate to the output, independent of any pulse will propagate to the output, independent of any pulse will propagate to the output, independent of

the delaythe delaythe delaythe delay


out1out1out1out1

5555 10101010 15151515 20202020 25252525 30303030 35353535 40404040


8 ns8 ns8 ns8 ns output for delay: 8 nsoutput for delay: 8 nsoutput for delay: 8 nsoutput for delay: 8 ns

inputinputinputinputoutoutoutout

out1 <= transport (a out1 <= transport (a out1 <= transport (a out1 <= transport (a xorxorxorxor b) after 8 ns;b) after 8 ns;b) after 8 ns;b) after 8 ns;


JMM v1.5

Delay Model in PracticeDelay Model in PracticeDelay Model in PracticeDelay Model in Practice� Accurate delay Accurate delay Accurate delay Accurate delay

modeling of wire modeling of wire modeling of wire modeling of wire delays is possible, delays is possible, delays is possible, delays is possible, although in practice it although in practice it although in practice it although in practice it is difficult to obtain is difficult to obtain is difficult to obtain is difficult to obtain accurate estimates of accurate estimates of accurate estimates of accurate estimates of the wire delay without the wire delay without the wire delay without the wire delay without proceeding through proceeding through proceeding through proceeding through physical design and physical design and physical design and physical design and layout of the circuit.layout of the circuit.layout of the circuit.layout of the circuit.



carry,sum:outoutoutout std_logic);endendendend HalfAdder;

architecturearchitecturearchitecturearchitecture transport_delay ofofofof HalfAdder isisisissignal signal signal signal s1,s2: std_logic:=‘0’;beginbeginbeginbegins1 <= (a xorxorxorxor b) afterafterafterafter 2 nsnsnsns;s2 <= (a andandandand b) afterafterafterafter 2 nsnsnsns;sum <= transporttransporttransporttransport s1 afterafterafterafter 4 nsnsnsns;carry <= transporttransporttransporttransport s2 afterafterafterafter 4 nsnsnsns;

endendendend transport_delay;

s1s1s1s1

s2s2s2s2

aaaabbbb

sumsumsumsum


aaaabbbbsumsumsumsumcarrycarrycarrycarrys1s1s1s1s2s2s2s2

0000 2222 4444 6666 8888 10101010 12121212 14141414


inertialinertialinertialinertial

transporttransporttransporttransport


JMM v1.5

EEEExercises vlsi21: Conditional xercises vlsi21: Conditional xercises vlsi21: Conditional xercises vlsi21: Conditional AssignmentsAssignmentsAssignmentsAssignments

� Ex403 (difficulty: easy): Ex403 (difficulty: easy): Ex403 (difficulty: easy): Ex403 (difficulty: easy): Write and simulate a Write and simulate a Write and simulate a Write and simulate a VHDL model of a 2VHDL model of a 2VHDL model of a 2VHDL model of a 2----bit comparator (compare on bit comparator (compare on bit comparator (compare on bit comparator (compare on equality, filename: Comp2.vhd). equality, filename: Comp2.vhd). equality, filename: Comp2.vhd). equality, filename: Comp2.vhd).

� Ex404 (difficulty: easy): Ex404 (difficulty: easy): Ex404 (difficulty: easy): Ex404 (difficulty: easy): Construct and test a Construct and test a Construct and test a Construct and test a VHDL module for generating the following VHDL module for generating the following VHDL module for generating the following VHDL module for generating the following waveforms.waveforms.waveforms.waveforms.

� Ex vlsi21 (difficulty: easy): Ex vlsi21 (difficulty: easy): Ex vlsi21 (difficulty: easy): Ex vlsi21 (difficulty: easy): Have a look at the Have a look at the Have a look at the Have a look at the exercises at the end of chapter 3 of “VHDL: exercises at the end of chapter 3 of “VHDL: exercises at the end of chapter 3 of “VHDL: exercises at the end of chapter 3 of “VHDL: Starter’s Guide”Starter’s Guide”Starter’s Guide”Starter’s Guide”

Comp2Comp2Comp2Comp2aaaa

bbbbcccc

aaaabbbbcccc

0000 10101010 20202020 30303030 40404040 50505050 60606060



JMM v1.5

The The The The Process Construct #1Process Construct #1Process Construct #1Process Construct #1

� The continuous assignment model is used when The continuous assignment model is used when The continuous assignment model is used when The continuous assignment model is used when components correspond to gates.components correspond to gates.components correspond to gates.components correspond to gates.

� The The The The processprocessprocessprocess construct enables the use of construct enables the use of construct enables the use of construct enables the use of conventional programming language constructs.conventional programming language constructs.conventional programming language constructs.conventional programming language constructs.

� In contrast to concurrent signal assignment In contrast to concurrent signal assignment In contrast to concurrent signal assignment In contrast to concurrent signal assignment statements a process is a sequentially executed statements a process is a sequentially executed statements a process is a sequentially executed statements a process is a sequentially executed block of code.block of code.block of code.block of code.

� Control flow within a process is strictly sequential.Control flow within a process is strictly sequential.Control flow within a process is strictly sequential.Control flow within a process is strictly sequential.� With respect to simulation time a process executes With respect to simulation time a process executes With respect to simulation time a process executes With respect to simulation time a process executes

in zero time.in zero time.in zero time.in zero time.

architecturearchitecturearchitecturearchitecture behavior ofofofof MyProcess isisisisbeginbeginbeginbeginprocessprocessprocessprocess

beginbeginbeginbegin

end processend processend processend process;endendendend behavior;

process body

process declarative part



JMM v1.5

Example: Process StatementExample: Process StatementExample: Process StatementExample: Process Statement

library library library library IEEE;;;;useuseuseuse IEEE.std_logic_1164.all;useuseuseuse IEEE.std_logic_unsigned.all;

entityentityentityentity Memory isisisisportportportport (addr,wrData: inininin std_logic_vector(31 downtodowntodowntodownto 0);

wr,rd: inininin std_logic;rdData :outoutoutout std_logic_vector(31 downtodowntodowntodownto 0));

endendendend Memory;

architecturearchitecturearchitecturearchitecture behavioral ofofofof Memory isisisistypetypetypetype memArray is arrayis arrayis arrayis array(0 totototo 1024) of std_logic_vector(31 downtodowntodowntodownto 0);beginbeginbeginbeginMemProcess: : : : processprocessprocessprocess(addr,wr,rd)variablevariablevariablevariable mem: memArray :=((x“00000A06“), -- initializing memory dataothers => (x“00000000“));

variablevariablevariablevariable addrIndex: integerintegerintegerinteger;beginbeginbeginbeginaddrIndex:=conv_integer(addr);ifififif (wr = ‘1‘) thenthenthenthenmem(addrIndex):=wrData;

elsifelsifelsifelsif (rd = ‘1’) thenthenthenthenrdData <=mem(addrIndex) afterafterafterafter 10 nsnsnsns;

end ifend ifend ifend if;end process;end process;end process;end process;endendendend behavioral;

immediateimmediateimmediateimmediatevariablevariablevariablevariableassignmentassignmentassignmentassignment

sensitivity listsensitivity listsensitivity listsensitivity list

concurrentconcurrentconcurrentconcurrentsignalsignalsignalsignalassignmentassignmentassignmentassignment


JMM v1.5

TTTThe Process Construct #2he Process Construct #2he Process Construct #2he Process Construct #2

� The execution of a process is initiated whenever an The execution of a process is initiated whenever an The execution of a process is initiated whenever an The execution of a process is initiated whenever an eventeventeventevent occurs on any signal in the occurs on any signal in the occurs on any signal in the occurs on any signal in the sensitivity listsensitivity listsensitivity listsensitivity list

� Once started the process executes to completion in Once started the process executes to completion in Once started the process executes to completion in Once started the process executes to completion in zero (simulation) time.zero (simulation) time.zero (simulation) time.zero (simulation) time.

� Processes execute concurrently with other Processes execute concurrently with other Processes execute concurrently with other Processes execute concurrently with other processes and concurrent signal assignments.processes and concurrent signal assignments.processes and concurrent signal assignments.processes and concurrent signal assignments.

� Concurrent signal assignments are in fact only Concurrent signal assignments are in fact only Concurrent signal assignments are in fact only Concurrent signal assignments are in fact only special cases of processes.special cases of processes.special cases of processes.special cases of processes.

architecturearchitecturearchitecturearchitecture behavior ofofofof MyBlock2 isisisisbeginbeginbeginbeginprocessprocessprocessprocess(a,b)beginbeginbeginbeginc <= a andandandand b afterafterafterafter 5 nsnsnsns;

end processend processend processend process;endendendend behavior;

architecturearchitecturearchitecturearchitecture behavior ofofofof MyBlock1 isisisisbeginbeginbeginbeginc <= a andandandand b afterafterafterafter 5 nsnsnsns;


identical behavior identical behavior identical behavior identical behavior

concurrent signal assignmentconcurrent signal assignmentconcurrent signal assignmentconcurrent signal assignment

processprocessprocessprocess


JMM v1.5

VHDL vs. VHDL vs. VHDL vs. VHDL vs. VeriloVeriloVeriloVerilogggg: Events: Events: Events: Events

� process process process process sensitivity listbegin begin begin begin statements; ; ; ; end process;end process;end process;end process;

� wait on/until/for wait on/until/for wait on/until/for wait on/until/for event;;;;

� always @(always @(always @(always @(sensitivity list) ) ) ) statement

� initial (initial (initial (initial (sensitivity list) ) ) ) statement

Events are variable or signal changes.Events are variable or signal changes.Events are variable or signal changes.Events are variable or signal changes.Real circuits are event driven.Real circuits are event driven.Real circuits are event driven.Real circuits are event driven.


whowwhowwhowwhow! ! ! ! everything is everything is everything is everything is event driven like event driven like event driven like event driven like in real lifein real lifein real lifein real life


JMM v1.5

Conditional Programming ConstructsConditional Programming ConstructsConditional Programming ConstructsConditional Programming Constructs

� IfIfIfIf----thenthenthenthen----else statementelse statementelse statementelse statementif if if if condition then then then then sequential statement [ elsifelsifelsifelsif condition thenthenthenthen sequential statement ][ elseelseelseelse sequential statement ] end if;end if;end if;end if;

� case statementcase statementcase statementcase statementcase case case case expression isisisis{when when when when choices => => => => sequential statements }[ when others => when others => when others => when others => sequential statements ]end case;end case;end case;end case;


JMM v1.5

Example: Condition StatementsExample: Condition StatementsExample: Condition StatementsExample: Condition Statementslibrary library library library IEEE;;;;useuseuseuse IEEE.std_logic_1164.all;


sum,carry: outoutoutout std_logic);endendendend HalfAdder;

architecturearchitecturearchitecturearchitecture behavioral ofofofof HalfAdder isisisisbeginbeginbeginbeginIf_Process: process: process: process: process(a,b)

beginbeginbeginbeginifififif (a = b) thenthenthenthensum<= ‘ 0‘ afterafterafterafter 5 nsnsnsns;

elseelseelseelsesum<= (a orororor b) afterafterafterafter 5 nsnsnsns;

end ifend ifend ifend if;end process;end process;end process;end process;

Case_Process: process: process: process: process(a,b)beginbeginbeginbegincasecasecasecase a isisisiswhenwhenwhenwhen ‘0‘ => carry <= a afterafterafterafter 5 nsnsnsns;whenwhenwhenwhen ‘1‘ => carry <= b afterafterafterafter 5 nsnsnsns;when otherswhen otherswhen otherswhen others => carry <= ‘x‘ afterafterafterafter 5 nsnsnsns;

end caseend caseend caseend case;end process;end process;end process;end process;

endendendend behavioral;


JMM v1.5

VHDL vs. VHDL vs. VHDL vs. VHDL vs. VerilogVerilogVerilogVerilog: : : : Combinational Logic ECombinational Logic ECombinational Logic ECombinational Logic Examplexamplexamplexample


VHDLVHDLVHDLVHDL

entityentityentityentity Multiplexer4to1 isisisisport port port port (sel: inininin std_logic_vector (1 downtodowntodowntodownto 0);

a,b,c,d: inininin std_logic_vector (15 downtodowntodowntodownto 0);z:out std_logic_vector (15 downto0downto0downto0downto0));

endendendend Multiplexer4to1;

architecture architecture architecture architecture DemoExample of of of of Multiplexer4to1 isisisisbeginbeginbeginbegin

processprocessprocessprocess (a,b,c,d,sel)beginbeginbeginbegin

case case case case sel isisisiswhenwhenwhenwhen (“00“) => z <= a;whenwhenwhenwhen (“01“) => z <= b;whenwhenwhenwhen (“10“) => z <= c;whenwhenwhenwhen (“11“) => z <= d;whenwhenwhenwhen othersothersothersothers => z<=“-------“;

end case;end case;end case;end case;end process;end process;end process;end process;

endendendend DemoExample;

modulemodulemodulemodule Multiplexer4to1(sel,a,b,c,d,z);inputinputinputinput [[[[1:0]]]] sel;inputinputinputinput [[[[15:0]]]] a,b,c,d;outputoutputoutputoutput [[[[15:0] ] ] ] z;

assignassignassignassign z =(sel == 2’d0) ? a:(sel == 2’d1) ? b:(sel == 2’d2) ? c:(sel == 2’d3) ? d:16’bx;


4 to 1 multiplexer4 to 1 multiplexer4 to 1 multiplexer4 to 1 multiplexer(no interfered memory)(no interfered memory)(no interfered memory)(no interfered memory)


JMM v1.5

Loop Programming ConstructsLoop Programming ConstructsLoop Programming ConstructsLoop Programming Constructs

� for loop statementfor loop statementfor loop statementfor loop statementfor for for for index in in in in range looplooplooploop

sequential statementsend loop;end loop;end loop;end loop;

� while loop statementwhile loop statementwhile loop statementwhile loop statementwhile while while while condition looplooplooploop

sequential statementsend loop;end loop;end loop;end loop;

loop index has not to be loop index has not to be loop index has not to be loop index has not to be declared but can only be declared but can only be declared but can only be declared but can only be used locallyused locallyused locallyused locally


JMM v1.5

Example: Loop Statements Example: Loop Statements Example: Loop Statements Example: Loop Statements library library library library IEEE;;;;useuseuseuse IEEE.std_logic_1164.all;useuseuseuse IEEE.std_logic_unsigned.all;

entityentityentityentity Multiplier isisisisportportportport (a,b: inininin std_logic_vector(31 downtodowntodowntodownto 0);

m: outoutoutout std_logic_vector(63 downtodowntodowntodownto 0));endendendend Multiplier;

architecturearchitecturearchitecturearchitecture behavioral ofofofof Multiplier isisisisconstant constant constant constant modulDelay: TimeTimeTimeTime:=10 ns;beginbeginbeginbeginprocessprocessprocessprocess(a,b)variablevariablevariablevariable bReg: std_logic_vector(63 downtodowntodowntodownto 0);variablevariablevariablevariable aReg: std_logic_vector(31 downtodowntodowntodownto 0);beginbeginbeginbeginaReg:=a;bReg:=(x“00000000“) & b;forforforfor index inininin 1 totototo 32 looplooplooploopifififif bReg(0)= ‘ 1‘ thenthenthenthenbReg(63 downtodowntodowntodownto 32):=bReg(63 downtodowntodowntodownto 32)+aReg(31 downtodowntodowntodownto 0);end ifend ifend ifend if;bReg(63 downtodowntodowntodownto 0):= ‘ 0‘ &&&& bReg(63 downtodowntodowntodownto 1);

end loopend loopend loopend loop;m<=bReg afterafterafterafter modulDelay;

end process;end process;end process;end process;endendendend behavioral;

MultiplierMultiplierMultiplierMultiplier(32 bit(32 bit(32 bit(32 bit))))

a a a a

b b b b m m m m


JMM v1.5

Exercises vlsiExercises vlsiExercises vlsiExercises vlsi21: 21: 21: 21: LoopsLoopsLoopsLoops

� Ex405 (difficulty: easy): Ex405 (difficulty: easy): Ex405 (difficulty: easy): Ex405 (difficulty: easy): Write a VHDL code for a Write a VHDL code for a Write a VHDL code for a Write a VHDL code for a combinational shift logic block with 8 bit data combinational shift logic block with 8 bit data combinational shift logic block with 8 bit data combinational shift logic block with 8 bit data buses with zero fill. Use the 2 bit signal buses with zero fill. Use the 2 bit signal buses with zero fill. Use the 2 bit signal buses with zero fill. Use the 2 bit signal shiftNumshiftNumshiftNumshiftNumto indicate the number of bits to be shifted. If a to indicate the number of bits to be shifted. If a to indicate the number of bits to be shifted. If a to indicate the number of bits to be shifted. If a std_logic_vectorstd_logic_vectorstd_logic_vectorstd_logic_vector has to be converted to an has to be converted to an has to be converted to an has to be converted to an integerintegerintegerintegertype, the type, the type, the type, the conv_integerconv_integerconv_integerconv_integer()()()() function from the function from the function from the function from the std_logic_unsignedstd_logic_unsignedstd_logic_unsignedstd_logic_unsigned package can be used.package can be used.package can be used.package can be used.

ShiftShiftShiftShiftdataIndataIndataIndataIn

shiftLeftshiftLeftshiftLeftshiftLeft shiftRightshiftRightshiftRightshiftRight

shiftNumshiftNumshiftNumshiftNum

datadatadatadataOutOutOutOut


JMM v1.5

More on ProcessesMore on ProcessesMore on ProcessesMore on Processes

� Never assign a value to a signal in different Never assign a value to a signal in different Never assign a value to a signal in different Never assign a value to a signal in different processes (multiple drives).processes (multiple drives).processes (multiple drives).processes (multiple drives).

� Upon initialization all processes are executed at Upon initialization all processes are executed at Upon initialization all processes are executed at Upon initialization all processes are executed at once.once.once.once.

� Thereafter processes are executed in a dataThereafter processes are executed in a dataThereafter processes are executed in a dataThereafter processes are executed in a data----driven driven driven driven manner: manner: manner: manner: � activated by events on activated by events on activated by events on activated by events on signal listsignal listsignal listsignal list of the process orof the process orof the process orof the process or� by waiting on occurrences of specific events using by waiting on occurrences of specific events using by waiting on occurrences of specific events using by waiting on occurrences of specific events using wait wait wait wait

statementsstatementsstatementsstatements

process Aprocess Aprocess Aprocess Ay<=‘0‘;y<=‘0‘;y<=‘0‘;y<=‘0‘;

process Bprocess Bprocess Bprocess By<=‘1‘;y<=‘1‘;y<=‘1‘;y<=‘1‘;

conflictconflictconflictconflict---- two drivers!two drivers!two drivers!two drivers!---- not not not not synthesisynthesisynthesisynthesissssable!able!able!able!


JMM v1.5

The Wait StateThe Wait StateThe Wait StateThe Wait Statementmentmentment

� A more general way to specify when a process A more general way to specify when a process A more general way to specify when a process A more general way to specify when a process executes is the wait statement.executes is the wait statement.executes is the wait statement.executes is the wait statement.

� Wait statements explicitly specify the conditions Wait statements explicitly specify the conditions Wait statements explicitly specify the conditions Wait statements explicitly specify the conditions under which a process may resume execution after under which a process may resume execution after under which a process may resume execution after under which a process may resume execution after being suspendbeing suspendbeing suspendbeing suspendedededed. . . .

� With wait statements a process can be suspended at With wait statements a process can be suspended at With wait statements a process can be suspended at With wait statements a process can be suspended at multiple points.multiple points.multiple points.multiple points.

wait for wait for wait for wait for time expression;example: wait forwait forwait forwait for 20 nsnsnsns;

wait on wait on wait on wait on signal;example: wait on wait on wait on wait on clk,reset,status;

wait until wait until wait until wait until condition;example: wait until wait until wait until wait until (a = ‘1‘);

wait;wait;wait;wait;


JMM v1.5

Example: Wait StatementsExample: Wait StatementsExample: Wait StatementsExample: Wait Statementslibrary library library library IEEE;;;;useuseuseuse IEEE.std_logic_1164.all;

entityentityentityentity Dff2 isisisisportportportport (d,clk,rst: inininin std_logic;

q,qBar: outoutoutout std_logic);endendendend Dff2;

architecturearchitecturearchitecturearchitecture behavioral ofofofof Dff2 isisisisbeginbeginbeginbeginprocessprocessprocessprocess(clk,rst);beginbeginbeginbegin

ifififif (rst=‘0‘) thenthenthenthenq <= ‘0‘ afterafterafterafter 1 nsnsnsns;qBar<= ‘1‘ afterafterafterafter 1 nsnsnsns;

elsifelsifelsifelsif (clk‘eventeventeventevent andandandand clk=‘1‘) thenthenthenthenq <=d afterafterafterafter 1 nsnsnsns;qBar<=notnotnotnot d afterafterafterafter 1 nsnsnsns;

end ifend ifend ifend if;end process;end process;end process;end process;

endendendend behavioral;


entityentityentityentity Dff1 isisisisportportportport (d,clk: inininin std_logic;

q,qBar: outoutoutout std_logic);endendendend Dff1;

architecturearchitecturearchitecturearchitecture behavioral ofofofof Dff1 isisisisbeginbeginbeginbeginprocessprocessprocessprocessbeginbeginbeginbeginwait untilwait untilwait untilwait until (clk‘eventeventeventevent andandandand clk=‘1‘);q <=d afterafterafterafter 1 nsnsnsns;qBar<=notnotnotnot d afterafterafterafter 1 nsnsnsns;

end process;end process;end process;end process;endendendend behavioral;

if a process has no sensitivity list you MUST if a process has no sensitivity list you MUST if a process has no sensitivity list you MUST if a process has no sensitivity list you MUST use wait statements, otherwise your process use wait statements, otherwise your process use wait statements, otherwise your process use wait statements, otherwise your process never suspends and blocks your simulationnever suspends and blocks your simulationnever suspends and blocks your simulationnever suspends and blocks your simulation


JMM v1.5

Latch vs. FLatch vs. FLatch vs. FLatch vs. Fliplipliplip----FFFFloploploplop

processprocessprocessprocess(clk,reset)beginbeginbeginbegin

if if if if (reset = ‘0’) thenthenthenthenq <= ‘0’;

elsifelsifelsifelsif (clk’eventeventeventevent and clk=‘1’) thenthenthenthenq <= d;

end if;end if;end if;end if;end process;end process;end process;end process;

processprocessprocessprocess(clk,reset,d)beginbeginbeginbegin

if if if if (reset = ‘0’) thenthenthenthenq <= ‘0’;

elsifelsifelsifelsif (clk=‘1’) thenthenthenthenq <= d;


dddd qqqq

clkclkclkclk

resetresetresetreset

DDDD QQQQ

LatchLatchLatchLatch

dddd qqqq

clkclkclkclk


DDDD QQQQ

FlipFlipFlipFlip----FlopFlopFlopFlop

processprocessprocessprocess(clk,reset)beginbeginbeginbegin

if if if if (reset = ‘0‘) thenthenthenthenq <= “00000000“;

elsifelsifelsifelsif rising_edge(clk) thenthenthenthenifififif (enable = ‘1’) thenthenthenthenq <= d;

end ifend ifend ifend if;end if;end if;end if;end if;

end process;end process;end process;end process;

DDDD QQQQ

enableenableenableenable

qqqq

clkclkclkclk

dddd MuxMuxMuxMux


registerregisterregisterregister


JMM v1.5

Exercises vlsiExercises vlsiExercises vlsiExercises vlsi21: Synchronous21: Synchronous21: Synchronous21: Synchronous

� Ex406 (difficulty: easy): Ex406 (difficulty: easy): Ex406 (difficulty: easy): Ex406 (difficulty: easy): Write a VHDL code for a Write a VHDL code for a Write a VHDL code for a Write a VHDL code for a 16 bit register with an 16 bit register with an 16 bit register with an 16 bit register with an enableenableenableenable and a asynchronous and a asynchronous and a asynchronous and a asynchronous resetresetresetreset input.input.input.input.

� Ex40Ex40Ex40Ex407777 (difficulty: easy): (difficulty: easy): (difficulty: easy): (difficulty: easy): Write a VHDL code for a Write a VHDL code for a Write a VHDL code for a Write a VHDL code for a 16 bit counter with an 16 bit counter with an 16 bit counter with an 16 bit counter with an enableenableenableenable a a a a loadloadloadload aaaand and and and aasynchronous asynchronous asynchronous asynchronous resetresetresetreset input.input.input.input.

enableenableenableenablecountcountcountcount

clkclkclkclk


loadloadloadload

datadatadatadata

Counter16Counter16Counter16Counter16

enableenableenableenableqqqq

clkclkclkclk


dddd

Register16Register16Register16Register16


JMM v1.5

More on Wait: InterMore on Wait: InterMore on Wait: InterMore on Wait: Inter----Process Process Process Process Comm. Comm. Comm. Comm. transmitDatatransmitDatatransmitDatatransmitData

requestrequestrequestrequestacknowledgeacknowledgeacknowledgeacknowledgereceiveDreceiveDreceiveDreceiveDataataataata

timetimetimetime

entityentityentityentity Handshake isisisisportportportport(inputData: inininin std_logic_vector(31 downtodowntodowntodownto 0));endendendend Handshake;

architecturearchitecturearchitecturearchitecture behavioral ofofofof Handshake isisisissignalsignalsignalsignal transmitData: std_logic_vector(31 downtodowntodowntodownto 0);signalsignalsignalsignal request, acknowledge: std_logic;beginbeginbeginbegin

producer: process: process: process: processbeginbeginbeginbegin

wait until wait until wait until wait until inputData‘eventeventeventevent;transmitData<=inputData;request<=‘1‘;

wait untilwait untilwait untilwait until acknowledge=‘1‘;request<=‘0‘;

wait untilwait untilwait untilwait until acknowledge=‘0‘; end process;end process;end process;end process;

end end end end behavioral;;;;

consumer: process: process: process: processvariablevariablevariablevariable receiveData: std_logic_vector(31 downtodowntodowntodownto 0);

beginbeginbeginbeginwait until wait until wait until wait until request=‘1‘;receiveData:=transmitData;acknowledge<=‘1‘;

wait untilwait untilwait untilwait until request=‘0‘;acknowledge<=‘0‘;



JMM v1.5

Exercises vlsi21: HandshakeExercises vlsi21: HandshakeExercises vlsi21: HandshakeExercises vlsi21: Handshake

� Ex vlsi408a (difficulty: easy, optional): Ex vlsi408a (difficulty: easy, optional): Ex vlsi408a (difficulty: easy, optional): Ex vlsi408a (difficulty: easy, optional): Write a Write a Write a Write a VHDL model for communication between an VHDL model for communication between an VHDL model for communication between an VHDL model for communication between an input input input input processprocessprocessprocess and an and an and an and an output processoutput processoutput processoutput process using handshaking using handshaking using handshaking using handshaking protocol. The protocol. The protocol. The protocol. The input processinput processinput processinput process can only read a single can only read a single can only read a single can only read a single word (32 bit) at a time. The output device requires word (32 bit) at a time. The output device requires word (32 bit) at a time. The output device requires word (32 bit) at a time. The output device requires a reversing byte order, which is performed by the a reversing byte order, which is performed by the a reversing byte order, which is performed by the a reversing byte order, which is performed by the input processinput processinput processinput process. Assign a delay of 1 ns to each . Assign a delay of 1 ns to each . Assign a delay of 1 ns to each . Assign a delay of 1 ns to each handshake signal.handshake signal.handshake signal.handshake signal.

� Ex vlsi408b (difficulty: medium, optional):Ex vlsi408b (difficulty: medium, optional):Ex vlsi408b (difficulty: medium, optional):Ex vlsi408b (difficulty: medium, optional):Rewrite the above handshake model by using a clk1, Rewrite the above handshake model by using a clk1, Rewrite the above handshake model by using a clk1, Rewrite the above handshake model by using a clk1, clk2 signal for the two synchronous processes as clk2 signal for the two synchronous processes as clk2 signal for the two synchronous processes as clk2 signal for the two synchronous processes as well as a well as a well as a well as a rstrstrstrst for initialization, and a start signal to for initialization, and a start signal to for initialization, and a start signal to for initialization, and a start signal to initiate one data transfer. Do not use any wait initiate one data transfer. Do not use any wait initiate one data transfer. Do not use any wait initiate one data transfer. Do not use any wait constructions within the processes.constructions within the processes.constructions within the processes.constructions within the processes.

output processoutput processoutput processoutput processinput processinput processinput processinput process

AsyncCommAsyncCommAsyncCommAsyncComm

inputDatainputDatainputDatainputData outputDataoutputDataoutputDataoutputData


JMM v1.5

AttributesAttributesAttributesAttributesattributeattributeattributeattribute functionfunctionfunctionfunctionsignal’event’event’event’event function returning a Boolean value function returning a Boolean value function returning a Boolean value function returning a Boolean value

signifying a change in value on this signalsignifying a change in value on this signalsignifying a change in value on this signalsignifying a change in value on this signalsignal’active’active’active’active function returning a Boolean value function returning a Boolean value function returning a Boolean value function returning a Boolean value

signifying an assignment made to this signifying an assignment made to this signifying an assignment made to this signifying an assignment made to this signal (may not be a new value)signal (may not be a new value)signal (may not be a new value)signal (may not be a new value)

signal’last_event’last_event’last_event’last_event function returning the time since thefunction returning the time since thefunction returning the time since thefunction returning the time since thelast eventlast eventlast eventlast event

signal’last_active’last_active’last_active’last_active function returning the time since the function returning the time since the function returning the time since the function returning the time since the signal was last activesignal was last activesignal was last activesignal was last active

signal’last_value’last_value’last_value’last_value function returning the previous value function returning the previous value function returning the previous value function returning the previous value of this signalof this signalof this signalof this signal

signal’left’left’left’left returns the leftmost value of signal in returns the leftmost value of signal in returns the leftmost value of signal in returns the leftmost value of signal in its defined rangeits defined rangeits defined rangeits defined range

signal’right’right’right’right returns the rightmost value of signal returns the rightmost value of signal returns the rightmost value of signal returns the rightmost value of signal in its defined rangein its defined rangein its defined rangein its defined range

signal’hight’hight’hight’hight returns the highest value of signal returns the highest value of signal returns the highest value of signal returns the highest value of signal in its defined rangein its defined rangein its defined rangein its defined range

signal’low’low’low’low returns the lowest value of signal returns the lowest value of signal returns the lowest value of signal returns the lowest value of signal in its defined rangein its defined rangein its defined rangein its defined range

signal’ascending’ascending’ascending’ascending returns true if signal has an ascending returns true if signal has an ascending returns true if signal has an ascending returns true if signal has an ascending range of valuesrange of valuesrange of valuesrange of values

signal’length’length’length’length returns the number of elements in the returns the number of elements in the returns the number of elements in the returns the number of elements in the array signalarray signalarray signalarray signal


JMM v1.5

Generating Periodic WaveformsGenerating Periodic WaveformsGenerating Periodic WaveformsGenerating Periodic Waveformslibrary IEEE;library IEEE;library IEEE;library IEEE;use use use use IEEE.std_logic_1164.all;

entityentityentityentity Periodic isisisisportportportport(Z: outoutoutout std_logic);endendendend Periodic;

architecturearchitecturearchitecturearchitecture behavioral ofofofof Periodic isisisisbeginbeginbeginbeginprocessprocessprocessprocessbeginbeginbeginbeginZ<=‘0’, ‘1’ afterafterafterafter 10 nsnsnsns, ‘0’ afterafterafterafter 20 nsnsnsns, ‘1’ afterafterafterafter 40 nsnsnsns;wait for wait for wait for wait for 50 nsnsnsns;

end process;end process;end process;end process;end end end end behavioral;;;;

ZZZZ

0000 10101010 20202020 30303030 40404040 50505050


library IEEE;library IEEE;library IEEE;library IEEE;use use use use IEEE.std_logic_1164.all;

entityentityentityentity TwoPhase isisisisportportportport(phi1,phi2,reset: outoutoutout std_logic);endendendend twoPhase;

architecturearchitecturearchitecturearchitecture behavioral ofofofof TwoPhase isisisisbeginbeginbeginbeginreset_process: reset<=‘1’, ‘0’ afterafterafterafter 10 nsnsnsns;clock_process: processprocessprocessprocessbeginbeginbeginbeginphi1<=‘1’, ‘0’ afterafterafterafter 10 nsnsnsns;phi2<=‘0’, ‘1’ afterafterafterafter 12 nsnsnsns, ‘0’ after after after after 18 nsnsnsns;wait for wait for wait for wait for 20 nsnsnsns;

end process;end process;end process;end process;end end end end behavioral;;;;

resetresetresetresetphi1phi1phi1phi1phi2phi2phi2phi2

0000 10101010 20202020 30303030 40404040 50505050time (ns)time (ns)time (ns)time (ns)

60606060


JMM v1.5

Modeling Finite State MachinesModeling Finite State MachinesModeling Finite State MachinesModeling Finite State Machines

enableenableenableenable

clkclkclkclk

outputoutputoutputoutputprocessprocessprocessprocess


statestatestatestateregisterregisterregisterregister

inputDatainputDatainputDatainputDataoutputDataoutputDataoutputDataoutputData

outSig0outSig0outSig0outSig0outSig1outSig1outSig1outSig1outSig2outSig2outSig2outSig2

statestatestatestatetransitiontransitiontransitiontransitionprocessprocessprocessprocess

architecturearchitecturearchitecturearchitecture behavioral ofofofof MooreFSM isisisistype type type type StateType is is is is (MyState,YourState,InitState);signalsignalsignalsignal state :::: StateType;signalsignalsignalsignal outputData: std_logic_vector(5 downtodowntodowntodownto 0);beginbeginbeginbegin

transition_process: processprocessprocessprocess(reset,clk)beginbeginbeginbegin

if if if if (reset = ‘0’) thenthenthenthenstate <= InitState;

elsifelsifelsifelsif rising_edge(clk) thenthenthenthencasecasecasecase state is is is is

whenwhenwhenwhen MyState => state<=YourState;

whenwhenwhenwhen YourState =>ifififif (inputDataSignal = ‘1’) thenthenthenthenstate<=MyState;

end ifend ifend ifend if;when otherswhen otherswhen otherswhen others => nullnullnullnull;

end caseend caseend caseend case;end ifend ifend ifend if;

end processend processend processend process;

output_process: processprocessprocessprocess(state)beginbeginbeginbegincasecasecasecase state isisisis

whenwhenwhenwhen MyState => outputData<=“01—00”;

whenwhenwhenwhen YourState =>outputData<=“00100-”;

whenwhenwhenwhen InitState =>outputData<= “100100”;

when otherswhen otherswhen otherswhen others => outputData<=“000000”;

end caseend caseend caseend case;end processend processend processend process;

outSig0<=outputData(0);outSig1 <=outputData(1);outSig2<=outputData(2);

end end end end behavioral;


JMM v1.5

Exercises vlsi21Exercises vlsi21Exercises vlsi21Exercises vlsi21: : : : FSMFSMFSMFSM

� Ex409 (difficulty: easy): Ex409 (difficulty: easy): Ex409 (difficulty: easy): Ex409 (difficulty: easy): Write a VHDL model for Write a VHDL model for Write a VHDL model for Write a VHDL model for a traffic light controller. Use a Moore type FSM. a traffic light controller. Use a Moore type FSM. a traffic light controller. Use a Moore type FSM. a traffic light controller. Use a Moore type FSM. The signal The signal The signal The signal carPresentcarPresentcarPresentcarPresent indicates cars running on the indicates cars running on the indicates cars running on the indicates cars running on the main street which always have priority. If no cars main street which always have priority. If no cars main street which always have priority. If no cars main street which always have priority. If no cars are present on the main street, the secondary street are present on the main street, the secondary street are present on the main street, the secondary street are present on the main street, the secondary street gets green lights.gets green lights.gets green lights.gets green lights.

0 0 11 0 0

red

red

redred

oran

geor

ange

oran

geor

ange

gree

ngr

een

gree

ngr

een

GreenStateGreenStateGreenStateGreenState

OrangeStateOrangeStateOrangeStateOrangeState

RedState1RedState1RedState1RedState1

RedState2RedState2RedState2RedState2

carPresentcarPresentcarPresentcarPresent




mainmainmainmainsecondsecondsecondsecond

1 0 00 1 0

red

red

redred

oran

geor

ange

oran

geor

ange

gree

ngr

een

gree

ngr

een


1 0 00 0 1

red

red

redred

oran

geor

ange

oran

geor

ange

gree

ngr

een

gree

ngr

een


0 1 01 0 0

red

red

redred

oran

geor

ange

oran

geor

ange

gree

ngr

een

gree

ngr

een




JMM v1.5

Modeling StructureModeling StructureModeling StructureModeling Structure

� a structural model of a system is described in terms a structural model of a system is described in terms a structural model of a system is described in terms a structural model of a system is described in terms of interconnection of its componentsof interconnection of its componentsof interconnection of its componentsof interconnection of its components

� a structural model consists of 3 features:a structural model consists of 3 features:a structural model consists of 3 features:a structural model consists of 3 features:� component declarationcomponent declarationcomponent declarationcomponent declaration� signal declarationsignal declarationsignal declarationsignal declaration� component interconnectioncomponent interconnectioncomponent interconnectioncomponent interconnection

aaaabbbb

sumsumsumsumcarrycarrycarrycarry

HalfAdderHalfAdderHalfAdderHalfAdder3333

aaaabbbb


HalfAdderHalfAdderHalfAdderHalfAdder3333aaaabbbb


HalfAdderHalfAdderHalfAdderHalfAdder3333in1in1in1in1in2in2in2in2

cIncIncIncIn

sumsumsumsum

cOutcOutcOutcOut

s1s1s1s1

s2s2s2s2

s3s3s3s3

zzzzaaaa

bbbb

OR2OR2OR2OR2

portsportsportsports

componentcomponentcomponentcomponentdeclarationdeclarationdeclarationdeclaration

componentcomponentcomponentcomponentinterconnectioninterconnectioninterconnectioninterconnectionH1H1H1H1 H2H2H2H2

O3O3O3O3

component component component component labellabellabellabel

zzzzaaaa

bbbb

OR2OR2OR2OR2



JMM v1.5

Example: Structural ModelExample: Structural ModelExample: Structural ModelExample: Structural Model

librarylibrarylibrarylibrary IEEE;useuseuseuse IEEE.std_logic_1164.all;

entityentityentityentity FullAdder3 isisisisportportportport (in1,in2,cIn: inininin std_logic;

sum,cOut: outoutoutout std_logic);endendendend FullAdder3;

architecturearchitecturearchitecturearchitecture structural ofofofof FullAdder3 isisisiscomponentcomponentcomponentcomponent HalfAdder3portportportport(a,b: inininin std_logic;

sum,carry: outoutoutout std_logic);end componentend componentend componentend component;

componentcomponentcomponentcomponent OR2portportportport(a,b: inininin std_logic;

z: outoutoutout std_logic);end componentend componentend componentend component;

signalsignalsignalsignal s1,s2,s3: std_logic;

beginbeginbeginbeginH1: HalfAdder3 port mapport mapport mapport map(a=>in1,b=>in2,

sum=>s1,carry=>s3);H2: HalfAdder3 port mapport mapport mapport map(a=>s1,b=>cIn,

sum=>sum,carry=>s2);O3: OR2 port mapport mapport mapport map(a=>s2,b=>s3,

z=>cOut);endendendend structural;

component component component component declarationdeclarationdeclarationdeclaration

signal signal signal signal declarationdeclarationdeclarationdeclaration

componentcomponentcomponentcomponentinterconnectioninterconnectioninterconnectioninterconnection((((netlistnetlistnetlistnetlist))))

component behaviorcomponent behaviorcomponent behaviorcomponent behaviordescribed elsewheredescribed elsewheredescribed elsewheredescribed elsewhere


JMM v1.5

Exercises Exercises Exercises Exercises vlsi21: Structural Modelvlsi21: Structural Modelvlsi21: Structural Modelvlsi21: Structural Model

� Ex410 (difficulty: medium): Ex410 (difficulty: medium): Ex410 (difficulty: medium): Ex410 (difficulty: medium): Write a VHDL code Write a VHDL code Write a VHDL code Write a VHDL code for the structural model of the FullAdder3 for the structural model of the FullAdder3 for the structural model of the FullAdder3 for the structural model of the FullAdder3 described in the previous transparency. Assume a described in the previous transparency. Assume a described in the previous transparency. Assume a described in the previous transparency. Assume a delay of 1 ns for all logic gates delay of 1 ns for all logic gates delay of 1 ns for all logic gates delay of 1 ns for all logic gates

a)a)a)a) Write the structural VHDL code for a Write the structural VHDL code for a Write the structural VHDL code for a Write the structural VHDL code for a HalfAdderHalfAdderHalfAdderHalfAdder....b)b)b)b) Write the VHDL codes for the necessary logic Write the VHDL codes for the necessary logic Write the VHDL codes for the necessary logic Write the VHDL codes for the necessary logic

gates like OR2 and others in one file gates like OR2 and others in one file gates like OR2 and others in one file gates like OR2 and others in one file ((((logicgates.vhdlogicgates.vhdlogicgates.vhdlogicgates.vhd))))

b)b)b)b) Write the VHDL code for FullAdder3 Write the VHDL code for FullAdder3 Write the VHDL code for FullAdder3 Write the VHDL code for FullAdder3 c)c)c)c) Analyze and simulate the whole circuit. Be aware Analyze and simulate the whole circuit. Be aware Analyze and simulate the whole circuit. Be aware Analyze and simulate the whole circuit. Be aware

of the correct sequence of analyzing.of the correct sequence of analyzing.of the correct sequence of analyzing.of the correct sequence of analyzing.


JMM v1.5

VHDL vs. VHDL vs. VHDL vs. VHDL vs. VeriloVeriloVeriloVerilogggg: : : : StructuralStructuralStructuralStructuralDescription Description Description Description

librarylibrarylibrarylibrary IEEE;useuseuseuse IEEE.std_logic_1164.all;entityentityentityentity FullAdder4 isisisis

portportportport (a,b,cIn:inininin std_logic; cOut,sum:outoutoutout std_logic);

endendendend FullAdder4;

architecturearchitecturearchitecturearchitecture flatStructure ofofofof FullAdder4 isisisiscomponentcomponentcomponentcomponent XOR

portportportport(a,b: inininin std_logic; z:outoutoutout std_logic);end componentend componentend componentend component;componentcomponentcomponentcomponent AND2

portportportport(a,b: inininin std_logic; z:outoutoutout std_logic);end componentend componentend componentend component;componentcomponentcomponentcomponent OR3

portportportport(a,b,c: inininin std_logic; z:outoutoutout std_logic);end componentend componentend componentend component;signalsignalsignalsignal net1,net2,net3,net4:std_logic;

beginbeginbeginbeginu1: XOR port map port map port map port map (a,b,net1);u2: XOR port map port map port map port map (cIn,net1,sum);u3: AND2 port map port map port map port map (cIn,a,net2);u4: AND2 port map port map port map port map (cIn,b,net3);u5: AND2 port map port map port map port map (a,b,net4);u6: OR3 port map port map port map port map (net2,net3,net4,cOut);

endendendend flatStructure;

module module module module FullAdder4(a,b,cIn,cOut,sum);inputinputinputinput a,b,cIn;outputoutputoutputoutput cOut,sum;wirewirewirewire net1,net2,net3,net4;

XOR u1(net1,a,b);XOR u2(sum,cIn,net1);AND2 u3(net2,cIn,a);AND2 u4(net3,cIn,a);AND2 u5(net4,a,b);OR3u6(cOut,net2,net3,net4);


VHDLVHDLVHDLVHDL



JMM v1.5

VHDL vs. VHDL vs. VHDL vs. VHDL vs. VerilogVerilogVerilogVerilog::::Data FloData FloData FloData Flowwww DescriptionDescriptionDescriptionDescription

library library library library IEEE;useuseuseuse IEEE.std_logic_1164.all;useuseuseuse IEEE.std_logic_unsigned.all;

entityentityentityentity FullAdder5 isisisisportportportport (a,b,cIn:inininin std_logi;

sum,cOut:outoutoutout std_logic);endendendend FullAdder5;

architecturearchitecturearchitecturearchitecture dataFlow ofofofof FullAdder5 isisisissignal signal signal signal tmp: std_logic_vector(1 downtodowntodowntodownto 0);beginbeginbeginbegin

tmp <= ‘0‘ & a + b + cIn;cOut <= tmp(1);sum <= tmp(0);

endendendend behavior; module module module module FullAdder5 (a,b,cIn,sum,cOut);inputinputinputinput a,b,cIn;outputoutputoutputoutput cOut,sum;

assignassignassignassign {cOut,sum} = a + b + cIn;endmoduleendmoduleendmoduleendmodule

VHDLVHDLVHDLVHDL



JMM v1.5

Hierarchy, Abstraction, and AccuracyHierarchy, Abstraction, and AccuracyHierarchy, Abstraction, and AccuracyHierarchy, Abstraction, and Accuracy

� Structural models simply describe interconnectionsStructural models simply describe interconnectionsStructural models simply describe interconnectionsStructural models simply describe interconnections� Structural models do not describe any form of Structural models do not describe any form of Structural models do not describe any form of Structural models do not describe any form of

behaviorbehaviorbehaviorbehavior� Hierarchy expresses different levels of detailHierarchy expresses different levels of detailHierarchy expresses different levels of detailHierarchy expresses different levels of detail� Structural models are a way to manage large, Structural models are a way to manage large, Structural models are a way to manage large, Structural models are a way to manage large,

complex designscomplex designscomplex designscomplex designs� Modern designs have several 10 millions of gatesModern designs have several 10 millions of gatesModern designs have several 10 millions of gatesModern designs have several 10 millions of gates� Simulation time: the more detailed a design is Simulation time: the more detailed a design is Simulation time: the more detailed a design is Simulation time: the more detailed a design is

described, the more events are generated and thus described, the more events are generated and thus described, the more events are generated and thus described, the more events are generated and thus the larger the simulation time will be needed.the larger the simulation time will be needed.the larger the simulation time will be needed.the larger the simulation time will be needed.

FullAdder3FullAdder3FullAdder3FullAdder3

OR2OR2OR2OR2 HalfAdder3HalfAdder3HalfAdder3HalfAdder3

AND2AND2AND2AND2 XOR2XOR2XOR2XOR2

top leveltop leveltop leveltop level

bottom levelbottom levelbottom levelbottom level


JMM v1.5

GenericsGenericsGenericsGenerics� The VHDL language provides the ability to construct The VHDL language provides the ability to construct The VHDL language provides the ability to construct The VHDL language provides the ability to construct

parameterized models using the concept of parameterized models using the concept of parameterized models using the concept of parameterized models using the concept of genericsgenericsgenericsgenerics

library library library library IEEE;useuseuseuse IEEE.std_logic_1164.all;

entityentityentityentity HalfAdder4 isisisisgenericgenericgenericgeneric(adderDelay: TimeTimeTimeTime:=3 nsnsnsns);portportportport(a,b : inininin std_logic;

sum,carry: outoutoutout std_logic;endendendend HalfAdder4;

architecturearchitecturearchitecturearchitecture genericDelay ofofofof HalfAdder4 isisisiscomponentcomponentcomponentcomponent AND2 isisisisgenericgenericgenericgeneric(andDelay: TimeTimeTimeTime);portportportport(a,b : inininin std_logic; z: outoutoutout std_logic;endendendend component;

componentcomponentcomponentcomponent XOR2 isisisisgenericgenericgenericgeneric(xorDelay: TimeTimeTimeTime);portportportport(a,b : inininin std_logic; z: outoutoutout std_logic;endendendend component;

beginbeginbeginbeginC1: XOR2 generic mapgeneric mapgeneric mapgeneric map(12 nsnsnsns) port mapport mapport mapport map(a,b,sum);C2: AND2 generic mapgeneric mapgeneric mapgeneric map(adderDelay) port mapport mapport mapport map(a,b,carry);endendendend genericDelay;

library library library library IEEE;useuseuseuse IEEE.std_logic_1164.all;

entityentityentityentity HalfAdder4 isisisisgenericgenericgenericgeneric(adderDelay: TimeTimeTimeTime:=3 nsnsnsns);portportportport(a,b : inininin std_logic;

sum,carry: outoutoutout std_logic;endendendend HalfAdder4;

architecturearchitecturearchitecturearchitecture genericDelay ofofofof HalfAdder4 isisisiscomponentcomponentcomponentcomponent AND2 isisisisgenericgenericgenericgeneric(andDelay: TimeTimeTimeTime);portportportport(a,b : inininin std_logic; z: outoutoutout std_logic;endendendend component;

componentcomponentcomponentcomponent XOR2 isisisisgenericgenericgenericgeneric(xorDelay: TimeTimeTimeTime);portportportport(a,b : inininin std_logic; z: outoutoutout std_logic;endendendend component;

beginbeginbeginbeginC1: XOR2 generic mapgeneric mapgeneric mapgeneric map(12 nsnsnsns) port mapport mapport mapport map(a,b,sum);C2: AND2 generic mapgeneric mapgeneric mapgeneric map(adderDelay) port mapport mapport mapport map(a,b,carry);endendendend genericDelay;

entityentityentityentity AND2 isgenericgenericgenericgeneric(andDelay: TimeTimeTimeTime);portportportport(a,b : inininin std_logic; z: outoutoutout std_logic;endendendend AND2;

architecturearchitecturearchitecturearchitecture genericDelay ofofofof AND2 isisisisbeginbeginbeginbeginz<=a andandandand b afterafterafterafter andDelay;

endendendend genericDelay;

values to genericsvalues to genericsvalues to genericsvalues to genericscan be assigned atcan be assigned atcan be assigned atcan be assigned atdifferent locationsdifferent locationsdifferent locationsdifferent locations

no semi columnno semi columnno semi columnno semi columnneededneededneededneeded


JMM v1.5

More on GenericsMore on GenericsMore on GenericsMore on Generics� Within a structural model there are two ways in Within a structural model there are two ways in Within a structural model there are two ways in Within a structural model there are two ways in

which the values of generic constants of lower level which the values of generic constants of lower level which the values of generic constants of lower level which the values of generic constants of lower level components can be specified:components can be specified:components can be specified:components can be specified:� in the component declarationin the component declarationin the component declarationin the component declaration� in the component instantiationin the component instantiationin the component instantiationin the component instantiation

� If both are specified, then the value provided by the If both are specified, then the value provided by the If both are specified, then the value provided by the If both are specified, then the value provided by the generic map() takes precedence.generic map() takes precedence.generic map() takes precedence.generic map() takes precedence.

� If neither is specified, then the default value If neither is specified, then the default value If neither is specified, then the default value If neither is specified, then the default value defined in the model is used.defined in the model is used.defined in the model is used.defined in the model is used.

library library library library IEEE;useuseuseuse IEEE.std_logic_1164.all;entityentityentityentity GenericOR isisisisgenericgenericgenericgeneric(n: positivepositivepositivepositive:=2);portportportport(in1: inininin std_logic_vector((n-1) downtodowntodowntodownto 0); z: outoutoutout std_logic);endendendend GenericOR;

architecturearchitecturearchitecturearchitecture behavioral ofofofof GenericOR isisisisbeginbeginbeginbeginprocessprocessprocessprocess(in1)variablevariablevariablevariable sum: std_logic:=‘0‘;

beginbeginbeginbeginsum:=‘0‘;forforforfor i inininin 0 totototo (n-1) looplooplooploopsum:=sum orororor in1(i);

end loopend loopend loopend loop;z<=sum;

endendendend processprocessprocessprocess;endendendend behavioral;


JMM v1.5

Exercises vlsi21: Hierarchy, GenericExercises vlsi21: Hierarchy, GenericExercises vlsi21: Hierarchy, GenericExercises vlsi21: Hierarchy, Generic

� Ex411 (difficulty: medium): Ex411 (difficulty: medium): Ex411 (difficulty: medium): Ex411 (difficulty: medium): Write a VHDL code Write a VHDL code Write a VHDL code Write a VHDL code of of of of an an an an 8 bit ALU based on the 8 bit ALU based on the 8 bit ALU based on the 8 bit ALU based on the definitionsdefinitionsdefinitionsdefinitions made in made in made in made in Ex402 with the Ex402 with the Ex402 with the Ex402 with the Simple1BitALUSimple1BitALUSimple1BitALUSimple1BitALU. . . .

a)a)a)a) Write a behavioral VHDL code for ALU8b.vhd Write a behavioral VHDL code for ALU8b.vhd Write a behavioral VHDL code for ALU8b.vhd Write a behavioral VHDL code for ALU8b.vhd b)b)b)b) Write the structural VHDL code for ALU8 in one Write the structural VHDL code for ALU8 in one Write the structural VHDL code for ALU8 in one Write the structural VHDL code for ALU8 in one

file file file file ALU8s.vhdALU8s.vhdALU8s.vhdALU8s.vhd. Assume a delay of 1 ns for all . Assume a delay of 1 ns for all . Assume a delay of 1 ns for all . Assume a delay of 1 ns for all logic gates. What is the worst case delay of the logic gates. What is the worst case delay of the logic gates. What is the worst case delay of the logic gates. What is the worst case delay of the ALU8.ALU8.ALU8.ALU8.

� Ex412 (difficulty: easy): Ex412 (difficulty: easy): Ex412 (difficulty: easy): Ex412 (difficulty: easy): Write a VHDL code of Write a VHDL code of Write a VHDL code of Write a VHDL code of an an an an nnnn bit register with bit register with bit register with bit register with resetresetresetreset and and and and enableenableenableenable inputs inputs inputs inputs ((((NbitRegister.vhdNbitRegister.vhdNbitRegister.vhdNbitRegister.vhd). ). ). ).


JMM v1.5

ConConConConfigurationfigurationfigurationfiguration

� Structural models may employ different levels of Structural models may employ different levels of Structural models may employ different levels of Structural models may employ different levels of abstractionabstractionabstractionabstraction

� Each component in a structural model may be Each component in a structural model may be Each component in a structural model may be Each component in a structural model may be described as a behavioral or a structural modeldescribed as a behavioral or a structural modeldescribed as a behavioral or a structural modeldescribed as a behavioral or a structural model

� Configuration allows stepwise refinement in a Configuration allows stepwise refinement in a Configuration allows stepwise refinement in a Configuration allows stepwise refinement in a design cycledesign cycledesign cycledesign cycle

� Configuration represents resource bindingConfiguration represents resource bindingConfiguration represents resource bindingConfiguration represents resource binding� DescriptionDescriptionDescriptionDescription----synthesis design methodsynthesis design methodsynthesis design methodsynthesis design method


OR2OR2OR2OR2 HalfAdder3HalfAdder3HalfAdder3HalfAdder3

AND2AND2AND2AND2 XOR2XOR2XOR2XOR2

Configuration associates Configuration associates Configuration associates Configuration associates an architecturean architecturean architecturean architecturedescription to each description to each description to each description to each component:component:component:component:

- behavioralbehavioralbehavioralbehavioral or or or or - structuralstructuralstructuralstructural for for for for



JMM v1.5

Configuration: Component BindingConfiguration: Component BindingConfiguration: Component BindingConfiguration: Component Binding

qqqq

clkclkclkclk


dddd

CombCombCombComb((((combinationalcombinationalcombinationalcombinational

logiclogiclogiclogic)))) carrycarrycarrycarry

aaaabbbb

sumsumsumsum

architecture architecture architecture architecture gataLevel of of of of Comb isisisis---- ---- ----

architecture architecture architecture architecture lowPower of of of of Comb isisisis---- ---- ----

architecture architecture architecture architecture highSpeed of of of of Comb isisisis---- ---- ----

architecture architecture architecture architecture behavioral of of of of Comb isisisis---- ---- ----

� Example of binding architectures: A bitExample of binding architectures: A bitExample of binding architectures: A bitExample of binding architectures: A bit----serial adderserial adderserial adderserial adder� one of the different architectures must be one of the different architectures must be one of the different architectures must be one of the different architectures must be

bound to the component C1 for simulationbound to the component C1 for simulationbound to the component C1 for simulationbound to the component C1 for simulation� entity is not bound as interfaces do not changeentity is not bound as interfaces do not changeentity is not bound as interfaces do not changeentity is not bound as interfaces do not change

C1C1C1C1

C2C2C2C2DffDffDffDff

rstrstrstrst clockclockclockclock

carryIncarryIncarryIncarryIn


JMM v1.5

Configuration: Default Binding RulesConfiguration: Default Binding RulesConfiguration: Default Binding RulesConfiguration: Default Binding Rules

� To analyze different implementations, we simply To analyze different implementations, we simply To analyze different implementations, we simply To analyze different implementations, we simply change the configuration, compile and simulate.change the configuration, compile and simulate.change the configuration, compile and simulate.change the configuration, compile and simulate.

� When newer component models become available we When newer component models become available we When newer component models become available we When newer component models become available we bind the new architecture to the componentbind the new architecture to the componentbind the new architecture to the componentbind the new architecture to the component

Default binding rules:Default binding rules:Default binding rules:Default binding rules:� if the entity name is the same as the component if the entity name is the same as the component if the entity name is the same as the component if the entity name is the same as the component

name, then this entity is bound to the componentname, then this entity is bound to the componentname, then this entity is bound to the componentname, then this entity is bound to the component� if there are different architectures in the working if there are different architectures in the working if there are different architectures in the working if there are different architectures in the working

directory, the last compiled architecture is bound to directory, the last compiled architecture is bound to directory, the last compiled architecture is bound to directory, the last compiled architecture is bound to the entitythe entitythe entitythe entity


JMM v1.5

Example: ConfigurationExample: ConfigurationExample: ConfigurationExample: Configuration

configurationconfigurationconfigurationconfiguration CFG_HighSpeed ofofofof SerialAdder isisisis

forforforfor structuralforforforfor C1: Comb use entityuse entityuse entityuse entity WORK.Comb(highSpeed);end forend forend forend for;

forforforfor C2: Dff use entityuse entityuse entityuse entity MyLibrary.MyDff(behavioral)generic generic generic generic mapmapmapmap(gateDelay=>5 ns)port port port port mapmapmapmap(my_clk=>clk, my_d=>d,

my_q=>q, my_rst=>rst);end forend forend forend for;

end forend forend forend for;

endendendend CFG_HighSpeed;

library namelibrary namelibrary namelibrary nameentity nameentity nameentity nameentity namearchitecture namearchitecture namearchitecture namearchitecture name

entity nameentity nameentity nameentity nameconfiguration nameconfiguration nameconfiguration nameconfiguration name(used for simulation)(used for simulation)(used for simulation)(used for simulation)

if different component if different component if different component if different component than described in than described in than described in than described in entity is used, thenentity is used, thenentity is used, thenentity is used, thenI/O mapping must I/O mapping must I/O mapping must I/O mapping must be declared.be declared.be declared.be declared.

qqqq

clkclkclkclk


dddd

CombCombCombComb(combinational(combinational(combinational(combinational

logic)logic)logic)logic)carrycarrycarrycarry

in1in1in1in1in2in2in2in2

C1C1C1C1

C2C2C2C2 MyDffMyDffMyDffMyDff



highSpeedhighSpeedhighSpeedhighSpeed

behavioralbehavioralbehavioralbehavioral

sumsumsumsum


JMM v1.5

Exercises vlsi21: ConfigurationExercises vlsi21: ConfigurationExercises vlsi21: ConfigurationExercises vlsi21: Configuration

� Ex 413 (difficulty: easy): Ex 413 (difficulty: easy): Ex 413 (difficulty: easy): Ex 413 (difficulty: easy): Write a VHDL code of Write a VHDL code of Write a VHDL code of Write a VHDL code of the bitthe bitthe bitthe bit----serial adder shown in the previous serial adder shown in the previous serial adder shown in the previous serial adder shown in the previous transparency transparency transparency transparency SerialAdder.vhdSerialAdder.vhdSerialAdder.vhdSerialAdder.vhd

a)a)a)a) Construct a model for the two components Comb Construct a model for the two components Comb Construct a model for the two components Comb Construct a model for the two components Comb and and and and MyDffMyDffMyDffMyDff and place them both in your WORK and place them both in your WORK and place them both in your WORK and place them both in your WORK library (don‘t use the library library (don‘t use the library library (don‘t use the library library (don‘t use the library MyLibraryMyLibraryMyLibraryMyLibrary yet).yet).yet).yet).

b)b)b)b) Adapt the configuration, compile and simulate itAdapt the configuration, compile and simulate itAdapt the configuration, compile and simulate itAdapt the configuration, compile and simulate it....

� Ex414 (difficulty: medium): Ex414 (difficulty: medium): Ex414 (difficulty: medium): Ex414 (difficulty: medium): Consider the circuit Consider the circuit Consider the circuit Consider the circuit shown below (shown below (shown below (shown below (ConfigExampleConfigExampleConfigExampleConfigExample). Construct a ). Construct a ). Construct a ). Construct a structural model comprised of three components. structural model comprised of three components. structural model comprised of three components. structural model comprised of three components. However in the configuration use only two However in the configuration use only two However in the configuration use only two However in the configuration use only two components by using a ncomponents by using a ncomponents by using a ncomponents by using a n----input AND gate.input AND gate.input AND gate.input AND gate.

&

&

1≥

i1i1i1i1i2i2i2i2i3i3i3i3

o1o1o1o1


JMM v1.5

Subprograms, Packages and LibrariesSubprograms, Packages and LibrariesSubprograms, Packages and LibrariesSubprograms, Packages and Libraries

� VHDL provides mechanisms for structuring VHDL provides mechanisms for structuring VHDL provides mechanisms for structuring VHDL provides mechanisms for structuring programs, reusing software modules, and otherwise programs, reusing software modules, and otherwise programs, reusing software modules, and otherwise programs, reusing software modules, and otherwise managing design complexity.managing design complexity.managing design complexity.managing design complexity.

� Packages contain definitions of procedures and Packages contain definitions of procedures and Packages contain definitions of procedures and Packages contain definitions of procedures and functions that can be shared across different VHDL functions that can be shared across different VHDL functions that can be shared across different VHDL functions that can be shared across different VHDL models.models.models.models.

� Packages may contain user defined data types and Packages may contain user defined data types and Packages may contain user defined data types and Packages may contain user defined data types and constants and can be placed in libraries.constants and can be placed in libraries.constants and can be placed in libraries.constants and can be placed in libraries.

� Summary: Summary: Summary: Summary: proceduresproceduresproceduresprocedures, , , , functionsfunctionsfunctionsfunctions, , , , packagespackagespackagespackages and and and and librarieslibrarieslibrarieslibraries provide facilities for creating and provide facilities for creating and provide facilities for creating and provide facilities for creating and maintaining modular and reusable VHDL programs.maintaining modular and reusable VHDL programs.maintaining modular and reusable VHDL programs.maintaining modular and reusable VHDL programs.



JMM v1.5

FunctionsFunctionsFunctionsFunctions

� Functions are used to compute a value based on the Functions are used to compute a value based on the Functions are used to compute a value based on the Functions are used to compute a value based on the values of the input parameters. Functions are values of the input parameters. Functions are values of the input parameters. Functions are values of the input parameters. Functions are placed in declarative parts. Example of function placed in declarative parts. Example of function placed in declarative parts. Example of function placed in declarative parts. Example of function definition:definition:definition:definition:

� Functions cannot modify parameter values Functions cannot modify parameter values Functions cannot modify parameter values Functions cannot modify parameter values (procedures can). Example of function call:(procedures can). Example of function call:(procedures can). Example of function call:(procedures can). Example of function call:

� Functions execute in zero simulation time, thus Functions execute in zero simulation time, thus Functions execute in zero simulation time, thus Functions execute in zero simulation time, thus wait statements cannot exist in functions. wait statements cannot exist in functions. wait statements cannot exist in functions. wait statements cannot exist in functions. Parameters are restricted to be of mode Parameters are restricted to be of mode Parameters are restricted to be of mode Parameters are restricted to be of mode inininin....

function function function function rising_edge (signalsignalsignalsignal clock: inininin std_logic) return return return return booleanbooleanbooleanboolean;

rising_edge(clk)

functionfunctionfunctionfunction rising_edge (signalsignalsignalsignal clock: std_logic) return return return return booleanbooleanbooleanboolean isisisisvariablevariablevariablevariable edge: booleanbooleanbooleanboolean:=falsefalsefalsefalse;beginbeginbeginbeginedge:=(clock= ‘ 1‘ andandandand clock‘event‘event‘event‘event);returnreturnreturnreturn(edge);

endendendend rising_edge;

mode not necessarymode not necessarymode not necessarymode not necessary


JMM v1.5

Example: Type Conversion Function Example: Type Conversion Function Example: Type Conversion Function Example: Type Conversion Function witwitwitwith Functionsh Functionsh Functionsh Functions

� As VHDL is a type sensitive language, type As VHDL is a type sensitive language, type As VHDL is a type sensitive language, type As VHDL is a type sensitive language, type conversions are quite often necessary.conversions are quite often necessary.conversions are quite often necessary.conversions are quite often necessary.

� Many conversion procedures as well as resolution Many conversion procedures as well as resolution Many conversion procedures as well as resolution Many conversion procedures as well as resolution functions can be found in std_logic_1164 or functions can be found in std_logic_1164 or functions can be found in std_logic_1164 or functions can be found in std_logic_1164 or std_logic_arithstd_logic_arithstd_logic_arithstd_logic_arith libraries and others. Have a look at libraries and others. Have a look at libraries and others. Have a look at libraries and others. Have a look at $SYNOPSYS/packages/IEEE/$SYNOPSYS/packages/IEEE/$SYNOPSYS/packages/IEEE/$SYNOPSYS/packages/IEEE/srcsrcsrcsrc////

functionfunctionfunctionfunction to_bitvector(svalue: std_logic_vector) returnreturnreturnreturn bit_vector isisisisvariablevariablevariablevariable outvalue: bit_vector(svalue‘length‘length‘length‘length-1 downtodowntodowntodownto 0);beginbeginbeginbeginforforforfor i inininin svalue‘range‘range‘range‘range looplooplooploopcasecasecasecase svalue i isisisiswhenwhenwhenwhen ‘0‘ => outvalue i:=‘0‘;whenwhenwhenwhen ‘1‘ => outvalue i:=‘1‘;when otherswhen otherswhen otherswhen others => outvalue i:=‘0‘;end caseend caseend caseend case;

end loopend loopend loopend loop;endendendend to_bitvector;

note: size is not declarednote: size is not declarednote: size is not declarednote: size is not declared


JMM v1.5

ProceduresProceduresProceduresProcedures� Procedures are subprograms that can modify one or Procedures are subprograms that can modify one or Procedures are subprograms that can modify one or Procedures are subprograms that can modify one or

more of the input parameters. Example of procedure more of the input parameters. Example of procedure more of the input parameters. Example of procedure more of the input parameters. Example of procedure declaration reading from a file f:declaration reading from a file f:declaration reading from a file f:declaration reading from a file f:

� if the class of the procedure parameters is not if the class of the procedure parameters is not if the class of the procedure parameters is not if the class of the procedure parameters is not explicitly declared, then the following rules apply:explicitly declared, then the following rules apply:explicitly declared, then the following rules apply:explicitly declared, then the following rules apply:� parameters of mode in are assumed to be of class constantparameters of mode in are assumed to be of class constantparameters of mode in are assumed to be of class constantparameters of mode in are assumed to be of class constant� parameters of mode out or parameters of mode out or parameters of mode out or parameters of mode out or inoutinoutinoutinout are assumed to be of class are assumed to be of class are assumed to be of class are assumed to be of class

variablevariablevariablevariable

� Variables declared within a procedure are initialized Variables declared within a procedure are initialized Variables declared within a procedure are initialized Variables declared within a procedure are initialized on each call to the procedure and their values do not on each call to the procedure and their values do not on each call to the procedure and their values do not on each call to the procedure and their values do not persists across invocations of the procedure.persists across invocations of the procedure.persists across invocations of the procedure.persists across invocations of the procedure.

� Signals cannot be declared within proceduresSignals cannot be declared within proceduresSignals cannot be declared within proceduresSignals cannot be declared within procedures� Poor programming: Procedures declared within Poor programming: Procedures declared within Poor programming: Procedures declared within Poor programming: Procedures declared within

process can make assignments to signals process can make assignments to signals process can make assignments to signals process can make assignments to signals corresponding to the ports of the encompassing corresponding to the ports of the encompassing corresponding to the ports of the encompassing corresponding to the ports of the encompassing entity.entity.entity.entity.

� Procedure call:Procedure call:Procedure call:Procedure call:

procedure procedure procedure procedure read_v1d (variablevariablevariablevariable f: in text; in text; in text; in text; v: outoutoutout std_logic_vector);

Dff(clk=>clk,reset=>reset,d=>s2,q=>s1,qbar=>openopenopenopen);


JMM v1.5

Example: ProcedureExample: ProcedureExample: ProcedureExample: Procedurelibrary IEEElibrary IEEElibrary IEEElibrary IEEE;useuseuseuse IEEE.std_logic_1164.all;entityentityentityentity CPU isisisisportportportport(di: outoutoutout std_logic_vector(31 downtodowntodowntodownto );

addr: outoutoutout std_logic_vector(2 downtodowntodowntodownto 0);r,w: outoutoutout std_logic;do: inininin std_logic_vector(31 downtodowntodowntodownto 0);s: inininin std_logic);

endendendend CPU;

architecturearchitecturearchitecturearchitecture behavioral ofofofof CPU isisisisprocedureprocedureprocedureprocedure Mread(address: inininin std_logic_vector(2 downtodowntodowntodownto 0);

signalsignalsignalsignal r: outoutoutout std_logic;signalsignalsignalsignal s: inininin std_logic;signalsignalsignalsignal addr: outoutoutout std_logic_vector(2 downtodowntodowntodownto 0);signalsignalsignalsignal data: outoutoutout std_logic_vector(31 downtodowntodowntodownto 0)) isisisis

beginbeginbeginbeginaddr<=address;r<=‘1‘;wait untilwait untilwait untilwait until s=‘1‘;data <= do;r<=‘0‘;

endendendend Mread;

beginbeginbeginbegin-- CPU behavioral-- descriptionendendendend behavioral;

procedureprocedureprocedureprocedure Mwrite(address: inininin std_logic_vector(2 downtodowntodowntodownto 0);signalsignalsignalsignal data: inininin std_logic_vector(31 downtodowntodowntodownto 0);signalsignalsignalsignal addr: outoutoutout std_logic_vector(2 downtodowntodowntodownto 0);signalsignalsignalsignal w: outoutoutout std_logic;signalsignalsignalsignal di: outoutoutout std_logic_vector(31 downtodowntodowntodownto 0)) isisisis

beginbeginbeginbeginaddr<=address;w<=‘1‘;wait untilwait untilwait untilwait until s=‘1‘;di <= data;w<=‘0‘;

endendendend Mwrite;


JMM v1.5

OverloadinOverloadinOverloadinOverloadingggg

� A very useful feature of the VHDL language is the A very useful feature of the VHDL language is the A very useful feature of the VHDL language is the A very useful feature of the VHDL language is the ability to ability to ability to ability to overloadoverloadoverloadoverload a subprogram or an operator.a subprogram or an operator.a subprogram or an operator.a subprogram or an operator.

� Imagine writing different FlipImagine writing different FlipImagine writing different FlipImagine writing different Flip----Flop models with no Flop models with no Flop models with no Flop models with no and with asynchronous inputs and with different and with asynchronous inputs and with different and with asynchronous inputs and with different and with asynchronous inputs and with different argument types. With the overloading feature only argument types. With the overloading feature only argument types. With the overloading feature only argument types. With the overloading feature only one single Flipone single Flipone single Flipone single Flip----Flop name can be used.Flop name can be used.Flop name can be used.Flop name can be used.

� Example for Example for Example for Example for DffDffDffDff calls:calls:calls:calls:

� From the type and number of arguments we can tell From the type and number of arguments we can tell From the type and number of arguments we can tell From the type and number of arguments we can tell which procedure we meant to use.which procedure we meant to use.which procedure we meant to use.which procedure we meant to use.

� Note that in Note that in Note that in Note that in std_logic_1164.vhdstd_logic_1164.vhdstd_logic_1164.vhdstd_logic_1164.vhd the the the the booleanbooleanbooleanbooleanfunctions functions functions functions andandandand, , , , orororor, etc have been defined for , etc have been defined for , etc have been defined for , etc have been defined for std_logic types, the functions std_logic types, the functions std_logic types, the functions std_logic types, the functions ++++,,,,****, etc have been , etc have been , etc have been , etc have been defined for certain predefined types of the language defined for certain predefined types of the language defined for certain predefined types of the language defined for certain predefined types of the language such as integer. See also such as integer. See also such as integer. See also such as integer. See also std_logic_arithstd_logic_arithstd_logic_arithstd_logic_arith package.package.package.package.

DffDffDffDff((((clk,d,q,qbar);clk,d,q,qbar);clk,d,q,qbar);clk,d,q,qbar);

DffDffDffDff((((clk,d,q,qbarclk,d,q,qbarclk,d,q,qbarclk,d,q,qbar,,,,resetresetresetreset,,,,clear);clear);clear);clear);

function “*“(arg1,ar2: std_logic_vector) return std_logic_vectorfunction “*“(arg1,ar2: std_logic_vector) return std_logic_vectorfunction “*“(arg1,ar2: std_logic_vector) return std_logic_vectorfunction “*“(arg1,ar2: std_logic_vector) return std_logic_vector;;;;

function “function “function “function “+“(arg1,ar2: singed) return signed;+“(arg1,ar2: singed) return signed;+“(arg1,ar2: singed) return signed;+“(arg1,ar2: singed) return signed;


JMM v1.5

PackagesPackagesPackagesPackages

� Locally related functions and procedures can be Locally related functions and procedures can be Locally related functions and procedures can be Locally related functions and procedures can be grouped into packages, and thus easily be shared grouped into packages, and thus easily be shared grouped into packages, and thus easily be shared grouped into packages, and thus easily be shared among designs and people.among designs and people.among designs and people.among designs and people.

package package package package MyLibraryPackage isisisis---- type declarations-- function declarations-- procedure declarations--endendendend MyLibraryPackage;

package body package body package body package body MyLibraryPackage isisisis---- functions-- procedures--endendendend MyLibraryPackage;

package declarationpackage declarationpackage declarationpackage declaration

package bodypackage bodypackage bodypackage body

similar to VHDL entitysimilar to VHDL entitysimilar to VHDL entitysimilar to VHDL entitydefines interfacesdefines interfacesdefines interfacesdefines interfaces

similar to VHDL architecturesimilar to VHDL architecturesimilar to VHDL architecturesimilar to VHDL architecturedefines behaviordefines behaviordefines behaviordefines behavior

� package declaration needs to be analyzed first, and package declaration needs to be analyzed first, and package declaration needs to be analyzed first, and package declaration needs to be analyzed first, and then package body can be analyzed.then package body can be analyzed.then package body can be analyzed.then package body can be analyzed.

� Packages are used as Packages are used as Packages are used as Packages are used as librarieslibrarieslibrarieslibraries and referenced within and referenced within and referenced within and referenced within VHDL design units via the VHDL design units via the VHDL design units via the VHDL design units via the useuseuseuse clause. clause. clause. clause.


JMM v1.5

Example: Package DeclarationExample: Package DeclarationExample: Package DeclarationExample: Package Declaration

package package package package std_logic_1164 isisisis

typetypetypetype std_ulogic isisisis (‘U‘, -- uninitialized‘X‘, -- forcing unknown‘0‘, -- forcing 0‘1‘, -- forcing 1‘Z‘, -- high impedance‘W‘, -- weak unknown‘L‘, -- weak 0‘H‘, -- weak 1‘-‘ -- don‘t care);

typetypetypetype std_ulogic_vector is arrayis arrayis arrayis array (natural rangenatural rangenatural rangenatural range <>) ofofofof std_ulogic;subtypesubtypesubtypesubtype std_logic is resolvedis resolvedis resolvedis resolved std_ulogic;

typetypetypetype std_logic_vector is arrayis arrayis arrayis array (natural rangenatural rangenatural rangenatural range <>) ofofofof std_logic;

functionfunctionfunctionfunction “and“ (l,r: std_logic_vector) returnreturnreturnreturn std_logic_vector;functionfunctionfunctionfunction “and“ (l,r: std_ulogic_vector) returnreturnreturnreturn std_ulogic_vector;

-- rest of package declaration

endendendend std_logic_1164;


JMM v1.5

LibrariesLibrariesLibrariesLibraries

� Each design unit Each design unit Each design unit Each design unit ---- entity, architecture, package entity, architecture, package entity, architecture, package entity, architecture, package ---- is is is is analyzed (compiled) and placed in a analyzed (compiled) and placed in a analyzed (compiled) and placed in a analyzed (compiled) and placed in a design librarydesign librarydesign librarydesign library....

� Libraries are generally implemented as directories Libraries are generally implemented as directories Libraries are generally implemented as directories Libraries are generally implemented as directories and are referenced by a logical name.and are referenced by a logical name.and are referenced by a logical name.and are referenced by a logical name.

� In VHDL the libraries STD and WORK are In VHDL the libraries STD and WORK are In VHDL the libraries STD and WORK are In VHDL the libraries STD and WORK are implicitly declared.implicitly declared.implicitly declared.implicitly declared.

� WORK is the working design library normally WORK is the working design library normally WORK is the working design library normally WORK is the working design library normally placed in a local directory.placed in a local directory.placed in a local directory.placed in a local directory.

� Once a library has been declared, all of the Once a library has been declared, all of the Once a library has been declared, all of the Once a library has been declared, all of the functions, procedures and type declarations of a functions, procedures and type declarations of a functions, procedures and type declarations of a functions, procedures and type declarations of a package can be accessed.package can be accessed.package can be accessed.package can be accessed.

visibility must be establishedvisibility must be establishedvisibility must be establishedvisibility must be establishedfor each design unit for each design unit for each design unit for each design unit –––– entityentityentityentity----separatelyseparatelyseparatelyseparately

all functions, procedures, typed all functions, procedures, typed all functions, procedures, typed all functions, procedures, typed are visibleare visibleare visibleare visible

only the „only the „only the „only the „xnorxnorxnorxnor“ function is visible“ function is visible“ function is visible“ function is visible

library IEEE;use IEEE.std_logic_1164.all;

library IEEE;use IEEE.std_logic_1164.xnor;


JMM v1.5

Example: Libraries anExample: Libraries anExample: Libraries anExample: Libraries and Packagesd Packagesd Packagesd Packages

packagepackagepackagepackage MyPackage isisisis--endendendend MyPackage;

package bodypackage bodypackage bodypackage body MyPackage isisisis--endendendend MyPackage;

MyPackage.vhd

DEFAULT: ./WORK

MyLibrary : ./libuse = . ./srctimebase = ns

.synopsys_vss.setup

/home/MyHome/- VHDLdesign/

- WORK/- lib/- src/

design environmentdesign environmentdesign environmentdesign environment .synopsys_vss.setup

source file:source file:source file:source file: MyPackage.vhd

cd /home/MyHome/VHDLdesigngvan –w MyLibrary src/MyPackage.vhd

gvan MyVHDLdesign.vhd

in a in a in a in a unixunixunixunix shell:shell:shell:shell:analyze the package analyze the package analyze the package analyze the package MyPackageMyPackageMyPackageMyPackageanalyze the design analyze the design analyze the design analyze the design MyVHDLdesignMyVHDLdesignMyVHDLdesignMyVHDLdesign

all source VHDL design filesall source VHDL design filesall source VHDL design filesall source VHDL design files

/home/MyHome/VHDLdesign/WORK/home/MyHome/VHDLdesign/lib

compiled package:compiled package:compiled package:compiled package: MyPackageall compiled designsall compiled designsall compiled designsall compiled designslibrary:library:library:library:

MyLibraryMyLibraryMyLibraryMyLibrary

librarylibrarylibrarylibrary MyLibrary;useuseuseuse MyLibrary.MyPackage.all;-- useuseuseuse MyLibrary.all;

entityentityentityentity MyVHDLdesign isisisis...

MyVHDLdesign.vhd

SynopsysSynopsysSynopsysSynopsys tools on tools on tools on tools on unixunixunixunix workstationsworkstationsworkstationsworkstations

componentscomponentscomponentscomponentscan also becan also becan also becan also beplaced intoplaced intoplaced intoplaced intolibrarieslibrarieslibrarieslibraries

librarylibrarylibrarylibraryWORKWORKWORKWORK

librarylibrarylibrarylibraryMyLibraryMyLibraryMyLibraryMyLibrary


JMM v1.5

Exercises vlsi21: Libraries & PackagesExercises vlsi21: Libraries & PackagesExercises vlsi21: Libraries & PackagesExercises vlsi21: Libraries & Packages� Ex415 (difficulty: medium): Ex415 (difficulty: medium): Ex415 (difficulty: medium): Ex415 (difficulty: medium): The small circuit The small circuit The small circuit The small circuit

ConfigExampleConfigExampleConfigExampleConfigExample from exercise Ex414 shall be from exercise Ex414 shall be from exercise Ex414 shall be from exercise Ex414 shall be rewritten by using the components OR2 and rewritten by using the components OR2 and rewritten by using the components OR2 and rewritten by using the components OR2 and ANDnANDnANDnANDnfrom the library from the library from the library from the library MyLibraryMyLibraryMyLibraryMyLibrary....

a)a)a)a) Write the VHDL file Write the VHDL file Write the VHDL file Write the VHDL file MyComponents.vhdMyComponents.vhdMyComponents.vhdMyComponents.vhd holding holding holding holding the two components OR2 and the two components OR2 and the two components OR2 and the two components OR2 and ANDnANDnANDnANDn and compile it and compile it and compile it and compile it into the library into the library into the library into the library MyLibraryMyLibraryMyLibraryMyLibrary....

b)b)b)b) Rewrite the Rewrite the Rewrite the Rewrite the ConfigExampleConfigExampleConfigExampleConfigExample circuit using only circuit using only circuit using only circuit using only library elements and call it library elements and call it library elements and call it library elements and call it LibraryExample.vhdLibraryExample.vhdLibraryExample.vhdLibraryExample.vhd, , , , compile and simulate it.compile and simulate it.compile and simulate it.compile and simulate it.

� Ex416 (difficulty: medium):Ex416 (difficulty: medium):Ex416 (difficulty: medium):Ex416 (difficulty: medium): Write the VHDL Write the VHDL Write the VHDL Write the VHDL package package package package MyPackageMyPackageMyPackageMyPackage with the functions OneCounter with the functions OneCounter with the functions OneCounter with the functions OneCounter (counting ‚1‘) and Parity(counting ‚1‘) and Parity(counting ‚1‘) and Parity(counting ‚1‘) and ParityGenerator should accept Generator should accept Generator should accept Generator should accept std_logic_vectors or bit_vectors of any sizestd_logic_vectors or bit_vectors of any sizestd_logic_vectors or bit_vectors of any sizestd_logic_vectors or bit_vectors of any size), ), ), ), and and and and analyze it into the library analyze it into the library analyze it into the library analyze it into the library MyLibraryMyLibraryMyLibraryMyLibrary. Use the . Use the . Use the . Use the defined functions in your design defined functions in your design defined functions in your design defined functions in your design PackageExamplePackageExamplePackageExamplePackageExample to to to to show its functionality.show its functionality.show its functionality.show its functionality.

&

&

1≥

i1i1i1i1i2i2i2i2i3i3i3i3

o1o1o1o1

OR2OR2OR2OR2

ANDnANDnANDnANDn

ANDnANDnANDnANDn


JMM v1.5

Exercises vlsi21: PackagesExercises vlsi21: PackagesExercises vlsi21: PackagesExercises vlsi21: Packages� Ex417 (difficulty: medium): Ex417 (difficulty: medium): Ex417 (difficulty: medium): Ex417 (difficulty: medium): The bitThe bitThe bitThe bit----serial adder of serial adder of serial adder of serial adder of

exercise Ex413 shall we rewritten using a exercise Ex413 shall we rewritten using a exercise Ex413 shall we rewritten using a exercise Ex413 shall we rewritten using a procedure call for the procedure call for the procedure call for the procedure call for the DffDffDffDff instead of a component instead of a component instead of a component instead of a component ((((SerialAdder2.vhdSerialAdder2.vhdSerialAdder2.vhdSerialAdder2.vhd). Place the procedure into a ). Place the procedure into a ). Place the procedure into a ). Place the procedure into a package package package package MyPackageMyPackageMyPackageMyPackage and analyze it into the library and analyze it into the library and analyze it into the library and analyze it into the library MyLibraryMyLibraryMyLibraryMyLibrary. Verify the functionality.. Verify the functionality.. Verify the functionality.. Verify the functionality.

qqqq

clkclkclkclk


dddd

CombCombCombComb((((combinationalcombinationalcombinationalcombinational

logiclogiclogiclogic))))carrycarrycarrycarry

in1in1in1in1in2in2in2in2

C1C1C1C1

DffDffDffDff



highSpeedhighSpeedhighSpeedhighSpeed

behavioralbehavioralbehavioralbehavioral

sumsumsumsum

librarylibrarylibrarylibraryMyLibraryMyLibraryMyLibraryMyLibrary


JMM v1.5

VVVVHDL vs. HDL vs. HDL vs. HDL vs. VerilogVerilogVerilogVerilog: Data Types: Data Types: Data Types: Data Types

� type driven languagetype driven languagetype driven languagetype driven language� predefined data types predefined data types predefined data types predefined data types

in packages: in packages: in packages: in packages: character, integer, real, character, integer, real, character, integer, real, character, integer, real, bit, stdbit, stdbit, stdbit, std_logic, _logic, _logic, _logic, textiotextiotextiotextio, ..., ..., ..., ...

� enumerate typesenumerate typesenumerate typesenumerate types� arraysarraysarraysarrays� recordsrecordsrecordsrecords� pointerspointerspointerspointers

� arraysarraysarraysarrays� runrunrunrun----time constants: time constants: time constants: time constants:

parameterparameterparameterparameter� continuous driven continuous driven continuous driven continuous driven

nets: wire, tri, ...nets: wire, tri, ...nets: wire, tri, ...nets: wire, tri, ...� triggered assignments: triggered assignments: triggered assignments: triggered assignments:

regregregreg, integer, real, ..., integer, real, ..., integer, real, ..., integer, real, ...



JMM v1.5

VHDL vs. VHDL vs. VHDL vs. VHDL vs. VerilogVerilogVerilogVerilog: Operators: Operators: Operators: Operators

Operator typeOperator typeOperator typeOperator type functionfunctionfunctionfunction VHDLVHDLVHDLVHDL VerilogVerilogVerilogVerilog arithmeticarithmeticarithmeticarithmetic a + ba + ba + ba + b ++++ ++++ a a a a ---- b b b b ---- ---- a * ba * ba * ba * b **** **** a / ba / ba / ba / b //// //// aaaa----b*nb*nb*nb*n a div ba div ba div ba div b modmodmodmod %%%% aaaa----(a/b)*b(a/b)*b(a/b)*b(a/b)*b remremremrem logicallogicallogicallogical a and ba and ba and ba and b andandandand &&&& a or ba or ba or ba or b orororor ¦¦¦¦ not(a and b)not(a and b)not(a and b)not(a and b) nandnandnandnand ~&~&~&~& a exor ba exor ba exor ba exor b xorxorxorxor ^̂̂̂ shift logicshift logicshift logicshift logic srl,sllsrl,sllsrl,sllsrl,sll >>>>>>>> shift arith.shift arith.shift arith.shift arith. sra,slasra,slasra,slasra,sla rotate rotate rotate rotate ror, rolror, rolror, rolror, rol reduction, reduction, reduction, reduction, concatenation concatenation concatenation concatenation

&&&& {a,b}{a,b}{a,b}{a,b}

replicationreplicationreplicationreplication {4{a}}{4{a}}{4{a}}{4{a}} relationalrelationalrelationalrelational >>>> >>>> >>>> >=>=>=>= >=>=>=>= >=>=>=>= /=/=/=/=


JMM v1.5

VHDL vs. VHDL vs. VHDL vs. VHDL vs. VerilogVerilogVerilogVerilog: : : : SeSeSeSequential Structuresquential Structuresquential Structuresquential Structures

/* /* /* /* inside a module */module */module */module */...wirewirewirewire [[[[7:0]]]] inp;regregregreg [[[[7:0] ] ] ] outp, cou;...always @(always @(always @(always @(posedgeposedgeposedgeposedge clk))))beginbeginbeginbegin

outp = oupt + inp;cout = outp + 1;

endendendend...VerilogVerilogVerilogVerilog----HDLHDLHDLHDL

-------- inside an architecturearchitecturearchitecturearchitecture...variablevariablevariablevariable inp: std_logic_vector ((((7 downtodowntodowntodownto 0););););variablevariablevariablevariable outp,cout:std_logic_vector ((((7 downtodowntodowntodownto 0););););

processprocessprocessprocess (clk)beginbeginbeginbegin

if (if (if (if (clk’even’even’even’event andandandand clk = ‘1’) thenthenthenthenoutp := outp + inp;cout := outp + 1;

end if;end if;end if;end if;end process;end process;end process;end process;...

VHDLVHDLVHDLVHDL

sequentially executed statementssequentially executed statementssequentially executed statementssequentially executed statements


JMM v1.5

VHDL vs. VHDL vs. VHDL vs. VHDL vs. VerilogVerilogVerilogVerilog::::Parallel StructuresParallel StructuresParallel StructuresParallel Structures


/* /* /* /* in a module */module */module */module */...wirewirewirewire [[[[7:0]]]] inp;regregregreg [[[[7:0] ] ] ] outp, cou;...always @(always @(always @(always @(posedgeposedgeposedgeposedge clk))))forkforkforkfork

outp = outp + inp;cout = outp + 1;

joinjoinjoinjoin

always @(always @(always @(always @(reset))))ifififif (!!!!reset)

outp = 8’b0;...

-------- in an architecturearchitecturearchitecturearchitecture...variablevariablevariablevariable inp: std_logic_vector ((((7 downtodowntodowntodownto 0););););signalsignalsignalsignal outp,cout:std_logic_vector ((((7 downtodowntodowntodownto 0););););

p1: processprocessprocessprocess (clk)beginbeginbeginbegin

if if if if (clk’even’even’even’event andandandand clk = ‘1’) thenthenthenthenoutp <= outp + inp;cout <= outp + 1;


p2: processprocessprocessprocess (reset)beginbeginbeginbegin

ifififif (reset = ‘0’) thenthenthenthenoutp <= “00000000“;

end if;end if;end if;end if;end process;end process;end process;end process;...

VHDLVHDLVHDLVHDL

parallel executedparallel executedparallel executedparallel executedstatementsstatementsstatementsstatements

parallel parallel parallel parallel executed blocksexecuted blocksexecuted blocksexecuted blocks

two driverstwo driverstwo driverstwo drivers


JMM v1.5

VHDL vs. VHDL vs. VHDL vs. VHDL vs. VerilogVerilogVerilogVerilog: : : : AssignmentsAssignmentsAssignmentsAssignments

modulemodulemodulemodule AssignExamplewirewirewirewire [[[[7:0]]]] v,y2,z2;regregregreg [[[[7:0] ] ] ] x1,y1,z1,x2;

...always @(always @(always @(always @(posedgeposedgeposedgeposedge clk))))forkforkforkfork

x1 = y1;y1 = x1;z1 ####(12) = y1;

joinjoinjoinjoin

assignassignassignassign x2 = y2;assignassignassignassign y2 = x2;assignassignassignassign ####(12) z2 = y2;



VHDLVHDLVHDLVHDL

architecture architecture architecture architecture ex1 of of of of AssignExample isisisissignalsignalsignalsignal x1, y1, y2, z1, z2:

std_logic_vector ((((7 downtodowntodowntodownto 0););););variablevariablevariablevariable x2: std_logic_vector ((((7 downtodowntodowntodownto 0););););...beginbeginbeginbeginp1: processprocessprocessprocess (clk)

beginbeginbeginbeginif (if (if (if (clk’even’even’even’event andandandand clk = ‘0’) then

x1 <= y1;y1 <= x1;z1 <= y1 afterafterafterafter 12ns;ns;ns;ns;


p2: processprocessprocessprocess (y2)beginbeginbeginbegin

x2 := y2;y2 <= x2;z2 <= y2 after 12ns;

end process;end process;end process;end process;endendendend ex1;

before the falling edge of before the falling edge of before the falling edge of before the falling edge of clkclkclkclk::::x=1, y=2, z=3x=1, y=2, z=3x=1, y=2, z=3x=1, y=2, z=3

12ns after falling edge of 12ns after falling edge of 12ns after falling edge of 12ns after falling edge of clkclkclkclk::::x=x=x=x= y=y=y=y= z=z=z=z= ????

signal assignmentsignal assignmentsignal assignmentsignal assignmentvariable assignmentvariable assignmentvariable assignmentvariable assignment


JMM v1.5

VHDL vs. VHDL vs. VHDL vs. VHDL vs. VerilogVerilogVerilogVerilog::::Sequential LogiSequential LogiSequential LogiSequential Logicccc

modulemodulemodulemodule AsynRegister(clk,rst,a,z);inputinputinputinput clk,rst;inputinputinputinput [[[[15:0]]]] a;outputoutputoutputoutput [[[[15:0] ] ] ] z;

always @(always @(always @(always @(posedgeposedgeposedgeposedge clk))))ifififif (rst == 1’b0)

z = 16’b0;elseelseelseelse

z = a;endmoduleendmoduleendmoduleendmodule


VHDLVHDLVHDLVHDL

library library library library IEEE;useuseuseuse IEEE.std_logic_1164.all;package package package package MyDefinition isisisis

typetypetypetype vector16 is array is array is array is array (15 downtodowntodowntodownto 0) ofofofofstd_logic;

endendendend MyDefinition;

library library library library IEEE;useuseuseuse IEEE.std_logic_1164.all;useuseuseuse work.MyDefinition.all;

entityentityentityentity AsynRegister isisisisport port port port (clk,rst: inininin std_logic;

a: inininin vector16; z: out vector16);endendendend AsynRegister;

architecture architecture architecture architecture DemoExample of of of of AsynRegister isisisisbeginbeginbeginbegin

processprocessprocessprocess (clk, rst);beginbeginbeginbegin

ifififif (rst = ‘0’) thenthenthenthenz <= vector16’(othersothersothersothers => ‘0‘);

elsifelsifelsifelsif (clk’even’even’even’event andandandand clk = ‘1’) thenthenthenthenz <= a;


endendendend DemoExample;

register with register with register with register with asynchronous resetasynchronous resetasynchronous resetasynchronous reset


JMM v1.5

““““Dataflow” ModelingDataflow” ModelingDataflow” ModelingDataflow” Modelinglibrary IEEE;library IEEE;library IEEE;library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;

entity Dentity Dentity Dentity Demuxemuxemuxemux2x4 is port(2x4 is port(2x4 is port(2x4 is port(a,b,enable: in std_logic;a,b,enable: in std_logic;a,b,enable: in std_logic;a,b,enable: in std_logic;z: out std_logic_vector(0 to 3);); z: out std_logic_vector(0 to 3);); z: out std_logic_vector(0 to 3);); z: out std_logic_vector(0 to 3););

end Dend Dend Dend Demuxemuxemuxemux2x4;2x4;2x4;2x4;

architecture architecture architecture architecture dataflowdataflowdataflowdataflowof Dof Dof Dof Demuxemuxemuxemux2x4 is2x4 is2x4 is2x4 issignal signal signal signal abar,bbarabar,bbarabar,bbarabar,bbar: std_logic;: std_logic;: std_logic;: std_logic;

beginbeginbeginbeginzzzz(3) <= not(a and b and enable);(3) <= not(a and b and enable);(3) <= not(a and b and enable);(3) <= not(a and b and enable);zzzz(0) <= (0) <= (0) <= (0) <= not(abarnot(abarnot(abarnot(abar and and and and bbarbbarbbarbbar and enable);and enable);and enable);and enable);abarabarabarabar <= not a;<= not a;<= not a;<= not a;zzzz(2) <= not(a and (2) <= not(a and (2) <= not(a and (2) <= not(a and bbarbbarbbarbbar and enable);and enable);and enable);and enable);abarabarabarabar <= not a;<= not a;<= not a;<= not a;zzzz(1) <= (1) <= (1) <= (1) <= not(abarnot(abarnot(abarnot(abar and b and enable);and b and enable);and b and enable);and b and enable);

endendendend dataflowdataflowdataflowdataflow;;;;

All the signal assignment statements (“<=“) happenAll the signal assignment statements (“<=“) happenAll the signal assignment statements (“<=“) happenAll the signal assignment statements (“<=“) happenconcurrentlyconcurrentlyconcurrentlyconcurrently after some specified delay which defaultsafter some specified delay which defaultsafter some specified delay which defaultsafter some specified delay which defaultsto 1 “delta”, an infinitesimally small delay. Note thatto 1 “delta”, an infinitesimally small delay. Note thatto 1 “delta”, an infinitesimally small delay. Note thatto 1 “delta”, an infinitesimally small delay. Note thatconcurrent statements are always “running” so wheneverconcurrent statements are always “running” so wheneverconcurrent statements are always “running” so wheneverconcurrent statements are always “running” so wheneverA, B or ENABLE change then ABAR, BBAR, and Z(0 to 3)A, B or ENABLE change then ABAR, BBAR, and Z(0 to 3)A, B or ENABLE change then ABAR, BBAR, and Z(0 to 3)A, B or ENABLE change then ABAR, BBAR, and Z(0 to 3)will also change after some delay.will also change after some delay.will also change after some delay.will also change after some delay.

The delay in assigning a signal its new value means thatThe delay in assigning a signal its new value means thatThe delay in assigning a signal its new value means thatThe delay in assigning a signal its new value means thatthe following statement is meaningful (it generates athe following statement is meaningful (it generates athe following statement is meaningful (it generates athe following statement is meaningful (it generates aperiodic waveform):periodic waveform):periodic waveform):periodic waveform):

CLK <= not CLK after 10 ns;CLK <= not CLK after 10 ns;CLK <= not CLK after 10 ns;CLK <= not CLK after 10 ns;


JMM v1.5

VHDL EVHDL EVHDL EVHDL Example: Behavioral Modelingxample: Behavioral Modelingxample: Behavioral Modelingxample: Behavioral Modelinglibrary IEEE;library IEEE;library IEEE;library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;use IEEE.std_logic_1164.all;use use use use IEEE.std_logic_arith.allIEEE.std_logic_arith.allIEEE.std_logic_arith.allIEEE.std_logic_arith.all;;;;

entity Demux2x4 is port(entity Demux2x4 is port(entity Demux2x4 is port(entity Demux2x4 is port(a,b,enable: in std_logic;a,b,enable: in std_logic;a,b,enable: in std_logic;a,b,enable: in std_logic;z: out std_logic_vector(0 to 3);); z: out std_logic_vector(0 to 3);); z: out std_logic_vector(0 to 3);); z: out std_logic_vector(0 to 3););

end Demux2x4;end Demux2x4;end Demux2x4;end Demux2x4;

architecture behavioral of Demux2x4 isarchitecture behavioral of Demux2x4 isarchitecture behavioral of Demux2x4 isarchitecture behavioral of Demux2x4 isbeginbeginbeginbegin

process(a,b,enable)process(a,b,enable)process(a,b,enable)process(a,b,enable)variable variable variable variable abar,bbarabar,bbarabar,bbarabar,bbar: std_logic;: std_logic;: std_logic;: std_logic;

beginbeginbeginbeginabarabarabarabar := not a;:= not a;:= not a;:= not a;bbarbbarbbarbbar := not b;:= not b;:= not b;:= not b;if (enable = ‘1’) thenif (enable = ‘1’) thenif (enable = ‘1’) thenif (enable = ‘1’) then

z(3) <= not(a and b);z(3) <= not(a and b);z(3) <= not(a and b);z(3) <= not(a and b);z(2) <= not(a and z(2) <= not(a and z(2) <= not(a and z(2) <= not(a and bbarbbarbbarbbar););););z(1) <= z(1) <= z(1) <= z(1) <= not(abarnot(abarnot(abarnot(abar and b);and b);and b);and b);z(0) <= z(0) <= z(0) <= z(0) <= not(abarnot(abarnot(abarnot(abar and and and and bbarbbarbbarbbar););););

elseelseelseelsez <= “1111”;z <= “1111”;z <= “1111”;z <= “1111”;


end behavioral;end behavioral;end behavioral;end behavioral;

Statements within a process are executed seStatements within a process are executed seStatements within a process are executed seStatements within a process are executed sequentially,quentially,quentially,quentially,like a program. The process is scheduled for executionlike a program. The process is scheduled for executionlike a program. The process is scheduled for executionlike a program. The process is scheduled for executionafter any events are processed for variables on itsafter any events are processed for variables on itsafter any events are processed for variables on itsafter any events are processed for variables on itssensitivity list. Values of local variables are maintainedsensitivity list. Values of local variables are maintainedsensitivity list. Values of local variables are maintainedsensitivity list. Values of local variables are maintainedbetween executions.between executions.between executions.between executions.

local variables (separatelocal variables (separatelocal variables (separatelocal variables (separatecopies for each instancecopies for each instancecopies for each instancecopies for each instanceof Dof Dof Dof Demuxemuxemuxemux2x4)2x4)2x4)2x4)

Process statementsProcess statementsProcess statementsProcess statementscan be compiled socan be compiled socan be compiled socan be compiled sobehavioral simulationsbehavioral simulationsbehavioral simulationsbehavioral simulationscan be quite fast.can be quite fast.can be quite fast.can be quite fast.

vector constantvector constantvector constantvector constant


JMM v1.5

SynthesisSynthesisSynthesisSynthesis

IdeaIdeaIdeaIdea: once an behavioral model has been finished why not : once an behavioral model has been finished why not : once an behavioral model has been finished why not : once an behavioral model has been finished why not use it to automaticallyuse it to automaticallyuse it to automaticallyuse it to automatically synthesize synthesize synthesize synthesize a logic implementation in a logic implementation in a logic implementation in a logic implementation in much the same was as a compiler generates executable code much the same was as a compiler generates executable code much the same was as a compiler generates executable code much the same was as a compiler generates executable code from a source program?from a source program?from a source program?from a source program?

Synthesis programs process the HDL then Synthesis programs process the HDL then Synthesis programs process the HDL then Synthesis programs process the HDL then

�� infer logic and state elementsinfer logic and state elementsinfer logic and state elementsinfer logic and state elements

�� perform technologyperform technologyperform technologyperform technology----independent independent independent independent optimioptimioptimioptimizzzzationsationsationsations(e.g., logic simplification, state assignment)(e.g., logic simplification, state assignment)(e.g., logic simplification, state assignment)(e.g., logic simplification, state assignment)

�� map elements to the target technologymap elements to the target technologymap elements to the target technologymap elements to the target technology

�� perform technologyperform technologyperform technologyperform technology----dependent optimizationsdependent optimizationsdependent optimizationsdependent optimizations(e.g., multi(e.g., multi(e.g., multi(e.g., multi----level logic optimization, chooselevel logic optimization, chooselevel logic optimization, chooselevel logic optimization, choosegate strengths to achieve speed goals)gate strengths to achieve speed goals)gate strengths to achieve speed goals)gate strengths to achieve speed goals)

SynopsysSynopsysSynopsysSynopsys, Inc. is the current leader in, Inc. is the current leader in, Inc. is the current leader in, Inc. is the current leader inproviding synthesis tools and synthesizableproviding synthesis tools and synthesizableproviding synthesis tools and synthesizableproviding synthesis tools and synthesizableHDL modules.HDL modules.HDL modules.HDL modules.

a.k.a. “silicon compilers”a.k.a. “silicon compilers”a.k.a. “silicon compilers”a.k.a. “silicon compilers”


JMM v1.5

Logic SynthesisLogic SynthesisLogic SynthesisLogic SynthesisZ <= (A and B) or C;Z <= (A and B) or C;Z <= (A and B) or C;Z <= (A and B) or C; if (SEL = ‘1’) then Z <= B;if (SEL = ‘1’) then Z <= B;if (SEL = ‘1’) then Z <= B;if (SEL = ‘1’) then Z <= B;

else Z <= A;else Z <= A;else Z <= A;else Z <= A;end if;end if;end if;end if;

process(word)process(word)process(word)process(word)variable result: std_logic;variable result: std_logic;variable result: std_logic;variable result: std_logic;

beginbeginbeginbeginresult := ‘0’;result := ‘0’;result := ‘0’;result := ‘0’;for j in 0 to 3 loopfor j in 0 to 3 loopfor j in 0 to 3 loopfor j in 0 to 3 loopresult := result result := result result := result result := result xorxorxorxor word(j);word(j);word(j);word(j);

end loop;end loop;end loop;end loop;parity <= result;parity <= result;parity <= result;parity <= result;


signal x,y,sum: std_logic_vector(3 signal x,y,sum: std_logic_vector(3 signal x,y,sum: std_logic_vector(3 signal x,y,sum: std_logic_vector(3 downtodowntodowntodownto 0);0);0);0);sum <= unsigned(x) + unsigned(y);sum <= unsigned(x) + unsigned(y);sum <= unsigned(x) + unsigned(y);sum <= unsigned(x) + unsigned(y);

AAAABBBBCCCC

AAAABBBBCCCC

ZZZZ

ZZZZ

11110000AAAA

BBBB

SELSELSELSEL

ZZZZ

AAAA

BBBBSELSELSELSEL ZZZZ

fullfullfullfulladderadderadderadder

Y(0)Y(0)Y(0)Y(0)X(0)X(0)X(0)X(0)

SUM(0)SUM(0)SUM(0)SUM(0)

0000fullfullfullfull

adderadderadderadder

Y(1)Y(1)Y(1)Y(1)X(1)X(1)X(1)X(1)


Y(2)Y(2)Y(2)Y(2)X(2)X(2)X(2)X(2)


Y(3)Y(3)Y(3)Y(3)X(3)X(3)X(3)X(3)

SUM(1)SUM(1)SUM(1)SUM(1) SUM(2)SUM(2)SUM(2)SUM(2) SUM(3)SUM(3)SUM(3)SUM(3)

NCNCNCNC

WORD(1) WORD(1) WORD(1) WORD(1) WORD(0) WORD(0) WORD(0) WORD(0)

WORD(2) WORD(2) WORD(2) WORD(2)

WORD(3) WORD(3) WORD(3) WORD(3) PARITYPARITYPARITYPARITY


JMM v1.5

Further ReadingFurther ReadingFurther ReadingFurther Reading

ISBN 0ISBN 0ISBN 0ISBN 0----13131313----181447181447181447181447----8888 ISBN 0ISBN 0ISBN 0ISBN 0----7923792379237923----9472947294729472----0000

Also:Also:Also:Also:

�� D. Perry, D. Perry, D. Perry, D. Perry, VHDL, Second Edition,VHDL, Second Edition,VHDL, Second Edition,VHDL, Second Edition, McMcMcMcGraw Hill, 1993Graw Hill, 1993Graw Hill, 1993Graw Hill, 1993

�� see VHDL tutorials at I3Ssee VHDL tutorials at I3Ssee VHDL tutorials at I3Ssee VHDL tutorials at I3S----CD or on the web CD or on the web CD or on the web CD or on the web http://http://http://http://www.microlab.ch/academics/courses/vlsi/g.htmlwww.microlab.ch/academics/courses/vlsi/g.htmlwww.microlab.ch/academics/courses/vlsi/g.htmlwww.microlab.ch/academics/courses/vlsi/g.html

�� don‘t forget to study the CBT tutorial on VHDL don‘t forget to study the CBT tutorial on VHDL don‘t forget to study the CBT tutorial on VHDL don‘t forget to study the CBT tutorial on VHDL


JMM v1.5

Test Bench Test Bench Test Bench Test Bench /1/1/1/1

� avoid interactive simulation, because it can never avoid interactive simulation, because it can never avoid interactive simulation, because it can never avoid interactive simulation, because it can never be used againbe used againbe used againbe used again

� test benches reduce total simulation development test benches reduce total simulation development test benches reduce total simulation development test benches reduce total simulation development timetimetimetime

� test benches are used to verify designs during test benches are used to verify designs during test benches are used to verify designs during test benches are used to verify designs during stepwise refinementstepwise refinementstepwise refinementstepwise refinement

� test bench methodology bridges simulation with test bench methodology bridges simulation with test bench methodology bridges simulation with test bench methodology bridges simulation with automatic test equipment (ATE)automatic test equipment (ATE)automatic test equipment (ATE)automatic test equipment (ATE)

I can relaxI can relaxI can relaxI can relaxmy test bench does my test bench does my test bench does my test bench does everything automaticallyeverything automaticallyeverything automaticallyeverything automatically


JMM v1.5

Test Bench /2Test Bench /2Test Bench /2Test Bench /2

� compare a test bench with MicroLabcompare a test bench with MicroLabcompare a test bench with MicroLabcompare a test bench with MicroLab----I3S:I3S:I3S:I3S:� there are chips and PCBs needed to be testedthere are chips and PCBs needed to be testedthere are chips and PCBs needed to be testedthere are chips and PCBs needed to be tested� there is a nice measurement equipmentthere is a nice measurement equipmentthere is a nice measurement equipmentthere is a nice measurement equipment� there are skilled and hard working peoplethere are skilled and hard working peoplethere are skilled and hard working peoplethere are skilled and hard working people� there are no signals coming or going to the outside of the there are no signals coming or going to the outside of the there are no signals coming or going to the outside of the there are no signals coming or going to the outside of the

lablablablab

responsegeneration

andverification

controland

stimulusgeneration

Test Bench

device under test (DUT)

why do we need why do we need why do we need why do we need MicroLabMicroLabMicroLabMicroLabif my test bench does theif my test bench does theif my test bench does theif my test bench does thejob as welljob as welljob as welljob as well


JMM v1.5

Test Bench in Design FlowTest Bench in Design FlowTest Bench in Design FlowTest Bench in Design Flowdesign ofdesign ofdesign ofdesign ofVHDL modelVHDL modelVHDL modelVHDL model

test benchtest benchtest benchtest bench

inpinpinpinp outoutoutout


inpinpinpinp outoutoutout

simulation ofsimulation ofsimulation ofsimulation ofVHDL modelVHDL modelVHDL modelVHDL model

synthesis ofsynthesis ofsynthesis ofsynthesis oflogic modellogic modellogic modellogic model

simulation ofsimulation ofsimulation ofsimulation oflogic modellogic modellogic modellogic model

place & routeplace & routeplace & routeplace & routephysical designphysical designphysical designphysical design

simulation ofsimulation ofsimulation ofsimulation ofextracted modelextracted modelextracted modelextracted model

ASIC fabricationASIC fabricationASIC fabricationASIC fabrication

prototype testprototype testprototype testprototype test(ASIC)(ASIC)(ASIC)(ASIC)

FPGA synthesisFPGA synthesisFPGA synthesisFPGA synthesisplace & routeplace & routeplace & routeplace & route

FPGA testFPGA testFPGA testFPGA test(debugger)(debugger)(debugger)(debugger)


inpinpinpinp outoutoutoutVHDLVHDLVHDLVHDLmodelmodelmodelmodel

test benchtest benchtest benchtest benchtest machinetest machinetest machinetest machine

inpinpinpinp outoutoutoutFPGAFPGAFPGAFPGAchipchipchipchip

test benchtest benchtest benchtest benchtest machinetest machinetest machinetest machine

inpinpinpinp outoutoutoutASICASICASICASICchipchipchipchip


JMM v1.5

VVVVHDL Test BenchHDL Test BenchHDL Test BenchHDL Test Benchuseuseuseuse IEEE.std_logic_1164.allentityentityentityentity TestBench isisisisendendendend TestBench;architecturearchitecturearchitecturearchitecture sample ofofofof TestBench isisisis

signal signal signal signal clk, a: bit;bit;bit;bit;signal signal signal signal b: bit;bit;bit;bit;componentcomponentcomponentcomponent MyCircuit

portportportport(clk,a:inininin bit; b: outoutoutout bit);end componentend componentend componentend component;

beginbeginbeginbeginDUT: MyCircuit port map port map port map port map (clk,a,b);processprocessprocessprocessbeginbeginbeginbeginclk <= ‘0’, ‘1‘ after 20 ns, ‘0‘ after 70 ns; wait forwait forwait forwait for 100 ns;

end process;end process;end process;end process;TestPatternGenerator: blockblockblockblockbeginbeginbeginbegin

processprocessprocessprocessbeginbeginbeginbegina <= ‘0’; -- test cycle 1wait forwait forwait forwait for 100 nsnsnsns;a <= ‘1’; -- test cycle 2wait forwait forwait forwait for 100 nsnsnsns;...

end process;end process;end process;end process;end block;end block;end block;end block;

endendendend sample;

test bench hastest bench hastest bench hastest bench hasno inputs, no outputsno inputs, no outputsno inputs, no outputsno inputs, no outputs

call of device under testcall of device under testcall of device under testcall of device under test(DUT)(DUT)(DUT)(DUT)

clkclkclkclk generationgenerationgenerationgeneration

test pattern generationtest pattern generationtest pattern generationtest pattern generationon a cycle by cycle basison a cycle by cycle basison a cycle by cycle basison a cycle by cycle basis

response patternresponse patternresponse patternresponse patternverification notverification notverification notverification notyet implemented!yet implemented!yet implemented!yet implemented!


JMM v1.5

Test Bench Test Bench Test Bench Test Bench ---- Test CycleTest CycleTest CycleTest Cycle

� design strictly synchronous circuitsdesign strictly synchronous circuitsdesign strictly synchronous circuitsdesign strictly synchronous circuits�cycle based test benchescycle based test benchescycle based test benchescycle based test benches

clockclockclockclock

apply input patternsapply input patternsapply input patternsapply input patterns capture output responsecapture output responsecapture output responsecapture output response

test cycletest cycletest cycletest cycle


outputoutputoutputoutput

validvalidvalidvalid

stablestablestablestable stablestablestablestable stablestablestablestable


JMM v1.5

ProTestProTestProTestProTest Test MachTest MachTest MachTest Machineineineine

� test bench controls CAD simulator and test machinetest bench controls CAD simulator and test machinetest bench controls CAD simulator and test machinetest bench controls CAD simulator and test machine� low cost rapid prototyping and test systemlow cost rapid prototyping and test systemlow cost rapid prototyping and test systemlow cost rapid prototyping and test system


JMM v1.5

ConclusionsConclusionsConclusionsConclusions

� HDLsHDLsHDLsHDLs are very useful for behavioral hardware are very useful for behavioral hardware are very useful for behavioral hardware are very useful for behavioral hardware system descriptionssystem descriptionssystem descriptionssystem descriptions

� abstract models do not precisely reflect the realityabstract models do not precisely reflect the realityabstract models do not precisely reflect the realityabstract models do not precisely reflect the reality� restriction to synthesizable coding is necessaryrestriction to synthesizable coding is necessaryrestriction to synthesizable coding is necessaryrestriction to synthesizable coding is necessary� technology independency opens the possibility to technology independency opens the possibility to technology independency opens the possibility to technology independency opens the possibility to

fast FPGA prototypingfast FPGA prototypingfast FPGA prototypingfast FPGA prototyping� test benches increase chip quality and highly test benches increase chip quality and highly test benches increase chip quality and highly test benches increase chip quality and highly

decrease simulation timedecrease simulation timedecrease simulation timedecrease simulation time


JMM v1.5

Exercises: VLSIExercises: VLSIExercises: VLSIExercises: VLSI----21: Test21: Test21: Test21: Test----BenchBenchBenchBench

� CAD Ex418: TestCAD Ex418: TestCAD Ex418: TestCAD Ex418: Test----Bench (difficulty: easy) Bench (difficulty: easy) Bench (difficulty: easy) Bench (difficulty: easy) Instead Instead Instead Instead of interactive simulation or writing macros for of interactive simulation or writing macros for of interactive simulation or writing macros for of interactive simulation or writing macros for interactive simulation, it is stateinteractive simulation, it is stateinteractive simulation, it is stateinteractive simulation, it is state----ofofofof----thethethethe----art to use art to use art to use art to use testtesttesttest----benches for simulation and chip test. benches for simulation and chip test. benches for simulation and chip test. benches for simulation and chip test. Write a Write a Write a Write a test bench file test bench file test bench file test bench file tb_SerialAdder2.vhdtb_SerialAdder2.vhdtb_SerialAdder2.vhdtb_SerialAdder2.vhd for the for the for the for the previous exercise Ex417. Generate the clock signal previous exercise Ex417. Generate the clock signal previous exercise Ex417. Generate the clock signal previous exercise Ex417. Generate the clock signal with a process and write sequential test cycles for with a process and write sequential test cycles for with a process and write sequential test cycles for with a process and write sequential test cycles for the input signals. Be aware that the testthe input signals. Be aware that the testthe input signals. Be aware that the testthe input signals. Be aware that the test----bench has bench has bench has bench has no input and output signals, but calls the unitno input and output signals, but calls the unitno input and output signals, but calls the unitno input and output signals, but calls the unit----underunderunderunder----test (UUT) and generates all stimuli.test (UUT) and generates all stimuli.test (UUT) and generates all stimuli.test (UUT) and generates all stimuli.


inpinpinpinp outoutoutoutVHDLVHDLVHDLVHDLmodelmodelmodelmodel


JMM v1.5

Coming Up...Coming Up...Coming Up...Coming Up...

� Next topic…Next topic…Next topic…Next topic…CAD exercises and mini FPGA projects PWM, blackjack CAD exercises and mini FPGA projects PWM, blackjack CAD exercises and mini FPGA projects PWM, blackjack CAD exercises and mini FPGA projects PWM, blackjack

dealer, simple microprocessor, etcdealer, simple microprocessor, etcdealer, simple microprocessor, etcdealer, simple microprocessor, etc

� Readings for next time...Readings for next time...Readings for next time...Readings for next time...VHDL tutorialsVHDL tutorialsVHDL tutorialsVHDL tutorialsA Prototype Test System for A Prototype Test System for A Prototype Test System for A Prototype Test System for ASICsASICsASICsASICs and and and and FPGAsFPGAsFPGAsFPGAs with a Tight with a Tight with a Tight with a Tight

Link to VHDL and Link to VHDL and Link to VHDL and Link to VHDL and VerilogVerilogVerilogVerilog----HDL Based CAD Simulators, HDL Based CAD Simulators, HDL Based CAD Simulators, HDL Based CAD Simulators, DATE’99. Design Automation and Test Engineering in DATE’99. Design Automation and Test Engineering in DATE’99. Design Automation and Test Engineering in DATE’99. Design Automation and Test Engineering in Europe Conference, Europe Conference, Europe Conference, Europe Conference, JacometJacometJacometJacomet et. al. (see on the et. al. (see on the et. al. (see on the et. al. (see on the MicroLabMicroLabMicroLabMicroLabweb)web)web)web)

On a Development Environment for RealOn a Development Environment for RealOn a Development Environment for RealOn a Development Environment for Real----Time information Time information Time information Time information Processing in SystemProcessing in SystemProcessing in SystemProcessing in System----onononon----Chip Solutions, SBCCI’0Chip Solutions, SBCCI’0Chip Solutions, SBCCI’0Chip Solutions, SBCCI’01, 1, 1, 1, IEEE 14th Symposium on Integrated Circuit and System IEEE 14th Symposium on Integrated Circuit and System IEEE 14th Symposium on Integrated Circuit and System IEEE 14th Symposium on Integrated Circuit and System Design, Brazil Sept. 2001, Design, Brazil Sept. 2001, Design, Brazil Sept. 2001, Design, Brazil Sept. 2001, JacometJacometJacometJacomet et. al. (see on the et. al. (see on the et. al. (see on the et. al. (see on the MicroLabMicroLabMicroLabMicroLab web)web)web)web)


JMM v1.5

Project 1: DeProject 1: DeProject 1: DeProject 1: De----Bounce CircuitBounce CircuitBounce CircuitBounce Circuit

� CAD Ex440_1: DeCAD Ex440_1: DeCAD Ex440_1: DeCAD Ex440_1: De----Bounce Project (difficulty: Bounce Project (difficulty: Bounce Project (difficulty: Bounce Project (difficulty: easy; time: medium): easy; time: medium): easy; time: medium): easy; time: medium): Design of a push button deDesign of a push button deDesign of a push button deDesign of a push button de----bounce circuit. Start with a FSM design and bounce circuit. Start with a FSM design and bounce circuit. Start with a FSM design and bounce circuit. Start with a FSM design and synthesize the logic manually (only 1 flipsynthesize the logic manually (only 1 flipsynthesize the logic manually (only 1 flipsynthesize the logic manually (only 1 flip----flip is flip is flip is flip is necessary). Code and simulate the VHDnecessary). Code and simulate the VHDnecessary). Code and simulate the VHDnecessary). Code and simulate the VHDL design.L design.L design.L design.

� For example, on the GECKO I/O Expansion board For example, on the GECKO I/O Expansion board For example, on the GECKO I/O Expansion board For example, on the GECKO I/O Expansion board are different switches and push buttons available. are different switches and push buttons available. are different switches and push buttons available. are different switches and push buttons available. The push buttons schematic is as follows. DeThe push buttons schematic is as follows. DeThe push buttons schematic is as follows. DeThe push buttons schematic is as follows. De----bounce the pushbounce the pushbounce the pushbounce the push----buttons.buttons.buttons.buttons.� draw the timing diagram of the signals SWx and draw the timing diagram of the signals SWx and draw the timing diagram of the signals SWx and draw the timing diagram of the signals SWx and

SWx_inverted when switchingSWx_inverted when switchingSWx_inverted when switchingSWx_inverted when switching� develop the finite state machine to generate the signal develop the finite state machine to generate the signal develop the finite state machine to generate the signal develop the finite state machine to generate the signal

buttonbuttonbuttonbutton� develop the schematic of the circuitrydevelop the schematic of the circuitrydevelop the schematic of the circuitrydevelop the schematic of the circuitry� simulate your VHDL code including the push button SWsimulate your VHDL code including the push button SWsimulate your VHDL code including the push button SWsimulate your VHDL code including the push button SW

SWxSWxSWxSWx

SWx_invertedSWx_invertedSWx_invertedSWx_invertedSWxSWxSWxSWx

VddVddVddVdd

buttonbuttonbuttonbuttondededede----bouncebouncebouncebouncecircuitrycircuitrycircuitrycircuitry

SWxSWxSWxSWx buttonbuttonbuttonbuttonreleasedreleasedreleasedreleased ‘0‘‘0‘‘0‘‘0‘pressedpressedpressedpressed ‘1‘‘1‘‘1‘‘1‘


JMM v1.5

Project Project Project Project 2: Traffic Light2: Traffic Light2: Traffic Light2: Traffic Light

� CAD Ex440_2: Traffic Light (difficulty: easy; CAD Ex440_2: Traffic Light (difficulty: easy; CAD Ex440_2: Traffic Light (difficulty: easy; CAD Ex440_2: Traffic Light (difficulty: easy; time: medium): time: medium): time: medium): time: medium): Redesign and implement your Redesign and implement your Redesign and implement your Redesign and implement your traffic light design from exercise Ex409 into an traffic light design from exercise Ex409 into an traffic light design from exercise Ex409 into an traffic light design from exercise Ex409 into an FPGA on the GECKO main board. Use the push FPGA on the GECKO main board. Use the push FPGA on the GECKO main board. Use the push FPGA on the GECKO main board. Use the push buttons and buttons and buttons and buttons and LEDsLEDsLEDsLEDs from the GECKO I/O Expansion from the GECKO I/O Expansion from the GECKO I/O Expansion from the GECKO I/O Expansion board. The clock oscillator frequency of the GECKO board. The clock oscillator frequency of the GECKO board. The clock oscillator frequency of the GECKO board. The clock oscillator frequency of the GECKO main board is 13.56 Mmain board is 13.56 Mmain board is 13.56 Mmain board is 13.56 MHz. The time between a Hz. The time between a Hz. The time between a Hz. The time between a change of the traffic lights is 1.5 seconds. The change of the traffic lights is 1.5 seconds. The change of the traffic lights is 1.5 seconds. The change of the traffic lights is 1.5 seconds. The main street has a minimum green phase time of 6 main street has a minimum green phase time of 6 main street has a minimum green phase time of 6 main street has a minimum green phase time of 6 seconds.seconds.seconds.seconds.

33

mainmainmainmainstreetstreetstreetstreet

secondarysecondarysecondarysecondarystreetstreetstreetstreet




Traffic LightTraffic LightTraffic LightTraffic LightCircuitryCircuitryCircuitryCircuitry


JMM v1.5

Project 3: Stop Project 3: Stop Project 3: Stop Project 3: Stop WatchWatchWatchWatch

� CAD Ex440_3: Stop Watch (difficulty: easy; time: CAD Ex440_3: Stop Watch (difficulty: easy; time: CAD Ex440_3: Stop Watch (difficulty: easy; time: CAD Ex440_3: Stop Watch (difficulty: easy; time: medium): medium): medium): medium): Design an implement a stop watch into an Design an implement a stop watch into an Design an implement a stop watch into an Design an implement a stop watch into an FPGA on the GECKO main board. Use the push FPGA on the GECKO main board. Use the push FPGA on the GECKO main board. Use the push FPGA on the GECKO main board. Use the push buttons and 7buttons and 7buttons and 7buttons and 7----segment LCD from the GECKO I/O segment LCD from the GECKO I/O segment LCD from the GECKO I/O segment LCD from the GECKO I/O Expansion board. The clock oscillator frequency of Expansion board. The clock oscillator frequency of Expansion board. The clock oscillator frequency of Expansion board. The clock oscillator frequency of the GECKO main board is 13.56 the GECKO main board is 13.56 the GECKO main board is 13.56 the GECKO main board is 13.56 MHz. The stop MHz. The stop MHz. The stop MHz. The stop watch resolution is 1/100 seconds, its maximum watch resolution is 1/100 seconds, its maximum watch resolution is 1/100 seconds, its maximum watch resolution is 1/100 seconds, its maximum value is 99.99 seconds for the 4 digit display. value is 99.99 seconds for the 4 digit display. value is 99.99 seconds for the 4 digit display. value is 99.99 seconds for the 4 digit display. Show the value “End” on the display when the Show the value “End” on the display when the Show the value “End” on the display when the Show the value “End” on the display when the watch exceeds 99.99 seconds. Use only one single watch exceeds 99.99 seconds. Use only one single watch exceeds 99.99 seconds. Use only one single watch exceeds 99.99 seconds. Use only one single push button for “start” and “stop”.push button for “start” and “stop”.push button for “start” and “stop”.push button for “start” and “stop”.


start/stopstart/stopstart/stopstart/stop


Stop WatchStop WatchStop WatchStop WatchCircuitryCircuitryCircuitryCircuitry

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