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TRANSCRIPT
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SOC Encounter v4.1
Speaker: IWei Lai
AdvisorTzi-Dar ChiuehMar. 14, 2005
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Outline
Introduction of SOCE v4.1
New Functions inside SOCE v4.1
Design Flow Conclusion
Reference
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Introduction of SOCE v4.1
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Introduction of SOCE v4.1(1/2)
SOC EncounterTM is a EDA tool develop by
Cadence
From Gate level to GDSII
Support 50+ million gate design at 180nm and
below
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SOCE is a platform and integrates
First Encounter Ultra
CeltIC
NanoRoute
SignalStorm NDC
VoltageStorm
Fire& Ice QXC
Introduction of SOCE v4.1 (2/2)
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New Functions inside SOCE v4.1
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Design Flow
Route
Stramout
*CTS synthesis
*.gds*.DEF
Timing analysis
power analysis
SVP
Import data
Floorplan
powerplan
placementTiming Optimization
Library
User data
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Silicon Virtual Prototype
Providing quick feedback on the design
performance
Use Trial Route to build up SVP
Designer can perform
timing analysis (SignalStorm NDC)
power analysis (VoltageStorm)
immediately after each step
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Trial Route
Quick routing for estimating routing-related
congestion and capacitance values
Does not guarantee DRC-clean routing
Does not perform signal integrity analysis
Use WRoute or NRoute for final routing
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NanoRoute(1/2)
Nearnano effect
Wire delay
IR drop and SI effect
Suitable for
.13 technology
Chip more than 300K instances
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NanoRoute(2/2)
Supports
Timing issue
Signal integrity
Manufacturing Awareness
multi threading
Super threading
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Timing Optimization
Optimizing Correct DRVs
Reduce total negative slack
Setup & hold time
Skew optimization *
Optimizing by using techniques Adding buffers
Resizing gates
Restructuring the netlist Remapping logics
Swapping pins
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Design Flow (Encounter V4.1)
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Requiring Data
Library
Physical Library(*.LEF)
Timing Library(*.LIB)
Capacitance Table Celtic Library
Fire&Ice/VoltageStorm Library
User Data
Gate-Level netlist(*.v)
Timing constraints(*.sdc)
IO constraint(*.ioc)TCL format
Operation condition
Pin type
Path Delay
Timing constraint
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Environment Setting
Add
source /usr/cadence/SOC/CIC/soc.csh
source /usr/cadence/SOC/CIC/license.csh
in your .cshrc
Start SOC Encounter
unix%encounter
(dont run in background mode)
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Design Flow
Route
Stramout
*CT synthesis
*.gds
*.DEF
Import data
Floorplan
powerplan
placement
Library
User data
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GUI
Design->Design Import
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Import Design(1/3)
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Import Design(2/3)
Global nets
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*Import Design(3/3)
For more accuracyRC extraction (optional)
For crosstalk analysis
(optional)
Save these steps into *.conf
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Save/Restore design
The temporal design can be save or restore at
any point during the flow
*.enc
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Our design hard macro
Flight lines
Initial Floorplan view
Floorplan->Global Net Connections
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Global Connect
1a. VDD(VSS)
2. VDD(VSS)
3. Add to List
1b. VDD(VSS)
1c.Connect 1b1(1b0) toGlobal nets
4. Repeat 1a,b,c~3 six times
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FloorPlan(1/3)
Row spacing >1Row spacing =0
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Floorplan(2/3)
Place & *Place hard marco
1. Floorplan->Place Blocks/Modules->Place
2. *Select Place hard macros inside modules
3. Use
1. Floorplan->Edit Floorplan->Flip/Rotate Instances
2.
4. Floorplan->Set Block Placement Status
Set block state pre-state
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Floorplan(3/3) move the block
Floorplan->Edit Block Halo
initial move&rotate add block halo
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Powerplan(1/5)-Add Power Ring
Floorplan->Power
planning->Add Rings
Auto adjust spacing
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Powerplan(2/5) -Add Power Ring
The number of thin rings
Use Wire group prevent
slot error
Route->SRoute, SelectPad pins
connecting power ring to
power pad
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Powerplan(3/5)-interleave
Interleaving w/o interleaving
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Powerplan(4/5)-add power stripe
distance between adjacent stripe
Floorplan ->Power Planning
-> Add Stripes
Select Omit stripes inside
block rings at Advanced
tab
Use wire group, too
Route>SRoute, selectStripes(unconnectd)
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Powerplan(5/5)-add power stripe
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Placement
*Specify ScanChain First
Place->Place select Medium effort or High
effort,
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*CT synthesis(1/3)
1. Clock->Create Clock Tree Spec
2. Clock->Specify Clock Tree
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*CT synthesis(2/3)
3. Clock->Synthesize Clock Tree
4. Clock->Display->Display Clock Tree
The color means Phase delayMax/min path
clk pad
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*CT synthesis(3/3)
Clock->Clock Tree Browser...
open Clock Tree Browser form
Show the detail clock info. and modify the clock
tree
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Route(1/4)
- power route & Add Filler
Route->SRouteselect Standard Cell pins
Key in addIOFiller cell prefix PFEED
at command line Fillercellname
PFEED ex: PFEED50 PFEED5 PFEED01
The number means the size of filler cell
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Route(2/4)- nRoute
Route->nRoute
assign characteristics to special nets
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Route(3/4)-nRoute
SuperThreading
Use .rhosts to get the remote control
Global route
detail route
Final report
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Route(4/4)- Add Core Filler
Place->Filler->Add Filler
Fillers are placed from large to small
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Final view
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Streamout
Design->Save->GDS
Design->Save->DEF
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Design Flow
Timing analysis
power analysis
SVP
Timing Optimization
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SVP
Build up SVP before t/p analysis
Place->Place, Select Prototyping
Route->Trial Route, select Prototyping
Physical view Amoeba view
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Timing Analysis(1/2)
1. Timing->Extract RC
2. Timing->Timing Analysis
3. Timing->Timing Debug-
>Slack Browser
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Timing Analysis(2/2)
Slack browser
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Power Analysis(1/4)
1. Timing->Extract RC
2. Power->Edit Pad Location
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Power Analysis(2/4)
3. Power->Edit Net Toggle
Probability
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Power analysis(3/4)
4. Power->Power Analysis->
Statistical
VDD or VSS
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Power analysis(4/4)
Read Pa.report
Power->Display->Display Rail analysis Result
IR drop EM
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Timing Optimization
Timing->Optimization
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Suggested Design Flow
Route
Stramout
*CTS synthesis
*.gds*.DEF
Timing analysis
power analysis
SVP
Import data
Floorplan
powerplan
placementTiming Optimization
Library
User data
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Conclusion
SOC Encounter is an integrated platform for
near-nano and nanometer digital IC design
SVP can be used to analyze and optimize the
design immediately after step
Design flow of SOC Encounter is introduced
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Reference
CIC training program(A106) Cell-Based IC Physical Design andVerification with SOC Encounter, Jan. 2005
www.cadence.com
Cadence, EncounterTMUser Guide, Product Version 4.1, June
2004 Cadence, Whats New in EncounterTM, Product Version 4.1,
June 2004
Cadence, EncounterTM Known Problem and Solutions ,
Product Version 4.1, June 2004
Cadence, EncounterTM Database Access Command Reference,Product Version 4.1, June 2004
Trouble shooting(1)
http://www.cadence.com/http://www.cadence.com/ -
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Trouble shooting(1)
-How to modified layout
Change the width
Hotkey e call the Edit Route Form
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NanoRoute(2/3)
Global routing
Breaking the design into global cell (gcell)
Minimizing congestion and the number of gcell that
have more nets assigned than routing sourcesavailable
Detail routing
Dividing the design into switch boxes (SBoxes)
Search and repair routing
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Footprint
IPO
RC extraction
Net toggle prob.
Trail routenroute
Prototyping low effort medium effort
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Timing Optimization(1/2)
Three categories
Pre-CTS Optimization
Post-CTS Optimization
Post-Route Optimization
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Timing Library
Operating condition
Pin type
Path Delay
Timing constraint
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Timing constraint
Create clock
Input delay
Output delay
Input drive
Output loading
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I/O constraint
Pin name
Pad
Name
Position
Length
spacing
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Import Design(1/4)
Import verilog file
Top module name
Import LEF file
Import LIB file? Why max->slow->setup time
Footprint(optional)
I/O constraint (optional)
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Import Design(2/4)
*.tbl
timing constraint
h
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*CTS synthesis(2/4)
step 1
step 2, push this button thenclick the synchronous pins