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مذار های ترتیبي: هفتم فصل VLSI - مذارهای طراحي 1390 -مجیذ شالچیان

VLSIطراحي مدارهاي

مدار هاي ترتیبي : فصل هفتم

مجيد شالچيان

دانشكذه مهنذسي برق

دانشگاه صنعتي امیركبیر

مذار های ترتیبي پویا: بخش دوم


رجیستر هاي ایستا و پویا

زجيستس ای ایستا

است وگدازی می کىىد حالت زا تا شماويک مىبع تغری زيشه .

بس يجد حلق فيدبک مثبت بيه خسيجی ي يزيدی عمل می کىىد مبتىی .

ويست می تان با يقتی تغييسات سيگىال چىدان سسیعclock gating تان زا کم کسد.

زجيستس ای پیا

حالت دز خاشوای پازاشیتی ذخيس می شد .

حالت زا ذخيس می کىىد( ميلی ثاوي) بسای شمان ای بسياز کتا .

متىايب سيگىال دازود وياش ب باشساشی(Refresh)

تس دازای سسعتباالتس ي مصسف تان کمتس ستىد معمال ساد .


Timing Metricsیادآوري داوشگا صىعتی اميسکبيس

clock

In

Out

data

stable

output

stable

output

stable

time

time

time

clock

tsu thold

tc-q


Review: System Timing Constraints داوشگا صىعتی اميسکبيس

Combinational

Logic

clock

Outputs

Next

State

Current

State

Inputs

T tc-q + tplogic + tsu tcdreg + tcdlogic thold

T (clock period)


داوشگا صىعتی اميسکبيس مقایسه لچ ایستا و پویا

D

CLK

CLK

Q

Dynamic (charge-based)

CLK

CLK

CLK

D

Q

Static


داوشگا صىعتی اميسکبيس

T1

T2

I1 I2 Q

QM D

C1

C2

!clk

clk

clk

!clk

!clk

clk

master transparent

slave hold

master hold

slave transparent

master slave

tsu =

thold =

tc-q =

tpd_tx

zero

2 tpd_inv + tpd_tx

فلیپ فالپ حساس به لبه دینامیکي


race conditionهمپوشاني کالک و داوشگا صىعتی اميسکبيس

T1

T2

I1 I2 Q

QM D

C1

C2

!clk

clk

clk

!clk

!clk

clk

0-0 overlap race condition

toverlap0-0 < tT1 +tI1 + tT2

1-1 overlap race condition

toverlap1-1 < thold


استفاده از کالک هاي نا همپوشان داوشگا صىعتی اميسکبيس

clk2

clk1

tnon_overlap

T1

T2

I1 I2 Q

QM D

C1

C2

clk1

!clk1

clk2

!clk2

master transparent

slave hold

master hold

slave transparent


داوشگا صىعتی اميسکبيس Pseudostatic Dynamic Latch

Robustness considerations limit the use of dynamic FF’s

coupling between signal nets and internal storage nodes can inject significant noise and destroy the FF state

leakage currents cause state to leak away with time

internal dynamic nodes don’t track fluctuations in VDD that reduces noise margins

A simple fix is to make the circuit pseudostatic

D

!clk

clk

Add above logic added to all dynamic latches


C2MOS (Clocked CMOS) ET Flipflop داوشگا صىعتی اميسکبيس

clk

!clk

!clk

clk

QM

C1 C2

Q D

M1

M3

M4

M2 M6

M8

M7

M5

Master Slave

!clk

clk

master transparent

slave hold

master hold

slave transparent

on

on

off

off on

on off

off

A clock-skew insensitive FF


C2MOS FF 0-0 Overlap Case داوشگا صىعتی اميسکبيس

0 0 QM

C1 C2

Q D

M1

M4

M2 M6

M8

M5

!clk

clk

!clk

clk

Clock-skew insensitive as long as the rise and fall times of the clock edges are sufficiently small


C2MOS FF 1-1 Overlap Case داوشگا صىعتی اميسکبيس

1 1

QM

C1 C2

Q D

M1

M2 M6

M5

!clk

clk

M3 M7

!clk

clk

1-1 overlap constraint

toverlap1-1 < thold


C2MOS Transient Response داوشگا صىعتی اميسکبيس

-0.5

0

0.5

1

1.5

2

2.5

3

0 2 4 6 8

QM(3) Q(3)

Q(0.1)

Time (nsec)

clk(0.1)

clk(3)

For a

0.1 ns clock

For a

3 ns clock

(race condition

exists)


داوشگا صىعتی اميسکبيس Pipelining

RE

GR

EG

RE

G

log

a

CLK

CLK

CLK

Out

b

RE

GR

EG

RE

G

log

a

CLK

CLK

CLK

RE

G

CLK

RE

G

CLK

Out

b

Reference Pipelined


True Single Phase Clocked (TSPC) Latches داوشگا صىعتی اميسکبيس

clk clk In

Q

Positive Latch Negative Latch

transparent when clk = 1

hold when clk = 0

clk clk In

Q

hold when clk = 1



TSPC ET FF داوشگا صىعتی اميسکبيس

clk

master hold

slave transparent

clk clk

D

Master Slave

clk clk Q

QM

master transparent

slave hold

on on

off off

on on

off off

on on off off


Simplified TSPC ET FF داوشگا صىعتی اميسکبيس

clk D clk

Q

clk

clk

X

QM

M1

M2

M3 M6

M5

M4 M7

M8

M9

clk

master hold

slave transparent

master transparent

slave hold

on

on

off

off

1

!D on

off

on

off

D D


Sizing Issues in Simplified TSPC ET FF داوشگا صىعتی اميسکبيس

0

1

2

3

0 0.2 0.4 0.6 0.8 1

Time (nsec)

clk

!Qorig

Qorig

!Qmod

Qmod

Transistor sizing

Original width

M4, M5 = 0.5m

M7, M8 = 2m

Modified width

M4, M5 = 1m

M7, M8 = 1m


Split-Output TSPC Latches داوشگا صىعتی اميسکبيس

clk In

Q

Positive Latch Negative Latch


hold when clk = 0

clk In Q

hold when clk = 1


A

A

When In = 0, A = VDD - VTn When In = 1, A = | VTp |


Split-Output TSPC ET FF داوشگا صىعتی اميسکبيس

clk D

Q

clk

clk

QM


Pulsed FF (AMD-K6) داوشگا صىعتی اميسکبيس

Pulse registers - a short pulse (glitch clock) is generated locally from the rising (or falling) edge of the system clock and is used as the clock input to the flipflop

race conditions are avoided by keeping the transparent mode time very short (during the pulse only)

advantage is reduced clock load; disadvantage is substantial increase in verification complexity

clk

D

Q

M1

M2

M3

M4

M5

M6

P1

P2

P3 X

!clkd

0 ON Vdd

OFF OFF

1 1 0 ON

1/0 ON/

OFF

0/Vdd ON/OFF

1/0

0 OFF

1

1

OFF

ON ON

ON



Sense Amp FF (StrongArm SA100)

clk

D

Q

!Q

M1

M2

M3

M5

M6

M4

M9

M7

M8

M10

Sense amplifier (circuits that accept small swing input signals and amplify them to full rail-to-rail signals) flipflops

advantages are reduced clock load and that it can be used as a receiver for reduced swing differential buses

0

0

1

1

1

1

1

0

1

0

1


Flipflop Comparison Chart

Name Type #clk ld #tr tset-up thold tpFF

Mux Static 8 (clk-!clk) 20 3tpinv+tptx 0 tpinv+tptx

PowerPC Static 8 (clk-!clk) 16

2-phase Ps-Static 8 (clk1-clk2) 16

T-gate Dynamic 4 (clk-!clk) 8 tptx to1-1 2tpinv+tptx

C2MOS Dynamic 4 (clk-!clk) 8

TSPC Dynamic 4 (clk) 11 tpinv tpinv 3tpinv

S-O TSPC Dynamic 2 (clk) 10

AMD K6 Dynamic 5 (clk) 19

SA 100 SenseAmp 3 (clk) 20


داوشگا صىعتی اميسکبيس Choosing a Clocking Strategy

Choosing the right clocking scheme affects the functionality, speed, and power of a circuit

Two-phase designs

+ robust and conceptually simple

- need to generate and route two clock signals

- have to design to accommodate possible skew between the two clock signals

Single phase designs

+ only need to generate and route one clock signal

+ supported by most automated design methodologies

+ don’t have to worry about skew between the two clocks

- have to have guaranteed slopes on the clock edges

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