vlsi modules

7/30/2019 VLSI Modules

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Autumn Semester Spring Semester Summer

Core Modules

ASICS 1 ASICS 2

Test Engineering1 Test Engineering 2Semiconductor Technology Noise in Circuits and Systems

Project Project Project

Elective Modules

Digital Signal Processing Digital Control

Information Theory & Coding Digital Communications

Advanced Digital SystemDesign

Advanced Topic Seminars


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Module Code-Title:

EE6621 - ASICS 1 (DIGITAL ASICS)

Hours Per Week:

Lecture

2

Lab

2

Tutorial

0

Other

0

Private

6

Credits

6

Grading Type:

N

Prerequisite Modules:

Rationale And Purpose Of The Module:

This module introduces issues relating to the design and implementation of

application-speci?c integrated circuits (ASICS) for digital systems.

Syllabus:

Introduction to Design Methodology. Custom IC design. Standard cells.Programmable logic. Gate arrays. FPGAs. ASICs. VLSI Structures. CMOS, advanced

CMOS, ROMs and RAMs. Introduction to UNIX. Manipulating ?les and directroies.Information processing. Printing. Using remote systems. Tailoring the envioromnent.

Job control. Editors. Design entry and simulation. Schematic capture. Simulation.


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Verilog HDL. Module form general syntax. Data types. Constant assignment.Parameters. Arrays. Operators. Procedural statements. Using built-in functions in

Verilog. Additional Verilog constructs. Two behavioural examples: gate levelsimulation, tri-state gates. Device layout and fabrication. The CMOS IC fabrication

process. The CMOS inverter. Other CMOS Structures (in an n-well process).

Learning Outcomes:

Cognitive (Knowledge, Understanding, Application, Analysis, Evaluation, Synthesis)

Draw the design ?ow of a modern digital ASIC and list the inputs and outputs of each

of the stages in such a design ?ow. Write a synthesizable hardware descriptionlanguage module for a digital system, along with a test bench for the system. Design

and analyse CMOS inverter circuits driving capacitative loads based on the longchannel model. system. Describe the limitations of the long channel model for deep

submicron processes, and discuss the short channel model. Draw the schematic ofany standard logic cell and design the schematic of any composite gate in the CMOS

style.

Affective (Attitudes and Values)

None

Psychomotor (Physical Skills)

None

How The Module Will Be Taught and What Will Be The Learning Experiences

Of The Students:

Lectures/Labs

Research Findings Incorporated In To The Syllabus (If Relevant):

Prime Texts:

Smith, M.J.S. (1997)Application-Specific Integrated Circuits , Addison-Wesley

Other Relevant Texts:

Smith, D.J. (1996) HDL Chip Design , Doone PublicationsShoji, M. (1988) CMOS Digital Circuit Technology, Prentice Hall

Hurst, S.L. (1998) VLSI Testing: Digital and Mixed Analogue/Digital Techniques , IEEPress

Programme(s) In Which This Module Is Offered:

M.Eng. in VLSI Systems


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Module Code-Title:

EE6631 - TEST ENGINEERING 1 (PRODUCTION TEST SYSTEMS)

Hours Per Week:

Lecture

2

Lab

2

Tutorial

0

Other

0

Private

6

Credits

6

Grading Type:

N



The increasing complexities and speed of operation of modern digital circuits and

systems is increasing the demand on product testing. The purpose of the module is

to introduce the students to modern semiconductor integrated circuit (IC) testmethods, including automatic test equipment (ATE), design for testability (DfT) and

built-in self-test (BIST) for digital ICs.

Syllabus:


systems is increasing the demand on product testing. The module will concentrate on


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IC designs, with the following key areas covered:- 1. Semiconductor test overview:-test points for semiconductor devices from wafer to package. 2. Test Engineering

requirements. 3. Digital logic test concepts:- sequential and combinational logic. 4.Memory test:- RAM and ROM. 5. Fault modelling and fault simulation 6. Design for

Testability (DfT). 7. Built-In Self-Test (BIST). 8. Problem with design complexity:System on a Chip (SoC) test problem. 9. ATE systems. 10. IEEE Standard 1149.1

(Boundary Scan).

Learning Outcomes:


1. Understand the role of test engineering in the design and manufacturing of digital

circuits and systems using integrated circuit (IC) technology. 2. Understand thedifference between functional and structural testing, and the role of fault modelling

in structural testing. 3. Understand the different tests applied to the digital circuitstypically encountered in test: combinational & synchronous sequential logic and

memory. 4. Understand the concepts and design for testability (DfT) and built-in

self-test (BIST).


1. Appreciate the importance of the role of test in the production of digital circuits

and systems using integrated circuit (IC) technology.


1. Develop test patterns for the detection of stuck-at-faults (SAFs) in combinationallogic circuits in order to demonstrate the detection of SAFs. 2. Construct timing

diagrams for combinational and synchronous sequential logic circuits in order to des

How The Module Will Be Taught and What Will Be The Learning ExperiencesOf The Students:

The module is based on 12 teaching weeks within the semester, with 2 lecture hours

and 2 laboratory hours per week. The module contains a substantial project which isworth 40% of the module assessment (with the remaining 60% assigned to the end

of module examination). The 40/60 module assessment split is set to reflect thestuednt effort involved in the project. The project normally runs from week 3 to week

12 (week 3 for the project choice) and the presentations would be in week 12. Theproject presentation is based on a one-to-one presentation at the workstation in

order for the student to present the working solution and to discuss problemsarising/solutions attained. A project report (in the style of a technical conference

paper) is also to be provided by the student at the time of the presentation. Theproject details are changed every year. The students would be encouraged to discuss

the problems they encounter with each other, but it is made clear to them that thefinal work, report and presentation are individual efforts. The project would not start

at the commencement of the module as the students would need to learn specificskills first in the use of the design and analysis tools, in addition to circuit design

topics covered in the module.


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The module lecturer (Dr Ian Grout) is an active researcher in the area of mixed-signal integrated circuit IC design, test and design for testability (DfT). As such, the

examples and projects are based on current industry needs and the types of circuitsen

Prime Texts:

Hurst S (1998) VLSI Testing digital and mixed analogue/digital techniques , IEEBushnell M. and Agrawal V. (2000) Essentials of Electronic Testing for Digital,

Memory and Mixed-signal VLSI Circuits , Kluwer Academic PublishersRajsuman R (2000) System-on-a-Chip Design and Test, Artech House Publishers


Smith, D.J. (1993) Reliability, Maintainability & Risk, Butterworth-HeinemannOConnor P (2001) Test Engineering , Addison Wesley


LM347 (M.Eng. in VLSI Systems)


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Module Code-Title:

EE6641 - SEMICONDUCTOR TECHNOLOGY

Hours Per Week:

Lecture

2

Lab

2

Tutorial

0

Other

0

Private

6

Credits

6

Grading Type:

NRationale And Purpose Of The Module:

This module introduces students to the fundamentals of VLSI manufacturingprocesses and technology.

Syllabus:

IC Technology: Concept of die size and design rules; General overview of MOS and

Biplar technologies. Semiconductor Material: Crystal growth, defects and processingof silicon; alloying; epitaxial growth. Deposition: Atmospheric and low pressure

chemical vapour depostition, polycrystalline and amorphous ?lm deposition;evaporation; sputtering; properties of thin ?lms: aluminium, refactory metals and

silicides; Metalization; bonding; contacts; packaging. Oxidation: Kinetics of thermal

oxidation, dry, wet, pyrogenic, HCI and TCE ambient properties of interface, LOCOS.Diffusion: P and N type impurities, Constant and limited source, annealing and

diffusion in oxide; Gettering. Ion Implantation: process technique, trajectories.

Lithography: Optical exposure and resist system, process characterization, mask


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making, wet and dry etching. Process Simulation: lithography, oxidation, diffusion,etching. Process Integration: Overview of Bipolar, NMOS, CMOS and BiCMOS

technologies, threshold control, latch up prevention, parasitics; SOI and SOStechnologies.

Learning Outcomes:


Describe the concept of design rules and die size, with reference to MOS and Bipolartechnologies. List materials used in IC manufacturing, with reference to material

properties along with methods of crystal growth, alloying and epitaxial growth.Explain methods of thin-?lm deposition, such as CVD & sputtering, and properties of

the deposited ?lms. Describe kinetics of thermal oxidation and the properties of theoxide, including those at the interface. Describe diffusion of n-type and p-type

impurities using a constant or limited source. Describe ion implantation as analternative or complementary process to diffusion techniques. Explain optical

lithography, including the resist chemistry, process characterisation, mask making,

and wet or dry eching. Demonstrate through simulation lithography, oxidation,diffusion and etching processes. Describe process integration involving: Biplor / MOStechnologies; the use of SOI & SOS; latch-up & parasitics; contact formation;

packaging.


None


None


Lectures/Labs


Prime Texts:

Sze, S.M. (1988) VLSI Technology, McGraw-Hill


Einspruch, N.J. (1985) VLSI Handbook, McGraw-HillWolf & Touber (2000) Silicon Processing for the VLSI Era , Lattice Press




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U n i v e r s i t y of L i m e r i c kModule Description

1. Module Code - Title: EE6451 - DIGITAL SIGNAL PROCESSING

2. Hours Per Week: Lecture Lab TutorialOther Private ECTS Credits2 2 0 0 6 6

3. Grading Type: N

4. Prerequisite Modules:

5. Rationale and Purpose of the ModuleTo introduce the theory of digital signal processing, including the following veryimportant topics: the discrete Fourier Transform, the Z-transform and digital ?lter design.

6. Syllabus

Discrete signals and systems. The DFT, its properties and applications; relationship toother transforms; Fourier, Laplace, Z-transform etc. Railings as theoretical samplers.Spectral descriptions of sequences. Analogue and digital convolution, the z-transform inthe design of FIR digital ?lters. Linear-phase, all-pass ?lters, minimum-phase ?lters.Differentiators and Integrators. Windowing techniques in ?lter design. Filter design andfast convolution by FFT. Frequency-sampling ?lters. IIR ?lters: mapping from analogue ?lters, bi-linear mapping, review of other mappings, their application in digital andsampled-data (e.g. switched-capacitor) ?lters. Up-sampling and down-sampling. Band-pass signals and modulation. Finite word-length effects; impact on architectures. Noisetopics. Sigma-delta noise shaping, applications in A/D and D/A conversion. Correlationprinciples. Fast correlation by DFT. Introduction to adaptive ?ltering. Wiener ?lter. LMS

algorithm. Selected applications. Power spectra and spectral estimation.

7. Learning Outcomes

Cognitive (Knowledge, Understanding, Application, Analysis, Evaluation,

Synthesis)Examine the various components of a typical DSP system and identify factors thatinfluence their functionality, specifications and choice Demonstrate how digital signaland data are represented in time and frequency domains, and deal with relatedqunatisation issues Make use of the FFT to achieve large speed improvements in thecorrelation and ?ltering of data sets. Make use of the FFT and a choice of tapered

windows to monitor signals correctly while minimizing errors due to leakage and withdue compensation for tapered window properties. Model ?lters in the frequencydomain, using the Z-transform, for both FIR and IIR ?lter types. Derive digital ?ltersfrom analogue prototypes using common methods such as the Bilinear trasformation.Recognise, predict and quantify sources and levels of noise in DSP systems, anddevise means to reduce noise effect.



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None

Psychomotor (Physical Skills)None

8. How the module will be taught and what will be the learning experiences of the

studentsThe module is based on 12 teaching weeks and delivered via a set of lectures, labs andseminars. Assessment is based on 80% final exam and 20% coursework which involves 3assignments.

9. Research Findings incorporated into the syllabus (If relevant)

10. Prime Texts

Ifeachor, E. C. and Jervis, B. W. (2002)Digital Signal Processing: A PracticalApproach, 2/E, Prentice Hall, Essex, UK.

11. Other Relevant TextsDiniz, P. S. R., de Silva, E. A. B. and Netto, S. (2006)Digital Signal Processing: SystemAnalysis and Design, , Cambridge University Press, Cambridge, UK.Mitra, S. K. (2006)Digital Signal Processing: A Computer Based Approach, 3/E,McGraw-Hill, Boston, Massachusetts.

12. Programme(s) in which this Module is offeredM.Eng. in Computer and Communications Systems



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1. Module Code - Title: EE6461 - INFORMATION THEORY AND CODING


3. Grading Type: N


5. Rationale and Purpose of the ModuleThis module aims to guide the student through the implications and consequences offundamental theories and laws of information theory and to impart a comprehensivegrounding in source coding, random and burst error protection coding theory withreference to their increasingly wide application in present day digital communications

and computer systems.

6. SyllabusInformation Theory. Entropy. Information rate. Shannons Theorem, channel capacity:Bandwidth - S/N trade-off. Fundamentals of information theory: source encoding theoryand techniques. Communication channels: m-ary discrete memoryless, binary symmetric.Equivocation, mutual information, and channel capacity. Shannon-Hartley theorem.Channel coding: random and burst error protection on communication channels.Interleaving principles. Types and sources of error. Linear block coding. Standard Arrayand syndrome decoding. Cyclic and Convolution codes. Soft and hard decision detection.Viterbi decoding.



Synthesis)Name, depict and explain the operations preformed by a generic communicationssystem from the data source to the data sink. Analyse the characteristics of a datasource or communications channel using information theory. Design and analyseschemes for source coding. Design and analyse schemes for block and convolutionalcoding.

Affective (Attitudes and Values)None




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studentsLectures/Labs


10. Prime TextsUsher M.J. & Guy C.G. (1997)Information Theory and Communications for Engineers ,MacMillian Press Ltd

11. Other Relevant TextsWicker, S.B. (1995)Error Control systems for digital communications and storage ,Englewood CliffsLin, S. & D.J. Costello (1983)Error Coding: Fundamentals & Applications , PrenticeHall

12. Programme(s) in which this Module is offeredM.Eng. in Computer and Communications SystemsM.Eng. in VLSI Systems


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1. Module Code - Title: EE6471 - ADVANCED DIGITAL SYSTEM DESIGN


3. Grading Type: N


5. Rationale and Purpose of the ModuleThis module aims to equip the student with a range of techniques applicable to the designand test of very high speed and fault-tolerant digital circuits.

6. Syllabus

Review: High-speed design in the time and frequency domains; re?ection, ringing andcrosstalk, transmission lines. Transmission lines and termination strategies: Series,Thevenin, diode and AC terminations; Crosstalk, re?ections, ground bounce. Propertiesand behaviour of stripline and microstrip traces. Technology review: LVDS, ECL/PECL,GTL, SSTL, HSTL, and high-speed CMOS drivers and receivers; mixed voltage systems;bus-hold and bus-loading considerations; hot insertion. Synchronous Design: Clockoscillators and buffering, Clock Distribution, Metastability. System Design andManufacture: PCB materials; Layer build and speci?cation; Power supply considerations;Decoupling techniques. EMC/ESD: Radiated vs conducted; Filtering; Effects ofapertures, gasketing; Conducted emissions, coaxial cables, twisted pair; Shielding.Thermal Aspects: Sources of heat; Thermal resistance; Basic air?ow models; Impact on

reliability; Altitude Effects. Reliability: Bathtub curves; Highly Accelerated Life Testing(HALT). Models and Simulation: Spice and IBIS-based simulations. Fault-tolerance andredundancy: Fault-tolerant digital circuits. Architecture of fault-tolerant computers.



Synthesis)Describe metastability in digital systems and discuss how it may be avoided. Describethe effects of clock-skew and jitter in digital systems. Design synchronous digitalsystems that are clock-skew tolerant. Design high-speed clock distribution circuits for

digital systems. Design well-engineered transmission-line systems for high-speeddigital signals. Apply Dennards theory of constant-?eld scaling to digital systems.Analyse the loading and power consumption effects dictated by particular bus con?gurations. Describe and analyse the amount of crosstalk effects in high-speed circuits.Describe approaches to fault-tolerance in digital systems. Analyse fault-tolerantarchitectures in terms of MTBF.



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None





10. Prime TextsJohnson, H. & M. Graham (1993)High-Speed Digital Design , Prentice HallTocci, R. J., Widmer, N. S. & Moss, G. L. (2007)Digital Systems , Prentice Hall

Dally, W.J., & J.W. Poulton (1999)Digital Systems Engineering, Cambridge

11. Other Relevant TextsJohnson, H, (2000)Digital System Integrity , Prentice HallNeamen, D. A. (2001)Electronic Circuit Analysis and Design , McGraw-HillRazavi, B (2000)Design of Analog CMOS Integrated Circuits , McGraw-Hill



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Module Code-Title:

EE6622 - ASICS 2 (ANALOGUE ASICS)

Hours Per Week:

Lecture

2

Lab

2

Tutorial

0

Other

0

Private

6

Credits

6

Grading Type:

N


EE6621


This module aims to provide an introduction to the design of full custom analogue

ASICs (Application Speci?c Integrated Circuits). It follows on from EE6621 and

complements the material in the earlier module by shifting focus to consideranalogue IC design.

Syllabus:


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Review of basic CMOS process. Basic electrical properties and SPICE modelling ofMOS transistors. Circuit simulation and model complexity issues. Basic circuit

concepts. Resistors and capacitors in CMOS. Sheet resistance Rs. Resistor structures.Area capacitances of layers. Wiring capacitances. Bipolar Junction Transistors and

diodes. ESD protection structures. SPICE modelling of BJTs and diodes. Latch-up incircuits. The operational ampli?er. Functional operation and modelling. Macro and

transistor level models in SPICE. Op-amp design. Current mirrors, differential inputstage, voltage and power ampli?er stages. Single and dual-rail operation. AnalogueIC layout design. MOS transistors, capacitors, resistors, interconnect. CAD tool and

design issues. CIF output. The CMOS Inverter. Operation, modelling and simulation.

Static CMOS logic cell design. Inverter delays. Propagation delays. Analog to digitalconverters. Successive approximation, ?ash and staircase ADC. Architectures and

design. SPICE modeling and simulation. Digital to analog converters. Resistor stringand weighted-current DAC. Architectures and design. SPICE modelling and

simulation.

Learning Outcomes:


1. Describe the CMOS fabrication process for commonly required passive and active

devices at the IC level. 2. Analyse the operation of typical circuit building blocks

found in mixed-signal IC designs. 3. Develop the architectures for, and analyse theoperation of, typical data converter designs. 4. Develop, interpret and utilise SPICE

simulation model representations of typical circuit building blocks found in mixed-signal IC designs. 5. Utilise an analogue circuit simulator in order to simulate the

analogue circuit operation of typical mixed-signal IC designs. 6. Utilise a commercial

CAD tool in order to undertake full-custom circuit schematic capture, simulation andlayout of typical mixed-signal IC designs.


None


None


Lectures/Labs


Prime Texts:

Laker, K. & Sansen, W. (1994) Design of Analog Integrated Circuits and Systems ,

McGraw-Hill



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Pucknell, D. & Eshraghian, K. (1994) Basic VLSI Design , Silicon SystemsEngineering Series

Haskard, M. & May, I. (1988)Analog VLSI Design, nMOS and CMOS , SiliconSystems Engineering Series

Kang ,S. & Leblebici, Y. (1996) CMOS Digital Integrated Circuits , McGraw-HillNeamen, D. (1996) Electronic Circuit Analysis and Design , Irwin




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Module Code-Title:

EE6632 - TEST ENGINEERING 2 (DEVICE AND CIRCUIT LEVEL TEST)

Hours Per Week:

Lecture

2

Lab

2

Tutorial

0

Other

0

Private

6

Credits

6

Grading Type:

N


EE6631



systems is increasing the demand on product testing. The purpose of the module is

to introduce the students to modern semiconductor integrated circuit (IC) testmethods, including design for testability (DfT) and built-in self-test (BIST) for digital

ICs.

Syllabus:


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The increasing complexities and speed of operation of modern digital circuits andsystems is increasing the demand on product testing. The module will concentrate on

IC and SoC designs, with the following key areas covered:- 1. VLSI Testing 2.Product Quality, Yield 3. Fault Modelling & Testability Measures 4. Logic and Fault

Simulation 5. Combinational ATPG 5. Sequential ATPG 6. Design For Test 7. Built-In-Self-Test 8. Systems Testing: - PCB Testing - Boundary Scan - SoC Test and Core

Test - STIL, CTL standardisation

Learning Outcomes:


1. Explain the difference between functional and structural testing, and the role of

fault modelling in structural testing. 2. Calculate Fault Coverage for a given requiredDefect Level. 3. Develop test patterns for the detection of stuck-at-faults (SAFs) in

combinational logic circuits in order to demonstrate the detection of SAFs. 4.Differentiate between different fault simulation techniques and apply them to sample

circuits. 5. Analyse given circuits for Testability and derive quantitive figures for each

circuit node. 6. Apply industry standard ATPG algorithms and industry standard testtechniques to sequential and combinational circuitssample circuits 7. Describe therelevant Test Standards and apply them to IC and SoC designs


1. Appreciate the importance of the role of test in the production of digital circuits

and systems using integrated circuit (IC) technology. 2. Appreciate currents trendsand problems in the field of IC test engineering


None


Of The Students:

Lectures/Labs/Homework Assignments


The lecturer has carried out relevant research, especially as releted to System onChip Test and this work will be incorporated into the course material

Prime Texts:

Grout, I. (2005) Integrated Circuit Test Engineering: Modern Techniques , Springer

Wang, L-T, Wu, C-W and Wen, X (2006) VLSI Test Principles and Architectures ,Morgan Kaufmann

Bushnell, M.L. and V.D. Agrawal (2000) Essentials of Electronic Testing , KluwerAcademic Publishers

Jha, N and S. Gupta (2003) Testing of Digital Systems , Cambridge University Press


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Rajsuman, R. (2000) System-on-a-Chip Design and Test, Artech HouseCrouch, A (1999) Design for Test for Digital ICs and Embedded Core Systems ,

Prentice HallParker, P (2003) The Boundary-Scan Handbook (3rd Edition) , Kluwer Academic

Publishers




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Module Code-Title:

EE6642 - NOISE

Hours Per Week:

Lecture

2

Lab

2

Tutorial

0

Other

0

Private

6

Credits

6

Grading Type:

N


This module will equip the student with a sound understanding of the problemscaused by noise in electrical networks. Both fundamental and man-made noise are

discussed. Techniques to minimise noise are discussed.

Syllabus:

Fundamental Noise: Noise mechanisms in electronic components. Summation ofnoise signals, noise spectral density, noise summation in a band, noise bandwidth for

common ?lters. Ampli?er Noise: Representation of noise in ampli?ers, equivalentinput noise voltage and its equivalent input current and voltage sources. Noise

Figure. Semiconductor Noise: BJT noise model, noise in JFETs and MOSFETs. LowNoise Ampli?ers: Design. Methods of noise and noise ?gure measurement. Man-

Made Noise: European regulations, EMI emissions, EMI susceptability, conducted and


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radiated noise. Noise From PCBs: Track structures: strip line, microstrip and singlesided board. Calculation of capacitive and inductive coupling between tracks as well

as radiation from pcb tracks. Power Line Noise: Noise on power supply lines and itsminimisation. Power supply ?lters for minimisation of conducted noise, both common

and differential mode. Shielding: Effectiveness as function of frequency, shieldthickness, conductivity and permeability. Effectiveness to inductive and radiated ?

elds.

Learning Outcomes:


List the various sources of noise in an electronic system. Analyze the contributions of

various noise sources to the overall noise figure of an electronic system. Design low-noise amplifier systems using BJTs, JFETs and MOSFETs. Design low-noise PCBs.

Design filters to reduce the effects of power-line noise. Analyze the effectiveness ofshielding structures.


Appreciate the regulatory framework governing EM emissions from

electronic/electrical systems.


None


Of The Students:

Lectures/Labs


Prime Texts:

Motchenbacher, C.D. & Fitchen, F.C. (1973) Low-Noise Electronic Design , Wiley


Allen P.E. & Holberg, D.R. (1987) CMOS Analog Circuit Design , Holt, Rinehart &Winston

Laker, K.R. & Sansen, W.M. (1994) Design of Analog Integrated Circuits & Systems ,McGraw-Hill




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1. Module Code - Title: EE6452 - DIGITAL CONTROL


3. Grading Type: N


5. Rationale and Purpose of the ModuleTo study the application of digital computers to control engineering problems.

6. SyllabusBrief review of classical control system techniques covering stability analysis and design

methods for both continuous and sampled data systems including Nyquist, Bode, rootlocus. Design criteria including gain and phase margin, settling and rise time, steady stateand following error. Classical design techniques for, and implementation of, digitalcontrol systems; pole placement using state variable approach, direct design includingdeadbeat control, attenuation of ringing poles and multivariable design. Errormechanisms and sources including the algorithm, sampler, and word length. Issueshaving a signi?cant impact on the practical implementation of digital controllers such asdirect and canonical form for controller realisation, word length choice and processorhardware requirements. Development and testing; software structures; introduction tomodern control techniques such as system identi?cation, robust and optimal control.



Synthesis)The student will be able to: 1. Choose effective control strategies to address a range ofreal-world control problems. 2. Analyse problems to realise appropriate controllers. 3.Decide on appropriate processors and word-lengths for controller implementations. 4.Simulate plant and controller combinations using Matlab and Simulink. 5. Implementappropriate control algorithms on embedded processors.


None



students


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Lectures/Labs


10. Prime TextsForsythe, W. & R.M. Goddwall (1991)Digital Control, Macmillian

11. Other Relevant TextsFrankin, Powell & Worman (1990)Digital Control of Dynamic Systems , Addison-WesleyAstrom & Wittenmark (1990) Computer Controlled Systems, 2nd ed. , Prentice Hall



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1. Module Code - Title: EE6462 - DIGITAL COMMUNICATIONS


3. Grading Type: N

4. Prerequisite Modules: EE6461

5. Rationale and Purpose of the ModuleThis module is intended to provide a comprehensive coverage of digital communicationsystems, the signals and key processing steps are traced from the information sourcethrough the transmitter, channel, receiver and ultimately to the information sink.

6. SyllabusCommunication Theory: Nyquist Criteria, Shannon Sampling Theorem, Intersymbolinterference and Aliasing. Digital Signal Processing for voice and data communicationsystems. Performance criteria, NR and probability of error. Properties of line codes(Bipolar, manchester coding, HDBn, 4B3T etc). Modulation and Demodulation: bit errorperformance, bandwidth ef?eiency and signal to noise ratio. Advanced modulationschemes BMSK, II/4-OQPSK, Trellis Code Modulation. Multiple Access, TDMA,FDMA and CDMA. The Channel: AWGN, Linear Time Invariant (LTI) and Timevarying. Synchronization: Carrier and clock recovery. Adaptive Equalization. Case studyon a Spread Spectrum modem outlining the above principles is presented.



Synthesis)1. Describe the structure and operation of a modern, spread-spectrum modem. 2.Understand and be able to derive the Shannon limits for a channel. 3. Analyse acoding scheme in terms of Shannon efficiency. 4. Describe and analyse theperformance of various coding schemes. 5. Design and implement (in Matlab and Ccode) various coding schemes. 6. Design and implement (in Matlab and C code)carrier and clock recovery schemes.

Affective (Attitudes and Values)None




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9. Research Findings incorporated into the syllabus (If relevant)Guest presentations by current researcher within UL.

10. Prime TextsSklar, B. (2001)Digital Communications: Fundamentals and Applications, 2nd ed. ,Prentice Halla. Bateman (2000)Digital Communications: Design for the Real World, ADDISON-WESLEY

11. Other Relevant TextsCouch, L.W. (1990)Digital and Analog Communications Systems , Macmillian

12. Programme(s) in which this Module is offered

M.Eng. in Computer and Communications SystemsM.Eng. in VLSI Systems


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1. Module Code - Title: EE6472 - ADVANCED TOPIC SEMINARS


3. Grading Type: N


5. Rationale and Purpose of the ModuleThis module allows the participation of industry in the teaching of topics of specialist andcurrent interest as they arise from time to time.

6. Syllabus

This module will address topics of current interest in the VLSI and telecommunicationsindustries as these arise. Suitable topics include, inter alia: Advanced architectures formobile and 3rd generation telecommunications systems; Advanced topics in networking,such as VoIP, QoS, bandwidth provisioning and resource reservation; Radio FrequencyVLSI design; Advances in semiconductor fabrication techniques.



Synthesis)The student will be able to describe and analyse the particular topics presented in the

module. This will include, inter alia, the ability to generate implementations of thevarious subjects discussed.

Affective (Attitudes and Values)The student will gain an appreciation of the wider fields of computer, communicationsand VLSI systems, and will be able to place his/her course in the context of currentstate of the art practice.



studentsLectures/Seminars/Practical labs and demonstrations

9. Research Findings incorporated into the syllabus (If relevant)Current relevant research from faculty and guests will be presented in seminars.


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10. Prime Texts

11. Other Relevant Texts

12. Programme(s) in which this Module is offered

M.Eng. in Computer and Communications SystemsM.Eng. in VLSI Systems

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