vlsi lec 4
TRANSCRIPT
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VLSI DesignVLSI Design
By Dr. Yaseer A. DurraniDept. of Electronics Engineering
University of Engineering & Technology, Taxila
Outline Introduction to Combinational & Sequential
Circuits
De Morgans Law & Boolean Algebra Rules
Static & Dynamic Logic Circuits
Memory Logic Circuits
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Combinational Vs. Sequential Logic Combinational logic circuits
Output depends only on present input Sequential logic circuits
Output depends on present input and present state of circuit
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Circuit Circuit
Combinational Circuit
Sequential Circuits
State
Output=f(input)
Output=f(Input, Previous Input)
Design Procedure Combinational logic design procedure
Start with the problem statement Determine the number of inputs variables & required number of output variables Derive a truth table that defines the required relationship between I/O Simplify each output function (Karnaugh maps) Draw the logic diagram
Sequential logic design procedure Derive a state/output table from problem specification Minimize number of states in state/output table by eliminating equivalent states Choose a set of state variables. Assi n to each state a uni ue combination from set
4
derived above Create a transition/output table
Choose a flip-flop type & construct its excitation table Using excitation table fill the values for input excitation function columns on
transition/output table Derive the excitation & output equations Draw logic diagram
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De Mogans Law Commutative law of addition for two variables is written as: A+B = B+A
Commutative law of multiplication for two variables is written as: AB = BA
Associative law of addition for 3 variables is written as: A+(B+C) = (A+B)+C
A
B A+B
B
A B+A
A
B AB
B
A B+A
A A A+B
5
Associative law of multiplication for 3 variables is written as: A(BC) = (AB)C
Distributive law is written for 3 variables as follows: A(B+C) = AB + AC
B
C
B(A+B)+C
CB+C
A
B
A(BC)
C
A
B(AB)C
CBC
AB
B
C
A
B+C
A
B
C
A
XX
AB
AC
X=A(B+C) X=AB+AC
Rules of Boolean Algebra
DeMor ans theorems rovide mathematical verification of:
1.6
.5
1.4
00.3
11.2
0.1
=+
=+
=
=
=+
=+
AA
AAA
AA
A
A
AA
BCACABA
BABAA
AABA
AA
AA
AAA
+=++
+=+
=+
=
=
=
))(.(12
.11
.10
.9
0.8
.7
A, B, and C can represent a single variable or a combination of variables
6
Equivalency of NAND & negative-OR gates
Equivalency of NOR & negative-AND gates
ZYXW
ZYX
ZYX
ZYX
++
++
Complement of two or more ANDed variables is equivalent to OR ofcomplements of individual variables
Complement of two or more ORed variables is equivalent to AND ofcomplements of individual variables
YXYX +=
YXYX =+
Exercise
)(
)(
FEDCBA
EFDCBA
DEFABC
DCBA
+++
++
+
++
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Boolean function is a expression formed with binary variables, OR, AND, NOToperators
F=xyz Boolean function can be algebraically expressed from truth table by taking OR all
minterms that produce 1 as output in function
Boolean function can be algebraically expressed from truth table by taking ANDall maxterms that produce 0 as output in function
Boolean Function
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Digital Design Digital design engineers always tries to build circuit using universal gates
(NAND or NOR) as they are easy to fabricate
Rules of obtaining NAND gate implementation of Boolean function Convert all AND gates into NAND gates by using AND-NOT symbol Convert all OR gates into NAND gates by using NOT-OR symbol For every bubble that is not counteracted by another bubble along same line,
insert a NOT gate or complement the literal from its original appearance
Rules of obtaining NOR gate implementation of Boolean function
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- Convert all AND gates into NOR gates by using NOT-AND symbol For every bubble that is not counteracted by another bubble along same line,
insert a NOT gate or complement the literal from its original appearance
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Examples
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Simplification of Boolean Algebra
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Random Logic Random Logic: Circuit design using NAND, NOR & NOT gates (often
called AOI Logic gate represents = AND-OR-Inverter Logic)
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Random logic: Adder
Logic Families Logic families are classified as: Static Logic
Do not use clock signal Slower Easy to design
Dynamic Logic Use clock signal More faster Difficult to design
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Static CMOS Circuit At every point in time (except during switching transients) each gate output is
connected to either VDD or VSS via low-resistive path Outputs of gates assume at all times the value of Boolean function,
implemented by circuit (ignoring, once again, transient effects during switchingperiods)
PUN consists PMOS transistors & PDN consists NMOS transistors PUN & PDN implementations are complimentary to each other
PMOS NMOS Series topology Parallel topology VDD Make a connection from VDD to
F when F(In1, In2,Inn)=1
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VSS
PUN
PDN
In1
In2
In3
F =G
In1In2In3
PUN and PDN are Dual NetworksPUN and PDN are Dual Networks
PMOS Only
NMOS Only
Make a connection from VDD toVSS when F(In1, In2,Inn)=0
No steady state path b/w VDD & VSS (no staticpower consumption)
Delay a function of load capacitance &transistor resistance
Comparable rise & fall times (underappropriate transistor sizing conditions)
High noise margins Full rail to rail swing VOH & VOL are at VDD & VSS Low output impedance, high input impedance
Design Method NMOS devices pull the output to 0 when the gate inputs are 1
PMOS devices pull the output to 1 when the gate inputs are 0
Consider a function to be realized: F(A,B,C, . . .)
NMOS pull-down network must realize the pull-down function
FPD = F(A,B,C,)
PMOS pull-up network must realize the pull-up function
FPU = F(A,B,C) The literals in FPU have to be inverted, because the p-channel transistors
conduct, if their gate input is 0 (low)
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Rules for Logic Formation Rule 1: NMOS transistors in series implement the AND operation Rule 2: NMOS transistors in parallel implement the OR operation Rule 3: Logic functions in series are ANDed together
Rule 4: Parallel nMOS branches OR the individual branch functions Rule 5: Parallel connections of NMOS transistors have to be transformed to
serial connections of PMOS transistors. The input literals applied to the PMOStransistors are identical with the gate inputs of the NMOS transistors (noinversion needed)
Rule 6: Serial connections of NMOS transistors have to be transformed to.
Rule 7: Parallel connected logic blocks of the NMOS network Serial connection in the PMOS network
Rule 8: Serial connected logic blocks of the NMOS network Parallel connection in the PMOS network
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PUN/PDN Rules NMOS is ON when Vg=1, OFF when Vg=0. For PMOS vice versa NMOS produces strong Zeros while PMOS produces strong Ones NMOS connected in Series corresponds to AND function while in Parallel OR
function. PMOS connected in Series corresponds to NOR function & Parallel toNAND function
Using De Morgans Theorem usingPUN/PDN of complementary CMOS structure are dual network. This meansParallel connection in PUN corresponds to Series connection in PDN & vice
( )BABA =+)( BABA +=
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Complementary gates is naturally inverting, implementing only functions such asNAND, NOR and XNOR. Noninverting Boolean function such as AND, OR, XORin a single stage is not possible & requires addition of an extra inverter stage
Number of transistors required to implement an N-input logic gate is 2N
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NMOS/PMOS Serial/Parallel Connection Transistors can be thought as a switch controlled by its gate signal NMOS switch closes when switch control input is high PMOS switch closes when switch control input is low
NMOS: 1 = ON, PMOS: 0 = ON Series: both must be ON, Parallel: either can be ON
X Y
A B
X Y
A B
A C A C
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Y = X if A and B
NMOS Serial Connection
X Y
A
B
Y = X if A OR B
NMOS Transistors pass astrong 0 but a weak 1
NMOS Parallel Connection
Y = X if A AND B = A + B
PMOS Serial Connection
X YB
Y = X if A OR B = AB
PMOS Transistors pass astrong 1 but a weak 0
PMOS Parallel Connection
B D
A
B
C
D
A B C DA B
C D
B
D
Y
A
C
A
C
B D
B
D
Y
Construction of PDN NMOS devices in series implements NAND function NMOS devices in parallel implements NOR function
A
B
A B
A B
A + B
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CMOS Inverter
A Y
0
1 0
V DD
A= 1 Y= 0
GND
ON
OFF
A YA Y
0 1
1 0
V DD
A= 0 Y= 1
OFF
ON
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GND
CMOS NAND Gate
A B F
0 0 1
0 1 11 0 1
BAC =
20
1 1 0
A
B
Y
C
3 input NAND gate 4 input NAND gate
In3
In1
In2
In4
In1
In2 In3 In4
VDD
Out
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CMOS NOR Gate
BAC +=
A B C
0 0 1
A
B
C
D
Y
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1 0 0
1 1 0
4 input NOR gate
2 input NOR gate
AND/OR Gate
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BAC +=
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XOR Gate
A B C
0 0 0
0 1 1
1 0 1
A
B
A
A
B
B
A
B
A A
A
B
BABAY +=
BAABY +=
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1 1 0
A B
A
B
A
BA B
A B
BB
XNOR Gate
A B C
0 0 1
0 1 0
A
B
A
B
A B
A
B
A A
A
B
BB
BABAY +=
BAABY +=
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A B
A
B
A
BA B
1 0 0
1 1 1
A B
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Complex NMOS Logic
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2-input NMOS NOR gate
N-input NMOS NOR gate
2-input NMOS NAND gate
Complex NMOS Logic
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XOR gateXNOR gate
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Relatively it is easy to obtain PDN, simply because we already had Y in terms ofuncomplemeted inputs
To obtain PUN, we had to manipulate the given Boolean expression to express
Y as a function of complemented variables
)( CDBAY +=
)( CDBAY +=
Complex Gate
)(
CDBA
CDBAY
++=
+=
)( DCBA ++=
+=
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Systematic Function ConstructionF= A ( B C + D)
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F=AB+(A+B)C
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Examples
BCAF +=
BCAF +=
BCAF
BCAF
=
+=
)C(ABDAF ++=
Start from innermost term
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BC)A(F +=
Examples))C(ABDA()D(EF +++=
Start from the innermost term
VDD
A
B
C
D
F = D +A (B+C)
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D
A
B C
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Examples( )Y A B C D= + +
Y
DC
B
A
VDD
C
( )( )
( )( )( )( )( )( ) DCBAY
DCBAY
DCBAY
DCBAY
+=
++=
+=
++=
( )( ) DCBAY ++= F = (D + A (B + C))
D
A
B
C
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A B C
D
Y
A
A
B
B
C
D
D
D
A
B C
Full Adder
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AOI (AND-OR-INVERT) CMOS Gate AOI complex CMOS gate can be used to directly implement a sum-of-products
Boolean function Pull-down N-tree can be implemented as follows:
Product terms yield series-connected NMOS transistors Sums are denoted by parallel-connected legs
Complete function must be an inverted representation
Pull-up P-tree is derived as the dual of the N-tree
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OAI (OR-AND-INVERT) CMOS Gate An Or-And-Invert (OAI) CMOS gate is similar to the AOI gate except that it is an
implementation of product-of-sums realization of a function N-tree is implemented as follows:
Each product term is a set of parallel transistors for each input in the term All product terms (parallel groups) are put in series The complete function is again assumed to be an inverted representation
P-tree can be implemented as the dual of N-tree Note: AO & OA gates (non-inverted function representation) can be
implemented directly on the P-tree if inverted inputs are available
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Full AdderV
VDD
DD
VDD
VDD
A B
Ci
S
X
B
A
Ci A
BBA
Ci
A B Ci
Ci
A
Ci
A
B
BA
28 transistors
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Co B
C o = AB + C i (A+B)
VDD
Ci
A
BBA
B
A
A B
Kill
Generate"1"-Propagate
"0"-Propagate
V DD
Ci
A B Ci
Ci
B
A
Ci
A
BBA
V DD
SCo
24 transistors
Transistor Sizing Transistor sizing is the ratios of the Width/Length (W/L) of the transistor
These ratios provide the gate with current-driving capability in both directionsequal to that of the basic inverter
(W/L)=n and (W/L)p=P, n is usually 1.5 to 2 & for matched design p=(n/p)n
We should find the input combinations that result in lowest output current & thenchoose sizes that will make this current equal to that of the basic inverter
We consider the parallel/series connections & find equivalent W/L ratios
Transistors connected in series:
Transistors connected in parallel:
...)/(
1
)/(
1)/(
21
++
=
LWLW
LW eq
...)/()/()/( 21 ++= LWLWLW eq
VDD
GND
NMOS (2/.24 = 8/1)
PMOS (4/.24 = 16/1)
metal2
metal1 polysilicon
InOutmetal1-poly via
metal2-metal1 via
metal1-diff via
pdiff
ndiff
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Example Two identical MOS transistors with individual W/L ratios of 4 result in an
equivalent W/L of 2 when connected in series & of 8 when connected in parallel Worst case (lowest current) for PDN is obtained when only one of NMOS
transistors is conducting We therefore select W/L of each NMOS transistor to be equal to that of NMOS
transistor of basic inverter, namely, n For PUN, worst-case situation is when all inputs are low & four series PMOS
transistors are conducting Since equivalent W/K will be one-quarter of that of each PMOS device, we
P
basic inverter, that is ,4p
37n& pdenote the (W/L) ratios of QN&QP, of the basic inverter
Example Provide transistor W/L ratios for the logic circuit . Assume that for the basic
inverter n = 1.5 and p =5 and that the channel length is 0.25m? Solution: Consider PDN: In worst case, when QNB is ONB & either QNC or QND is ON Worst case, we have two transistors in series Therefore, we select each of QNB, QNC, and QND to have twice the width of the n-
channel device in the basic inverter, thus Q
NB
: W/L = 2n = 3 =0.75/0.25 QNC: W/L = 2n = 3 =0.75/0.25
ND . .
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Example For transistor QNA, select W/L to be equal to that of the n-channel device in the
basic inverter: QNA: W/L = n = 1.5 = 0.375/0.25
Next, consider the PUN Here, we see that in the worst case, we have three transistors in series: QPA,
QPC, and QPD. Therefore, we select the W/L ratios of each of these to be three times that of
QP in the basic inverter, that is, 3p, thus QPA: W/L = 3p = 15 =3.75/0.25
PC = = = . . QPD: W/L = 3p = 15 =3.75/0.25
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CMOS Transmission Gates (TG) CMOS TG can be constructed by parallel combination of NMOS & PMOS
transistors, with complementary gate signals TG input signal transmitted to output without threshold voltage attenuation
C
A B
C
BA
CB
C=0, CB=1
A B
C=1, CB=0A
0 Strong 0
Input Output
C=1, CB=0
C=1, CB=0
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C
BA
C
C
0V Vdd 0V
0V
|VTP|
Vdd
Vdd 0V Vdd
Vdd-VTN
Vdd
Vdd
A
B
F
B
A
B
B
M1
M2
M3/ M4
XOR
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CMOS Transmission Gate
B
B
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A
F
B
A
B
M1
M2
M3/M4
A
A
B
B
BABA +
XOR
Half Adder
TG based Full Adder
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Full Adder
A
B
P
Ci
VDD A
A A
VDD
Ci
A
P
AB
VDD
VDD
Ci
Ci
Co
S
Ci
P
P
P
P
P
Sum Generation
Carry Generation
Setup
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S
S
D0
D1
YS
2x1 MUXOnly 4 transistors
Multiplexers (MUX)
2x1 MUX
S
S
A
B
SBAS+
S0
A
B
C
S0 S1 S1
OUT
43
AM 2
M 1
B
S
S
S F
V DD
Pass Transistor based MUX4x1 Multiplexor
D
Two Level MUX
TG Tristates Tristate buffer produces Z when not enabled Non-restoring Tristate
TG acts as tristate buffer Only two transistors
But nonrestoring Noise on A is passed on to Y
EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1
A Y
EN
A Y
EN
EN
A Y
EN
EN
Tristate inverter produces restored output
Violates conduction complement rule
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A
Y
EN
A
Y
EN = 0
Y = 'Z'
Y
EN = 1
Y = A
A
EN
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Multiplexers (MUX) 2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 1
0
1
S
D0
D1
Y
Gate level MUX Desi n
45
01 DSSDY +=
4
4
D1
D0
SY
4
2
2
2 Y
2
D1
D0
S
20 transistors
Inverting MUX Use compound AOI Or pair of tristate inverters Essentially the same thing
Noninverting MUX adds an inverter
S
D0 D1
Y
S
D0
D1
Y
0
1S
Y
D0
D1
S
S
S
S
S
S
InvertingMUX
Multiplexers (MUX)
46
c ooses one o npu s us ng wo se ec s Two levels of 2:1 MUXes Or four tristates
S0
D0
D1
0
1
0
1
0
1Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0 S1S0 S1S0 S1S0
4x1 MUX
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Fast Complex Gate - Design Techniques Design techniques to reduce delay of large fan-in circuits Transistor Sizing Increase transistor size, while larger parasitic capacitances & propagation delay
Progressive Transistor Sizing Uniform sizing, reduces the dominant resistance
Input Reordering Some signals might critical than others. Not all inputs of a gate arrive at
same time Logic Restructuring
Mani ulatin lo ic e uations can reduce fan-in & reduce ate dela
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CL
In1
InN
In3
In2
Out
C1
C2
C3
M1 > M 2 > M3 > MN
M1
M2
M3
MN
Distributed RC-line
Can Reduce Delay with more than 30%!
In1
In3
In2
C1
C2
CL
M1
M2
M3
In3
In1
In2
C3
C2
CL
M3
M2
M1
critical pathcritical path
Buffering: Isolate Fan-in from Fan-out
CL CL
Improved Logic Design
Input reording
Fan-In & Fan-Out Fan-In = Number of inputs to a logic gate
4 input NAND has a FI = 4 2 input NOR has a FI = 2, etc.
Fan-Out = Number of gate inputs which are driven by a particular gate output FO = 4 in Fig. b below shows an output wire feeding an input on four
different logic gates Circuit delay of a gate is a function of both Fan-In & Fan-Out
Ex. m-input NAND: tdr
= (Rp
/n)(m.n.Cd
+ Cr
+ k.Cg
) = tinternal-r
+ k.toutput-rwhere n=width multiplier, m=fan-in, k=fan-out, Rp=resistance of min inverter P
, , ,capacitance
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Fan-In & Fan-Out Circuit fall delay can be written in a similar manner
Ex. m-input NAND: tdf = m(Rn/n)(m.n.Cd + Cr + k.Cg) = tinternal-f + k.toutput-fwhere n=width multiplier, m=fan-in, k=fan-out, Rn=resistance of min inverter
NMOS Tx, Cg=gate capacitance, Cd = source/drain capac, Cr = routing (wiring)capacitanceIf we set tdr=tdf for the case of symmetrical rise & fall delay, we get Rp = m Rn
pWp = (nWn)/m
49
CMOS Logic Families Complementary Logic
Standard CMOS Clocked CMOS (C2MOS) BICMOS (CMOS logic with Bipolar driver)
Ratio Circuit Logic Pseudo-NMOS Saturated NMOS Load Saturated PMOS Load Depletion NMOS Load (E/D) - -
Dynamic Logic: CMOS Domino Logic NP Domino Logic (also called Zipper CMOS) NORA Logic Cascade voltage Switch Logic (CVSL) Sample-Set Differential Logic (SSDL) Pass-Transistor Logic
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Clock Signal Used to synchronize data flow through a digital network
Clocked static or dynamic circuits Problems: clock skew (delay caused by clock distribution wires)
51
Ideal nonoverlapping 2-phase clocks 2-phase clocking
Single & Multiple Clock Signals For nonoverlapping clock phases and fine tuned and well designed delay
lines (realized as Transmission gates) have to be inserted in order to avoidoverlapping of and
Generation ofinverted clock phase TG delay circuit
52Psuedo 2- clocking
Clocked shift register circuitShift register
Clocked Static Logic
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Dynamic CMOS Circuits Dynamic logic is temporary (transient) in that output levels will remain valid
only for a certain period of time Static logic retains its output level as long as power is applied
Dynamic logic is due to charging & discharging capacitance Precharge clock to charge the capacitance Evaluate clock to discharge the capacitance depending on condition of
logic inputs
Precharge Evaluate Precharge
1
2A Y
1
1
A
Y
4/3
2/3
AY
53
Y
Dynamic NMOS Inverter Dynamic PMOS Inverter
Mp
Me
VDD
PDN
f
In1In2In3
Out
Me
Mp
VDD
PUN
f
In1In2In3
f
f
Out
CL
CL
f p networkfnnetwork
Static DynamicPseudo-NMOS
Dynamic CMOS Circuits Advantages over static logic:
Use of low leakage of FETs to store charge instead of moving current.Provides higher density, faster operation at cost of reduced noise immunity
Avoids duplicating logic twice as both N-tree & P-tree Faster gates & used in very high performance applications
Best for wide OR/NOR gates (e.g. bit-lines), providing 50% delayimprovement over static CMOS
Simple sequential memory circuits; amenable to synchronous logic
Transistor count is reduced from 2n (static CMOS) to n+2 for dynamicrechar ed CMOS but now: 2 hases of o eration
54
High density achievable Consumes less power (in some cases)
Consumes 2xpower due to its phase activity (unconditional pre-charging), not counting clock power
Disadvantages compared to static logic: Problems with clock synchronization & timing Design is more difficult
Increased sensitivity to noise Capacitive crosstalk, Charge sharing, Power supply, Feed through noise
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Single clock is to accomplish both pre-charge & evaluation operations When is low: PMOS pre-charge transistor Mp charges Vout to Vdd, since it
remains in its linear region during final pre-charge
During this time, logic inputs A1 B2 are active & Me is OFF, no chargewill be lost from Vout
When is high: Mp is turned OFF & NMOS evaluate transistor Me is turned ON,allowing for Vout to be selectively discharged to GND depending on logic inputs If A1 B2 inputs are such that a conducting path exists b/w Vout & Me,
then Vout will discharge to 0, Otherwise, Vout remains at Vdd No DC current flows durin rechar e or evaluate hase
Dynamic CMOS Circuits
Power is dynamic P = CN Vdd2 f where CN represents an equivalent total
capacitance on the output, f=clock frequency,=logic repetition rate
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Dynamic Logic
56
Dynamic NMOS inverterPrecharge & Evaluate
Precharge n/w for worse case
Evaluation discharge n/wComplex Dynamic Logic
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Cascading Problem in Dynamic CMOS Logic If several stages of dynamic circuit are cascaded together using same clock, a
problem in evaluation involving a built-in race condition will exist
Duringpre-charge, both Vout1 & Vout2 are pre-charged to Vdd
When goes high to beginevaluate, all inputs at stage-1 require some time toresolve, but during this time charge may erroneously be discharged from Vout2
Assume 1st-stage NMOS logic conducts & fully discharges Vout1, but allinputs are not resolved, it takes some time to discharge Vout1 to GND
If, during this time delay, 2nd-stage has input condition shown with bottomNMOS transistor gate at logic 1, then Vout2 will start to fall & discharge itsCL until Vout1 finall evaluates & turns OFF the to series NMOS transistorin stage-2
Result is an error in output of 2nd-stage Vout2
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Possible Solutions: Two phase clocks
Use of inverters to createDomino Logic
NP Domino Logic Zipper/NORA logic
Dynamic Cascades PMOS & NMOS blocks have to be installed alternated in order to avoid glitches
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Cascaded NMOS-NMOS glitch problemDynamic cascades
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Pass Transistor Logic Transistor are used as switches which are controlled by input literals do logic Inputs drive diffusion terminals as well as gates Limited fan-in & excessive fan-out
Noise vulnerability (not restoring) Supply voltage offset/bias vulnerability Decode exclusivity (else short-circuit!) Poor high voltage levels if NMOS-only Pass-logic may consume half the power of static logic. But be careful of Vt drop
resulting in static leakage Pass- ate lo ic is not a ro riate when lon interconnects se arate lo ic sta es
Pass Transistor Model
or when circuits have high fan-out load (use buffering)
59Complementary switchPass Transistor NXOR
A =5 VB
C =5V
CL
A =5 V
C =5 V
BM2
M1
Mn
VB
NMOS only switchDoes not pull up to 5V, but 5V Vth loss causes static power consumption
VTN
Pass Transistor Logic Criteria for Clocked CMOS & Pass-Gate Logic Clocked CMOS logic
Mitigates hot electron effects Pass-gate logic
Fast, if few pass gates in series Good for complex functions Small area, low power
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Clocked CMOS logic
Mitigates hot electron effects Pass-gate logic
Fast, if few pass gates in series
Good for complex functions
,
Pass Transistor Circuits Pass transistor (MP) is NMOS device, but could also be implemented with TG
Cx is equivalent capacitance of input gate of second NMOS (part of inverteror logic gate) & PN junction capacitance of MPs drain (source)
When clock (CK ) goes high, MP is turned ON & allows Vin to be placed oncapacitor Cx
When CK goes low, MP is turned OFF, trapping charge on Cx Operation for 1 or 0:
If Vin is high (say VOH), then MP will allow current to flow into Cx, charging it
up to Vdd Vtn (assume CK up level Vdd) If Vin is low sa GND then MP will allow current to flow out of Cx
discharging it to GND Due to leakage from drain (source) of MP, Cx can only retain charge Q for a
given period of time (called soft node) If MP is NMOS, Cx will discharge to GND If MP is PMOS, Cx will discharge to VDD If MP is a TG, Cx could discharge in either direction
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Pass Transistor Logic with PMOS Pull-Up For reduction of device count and area an NMOS version with PMOS pull-up
can also be useful (kind of pseudo NMOS)
63
Pass Transistors
Vdd-VTN Vdd-VTNVdd-VTN
Vdd-2VTN
Vdd-3VTN
NMOS Pass GateConfiguration
64
|VTP| |VTP|
|VTP|
2|VTP|
3|VTP|PMOS Pass GateConfiguration
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Complexity of CMOS pass-gate logic can be reduced by dropping PMOStransistors & using only NMOS pass transistors called CPL CMOS inverters must be used periodically to recover the full VDD level since NMOS
pass transistors will provide VOH of VDD
VTn in some cases CPL circuit requires complementary inputs & generates complementary outputsto pass on to next CPL stage
Complimentary Pass Transistor Logic (CPL)
FPass-Transistor
Network
A
ABB
B B
A
A =
FPass-Transistor
Network
A
ABB
Inverse
B
S
S
S
S
A
B
A
Y
YL
L
A
A F=A
65
Boolean Function CPL Pass-transistor logic used to design NOR, XOR, NAND, AND & OR gates
depending upon P1-P4 inputs: P1,P2,P3,P4 = 0,0,0,1 gives F(A,B) = NOR P1,P2,P3,P4 = 0,1,1,0 gives F(A,B) = XOR
P1,P2,P3,P4 = 0,1,1,1 gives F(A,B) = NAND P1,P2,P3,P4 = 1,0,0,0 gives F(A,B) = AND P1,P2,P3,P4 = 1,1,1,0 gives F(A,B) = OR
Circuit can be operated with clocked P pull-up device or inverter-based latch Output inverter provides F(A,B) and can be used to latch node F high (-F low)
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Mixing Domino Logic with Static Logic We can add even number of static inverting logic gates after Domino logic stage
prior to next Domino logic stage
Even number of inverting stages guarantees that inputs to second Domino
logic stage experience only 0-to-1 transitions In cascaded Domino logic structure, evaluation of each stage ripples through
cascaded stages similar to a chain of Dominos
Evaluate cycle must be sufficient duration to allow all cascaded logic stages(between latches) to complete their evaluation process within clockevaluation interval
71
NP Domino/NORA Logic In dynamic logic erroneous evaluation problem is to use NP Domino
Logic/NORA logic Alternate stages of N logic with stages of P logic:
N logic stages use true clock, normal pre-charge & evaluation phases, withN logic tree in the pull down leg
P logic stages use a complement clock, with P logic stage tied above theoutput node
During pre-charge clk is low (-clk is high) & P-logic output pre-charges to
ground while N-logic outputs pre-charge to Vdd Durin evaluate clk is hi h -clk is low and both t e sta es o throu h
evaluation; N-logic tree logically evaluates to ground while P-logic treelogically evaluates to Vdd
Inverter outputs can be used to feed other N-blocks from N-blocks, or to feedother P-blocks from P-blocks
72
Mp
Me
VDD
PDN
In1In2In3
Me
Mp
VDD
PUN
In4
Out1
Out2
Only 10 transitions allowed at inputs of PUN
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NP-CMOS Logic
VDD
B1
A1
VDD
A1 B1
Ci2
VDD
B1 Ci1
B1
A1A1
VDD
S1
Ci1
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VDD
Ci0
A0 B0 B0
A0 Ci1
Ci0Ci0
B0
A0B0
S0
A0
VDD
VDD
Carry PathNP CMOS AdderNP CMOS Adder
NORA Logic NO Raace:
Signal race can arise, when both TG conduct at same time. If new inputfrom TG1 reaches the input of TG2 while TG2 is still transmitting theoutput, output information will be lost. Imperfect TG synchronization occursbecause of normal transition intervals or clock skew
NORA is very insensitive to clock delay One clock signal & inverted clock signal with short slopes rise times are
sufficient No inverter is needed b/w logic stages due to use of n-& p-type blocks Last stage is a clocked inverter, a C2MOS latch
74Race Problem
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Pipelined NORA Logic With pipelined NORA CMOS logic design
One can alternate N and P stages betweenC2MOS latches where high is used for
evaluation as shown in (a) Or, one can alternate N and P stages similarly
between C2MOS latches with high used forevaluation as in (b)
sections may be alternately cascaded with sections as shown in (c)
,each stage in succession up to next C2MOS latch
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NORA Logic During low ( high), each stage pre-charges
N logic stages pre-charge to Vdd; P logic stages pre-charge to GND When goes high ( low), each stage enters the evaluation phase
N logic evaluates to GND; P logic stages evaluate to Vdd All NMOS & PMOS stages evaluate one after another in succession, as in
Domino logic Logic below:
Stage 1 is X = (A B) Stage 2 is G = X + Y
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Single-Phase NP Dynamic Logic Structures Combines NP Domino logic sections with C2MOS latch
n-logic block can drive p-logic block or another n-logic block with a static inverter Similarly for a p-logic block
Must end in a C2
MOS latch Clk logic: (a) prechrg on clk=0, eval clk=1 -Clk logic: (b) pre on clk=1, eval on clk=0 Clk logic can feed clk logic & vice-versa Can mix static logic with NP domino logic Rules to avoid race conditions:
During precharge, logic blocks are OFF
During eval, internal inputs make only one transition
Pipeline design: Even # of inversions between C2MOS, or at least 1 dynamic stage and even # inversions prior to it
77
f
inputs
Y
2/3 2/3
Pseudo-NMOS Logic Consists of a single PMOS load per gate & NMOS PDN It is a ratio circuit where DC current flows when N PDN is conducting Must design the ratio of N devices W/L to P load device W/L so that when N pull
down leg with max resistance is conducting, output is at a sufficiently low VOL Needs ratioed devices Dissipates static power, when PDN is ON Provides a method of emulating NMOS circuits in CMOS Reduced noise margin
VDD
A B C D
F
CL
Inverter NAND2NOR2
4/3
2/3
A
Y
8/3
8/3
B
AA B 4/34/3
Y
78
r er a or sue o og c Fully-complementary CMOS logic
Immune to noise Virtually zero static power Many stages required for high fan-in functions
Pseudo nMOS logic Good for high fan-in Nor function
ROM PLA Adder carry look-ahead
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Zipper Dynamic Logic Zipper CMOS logic is for improving charge leakage & charge sharing problems Pre-charge transistors receive a slightly modified clock where clock pulse
(during pre-charge off time) holds the pre-charge transistor at weak conduction
in order to provide a trickle pre-charge current during the evaluation phase PMOS pre-charge transistor gates are held at Vdd - |Vtp| NMOS pre-charge transistor gates are held at Vtn above GND
79
Source-Follower Pull-up Logic (SFPL) SFPL is a variation on pseudo-NMOS whereby load device is an N pull-down
transistor & N source-follower pull-ups are used on inputs N pull-up transistors can be small limiting input capacitance N transistors are also duplicated as pull-down devices in order to improve
fall time Rise time is determined by P1 inverter pull-up transistor when all low inputs
SFPL is useful for high fan-in NOR logic gates
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Ratioed Logic
VDD
VDD
VDD
Ratioed logic is an attempt to reduce number of transistors required toimplement a given function, often at cost reduced robustness & extra powerdissipation
Purpose of PUN is to provide conditional path b/w Vdd & output when PDN isOFF. In ratioed logic, entire PUN is replaced with load device that pulls up theoutput for high output
Psuedo NMOS gate reduced number of transistors (N+1) Vs. N
81
VSS
PDN
In1
In 2In
3
F
RLLoad
VSS
In1
In 2In
3
F
VSS
PDN
In1
In 2In
3
F
VSS
PDN
Resistive Depletion
Load
PMOS
Load
(a) resistive load (b) depletion load NMOS (c) pseudo-NMOS
VT
< 0
Goal: to reduce the number of devices over complementary CMOS
Differential Cascode Voltage Switch Logic(DCVSL)
VDD
Out
VDD
Out
M1 M2
Out
Out
82
VSS
PDN1
VSS
PDN2
A
AB
B
Even Better Noise Immunity/Density
A A
XOR-NXOR gate
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CMOS Circuit Styles - Summary
83
On-Chip Internal VDD Generator CMOS and Pseudo-NMOS circuitry often require an internally-generated Vdd
supply voltage or a bias voltage (above Vss) for on-chip use Requirements:
track supply voltages Vdd and Vss temperature compensation highly regulated de-coupled from power supply noise with use of on-chip capacitance
Circuit below utilizes a reference voltage generator comprised of series-connected saturated P devices feeding a current mirror to obtain Internal VDD 0
0 -> 1
1 -> 1
But not 1 -> 0 AX
Y
Precharge Evaluate
X
Precharge
A = 1
Y
A
Monotonicity Woes
86
Precharge Evaluate
Y
Precharge
A
Output should rise but does not
violates monotonicityduring evaluation
But dynamic gates produce monotonically falling outputs during evaluation
Illegal for one dynamic gate to drive another!
AX
Y
PrechargeEvaluate
X
Precharge
A = 1
Y should rise but cannot
Y
X monotonically falls during evaluation
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Leakage & Charge Sharing Dynamic node floats high during evaluation
Transistors are leaky (IOFF 0)
Dynamic value will leak away over time Formerly miliseconds, now nanoseconds!
Use keeper to hold dynamic node
Must be weak enough not to fight evaluation
A
H
2
2
1 k XY
weak keeper
87
Dynamic gates suffer from charge sharing
B = 0
A
Y
x
Cx
CYA
x
Y
Charge sharing noise
Yx Y DD
x Y
CV V VC C
= =+
Secondary Precharge Solution: add secondary precharge transistors
Typically need to precharge every other node
Big load capacitance CY helps as well
Y
secondaryprechargetransistor
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B
x
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Principle of CMOS MemoryLD=1 QD Q DLD=0 store current state
89
Dynamic Flip0Flops:Pseudo 2-Phase Clocking
90
Clock skew
Slow Clock Edges
Pseudo 2-Phase LatchCharge distribution problem in (b)
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Reduced Transistor Count Latch
With high impedance sustainer transistors
91
Dynamic D-Latches
Dynamic D-Latches
92
Pseudo 2-Phase dynamic logic
Pseudo 2-Phase domino logic
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2-Phase Memory
93
2-Phase Static D flip-flops
2-Phase Static D flip-flops
Static Memory
Static D flip-flop with set and reset
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Latch These sequential devices differ in way their outputs are changed:
Output of a latch changes independent of a clocking signal
Output of flipflop changes at specific times determined by clocking signal
SR Latch based on NOR gate S input sets Q output to 1 while R reset it to 0
When R=S=0 then output keeps previous value
When R=S=1 then Q=Q=0, and the latch maygo to an unpredictable next state
95
S input sets Q output to 1 while R reset it to 0
When R=S=1 then output keeps previousvalue
When R=S=1 then Q=Q=1, & latch may go toan unpredictable next state
D latch
This latch eliminates the problem that occurs in SRlatch when R=S=0
C is an enable input:
When C=1 then output follows the input D &latch is said to be open
When C=0 then output retains its last value &latch is said to be closed
Flip Flop D flip-flop is made out of two D latches. First latch is master, & second slave
When Ck = 0, master is open & slave is closed. Qm & Ds follow Dm When Ck = 1 master is closed, slave is open & Qm is transferred to Qs Note: Qs does not change because master latch is closed leaving Qm fixed
96
J-K flip-flop is similar to S-R flip-flop. Difference arises when J & K are assertedsimultaneously. In this situation output of J-K flip-flop inverts its current state
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Flip-Flop T flip-flop
When input T = 0, output Q retain its previous value
When input T = 1, output Q inverts on every tick of clock
When inputs J & K of a J-K flip-flop are connected together, J-K flip-flop willbehave like a T flip-flop
97
Flip-flops/Latches Flip-flops occupy a special place in conventional digital design
Always Dynamic Behavior
Allow time coherence across large parts of the circuit
Preserve data across synchronization boundaries
Inherently asynchronous design
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D Latch When CLK = 1, latch is transparent
D flows through to Q like a buffer When CLK = 0, the latch is opaque
Q holds its old value independent of D Transparent latch or level-sensitive latch
CLK
D Qtch D
CLK
CLK = 1
D Q
Q
D Q
Q
99
L Q
Multiplexer chooses D or old Q
1
0
D
CLK
QCLK
CLKCLK
CLK
DQ Q
Q
D Latch Operation
Advanced Latches
100
Tri-state based static Latch
Modified Svensson Latch 21064
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D Flip-flop Design When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop,
master-slaveflip-flop
Flop
CLK
D Q D
CLK
Q
CLK = 1
D
CLK = 0
Q
D
QM
QMQ
101
QM
CLK
CLKCLK
CLK
Q
CLK
CLK
CLK
CLK
D
Latch
Latch
D QQM
CLK
CLK
Built from master and slave D latches
D
CLK
Q
D-F/F Operation
Sense Amplifier-Based Flip-Flop
! "#$% & % %"'"" (!
102
Driver transistors are large
Keeper transistors are small
& disengaged during transitions
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Asymmetric Read/Write Ports
103
Multi porting
Dynamic Latches with a Single Clock Dynamic latches eliminate dc feedback leg by storing data on gate capacitance
of inverter (or logic gate) and switching charge in or out with a transmissiongate Minimum frequency operation is 50-100 KHz, not to lose data due to junction or gate
leakage from the node
Can be clocked at high frequency since very little delay in latch elements
Examples: (a) or (b) show simple transmission gate latch concept
(c ) tri-state inverter dynamic latch holds data on gate when clk is high (d) and (e) dynamic D register
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Dynamic Registers with two Phase Clocks Dynamic register with pass gates & two phase
clocking is shown
Clocks phi1 and phi2 are non-overlapping
When phi1 is high & phi2 is zero,
1st pass gate closed & D data chargesgate capacitance C1 of 1st inverter
2nd pass gate is open trapping priorcharge on C2
en p s ow an p s g ,
1st pass gate opens trapping D data onC1
2nd pass gate closes allowing C2 tocharge with inverted D data
If clock skew or sloppy rise/fall time clockbuffers cause overlap of phi1 and phi2 clocks,
Both pass gates can be closed at the sametime causing mixing of old and new dataand therefore loss of data integrity!
105
Two Phase Dynamic Registers (Compact Form) Compact implementation of of two phase
dynamic registers using a tri-state buffer form
Transmission gate & inverter integratedinto one circuit
Two versions:
Pass devices closest to output
Inverter devices closest to output
wo p ase ynam c reg s ers og c s o enpreferred over single phase because:
Due to finite rise/fall times, CLK & CLK arenot truly non-overlapping
Clock skew often is a problem due to CLKis usually generated from CLK using aninverter circuit & also due to practicalproblem of distributing clock lines withoutany skew
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Dynamic Shift Registers with Enhancement Load Dynamic shift register implemented with a
technique named ratioed dynamic logic. 1 and 2 are non-overlapping clocks
When 1 is high, Cin1 charges to Vdd Vt if Vinis high or to GND if Vin is low
When 1 drops and 2 comes up, the input datais trapped on Cin1 and yields a logic output onCout1 which is transferred to Cin2
When 2 drops and 1 comes up again, the logicoutput on Cout1 is trapped on Cin2, which yieldsa lo ic out ut on Cout2 which is transferred toCin3, etc.
To avoid losing too much voltage on the logic highlevel, Coutn >> Cinn+1 is desired
Each inverter must be ratioed to achieve adesired VOL (e.g. when 2 is high on 1
st inv)
Dynamic shift register is a ratioless dynamiclogic circuit When 2 is high transferring data to stage 2, 1
has already turned off the stage 1 load transistor,allowing a VOL = 0 to be obtained without a ratiocondition between load and driver transistors.
107