VLSI Digital System Design

1.Carry-Save,2.Pass-Gate,

3.Carry-Lookahead, and4.Manchester Adders

CS Adder Nomenclature

● Carry -Save Adder (CSA)● Carry -Select Adder● Carry -Skip Adder● Conditional -Sum Adder

Ripple-Carry Add Review

● Critical path:

b1

a1

b0

a0

b3

a3

b2

a2 s

2

s1

s0

s3

carry in

carry out

FA

FA

FA

FACritical path

Critical path

Carry-Save Add

● Sum in redundant form

b1

a1

c1

a0

b3

a3

b2

a2 s

2

s1

s0

s3

FA

FA

FA

FAb

0

c2

c3

c1

c0

c2

c3

c0

Critical pathCritical path

Carry-Save Add

● Reduce 3 binary numbers to 2● Also called 3:2 compressor

– Examples of other compressors: 4:2, 7:1● Can create tree of CSAs to reduce arbitrary

number of binary numbers– For example, to sum partial products

● Can compute final, nonredundant sum using carry-propagate adder

● Serial adder is special case of CSA

Pass-Gate Exclusive-Or Gate

● When a = 1, a ^ b = ~b, through b's inverter● When a = 0, a ^ b = b, through pass gate● Can also create Xnor gate

– Swap a and ~a to b's inverter and pass gate● 6 transistors. Circuit:

a

a ^ b

b

~a

Pass-Gate Full-Adder Truth Table

● c a b s co a^b0 0 0 0 0 0: b0 0 1 1 0 1: c0 1 0 1 0 1: c0 1 1 0 1 0: b1 0 0 1 0 0: b1 0 1 0 1 1: c1 1 0 0 1 1: c1 1 1 1 1 0: b

● carry out = (a ^ b) ? c : a= (a ^ b) ? c : b (if a ^ b, then a = b)

Pass-Gate Full-AdderEquations and Circuit

● s = (a ^ b) ^ c= (a ^ b) ? c : ~c

● carry out = (a ^ b) ? c : b (see errata)

10

co

10 sc

b

a

Pass-Gate Full-Adder Characteristics

● 24 transistors– 4 pass gates– 4 inverters– 2 Xor gates (which share their inverter portions)

● Delay to s = delay to co● Both outputs, s and co, are uninverted

The Carry Recurrence

● Ci= G

i + P

iC

i-1

–Ci

A Carry out will leave stage i● If

–Gi

a carry is Generated in stage i● Or

–Ci-1

a Carry in enters from stage i – 1● And

–Pi

is Propagated by stage i

Carry-Lookahead Equations

● Gi= A

i * B

i Generate

● Pi= A

i ^ B

i Propagate

● Ci= G

i + P

iC

i-1 Carry

= Gi + T

iC

i-1

● Ti= A

i + B

i Transmit

● Si= C

i-1 ^ A

i ^ B

i

= Ci-1

^ Pi

–Pi is a common subexpression to S

i and C

i

Transmit Can Replace Propagate

● Ti can replace P

i

–With one exception● P

i= A

i ^ B

i Propagate

● Ti= A

i + B

i Transmit

● Ci= G

i + T

iC

i-1 Carry

● Si

= Ci-1

^ Ai ^ B

i

≠ Ci-1

^ Ti

–The exception to Ti = P

i

Carry-Lookahead Add

● Gi= A

i * B

i

● Pi= A

i ^ B

i

● Si= C

i-1 ^ P

i

● CG: CarryGenerate Block

b2

a2

b3

a3

b0

a0

b1

a1

s0

s1

s2

s3

ci

c0

c1

c2

g0

g1

g2

g3

CG

Generalized Carry Recurrence

● Ci= G

i + P

iC

i-1

= Gi + P

i(G

i-1+ P

i-1C

i-2)

= Gi + P

iG

i-1+ P

iP

i-1C

i-2

= Gi + P

iG

i-1+ P

iP

i-1(G

i-2+ P

i-2C

i-3)

= Gi + P

iG

i-1+ P

iP

i-1G

i-2+ P

iP

i-1P

i-2C

i-3

● Ci = G

i +

n=1Σi (

m=nΠi P

m)G

n-1+ (

m=0Πi P

m)C

0

Unrolling the Carry Recurrence

● Ci = G

i + P

iC

i-1

● Ci = G

i +

n=iΣ1 (

m=iΠn P

m)G

n-1 + (

m=iΠ0 P

m)CI

● C0 = G

0 + P

0CI

● C1 = G

1 + P

1G

0 + P

1P

0CI

● C2 = G

2 + P

2G

1 + P

2P

1G

0 + P

2P

1P

0CI

● C3 =

G3 + P

3G

2 + P

3P

2G

1 + P

3P

2P

1G

0 + P

3P

2P

1P

0CI

Sum as an And Function of Transmit

● G = A * B● T = A + B● S = C ^ T * G'

= C ^ (A + B) *(A * B )'= C ^ (A + B) *(A' + B' )= C ^ (AA' + AB' + BA' + BB' )= C ^ ( AB' + BA' )= C ^ A ^ B

– (See errata.)

Sum as a Nor Function of Transmit

● G = A * B● T = A + B● S = C ^ ( T' + G )'

= C ^ ((A + B)' + (A * B ) )'= C ^ ((A + B) * (A * B )')= C ^ ((A + B) * (A' + B') )= C ^ (AA' + AB' + BA' + BB' )= C ^ ( AB' + BA' )= C ^ A ^ B

– (See errata.)

CarryEquationCommon Subexpression Elimination● C

3 =

G3 + P

3G

2 + P

3P

2G

1 + P

3P

2P

1G

0 + P

3P

2P

1P

0CI

● C3 =

G3 + P

3(G

2 + P

2(G

1 + P

1(G

0 + P

0CI)))

Domino cMOS Carry Gate Circuit

● C3 = G

3 + P

3( G

2 +P

2( G

1 +

P1( G

0 +

P0CI)))

● Worst-case delay path:– 6 nMOS in series

p3

g3

p2

g2

p1

g1

p0

g0

ci

clk

clk

c3

Dynamic Manchester Carry Chain Stage

1.Clk = 0, ~cn precharged by pMOS pull-up

2.Clk = 1, nMOS pull-down turned on

3.If gn = 1, ~c

n discharges

4.If pn = 1, ~c

n-1 may discharge ~c

n

gn

clk

clk

~cn-1

pn

~cn

Dynamic Manchester Carry Chain Adder

● Carry is actually propagated● 6 series nMOS transistors pull ~c

3 low

g pci co ~p

~c2

p2

g2

~p2

g pci co ~p

~c3

p3

g3

~p3

g pci co ~p

~ci

p0

g0

~p0

g pci co ~p

~c1

p1

g1

~p1

c3ci

clk

clk

~c0

Dynamic ManchesterCarry-Bypass Circuit

● Bypass the four stages if all pi are true

g pci co ~p

~c2

p2

~p2

g pci co ~p

~c3

p3

~p3

g pci co ~p

~ci

p0

g0

~p0

g pci co ~p

~c1

p1

~p1

c3ci

clk

clk

~c0

p2

g2

p3

g3

p0

p1

g1

Conflict-Free ManchesterCarry-Bypass Circuit

● Avoids conflicts at wired Or-node– Before final inverter– Improves speed. Note also inverter position

10

g0

p2

~g2

~g3

p0

p1

g1

10

210

10

cic

3

control