vlsi-81-3 the partitioning of concerns in digital system design

7/27/2019 VLSI-81-3 the Partitioning of Concerns in Digital System Design

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The Partitioning of Concernsin Digital System Designby Mark Stefik Daniel Bobrow Alan BellHarold Brown Lynn Conway and Christopher Tong


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The Partitioning of oncernsin igital System esign

by Mark Stefik Daniel Bobrow Alan BellHarold Brown Lynn Conway and Christopher TongVLSI System Design Area Xerox PARC andHeuristic Programming Project Stanford University

VLSI813 December 1981Copyright @ 1981 M Stefik D Bobrow A BellH Brown L. Conway and C Tong. All Rights Reserved


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BSTR CT

This paper proposes the use of explic it abstraction levels to organize decision making indigital design. These levels partition the concerns that a designer must consider at any time.They provide terms and composition rules for the composition of structural descriptionswithin a level. This allows multiple opportunities for mapping behavior into structure.

A version of this paper will be presented at the Conference on Advanced Research in VLSI,Massachusetts Institute of Technology, Cambridge, Massachusetts, January 25-27, 1982.

The Stanford University component of this research is funded by the Defense AdvancedResearch Projects Agency contract MDA-903-aO-C-007.


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ONTENTS

Introduction 1Getting Leverage from Abstraction 2Examples o Description LevelsThe Linked Module Abstraction LMA) Level 3The Clocked Registers and Logic CRL) Level 6The Clocked Primitive Switches CPS) Level 7Comparisons with Other Approaches 9Closing Remarks 9References 1


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IntroductionThe Mead and Conway textbookl presents a

methodology for designing digital integrated systemswhich exploits the properties of charge-storage devices.As in most texts concerning design. the methodology iscommunicated via examples. It is clear from theseexamples that designers work within multiple designspaces ranging from abstract system descriptions to circuitlayouts. At the layout level. the methodology isformalized in an explicit set of rules for composingprimitive terms. ..colored rectangles representing

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explicit constraints. We are developing transformationrules to take designs at one of these levels and expressthem at other levels.

To aid in testing these ideas, we are developing allexpert design system. Palladio, which will assist a user todesign with multiple levels of description. An active partof the system will suggest alternative implementations ofa higher level design as well as possible optimizations.Palladio is being built in the knowledge engineeringparadigm. Knowledge engineering is a branch of research


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Getting Leverage from AbstractionThe principle of divide nd conquer is an essential

part of mastering otherwise overwhelming tasks. AsSimon and many others have observed:

To design a complex structure, one powerfultechnique is to discover viable ways ofdecomposing it into semi-independent componentscorresponding to its many functional parts. Thedesign of each component can then be carried outwith some degree of independence of the designof others [page 148]4

That so many design systems have facilities forsupporting this kind of hierarchical design suggests thatthe point is widely appreciated. But exploitation of acomponent hierarchy is only one of several opportunitiesfor dividing up the design process. Design usingabstraction levels is a complementary way to do i t Themetaphor in force here is that design is search. Solutionsexist in a potentially large space of possible designs.Design is a process of generating alternatives and testingthem against requirements and constraints. Abstractsolutions are descriptions that stand for an equivalenceclass of detailed solutions.

The design process can be characterized as adialectic between goals and possibilities. Designersexplore parts of the design space as driven by theircurrent goals and they sharpen their goals as they learnwhat is possible. They decide how far the overall designshould be completed before designs for particular

Abstraction levels provide leverage for top-downprocesses by enabling a designer to deal with criticalissues early and across the breadth of a design. This is astep towards a principled approach for dealing withcritical considerations early in the design process anddefering others. For example, in the abstraction levels inthis paper computational issues are considered critical.Using these levels designers can work out certain storageand communication decisions before worrying aboutpower considerations. t each level, designers makedecisions about structures for implementing devices withthe desired behavior.

Abstract descriptions have fewer specifications thancomplete solutions and are generated more quickly. Wecan explore more territory because we travel faster.Familiarity with useful kinds of tradeoff can guide thegeneration process. Following tradeoffs we can movefrom one possible description to another having differentcosts along some design dimension (e.g., communicationvs. redundant computation). We explore more effectivelybecause we know where to look. Another benefi t ofdesigning with abstractions is early pruning. For thisthere must be a cost metric that can be applied to pruneparticular descriptions. .Using the metric to eliminate adescription, we avoid pursuing the members of theequivalence class of detailed solutions.

Abstraction levels and constraints have been usedbefore in expert systems, although this may be their firstapplication in an expert system for the design of digitalsystems. Multiple levels of abstraction have been used


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DescriptionLevelLinkedModuleAbstraction LMADockedRegisters

Concerns Terms

Event ModulesSequencing ForksJoinsBuffers

Clocking Stages

CompositionRulesTokenConservationForklJoin Rules

Connection

upAvoidedDeadlockData notReadyMixed DockBugs

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and Logic Register Transfer of Stages UnclockedCRL 2 Phase Transfer Functions FeedbackPull-Ups Connection hargeDocked DigitalPrimitive Behavior Pull-downs of switch SharingPass networks SwitchingSwitchesCPS Transistors Ratio Rules Levels

Physical Colored Lambda SpacingLayout Dimensions Rectangles Rules ErrorsFig. 1 Description Levels for Palladio

The layout description level is used in many digitaldesign systems. The terms at this level of description areregions e.g., rectangles) of metal, polysilicon, anddiffusion in nMOS. The composition rules at this levelare a set of ambda rules governing the sizes and spacingof the regions. The rules are intended to guarantee thatthere will be no spacing errors that would prevent correctoperation of a fabricated system.

The following sections give simple examples ofstructural descriptions and rules at each of the more

Terms. The basic elements of this level are modules.Modules are computational elements that perfonncomplete operations. Once a module has been started, itcompletes what it is doing before it can be restarted.Each module has a number of directional paths: a oand a Done path for synchronizing communication withother modules, optional Input and Output data paths,and an optional Interrupt path. Each module also has aset of input buffers corresponding to the input data paths.A module is controlled by the absorption and emission oftokens on the Go and Done paths. Besides modules


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Composition Rules. Composition rules at the LMAlevel govern the use of shared structures and provideconventions for control of infonnation flow. Thefollowing are examples of composition rules.

Fork Rule. f the output data paths of a moduleconnect to more than one other module. then itsDone path must be connected through a Fork tothe Go paths of all of the other modules.Join Rule. f the input data paths of a module areconnected to more than one other module. then itsGo path must be connected through a Join to theDone paths of all of the other modules.Shared Module Rule. Calls to shared modulesmust be buffered.

The composition rules of the LMA level prevent the useof data before it is ready (e.g.. has not settled) andprevent deadlock from the use of shared modules in thedigital system.

Exampies from the Design of a Stack. A niajor goalof the LMA level is to provide an expressive language fordescribing ,digital architecture. We believe that practicingdesigners do not share a common notation and that thismakes it unnecessarily difficult to understand designs.This section argues that the LMA language is expressiveenough to admit meaningful comparisons and abstractenough to provide leverage for exploring designalternatives.

Fig. 3 Pointer Stack

Module PointerStackinputs [command: action. dataln: item]outputs [dataOut: item]--These specify typedinput and output lines.parameters [depth: Integer. item: Type]--These are construction parameters.components (pointer: Registcr[addressWidth depth)]R: Sel[i. depth. Register[itemm--This specifies subcomponents of modules from a library.--Sel(i,n,typc) creates a set of n indexable items of ype type.action [Case commandpush if pointcrlthen {pointer pointer-l;interrupt [{pointer l}]endModule PointcrStack

select key .. pointer; dataOut R[key] I>}] ]

Roving Marker Stack. This version uses a mark bit


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Ganged Marker Stack This is similar to the previousstack except that all of the marker bits are moved, insteadof jus t the top ones. Architecturally, this stack is amixture of the first two. It combines an array of registersfor data storage with a shift: register for marker storage.

Fig . 5 Ganged Marker StackBuffered Stages Stack In the previous versions, thecell containing the data at the top of the stack varied

according to the number of pushes and pops. Anindicator was used to keep track of which cell was thecurrent top of the stack. In this implementation, the topof the stack is always the leftmost cell and all the data inthe stack move simultaneously. Intermediate stagesbuffer the data as it moves been cells.

MemoryCells

Left End [1] [ ] Right EndFig. 7 Ripple Stack

Module RipplcStactinputs [command: A ction. dataln: item]outputs .[dalaOut: item]parameters [depth: Integer. item: Type]C 1l5lants [moveRight, startMoveLeft, POP. store: Action]components [ DC: Set[i depth.DataCell[item: item

action [Cose command

LNbr: when i>1 then DC[i-l].RNbr: wilen i}]endModule RippleStaek

Module DataCellinputs [command: action. dataIn: item]outputs [dataOut: item]parameters [item: Type. LNbr: DataCell[item]. RNbr: DataCell[itemDcomponents [Filled: Bit]action [Cose command[moveRight 0 - 0[startMoveLeft

[moveLeft

{ifFilled=lthen RNbr moveRight);RNbr store. dataIn)}]{ifFilIed=Othen LNbr startMoveLeft)else {LNbr(moveLeft);Filled+-OH]{i Filled = 1then LNbr moveLeft);LNbr store. dataln)}][store(pop dataIn) - 0 { . data stored in dataln]o - dataOut) {dataOut+-dataIn; Filled+-O}D

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What determines the minimum delay between successivepush commands?

The ripple stack has a delay which increases as thestack is filled. This is because the push commandmust ripple through to the last filled stack cell.We have not worked out the details of a versionof a ripple stack in which the first few elementswould not have to wait for the ripple to finish; itwould allow successive push and pop transactionsto cancel without extensive rippling.) The timecomplexity of the pointer stack depends on thetime complexity of the adder and of the randomaccess memory.

LMA notation for distributed computing i.e:, activearchitectures is analogous to high level programminglanguages for sequential and parallel algorithms.Specification at the LMA level highlights criticalarchitectural tradeoffs such as communication versusredundant computation, copied structures versus sharedstructures, serial versus parallel computation. We believethat LMA programs are amenable to a physical theory ofcomputation, perhaps along the lines of the entropymodel in Mead and Conwayl pages 365-370. This wouldprovide an added abstract framework for space-timeenergy complexity analysis beyond that now emerging forVLSI circuitsl2.The Clocked Registers and Logic CRL) Level

The clocked registers nd logic CRL) level is

Terms. The terms at the CRL level are stages.Stages are logical devices having both a storage capacityand a transfer function.

Composition Rules. Common design practice is touse alternate clocks to load data into successive stages.This practice is captured by the following twocomposition rules:

All of the data inputs to a stage must be validduring the high interval of the same clock.All of the outputs of a stage must be valid duringthe high interval of the other clock.

Phil Phi 2 Phil Phi 2

Sequence ofStages

Phi 2

Oocked Feedback Loop


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Phi1 LdStraight-forward Version L

Optimized Version

- -Phi 2Phil Ld

LClockingGateOmitted

Fig. 9 Two Versions of a Memory Cell

The Clocked Primitive Switches (CPS) LevelThe CPS level is concerned with the digital behavior

of a system. This requires that circuits have two reliablydistinct logical levels. For example, near 5 volts we havea band which we interpret as logical I, and near 0 volts

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Terms. The terms at the CPS level are steeringlogic, clocking logic, and restoring logic. The basicelement of steering logic is a pass transistor. We label itsterminals as follows:

ControlInput--L

Data Input Steered OutputFig. 10 Pass Transistor

We define a steering logic chain (SLC) as seriesconnected pass transistors and define a steered logicnetwork (SLN) as the parallel composition of SLCs. AnSLN can have several outputs.

CONTROL


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The basic element of restoring logic is a restoring element.VDD

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PUE

RestoredOutput

Restored Inpu t -Steered Input - PDNClocked Inpu t - IGNDFig. 13 Restoring Element

A restoring element is made of a pull-up element PUE)and a pull-down network PDN). A PDN has three kindsof input.s restored steered or clocked. The three kinds ofinputs name the type of logic to which they areconnected. The composition rules in the next sectionexploit the type information to help prevent errors.Composition Rules. The composition rules at the CPSlevel specify how the terms can be connected and takeinto account requirements for voltage level restorationand charge storage. For example:

A control input can only be connected to arestored output

Because of our rules, clocking logic must always separateswitching logic from restoring logic. The purpose of thisis to prevent charge sharing. Charge sharing occurs whencharge is allowed to leak to or from a charge storagepoint, as illustrated in figure 14 For example, if PTI ison, the charge can spread through PTI into thecapacitance of points further back. Since the amount ofspreading can depend on the patterns of logical signals tothe pass transistors, failures can seem intermittentdepending on rare combinations of signals to a circuit

Another set of composition rules constrain thelayouts of pull-downs in terms of their impedances:Element ImQedance ConstraintPull-up element ZpUE = L WRestored PUE ZpUE = L WClocked PDE ZpDE = 2L WSteered PDE ZpDE = 2L WRestored PDE ZpDE = L W

The impedance of elements connected in series iscomputed as the sum of the individual impedances; theimpedance of elements connected in parallel is computedas the maximum of the individual impedances. For therestoring logic to restore voltage levels correctly, theimpedance ratio ZPU/ZpDN must be approximately 4OQtimization Rules. According to the ratio rules above,the impedance for the following network would becomputed as 8 In making this recommendation, thecomposition rules implicitly make a worst case


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Comparison with Other ApproachesThe philosophy behind our approach differs

significantly from that used in the construction of siliconcompilers. In a silicon compiler, the desired behavior ofa system is specified in a language at a single level. Thecompiler converts this behavioral description into astructural description in a standard format. This fails toexploit many possibilities in the design space. In our useof multiple descriptions, each level specifies bothbehavioral and structural information. User-chosentransformations can be made in the design at manydifferent levels all the way down. For example, in theLMA level, one might find optimizations which yieldedsubstantially different structures before deciding whetherto use two-phased clocking or self-timed circuits.

Multiple Level System e.g. Palladio)Behavioral Specification Structural SpecificationLMA

CRLCPSIAlyout

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The use of multiple levels for describing hardwarehas been tried many times. For example, there are logicdescriptions and register transfer descriptions14 Webelieve that the logic descriptions are too isolated and theRT descriptions are incomplete and insufficientlyformalized. For example, it is difficult even to find theclocking specifications in a typical RT description. Thecomposition of partial RT descriptions does not yield atest o correctness for clocking. In essence, thosedescriptions were not designed for synthesis. Theyprovide no composition rules, optimization rules, or bugcharacterizations. Our goal is to understand andformalize descriptive levels whose utility derives fromtheir coverage of critical design concerns.

Part of the culture of expert system building is theexplicit representation of entities from problem-solving,such as goals, constraints. tradeoffs, and reasons.Symbolic expressions for these need to refer to circuitdescriptions e.g., modules or pull-down networks) as partof the natural bookkeeping of the design process. Suchsymbolic representations are a prerequisite t embodyingexpertise bout design in an expert system. Figure 17provides a sketch of how our abstraction levels will beused in Palladio.

Closing RemarksThe utility of these levels of description remains to,be tested. Embedding them in Palladio and exercising

them will be our reality test. We expect libraries of


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LMA

Constraints implementations

MultipleAlternativesl \flDesign TaskAgendaCheck

CompositionRulesEstimatePropagationDelay

ProposeDesignAlternatives

Fig. 17 Snapshot of a Design Process in Palladio

Referencesl Mead, C., and Conway, L. Introduction to VLSISystems. Addison-Wesley Publishing Company, 1980.2. Feigenbaum. E. A. The art of artificial intelligence:themes and case studies of knowledge engineering.Proceedings of the National Computer Conference AFIPS1978, pp. 227-240.

8. Stefik, M. Bobrow, D. G Linked moduleabstraction: A methodology for designing thearchitectures of digital systems. (working paper),Knowledge-Based VLSI Design Group KB-VLSI-81-9,1981.9. Peterson, 1. L. Petri nets. Computing Surveys 9:3

The Partitioning of Concerns by Mark Stefik Daniel Bobrow


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in Digital System Design Alan Bell Harold Brown Lynn Conway and Christopher Tong

vlsi-81-3 the partitioning of concerns in digital system design

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